A semiconductor device terminal structure and preparation method thereof

Abstract

The present invention discloses a semiconductor device terminal structure and a method for fabricating the same. The structure comprises a wide-bandgap N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, and an N-type doped current diffusion layer. The terminal structure forms a main junction region at one end near the anode, a cut street at the end away from the anode, and a terminal region in the middle. The upper portion of the terminal region is etched to form a trench terminal comprising a main trench and a secondary trench. The main trench spans the P-type doped main junction region and extends deep into the N-type doped current diffusion layer. A secondary trench is etched at the bottom of the main trench, comprising an intermediate trench and side trenches. The intermediate trench passes through the P-type doped buried layer, with its bottom located within the N-type doped drift region. The spacing between the side trenches gradually decreases and / or the volume gradually increases in the direction from the main junction region to the terminal region and from the cut street region to the terminal region. The P-type doped buried layer, with its equivalent doping concentration gradually decreasing, can reduce the electric field concentration near the main junction region and the cut street.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a semiconductor device terminal structure and a preparation method thereof. Background Art

[0002] Traditional silicon devices are limited by their inherent material properties, and further performance improvements are expected to rely on higher-performance semiconductor materials. Third- and fourth-generation wide-bandgap semiconductor materials, represented by SiC and Ga2O3, have emerged as the answer to this question. Wide-bandgap semiconductor materials offer advantages over silicon in physical properties such as bandgap width, breakdown field strength, and electron saturation drift velocity.

[0003] In the blocking state, the device mainly bears voltage through the depletion region formed by the PN junction under reverse bias. According to Poisson's equation, the peak value of the electric field strength in the depletion region is located near the PN junction. When the peak value of the electric field strength reaches the critical breakdown electric field strength of the semiconductor material, the device will be broken down.

[0004] In the actual preparation process, cylindrical junctions and spherical junctions are formed at the edges and corners of the PN junction. Under the effect of curvature, the electric field near the cylindrical junction and spherical junction is more concentrated, and the electric field intensity is much greater than the electric field intensity of the parallel plane junction in the middle area. The edges and corners will break down before the parallel plane junction, resulting in the breakdown voltage of the device being much lower than the ideal case. Figure 21 shown.

[0005] In order to alleviate the problem of premature breakdown of the edges and corners of the PN junction (main junction of the device) due to the curvature effect, resulting in reduced device blocking capability, the industry often adds a junction termination structure around the PN junction (main junction). The introduced junction termination structure can disperse the electric field originally concentrated at the edge of the main junction, thereby reducing the electric field strength at the edge of the main junction and making the device breakdown voltage closer to the ideal value of a parallel plane junction.

[0006] Common junction termination structures include field plates, mesas, junction termination extensions, and field limiting rings, such as Figure 22As shown. The principle of the field plate (FP) structure is to expand the depletion layer on the junction termination surface by applying an external voltage to the field plate, thereby alleviating the electric field concentration phenomenon at the edge of the PN junction. The principle of the mesa (MESA) structure is to widen the depletion region width at the PN junction by etching a bevel, thereby reducing the electric field concentration phenomenon. The junction termination extension (JTE) structure expands the depletion region of the P+ main junction through its own depletion, thereby reducing the electric field concentration phenomenon at the main junction. The existence of the field limiting ring (FLR) structure is equivalent to adding a voltage divider to the edge of the main junction of a planar power device. By rationally optimizing the amount, ring width, doping concentration, and ring spacing of the FLR, the width of the main junction depletion region can be effectively widened, and the electric field concentration phenomenon of the main junction and the ring can be reduced, thereby increasing the breakdown voltage.

[0007] However, existing junction termination technology still has some problems. Taking SiC materials as an example, the main technical defects are as follows:

[0008] Technical Flaw 1: Although junction termination technology is relatively mature for Si materials, due to the extremely low diffusion coefficient of impurities in SiC materials, doping of SiC materials is often done through high-temperature ion implantation, forming a shallow PN junction. This results in a smaller radius of curvature of the PN junction in SiC power devices, making the electric field more easily concentrated, further reducing the device's blocking capability and the protection capabilities of the junction termination. In addition, with the development of device structure design capabilities, NPN epitaxial layers have emerged. However, due to limitations in implantation capabilities, existing terminations cannot effectively protect the main junction of devices based on NPN epitaxial layers.

[0009] Technical Defect 2: In high-voltage, high-temperature, and high-humidity environments, charge accumulation, moisture corrosion, and ion migration can occur at the terminals, potentially short-circuiting the front electrode and the cut path. In this situation, both the cut path and the back electrode, as well as the main junction and the back electrode, must withstand the device's blocking voltage. Traditional terminal structures only protect the main junction, neglecting the cut path area. This can lead to increased leakage current in the cut path area or premature breakdown in the cut path area, resulting in a lower-than-ideal breakdown voltage.

[0010] Technical Defect 3: Outside the junction terminal, at the very edge of the device, in the device's scribe area, when the device is in the blocking state, the potential in the scribe area is equal to the bus voltage, while the potential of the electrode in the middle of the device's front side is 0V. This means that there is a huge potential difference between the electrode and the scribe, and air breakdown may occur between the front electrode and the scribe, causing device burnout.

[0011] Technical Flaw 4: Existing power devices typically include a substrate, a drift layer disposed on the substrate, a metal layer evaporated on the drift layer, and then a passivation layer formed on the metal layer. Steep steps may form at the main junction or the edge of the scribe line. If the metal layer and passivation layer overlap the step, the mismatch in the expansion coefficients of the metal, passivation layer, and semiconductor materials can easily cause the passivation layer to crack at the step during reliability testing, resulting in reduced long-term reliability of the power device in high-temperature and high-humidity environments. Summary of the Invention

[0012] In view of the fact that the existing junction terminal structure is limited by the thermal diffusion coefficient of the material, the ion implantation depth and other reasons and cannot well protect the main junction of the power device, especially the problem that air breakdown occurs between the surface electrode and the cutting path of the NPN power device and the existing terminal structure cannot protect the cutting path area, which ultimately leads to a serious reduction in the breakdown characteristics of the device, the present invention provides a new junction terminal structure and a preparation method thereof.

[0013] The technical solution of the present invention to solve the above technical problems is as follows:

[0014] A semiconductor device terminal structure, comprising a wide bandgap N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, and an N-type doped current diffusion layer connected in sequence from bottom to top;

[0015] The side of the N-type doped current diffusion layer away from the P-type doped buried layer is connected to the P-type doped main junction region and the anode in sequence from bottom to top, and the side of the N-type doped substrate away from the P-type doped buried layer is connected to the cathode. The end of the terminal structure close to the anode forms the main junction region, the end away from the anode is the cutting path, and the middle is the terminal region;

[0016] Etching the upper portion of the terminal region into a trench terminal including a main trench and a sub-trench, wherein the main trench crosses the P-type doped main junction region and penetrates into the N-type doped current diffusion layer, and etching a sub-trench at the bottom of the main trench, wherein the sub-trench includes a middle trench that penetrates the P-type doped buried layer and at least one side trench on both sides that does not penetrate the P-type doped buried layer;

[0017] The middle trench passes through the P-type doped buried layer, and the bottom is located in the N-type doped drift region. The side trenches on both sides are arranged such that the spacing between the side trenches gradually decreases and / or the volume gradually increases in the direction from the main junction region to the terminal region and in the direction from the cutting street region to the terminal region, so that the equivalent doping concentration of the P-type doped buried layer in the direction from the main junction region to the terminal region and in the direction from the cutting street region to the terminal region shows a trend of gradually decreasing.

[0018] The gradual increase in volume includes a gradual increase in the width of the side grooves, and / or a gradual increase in the depth of the side grooves, and / or a gradual increase in the thickness of the side grooves.

[0019] Based on the above technical solutions, the present invention can also be improved as follows.

[0020] Furthermore, in the above-mentioned semiconductor device terminal structure, the inner sidewalls of the secondary trench and the main trench are connected to the first insulating dielectric layer, the space below the highest point in the secondary trench and the main trench is filled with the second insulating dielectric layer, the third insulating dielectric layer is connected above the second insulating dielectric layer, one end of the third insulating dielectric layer is connected to the anode, and the other end covers the N-type doped current diffusion layer, and the fourth insulating dielectric layer is connected above the third insulating dielectric layer.

[0021] Furthermore, the above-mentioned semiconductor device terminal structure,

[0022] The first insulating dielectric layer is silicon dioxide; and / or

[0023] The second insulating medium layer is PI glue; and / or

[0024] The third insulating dielectric layer is silicon nitride; and / or

[0025] The fourth insulating dielectric layer is silicon dioxide.

[0026] Furthermore, in the above-mentioned semiconductor device terminal structure, the material of the wide bandgap N-type doped substrate is SiC, GaN, Ga2O3, C or AlN.

[0027] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping types of the main junction region, the terminal region, and the cutting road region are changed from N-type to P-type, and from P-type to N-type.

[0028] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; and the doping element of the P-type doped main junction region is aluminum or boron.

[0029] Furthermore, in the above-mentioned semiconductor device terminal structure, the side trenches on both sides are replaced with a step structure with a larger step width as it approaches the middle trench; or

[0030] The side trenches on both sides are replaced by N-type doped charge compensation regions of the same size with decreasing spacing from the main junction region to the terminal region and from the cutting street region to the terminal region, wherein the doping element of the N-type doped charge compensation regions is nitrogen; or

[0031] The depth of the P-type doped main junction region is increased to completely replace the N-type doped current diffusion layer and penetrate into the P-type doped buried layer; or

[0032] connecting a P-type doped main junction region between the N-type doped current diffusion layer and the third insulating dielectric layer in the scribe line region; or

[0033] The terminal structures on the left and right sides of the middle groove are different; or

[0034] The middle trench and the side trench are replaced with an inverted trapezoidal structure tilted toward the N-type doped drift region, with both sides being inclined surfaces that extend into the N-type doped drift region, and the bottom surface of the inverted trapezoidal structure is located in the N-type doped drift region.

[0035] Furthermore, in the above-mentioned semiconductor device terminal structure, the doping element of the N-type doped charge compensation region is nitrogen.

[0036] The method for preparing a semiconductor device terminal structure as described in any one of the above items comprises the following steps:

[0037] growing an N-type doped drift region on a wide bandgap N-type doped substrate;

[0038] forming a P-type doped buried layer by ion implantation, epitaxy or growth of a P-type oxide;

[0039] forming an N-type doped current diffusion layer by epitaxy;

[0040] forming a P-type doped main junction region by ion implantation, epitaxy or growth of a P-type oxide;

[0041] forming trench terminations by dry etching and / or wet etching;

[0042] forming a first insulating dielectric layer by deposition or thermal oxidation;

[0043] The second insulating dielectric layer is formed by deposition or coating, exposure and development.

[0044] The above-mentioned method for preparing a semiconductor device terminal structure further includes the following steps:

[0045] Etching of the first insulating dielectric layer, deposition and etching of the anode metal;

[0046] A third insulating dielectric layer and a fourth insulating dielectric layer are deposited, the third insulating dielectric layer and the fourth insulating dielectric layer are etched, and a cathode metal is deposited.

[0047] Compared with the prior art, the technical solution of the present invention has the following beneficial technical effects:

[0048] 1. This structure involves etching a middle trench and multiple side trenches in a P-type doped main junction region, an N-type doped current diffusion layer, and a P-type doped buried layer. The deepest part of the middle trench needs to exceed the P-type doped buried layer, i.e., at least one trench needs to penetrate the P-type doped buried layer. The trench terminals can be achieved by gradually reducing the spacing between the side trenches in the direction from the main junction region to the terminal region or from the cutting path region to the terminal region, and / or gradually increasing the volume, or gradually increasing the doping concentration of the N-type doped charge compensation region that replaces the side trenches, or by other means to gradually reduce the equivalent acceptor impurity atomic weight of the P-type doped buried layer in the direction from the main junction region to the terminal region or from the cutting path region to the terminal region. The gradual increase in volume includes gradually increasing the width of the side trenches, and / or gradually increasing the depth of the side trenches, and / or gradually increasing the thickness of the side trenches.

[0049] This structure forms a P-type doped buried layer on the left side of the terminal near the anode (main junction region) in the middle trench and at least one side trench, with the equivalent doping concentration gradually decreasing in the direction away from the main junction region. This can reduce the curvature effect of the main junction region, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device.

[0050] 2. In this structure, a P-type doped buried layer with an equivalent doping concentration gradually decreasing in the direction away from the cutting street area is formed by the middle trench and at least one side trench near the cutting street area on the right side of the terminal area, or an N-type doped charge compensation area that replaces the side trench and has a gradually increasing doping concentration, and can reduce the curvature effect of the electric field in the cutting street area, alleviate the problem of electric field concentration near the cutting street, and prevent the cutting street area from breaking down prematurely after the cutting street surface is short-circuited with the anode metal (front electrode of the device).

[0051] 3. In the blocking state of the device, the P-type doped buried layer can block the cathode (device back electrode) potential and leakage current.

[0052] 4. Set up multiple layers of insulating dielectrics above the trench, including the second insulating dielectric layer. The function of this dielectric layer is to fill the trench, reduce the height difference of the device surface, prevent the metal layer or passivation layer from cracking at the step position, and ensure the long-term reliability of the device in high temperature and high humidity environments. The material used for this dielectric layer needs to have good hole-filling ability, such as PI glue or other organic matter.

[0053] 5. The trench that spans the P-type doped main junction region, the N-type doped current diffusion layer, the P-type doped buried layer and extends deep into the N-type doped drift region can act as a (field) stop ring. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1 A schematic structural diagram of a semiconductor terminal structure provided in Example 1 of the present invention;

[0055] Figure 2 This is the step of growing an N-type doped drift region on a substrate in the preparation method of embodiment 1 of the present invention;

[0056] Figure 3 The P-type doped buried layer is formed by ion implantation, epitaxy, growth of a P-type oxide, or the like in the preparation method of embodiment 1 of the present invention;

[0057] Figure 4 The N-type doped current diffusion layer is formed by epitaxy in the preparation method of embodiment 1 of the present invention;

[0058] Figure 5 The preparation method of embodiment 1 of the present invention forms a P-type doped main junction region by ion implantation, epitaxy, growth of a P-type oxide, or the like;

[0059] Figure 6 Forming a plurality of trench terminals by dry etching and / or wet etching in the preparation method of embodiment 1 of the present invention;

[0060] Figure 7 The first insulating dielectric layer is formed by deposition or thermal oxidation in the preparation method of embodiment 1 of the present invention;

[0061] Figure 8 The second insulating dielectric layer is formed by deposition, coating, exposure, and development in the preparation method of Example 1 of the present invention;

[0062] Figure 9 The first insulating dielectric layer is etched, and the anode metal is deposited and etched in the preparation method of Example 1 of the present invention;

[0063] Figure 10 This is a simulated structure doping concentration distribution diagram of the portion of the semiconductor terminal structure on the left side near the main junction region of the structure terminal of the embodiment 1 of the present invention;

[0064] Figure 11 A structural terminal breakdown characteristic curve diagram of a semiconductor terminal structure according to embodiment 1 of the present invention;

[0065] Figure 12 for Figure 10 Potential distribution diagram on the AA' tangent line;

[0066] Figure 13 for Figure 10 The electric field intensity distribution on the AA' tangent line;

[0067] Figure 14 A schematic structural diagram of a semiconductor terminal structure provided in embodiment 2 of the present invention;

[0068] Figure 15A schematic structural diagram of a semiconductor terminal structure provided in Example 3 of the present invention;

[0069] Figure 16 A schematic structural diagram of a semiconductor terminal structure provided in embodiment 4 of the present invention;

[0070] Figure 17 A schematic structural diagram of a semiconductor terminal structure provided in Example 5 of the present invention;

[0071] Figure 18 A schematic structural diagram of a semiconductor terminal structure provided in Example 6 of the present invention;

[0072] Figure 19 A schematic structural diagram of a semiconductor terminal structure provided in Example 7 of the present invention;

[0073] Figure 20 A schematic structural diagram of a semiconductor terminal structure provided in Example 8 of the present invention;

[0074] Figure 21 A schematic diagram of a structure in which the curvature effect of a PN junction edge leads to electric field concentration in the background technology of the present invention;

[0075] Figure 22 Schematic diagram of the common terminal structure in the background technology of the present invention, (a) field plate; (b) mesa; (c) junction terminal extension; (d) field limiting ring.

[0076] In the accompanying drawings, the components represented by the reference numerals are as follows:

[0077] 1. Main junction region, 2. Terminal region, 3. Cutting road, 4. N-type doped substrate, 5. N-type doped drift region, 6. P-type doped buried layer, 7. N-type doped current diffusion layer, 8. P-type doped main junction region, 9. Anode, 10. Cathode, 11. First insulating dielectric layer, 12. Second insulating dielectric layer, 13. Third insulating dielectric layer, 14. Fourth insulating dielectric layer, 15. Sub-trench, 151. Middle trench, 152. Side trench, 16. Step, 17. N-type doped charge compensation region, 18. Inclined surface, 19. P-type doped substrate, 20. P-type doped drift region, 21. N-type doped buried layer, 22. P-type doped current diffusion layer, 23. N-type doped main junction region. DETAILED DESCRIPTION

[0078] For ease of understanding of the present application, the present application will be described more fully below. The present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0079] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0080] It will be understood that spatial relational terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It will be understood that in addition to the orientations shown in the figures, spatial relational terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0081] It should be noted that when an element is considered to be "connected" to another element, it can be directly connected to the other element or connected to the other element through an intermediate element. In the following embodiments, "connection" should be understood as "electrical connection", "communication connection", etc., if the connected circuits, modules, units, etc. can transmit electrical signals or data to each other.

[0082] When used herein, the singular forms "a", "an", and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

[0083] Taking the terminal structure of a semiconductor device made of SiC material as a substrate as an example, the present invention aims to address the problem that the existing junction terminal structure is unable to well protect the main junction of the power device, especially the main junction of an NPN epitaxial wafer structure, due to limitations such as the thermal diffusion coefficient of the semiconductor material and the depth of ion implantation (technical defect 1); the problem that a short circuit may occur between the surface electrode of the power device and the cutting street 3, and the existing terminal structure cannot protect the cutting street 3 area, ultimately leading to a serious reduction in the breakdown characteristics of the device (technical defect 2); the problem that air breakdown is prone to occur in the cutting street 3 area (technical defect 3); and the problem that during reliability testing of the power device, due to the mismatch in the expansion coefficients of the metal, passivation layer and semiconductor material, the passivation layer is easily cracked at the step position of the metal layer, resulting in a reduction in the long-term reliability of the power device in a high temperature and high humidity environment (technical defect 4). The present invention provides a new junction terminal structure and a preparation method thereof.

[0084] A semiconductor device terminal structure, comprising a wide bandgap N-type doped substrate 4, an N-type doped drift region 5, a P-type doped buried layer 6, and an N-type doped current diffusion layer 7 connected sequentially from bottom to top;

[0085] The end of the N-type doped current diffusion layer 7 away from the P-type doped buried layer 6 is connected to the P-type doped main junction region 81 and the anode 9 in sequence from bottom to top. The end of the N-type doped substrate 4 away from the P-type doped buried layer 6 is connected to the cathode 10. The end of the terminal structure close to the anode 9 forms the main junction region 1, the end away from the anode 9 is the cutting street 3, and the middle is the terminal region 2;

[0086] Etching the upper portion of the terminal region 2 into a trench terminal including a main trench and a sub-trench 15, wherein the main trench crosses the P-type doped main junction region 81 and penetrates into the N-type doped current diffusion layer 7, and etching the sub-trench 15 at the bottom of the main trench. The sub-trench 15 includes a middle trench 151 that penetrates the P-type doped buried layer 6 and at least one side trench 152 on both sides that does not penetrate the P-type doped buried layer 6;

[0087] The middle trench 151 passes through the P-type doped buried layer 6, and its bottom is located in the N-type doped drift region 5. The side trenches 152 on both sides gradually decrease in spacing and / or increase in volume in the direction from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2, so that the equivalent doping concentration of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2 presents a trend of gradually decreasing.

[0088] The gradual increase in volume includes a gradual increase in the width of the side groove 152 , and / or a gradual increase in the depth of the side groove 152 , and / or a gradual increase in the thickness of the side groove 152 .

[0089] This structure is achieved by etching multiple trenches in the P-type doped main junction region 8, the N-type doped current diffusion layer 7, and the P-type doped buried layer 6. The deepest part of the trenches needs to exceed the P-type doped buried layer 6, that is, at least one trench needs to penetrate the P-type doped buried layer 6. The multiple trenches can be formed by gradually reducing the spacing between the trenches in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2, and / or gradually increasing the volume, or gradually increasing the doping concentration of the N-type doped charge compensation region that replaces the side trenches, or by other means so that the equivalent acceptor impurity atomic weight of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2 is gradually reduced. The gradual increase in volume includes gradually increasing the width of the side trenches, and / or gradually increasing the depth of the side trenches, and / or gradually increasing the thickness of the side trenches.

[0090] like Figure 1 As shown, at least one side trench 152 and a middle trench 151 are formed on the left side of the trench near the anode 9 (main junction region 1), or an N-type doped charge compensation region with gradually increasing doping concentration replacing the side trench, and a P-type doped buried layer 6 with a gradually decreasing equivalent doping concentration in the direction away from the main junction region 1 can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device, so as to solve the technical defect 1 in the background technology.

[0091] The P-type doped buried layer 6 with an equivalent doping concentration gradually decreasing in the direction away from the cutting road 3 area is formed by at least one side groove 152 and the middle groove 151 near the cutting road 3 area on the right side of the groove, or an N-type doped charge compensation area that replaces the side groove and has a gradually increasing doping concentration, and can reduce the curvature effect of the electric field in the cutting road 3 area, alleviate the problem of electric field concentration near the cutting road 3, and prevent the cutting road 3 area from breaking down prematurely after the surface of the cutting road 3 is short-circuited with the anode 9 metal (the front electrode of the device), so as to solve the technical defect 2 in the background technology.

[0092] In the blocking state of the device, the P-type doped buried layer 6 can block the cathode 10 (device back electrode) potential and leakage current, thereby solving technical defects 2 and 3 in the background technology.

[0093] In addition, multiple layers of insulating dielectric are provided above the trench, including a first insulating dielectric layer 11. The primary function of this dielectric layer is to isolate metal ions from affecting the electric field distribution within the semiconductor body. Silicon dioxide is commonly used as the material for this dielectric layer. A second insulating dielectric layer 12 is used to fill the trench, reduce the height difference on the device surface, prevent the metal layer or passivation layer from cracking at the step 16, and ensure the long-term reliability of the device in high temperature and high humidity environments, thereby resolving technical defect 4 in the background technology. The material used for this dielectric layer needs to have good hole-filling ability, such as PI glue or other organic materials. A third insulating dielectric layer 13 is used to isolate water vapor. Silicon nitride is commonly used as the material. A fourth insulating dielectric layer 14 is used to isolate the external electric field. Silicon dioxide is commonly used as the material for this dielectric layer.

[0094] Example 1

[0095] A semiconductor device terminal structure, comprising a wide bandgap N-type doped substrate 4, an N-type doped drift region 5, a P-type doped buried layer 6, and an N-type doped current diffusion layer 7 connected sequentially from bottom to top;

[0096] The end of the N-type doped current diffusion layer 7 away from the P-type doped buried layer 6 is connected to the P-type doped main junction region 81 and the anode 9 in sequence from bottom to top. The end of the N-type doped substrate 4 away from the P-type doped buried layer 6 is connected to the cathode 10. The end of the terminal structure close to the anode 9 forms the main junction region 1, the end away from the anode 9 is the cutting street 3, and the middle is the terminal region 2;

[0097] Etching the upper portion of the terminal region 2 into a trench terminal including a main trench and a sub-trench 15, wherein the main trench crosses the P-type doped main junction region 81 and penetrates into the N-type doped current diffusion layer 7, and etching the sub-trench 15 at the bottom of the main trench. The sub-trench 15 includes a middle trench 151 that penetrates the P-type doped buried layer 6 and at least one side trench 152 on both sides that does not penetrate the P-type doped buried layer 6;

[0098] The middle trench 151 passes through the P-type doped buried layer 6, and its bottom is located in the N-type doped drift region 5. The side trenches 152 on both sides gradually decrease in spacing and / or increase in volume in the direction from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2, or the doping concentration of the N-type doped charge compensation region replacing the side trench gradually increases, so that the equivalent doping concentration of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2 shows a trend of gradually decreasing.

[0099] The gradual increase in volume includes a gradual increase in the width of the side groove 152 , and / or a gradual increase in the depth of the side groove 152 , and / or a gradual increase in the thickness of the side groove 152 .

[0100] The number of side trenches 152 on both sides is not less than one, and can be one, two, three, six, etc. The number of side trenches 152 on both sides can be the same or different, such as more on the left side and fewer on the right side, fewer on the left side and more on the right side, or the same number on both sides. The middle trench 151 passes through the P-type doped buried layer 6, with its bottom located in the N-type doped drift region 5. The spacing between the side trenches 152 on both sides gradually decreases and / or the volume gradually increases in the direction from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2, or the doping concentration of the N-type doped charge compensation region replacing the side trench gradually increases, so that the area of ​​the P-type doped buried layer 6 etched away in the direction from the main junction region 1 to the terminal region 2 and from the cutting street 3 region to the terminal region 2 shows an increasing trend.

[0101] The cathode 10 is connected to a side of the N-type doped substrate 4 away from the P-type doped buried layer 6 , and the anode 9 is connected to a side of the P-type doped main junction region 8 away from the P-type doped buried layer 6 .

[0102] The sidewalls of the secondary trench 15 and the main trench are connected to the first insulating dielectric layer 11. The main function of this dielectric layer is to isolate metal ions from affecting the electric field distribution in the semiconductor body. The commonly used material for this dielectric layer is silicon dioxide. The space within the secondary trench 15 and the main trench below the highest point is filled with a second insulating dielectric layer 12. The function of this dielectric layer is to fill the trench, reduce the height difference of the device surface, prevent the metal layer or passivation layer from cracking at the step 16, and ensure the long-term reliability of the device in high temperature and high humidity environments, so as to solve the technical defect 4 in the background technology. This dielectric layer is PI glue. A third insulating dielectric layer 13 is connected above the second insulating dielectric layer 12. One end of the third insulating dielectric layer 13 is connected to the anode, and the other end is covered with an N-type doped current diffusion layer. The main function of this layer is to isolate water vapor. The commonly used material is silicon nitride. A fourth insulating dielectric layer is connected above the third insulating dielectric layer. The main function of this dielectric layer is to isolate the external electric field. The commonly used material for this dielectric layer is silicon dioxide.

[0103] The material of the wide bandgap N-type doped substrate 4 is SiC.

[0104] The specific production process is as follows:

[0105] 1) Grow an N-type doped drift region 5 on a wide bandgap semiconductor material (SiC / GaN / Ga2O3 / C / AlN, etc.) substrate, such as Figure 2 As shown;

[0106] 2) Form a P-type doped buried layer 6 by ion implantation, epitaxy, growth of P-type oxide, etc. Figure 3 As shown;

[0107] 3) Forming an N-type doped current diffusion layer 7 by epitaxy, such as Figure 4As shown;

[0108] 4) Form a P-type doped main junction region 8 by ion implantation, epitaxy, growth of P-type oxide, etc. Figure 5 As shown;

[0109] 5) Form the terminal of the auxiliary trench 15 by dry etching and (or) wet etching, such as Figure 6 As shown;

[0110] 6) Forming a first insulating dielectric layer 11 by deposition or thermal oxidation, such as Figure 7 As shown;

[0111] 7) Forming a second insulating dielectric layer 12 by deposition or coating, exposure and development, etc. Figure 8 As shown;

[0112] 8) The first insulating dielectric layer 11 is etched, and the anode 9 metal is deposited and etched, such as Figure 9 As shown;

[0113] 9) Depositing the third insulating dielectric layer 13 and the fourth insulating dielectric layer 14, etching the third insulating dielectric layer 13 and the fourth insulating dielectric layer 14, and depositing the back metal (cathode metal), finally forming Figure 1 A semiconductor terminal structure is shown.

[0114] Regarding technical defect 1: This structure etches an intermediate trench and no less than one side trench in the P-type doped main junction region 8, the N-type doped current diffusion layer 7 and the P-type doped buried layer 6; the deepest part of the intermediate trench needs to exceed the P-type doped buried layer 6, and the intermediate trench needs to etch through the P-type doped buried layer 6; the main trench and the secondary trench 15 can gradually reduce the spacing between the side trenches in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2, and / or gradually increase the volume, or gradually increase the doping concentration of the N-type doped charge compensation region that replaces the side trench, or gradually reduce the equivalent acceptor impurity atomic weight of the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting road 3 region to the terminal region 2 through other forms.

[0115] This structure is formed by at least one trench on the left side of the terminal near the anode 9 (main junction region 1), or an N-type doped charge compensation region with gradually increasing doping concentration instead of the side trench, and a P-type doped buried layer 6 with gradually decreasing equivalent doping concentration in the direction away from the main junction region 1. It can reduce the curvature effect of the main junction region 1, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device, thereby solving technical defect 1.

[0116] In order to more intuitively demonstrate the effect of this structure, the protection effect of the left side structure of the patent terminal on the main junction is demonstrated by simulation software, such as Figures 10 to 13shown.

[0117] From the breakdown characteristic curve, it can be seen that the terminal structure of this patent achieves a withstand voltage of more than 1500V on an 11um SiC epitaxial layer, and the main trench, at least one side trench 152 and the middle trench 151 play a role in dispersing the potential and electric field strength distribution, avoiding the problem of premature breakdown caused by excessive concentration of the electric field at the edge of the main junction.

[0118] Regarding technical defect 2: This structure is formed by the middle trench near the cutting path 3 area on the right side of the terminal area 2, at least one side trench, or an N-type doped charge compensation area that replaces the side trench and has a gradually increasing doping concentration, and the P-type doped buried layer 6 with an equivalent doping concentration that gradually decreases in the direction away from the cutting path 3 area can reduce the curvature effect of the cutting path 3 area, alleviate the electric field concentration problem near the cutting path 3, and prevent the cutting path 3 area from breaking down prematurely after the surface of the cutting path 3 is short-circuited with the anode 9 metal (the front electrode of the device), so as to solve technical defect 2.

[0119] Regarding technical defect 3: in the blocking state of the device, the P-type doped buried layer 6 can play a role in isolating the cathode 10 (the back electrode of the device) potential and leakage current.

[0120] Regarding technical defect 4: a multi-layer insulating dielectric is set above the trench terminal, including a second insulating dielectric layer 12. The function of this dielectric layer is to fill the trench, reduce the height difference of the device surface, prevent the metal layer or passivation layer from cracking at the step 16, and ensure the long-term reliability of the device in high temperature and high humidity environments. The material used for this dielectric layer needs to have good hole-filling ability, such as PI glue or other organic matter.

[0121] Example 2

[0122] Example 2 is basically the same as Example 1, except that Figure 14 As shown, unlike the groove structure on both sides of the middle groove 151 in Example 1, Example 2 replaces the side grooves 152 on both sides of Example 1 with a step structure that becomes wider as it approaches the middle step 16, thereby achieving the effect of gradually reducing the equivalent acceptor impurity atomic weight of the P-type doped buried layer 6 in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting road 3 area to the terminal area 2, ultimately reducing the curvature effect of the main junction area 1, alleviating the problem of electric field concentration near the main junction, and avoiding the problem of premature breakdown of the main junction of the power device.

[0123] Example 3

[0124] Example 3 is basically the same as Example 1, except that Figure 15As shown, unlike the solution of etching side trenches 152 in Example 1, Example 3 replaces the side trenches 152 on both sides of Example 1 with N-type doped charge compensation regions 17 with the same width but with a smaller spacing closer to the middle trench 151. The doping element of the N-type doped charge compensation region 17 is nitrogen.

[0125] Example 3 achieves the effect of gradually reducing the equivalent acceptor impurity atomic weight of the P-type doped buried layer 6 in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting street 3 area to the terminal area 2 by means of injecting N-type doping impurities, thereby ultimately reducing the curvature effect of the main junction area 1, alleviating the problem of electric field concentration near the main junction, and avoiding the problem of premature breakdown of the main junction of the power device.

[0126] Example 4

[0127] Example 4 is substantially the same as Example 1, except that Figure 16 As shown, unlike Example 1 in which the N-type doped current diffusion layer 7 is located below the P-type doped main junction region 8, the depth of the P-type doped main junction region 8 in Example 4 is increased until it completely replaces the N-type doped current diffusion layer 7 and penetrates deep into the P-type doped buried layer, so that the P-type doped main junction region 8 and the P-type doped buried layer 6 are connected.

[0128] Example 5

[0129] Example 5 is basically the same as Example 1, except that Figure 17 As shown, unlike the first embodiment in which the third insulating dielectric layer 13 is located above the N-type doped current diffusion layer 7 , the fifth embodiment adds a P-type doped main junction region 8 between the N-type doped current diffusion layer 7 and the third insulating dielectric layer 13 .

[0130] By providing the P-type doped main junction region 8 in the cutting street 3 region, the risk of breakdown in the cutting street 3 region is further reduced.

[0131] Example 6

[0132] Example 6 is basically the same as Example 1, except that Figure 18 As shown, unlike Example 1, where the side grooves 152 on both sides have the same width but are deeper as they get closer to the middle groove 151 , Example 6 has the same depth on both sides but is wider as it gets closer to the middle groove 151 .

[0133] By gradually increasing the width of the side trench in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2, the area of ​​the P-type doped buried layer 6 in the direction from the main junction region 1 to the terminal region 2 and in the direction from the cutting path 3 region to the terminal region 2 tends to decrease (that is, the equivalent acceptor impurity atomic weight gradually decreases in this direction).

[0134] Example 7

[0135] Example 7 is substantially the same as Example 1, except that Figure 19 As shown, unlike the trench structure on both sides of the middle trench 151 in Example 1, Example 7 replaces the middle trench 151 and the side trench 152 with an inverted trapezoidal structure inclined toward the N-type doped drift region 5, so that the two sides are inclined surfaces 18, the inclined surfaces extend into the N-type doped drift region, and the bottom surface of the inverted trapezoidal structure is located in the N-type doped drift region 5.

[0136] By adopting a gradually decreasing slope in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting path 3 area to the terminal area 2, the equivalent acceptor impurity atomic weight of the P-type doped buried layer 6 is gradually reduced in the direction from the main junction area 1 to the terminal area 2 and in the direction from the cutting path 3 area to the terminal area 2.

[0137] Example 8

[0138] Example 8 is basically the same as Example 1, except that Figure 20 As shown, the semiconductor material in Example 1 is subjected to the opposite type of doping, such as changing N-type doping to P-type doping, or vice versa, and the same is applicable and falls within the scope of protection of this patent application. Specifically, the wide bandgap N-type doped substrate 4 is changed to a wide bandgap P-type doped substrate 19, the N-type doped drift region 5 is changed to a P-type doped drift region 20, the P-type doped buried layer 6 is changed to an N-type doped buried layer 21, the N-type doped current diffusion layer 7 is changed to a P-type doped current diffusion layer 22, and the P-type doped main junction region 8 is changed to an N-type doped main junction region 231.

[0139] Example 9

[0140] Example 9 is basically the same as Example 1, except that the terminal structures on the left and right sides of the middle trench 151 are different, that is, the terminal protection structure for the main junction region 1 and the terminal protection structure for the cutting street 3 can be freely combined.

[0141] Example 10

[0142] The semiconductor material used in the present invention takes SiC as an example, and the semiconductor material in the present invention can also be replaced by other semiconductor materials, such as Si, GaN, Ga2O3, AlN, diamond (C), etc.

[0143] The present invention has the following advantages:

[0144] 1. This structure involves etching a middle trench and multiple side trenches in a P-type doped main junction region, an N-type doped current diffusion layer, and a P-type doped buried layer. The deepest part of the middle trench needs to exceed the P-type doped buried layer, i.e., at least one trench needs to penetrate the P-type doped buried layer. The trench terminals can be achieved by gradually reducing the spacing between the side trenches in the direction from the main junction region to the terminal region or from the cutting path region to the terminal region, and / or gradually increasing the volume, or gradually increasing the doping concentration of the N-type doped charge compensation region that replaces the side trenches, or by other means to gradually reduce the equivalent acceptor impurity atomic weight of the P-type doped buried layer in the direction from the main junction region to the terminal region or from the cutting path region to the terminal region. The gradual increase in volume includes gradually increasing the width of the side trenches, and / or gradually increasing the depth of the side trenches, and / or gradually increasing the thickness of the side trenches.

[0145] This structure forms a P-type doped buried layer on the left side of the terminal near the anode (main junction region) in the middle trench and at least one side trench, with the equivalent doping concentration gradually decreasing in the direction away from the main junction region. This can reduce the curvature effect of the main junction region, alleviate the problem of electric field concentration near the main junction, and avoid the problem of premature breakdown of the main junction of the power device.

[0146] 2. In this structure, a P-type doped buried layer with an equivalent doping concentration gradually decreasing in the direction away from the cutting street area is formed by the middle trench and at least one side trench near the cutting street area on the right side of the terminal area, or an N-type doped charge compensation area that replaces the side trench and has a gradually increasing doping concentration, and can reduce the curvature effect of the electric field in the cutting street area, alleviate the problem of electric field concentration near the cutting street, and prevent the cutting street area from breaking down prematurely after the cutting street surface is short-circuited with the anode metal (front electrode of the device).

[0147] 3. In the blocking state of the device, the P-type doped buried layer can block the cathode (device back electrode) potential and leakage current.

[0148] 4. Set up multiple layers of insulating dielectrics above the trench, including the second insulating dielectric layer. The function of this dielectric layer is to fill the trench, reduce the height difference of the device surface, prevent the metal layer or passivation layer from cracking at the step position, and ensure the long-term reliability of the device in high temperature and high humidity environments. The material used for this dielectric layer needs to have good hole-filling ability, such as PI glue or other organic matter.

[0149] 5. The trench that spans the P-type doped main junction region, the N-type doped current diffusion layer, the P-type doped buried layer and extends deep into the N-type doped drift region can act as a (field) stop ring.

[0150] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A semiconductor device terminal structure, characterized in that: The terminal structure includes a wide bandgap N-type doped substrate, an N-type doped drift region, a P-type doped buried layer, and an N-type doped current diffusion layer connected in sequence from bottom to top; The side of the N-type doped current diffusion layer away from the P-type doped buried layer is connected to the P-type doped main junction region and the anode in sequence from bottom to top, and the side of the N-type doped substrate away from the P-type doped buried layer is connected to the cathode. The end of the terminal structure close to the anode forms the main junction region, the end away from the anode is the cutting path, and the middle is the terminal region; Etching the upper portion of the terminal region into a trench terminal including a main trench and a sub-trench, wherein the main trench crosses the P-type doped main junction region and penetrates into the N-type doped current diffusion layer, and etching a sub-trench at the bottom of the main trench, wherein the sub-trench includes a middle trench that penetrates the P-type doped buried layer and at least one side trench on both sides that does not penetrate the P-type doped buried layer; The middle trench passes through the P-type doped buried layer, and the bottom is located in the N-type doped drift region. The side trenches on both sides are arranged such that the spacing between the side trenches gradually decreases and / or the volume gradually increases in the direction from the main junction region to the terminal region and in the direction from the cutting street region to the terminal region, so that the equivalent doping concentration of the P-type doped buried layer in the direction from the main junction region to the terminal region and in the direction from the cutting street region to the terminal region shows a trend of gradually decreasing. The gradual increase in volume includes a gradual increase in the width of the side grooves, and / or a gradual increase in the depth of the side grooves, and / or a gradual increase in the thickness of the side grooves.

2. A semiconductor device terminal structure according to claim 1, characterized in that: The inner sidewalls of the secondary trench and the main trench are connected to the first insulating dielectric layer, the space below the highest point in the secondary trench and the main trench is filled with the second insulating dielectric layer, the third insulating dielectric layer is connected above the second insulating dielectric layer, one end of the third insulating dielectric layer is connected to the anode, and the other end covers the N-type doped current diffusion layer, and the fourth insulating dielectric layer is connected above the third insulating dielectric layer.

3. A semiconductor device terminal structure according to claim 2, characterized in that: The first insulating dielectric layer is silicon dioxide; and / or The second insulating medium layer is PI glue; and / or The third insulating dielectric layer is silicon nitride; and / or The fourth insulating dielectric layer is silicon dioxide.

4. A semiconductor device terminal structure according to claim 1, characterized in that: The material of the wide bandgap N-type doped substrate is SiC, GaN, Ga2O3, C or AlN.

5. A semiconductor device terminal structure according to claim 1, characterized in that: The doping types of the main junction region, the terminal region, and the cutting path region are: N-type is converted to P-type, and P-type is converted to N-type.

6. A semiconductor device terminal structure according to claim 1, characterized in that: The doping element of the N-type doped drift region is nitrogen; the doping element of the P-type doped buried layer is aluminum or boron; the doping element of the N-type doped current diffusion layer is nitrogen; and the doping element of the P-type doped main junction region is aluminum or boron.

7. A semiconductor device terminal structure according to claim 1, characterized in that: The side grooves on both sides are replaced with a step structure with a larger step width as it approaches the middle groove; or The side trenches on both sides are replaced by N-type doped charge compensation regions of the same size with decreasing spacing from the main junction region to the terminal region and from the cutting street region to the terminal region, wherein the doping element of the N-type doped charge compensation regions is nitrogen; or The depth of the P-type doped main junction region increases to completely replace the N-type doped current diffusion layer and penetrates deep into the P-type doped buried layer; or connecting a P-type doped main junction region between the N-type doped current diffusion layer and the third insulating dielectric layer in the cutting street region; or The terminal structures on the left and right sides of the middle groove are different; or The middle trench and the side trench are replaced with an inverted trapezoidal structure tilted toward the N-type doped drift region, with both sides being inclined surfaces that extend into the N-type doped drift region, and the bottom surface of the inverted trapezoidal structure is located in the N-type doped drift region.

8. The method for preparing a semiconductor device terminal structure according to any one of claims 1 to 7, wherein: The following steps are involved: growing an N-type doped drift region on a wide bandgap N-type doped substrate; forming a P-type doped buried layer by ion implantation, epitaxy or growth of a P-type oxide; forming an N-type doped current diffusion layer by epitaxy; forming a P-type doped main junction region by ion implantation, epitaxy or growth of a P-type oxide; forming trench terminations by dry etching and / or wet etching; forming a first insulating dielectric layer by deposition or thermal oxidation; The second insulating dielectric layer is formed by deposition or coating, exposure and development.

9. The method for preparing a semiconductor device terminal structure according to claim 8, wherein: The following steps are also included: Etching of the first insulating dielectric layer, deposition and etching of the anode metal; A third insulating dielectric layer and a fourth insulating dielectric layer are deposited, the third insulating dielectric layer and the fourth insulating dielectric layer are etched, and a cathode metal is deposited.

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