Enhanced MOSHEMT device with groove gate wrapped by ultrahigh K dielectric and preparation method of enhanced MOSHEMT device

Abstract

The invention discloses an enhanced MOSHEMT (Metal-Oxide-Semiconductor High Electron Mobility Transistor) device with an ultrahigh K dielectric wrapped groove gate, which structurally comprises a substrate, a buffer layer, a channel layer and a barrier layer in sequence, a source electrode and a drain electrode are respectively arranged on two sides of the barrier layer, a groove is arranged in the middle of the barrier layer close to the source electrode, a passivation layer is arranged in the area of the barrier layer except for the source electrode and the drain electrode, and a metal oxide semiconductor layer is arranged on the passivation layer. An ultrahigh K gate dielectric layer is arranged on the passivation layer, a groove gate is arranged above the ultrahigh K gate dielectric layer corresponding to the groove of the barrier layer, and an ultrahigh K dielectric layer is further arranged to cover the groove gate. The invention also discloses a preparation method. The enhanced HEMT device with high threshold voltage and high transconductance is realized by introducing a high-quality ultra-high K medium and utilizing polarization charges generated by the high-quality ultra-high K medium to assist depletion and accumulation of 2DEG under a gate; after the gate metal is deposited, the ultra-high K dielectric layer is secondarily covered to form a wrapped groove gate, a peak electric field can be effectively reduced by utilizing polarization charges, close to a drain end region, of the gate edge, and high breakdown voltage is achieved.

Description

Technical Field

[0001] The invention relates to an enhanced MOSHEMT device with an ultra-high-K dielectric wrapped groove gate and a preparation method thereof, belonging to the technical field of semiconductor devices. Background Art

[0002] AlGaN / GaN HEMT has a high breakdown electric field and excellent transmission characteristics, which makes it have great application prospects in high-voltage power switching devices. The presence of 2DEG makes the traditional AlGaN / GaN MISHEMT device a depletion-mode device (normally open). In order to reduce circuit loss, simplify the design of the drive circuit and consider circuit safety, etching is used to thin the AlGaN barrier layer under the gate and deplete the 2DEG in the channel under the gate, which becomes the main means to achieve an enhancement-mode device (normally off). However, the groove etching process will inevitably cause surface damage to the AlGaN barrier layer, resulting in increased gate leakage current, unstable threshold and other problems. Common gate dielectrics such as SiO2, SiN x etc. can reduce gate leakage and increase gate voltage swing, but the dielectric constants of these gate dielectrics are small, which makes the gate control ability of the device weak. The introduction of traditional high-K dielectrics such as Al2O3 and HfO2 can effectively regulate the channel and reduce transconductance loss, but it inevitably introduces the complexity of new interfaces. And due to the limitation of dielectric constant (<100), it is impossible to generate residual polarization charge to assist the depletion and accumulation of 2DEG, and it is even more impossible to solve the problem of premature breakdown of the device caused by the peak electric field at the edge of the gate. Therefore, the introduction of ultra-high K dielectrics (>100) and ensuring the quality of the gate dielectric / GaN interface are the main focuses of current research. At the same time, it is also of great significance to realize enhanced HEMT devices with high transconductance and high threshold voltage while ensuring the output current. Summary of the invention

[0003] The object of the present invention is to provide an enhanced MOSHEMT device with an ultra-high-K dielectric wrapped groove gate, which has the performance of high transconductance and high threshold voltage while obtaining a large output current.

[0004] The technical solution adopted by the present invention is:

[0005] An enhanced MOSHEMT device with an ultra-high-K dielectric wrapped groove gate, the structure of which comprises: a substrate, a buffer layer, a channel layer and a barrier layer in sequence, a source electrode and a drain electrode are respectively arranged on both sides of the barrier layer, a groove is arranged in the middle of the barrier layer near the source electrode, a passivation layer is arranged in the area of ​​the barrier layer other than the source electrode and the drain electrode, an ultra-high-K gate dielectric layer is arranged on the passivation layer, a groove gate electrode is arranged above the groove of the barrier layer corresponding to the ultra-high-K gate dielectric layer, and an ultra-high-K dielectric layer is also arranged to cover the groove gate electrode.

[0006] Preferably, the dielectric constant of the ultra-high K gate dielectric layer and the ultra-high K dielectric layer is above 100, the material is selected from barium titanate, lead titanate, strontium titanate, and barium strontium titanate, and the thickness is 20-50 nm.

[0007] Preferably, the barrier layer is Al 0.25 Ga 0.75 N, the thickness is 15nm, and the depth of the groove is 9.5nm.

[0008] Preferably, the passivation layer is Al2O 3、 HfO2 or Y2O3, thickness is 1-2nm.

[0009] Preferably, the substrate is a silicon substrate, SiC or sapphire substrate.

[0010] Preferably, the buffer layer is a C-doped GaN buffer layer with a thickness of 4-5 um.

[0011] Preferably, the channel layer is unintentionally doped n-type GaN with a thickness of 300-1000 nm.

[0012] Preferably, the source and drain are Ti / Al / Ni / Au multilayer metals with a thickness of 20 / 120 / 50 / 100 nm, and the gate is Ni / Au two-layer metal with a thickness of 50 / 100 nm.

[0013] The present invention also discloses a method for preparing the above-mentioned enhanced MOSHEMT device, the steps of which include:

[0014] (1) cleaning an epitaxial wafer, wherein the epitaxial wafer includes a buffer layer, a channel layer, and a barrier layer grown sequentially on a substrate;

[0015] (2) Photolithography is performed on the surface of the epitaxial wafer to form source and drain electrode patterns, followed by metal evaporation and annealing to form ohmic contact source and drain electrodes;

[0016] (3) performing photolithography on the surface of the epitaxial wafer to form a mesa isolation pattern;

[0017] (4) performing photolithography on the surface of the barrier layer near the source region to form a groove;

[0018] (5) depositing a passivation layer on the surface of the barrier layer;

[0019] (6) depositing an ultra-high-K gate dielectric layer on the surface of the passivation layer;

[0020] (7) evaporating metal in an area on the surface of the ultra-high-K gate dielectric layer corresponding to the groove of the barrier layer to form a groove gate;

[0021] (8) Growing an ultra-high-K dielectric layer on the surface of the ultra-high-K gate dielectric layer to cover the recessed gate.

[0022] Preferably, in step (4), after the grooves are formed by photolithography, the device is placed in a PECVD chamber to use N2O / N2 plasma to oxidize the Cl-based etching byproducts on the surface of the barrier layer, and immersed in a dilute hydrochloric acid solution to remove the oxide, and finally annealed in a N2 atmosphere to repair the surface damage caused by plasma bombardment.

[0023] Beneficial effects of the present invention:

[0024] 1. Compared with the traditional aluminum oxide dielectric, the present invention uses ultra-high K material as the gate dielectric, which can significantly increase the threshold voltage V of the groove gate device. TH (BaTiO3)~1.67V(V TH (Al2O3)~-0.36V), and while realizing an enhancement mode device, it ensures high output current and high transconductance (increased by ~60%).

[0025] 2. The present invention combines N2O plasma and thermal annealing to treat the groove surface, utilizes the Cl-based byproducts generated by N2O plasma oxidation etching interface, and combines thermal annealing to repair the damage caused by plasma bombardment, thereby significantly improving the interface quality and increasing the device output current.

[0026] 3. The present invention adopts ultra-high K material as the gate dielectric. The larger dielectric discontinuity makes the gate dielectric have a lower electric field, thereby reducing the generation of gate tunneling current, and using the polarized charge generated by it to assist the depletion and accumulation of the 2DEG under the gate, thereby realizing an enhanced HEMT device with high threshold voltage and high transconductance.

[0027] 4. The present invention deposits an ultra-thin Al2O3 passivation layer before introducing the ultra-high K dielectric to improve the device interface quality, avoid the influence of the complexity of the new interface on the device performance, and effectively reduce the gate leakage.

[0028] 5. The present invention covers the ultra-high K dielectric layer for a second time after the gate metal is deposited to form a wrapped groove gate structure. The synergistic effect of the two can not only utilize the negatively polarized bound charges induced by the BaTiO3 / AlGaN interface to compensate the positive charges in the depletion region to make the electric field distribution more uniform, but also utilize the polarized charges at the gate edge close to the drain region to effectively reduce the peak electric field and achieve a high breakdown voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram of the cross-sectional structure of an enhancement-mode MOSHEMT device with an ultra-high-K dielectric-wrapped recessed gate according to Example 1.

[0030] Figure 2 This is a schematic diagram of the cross-sectional structure of a recessed gate MOS HEMT device using Al2O3 as the gate dielectric in Comparative Example 1.

[0031] Figure 3 Schematic diagram of the cross-sectional structure of a MOSHEMT device with an ultra-high-K dielectric wrapped gate according to comparative example 2. DETAILED DESCRIPTION

[0032] The present invention is further described below in conjunction with embodiments, but the description of the embodiments does not impose any limitation on the protection scope of the present invention.

[0033] Unless otherwise defined, all technical terms and scientific terms used herein have the same meaning as those generally understood by those skilled in the art of the technical field of the present invention, and the terms used in the specification of the present invention herein are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. In addition, although a demonstration of parameters containing specific values ​​may be provided herein, it should be understood that the parameters do not need to be exactly equal to the corresponding values, but can be approximated to the corresponding values ​​within an acceptable error tolerance or design constraint. The directional terms mentioned in the embodiments, such as "up", "down", "front", "back", "left", "right", etc., are only with reference to the directions of the accompanying drawings. Therefore, the directional terms used are used to illustrate rather than to limit the scope of protection of the present invention.

[0034] Unless otherwise specified, the materials and instruments used in the following examples can be obtained from conventional commercial channels.

[0035] Example 1

[0036] This embodiment provides an enhancement mode MOSHEMT device with an ultra-high-K dielectric wrapped recessed gate and a method for manufacturing the same. Figure 1 As shown, the device structure includes a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a source 5, a drain 6, a passivation layer 7, an ultra-high K gate dielectric layer 8, a recessed gate 9 and an ultra-high K dielectric layer 10. The source and drain are located on both sides of the barrier layer, and the recessed gate is located on the side close to the source. The process flow includes the following steps:

[0037] (1) MOCVD was used to grow an epitaxial stack on a silicon substrate, including a ~4μm GaN buffer layer, a ~300nm GaN channel layer, and a 15nm AlGaN barrier layer. The epitaxial wafer was ultrasonically cleaned in acetone, alcohol, and deionized water for 5 minutes to remove organic pollutants on the surface of the epitaxial wafer, and finally the sample surface was dried with high-purity nitrogen.

[0038] (2) The surface of the epitaxial wafer is photolithographically processed to form source and drain electrode patterns. The photoresist is used as a mask to remove the residual photoresist in the pattern area in an RIE chamber for 30 seconds, and then the wafer is immersed in a BOE solution for 2 minutes to remove the surface oxide.

[0039] (3) Ti / Al / Ni / Au multilayer metals with a thickness of 20 / 120 / 50 / 100 nm were deposited on the epitaxial stack using an electron beam evaporation process, and then peeled off using acetone to form source and drain electrodes. Finally, the source and drain electrodes were rapidly annealed in a N2 atmosphere at 850°C for 30 seconds to form an ohmic contact with the channel layer.

[0040] (4) The surface of the substrate is photolithographically processed to form a mesa isolation pattern, and the mesa isolation is performed on the left and right sides of the source and drain electrodes by ICP dry etching, with a depth of ∼500 nm.

[0041] (5) A groove gate processing area is formed by photolithography on the surface of the barrier layer near the source region, and ICP slow etching is used to remove part of the AlGaN barrier layer with an etching depth of about 9.5 nm. Then, N2O / N2 plasma is used in a PECVD chamber to oxidize the Cl-based etching byproducts on the surface of the barrier layer. The gas flow rate is 50 / 100 sccm, the pressure is 600 mTorr, and the power is 18 W. The layer is immersed in a diluted HCl solution for 2 min to remove the oxide. Finally, the layer is annealed in a N2 atmosphere at 400 °C for 5 min to repair the surface damage caused by plasma bombardment.

[0042] (6) ALD technology is used to deposit a ~2 nm Al2O3 passivation layer on the surface of the barrier layer to reduce the induced damage and complex interface caused by the direct deposition of the ultra-high K gate dielectric on the surface of the barrier layer. Subsequently, a magnetron sputtering method is used to deposit ~20 nm of ultra-high K gate dielectric BaTiO3 on the surface of the passivation layer outside the source and drain electrodes, and rapid annealing is performed in an O2 atmosphere at 450°C for 5 minutes to prepare a high-quality gate dielectric layer.

[0043] (7) Electron beam evaporation is used to deposit two layers of Ni / Au metal with a thickness of 50 / 100 nm on the surface of the gate dielectric in the recessed gate region, and then acetone is used for stripping to form a gate electrode, which extends into the AlGaN barrier layer.

[0044] (8) The above substrate is subjected to photolithography to form a photoresist mask in the metal electrode pad area, and then a thin film of 30 nm is deposited on the substrate surface to wrap the recessed gate electrode using the ultra-high K dielectric preparation process in step 6. Finally, acetone is used for stripping to remove the gate dielectric layer in the pad electrode area.

[0045] After the above process steps, an enhancement-mode MOSHEMT device with an ultra-high-K dielectric wrapped recessed gate was successfully fabricated.

[0046] Comparative Example 1

[0047] A method for preparing a recessed gate MOSHEMT device using Al2O3 as a gate dielectric, such as Figure 2As shown, the device structure includes a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a source 5, a drain 6, an Al2O3 gate dielectric layer 7 and a recessed gate 8. The source and drain are located on both sides of the barrier layer, and the recessed gate is located on the side close to the source. The process flow includes the following steps:

[0048] (1) MOCVD was used to grow an epitaxial stack on a silicon substrate 1, including a ~4 μm GaN buffer layer 2, a ~300 nm GaN channel layer 3, and a 15 nm AlGaN barrier layer 4. The epitaxial wafer was ultrasonically cleaned in acetone, alcohol, and deionized water for 5 min in turn to remove organic pollutants on the surface of the epitaxial wafer, and finally the sample surface was dried with high-purity nitrogen.

[0049] (2) The surface of the epitaxial wafer is photolithographically processed to form source and drain electrode patterns. The residual photoresist in the pattern area is removed in an RIE chamber for 30 seconds using the photoresist as a mask. The wafer is then immersed in a BOE solution for 2 minutes to remove surface oxides.

[0050] (3) Ti / Al / Ni / Au multilayer metals were deposited on the epitaxial wafer using an electron beam evaporation process with a thickness of 20 / 120 / 50 / 100 nm, and then stripped using acetone to form source and drain electrodes. Finally, the wafer was rapidly annealed in a N2 atmosphere at 850°C for 30 seconds to form an ohmic contact with the channel layer.

[0051] (4) The surface of the substrate is photolithographically processed to form a mesa isolation pattern, and the mesa isolation is performed on the left and right sides of the source and drain electrodes by ICP dry etching, with a depth of 500 nm.

[0052] (5) A recessed gate processing area is formed by photolithography on the surface of the barrier layer near the source region, and a portion of the AlGaN barrier layer (~9.5 nm) is removed by ICP slow etching. Then, the Cl-based etching byproducts on the surface of the barrier layer are oxidized by N2O / N2 plasma in a PECVD chamber, and the oxide is removed by immersion in a diluted HCl solution for 2 min. Finally, the surface damage caused by plasma bombardment is repaired by annealing in a N2 atmosphere at 400°C for 5 min.

[0053] (6) ALD technology is used to deposit a traditional high-K gate dielectric layer (Al2O3) of ~12nm on the surface of the barrier layer.

[0054] (7) Electron beam evaporation is used to deposit two layers of Ni / Au metal on the surface of the gate dielectric in the groove gate area with a thickness of 50 / 100 nm, and then acetone is used for stripping to form a gate electrode.

[0055] After the above process steps, a comparative sample of a recessed gate MOSHEMT device using Al2O3 as a gate dielectric was successfully prepared.

[0056] Comparative Example 2

[0057] A MOSHEMT device with an ultra-high-K dielectric wrapped gate and a method for preparing the same, such as Figure 3 As shown, the device structure includes a substrate 1, a buffer layer 2, a channel layer 3, a barrier layer 4, a source 5, a drain 6, a passivation layer 7, an ultra-high K gate dielectric layer 8, a gate 9 and an ultra-high K dielectric layer 10. The source and drain are located on both sides of the barrier layer, and the gate is located on the side close to the source. The process flow includes the following steps:

[0058] (1) MOCVD was used to grow an epitaxial stack on a silicon substrate, including a ~4μm GaN buffer layer, a ~300nm GaN channel layer, and a 15nm AlGaN barrier layer. The epitaxial wafer was ultrasonically cleaned in acetone, alcohol, and deionized water for 5 minutes to remove organic pollutants on the surface of the epitaxial wafer, and finally the sample surface was dried with high-purity nitrogen.

[0059] (2) The surface of the epitaxial wafer is photolithographically processed to form source and drain electrode patterns. The photoresist is used as a mask to remove the residual photoresist in the pattern area in an RIE chamber for 30 seconds, and then the wafer is immersed in a BOE solution for 2 minutes to remove the surface oxide.

[0060] (3) Ti / Al / Ni / Au multilayer metals with a thickness of 20 / 120 / 50 / 100 nm were deposited on the epitaxial stack using an electron beam evaporation process, and then peeled off using acetone to form source and drain electrodes. Finally, the source and drain electrodes were rapidly annealed in a N2 atmosphere at 850°C for 30 seconds to form an ohmic contact with the channel layer.

[0061] (4) The surface of the substrate is photolithographically processed to form a mesa isolation pattern, and the mesa isolation is performed on the left and right sides of the source and drain electrodes by ICP dry etching, with a depth of ∼500 nm.

[0062] (5) ALD technology is used to deposit a ~2 nm Al2O3 passivation layer on the surface of the barrier layer to reduce the induced damage and complex interface caused by the direct deposition of the ultra-high K gate dielectric on the surface of the barrier layer. Subsequently, magnetron sputtering is used to deposit ~20 nm of ultra-high K gate dielectric BaTiO3 on the surface of the passivation layer outside the source and drain electrodes, and rapid annealing is performed in an O2 atmosphere at 450°C for 5 minutes to prepare a high-quality gate dielectric layer.

[0063] (6) A gate electrode region is formed by photolithography on the surface of the gate dielectric layer near the source region. Photoresist is used as a mask and two layers of Ni / Au metal are evaporated by electron beam evaporation process with a thickness of 50 / 100 nm. Then, acetone is used for stripping to form a gate electrode.

[0064] (7) The above substrate is subjected to photolithography to form a photoresist mask in the metal electrode pad area, and then a thin film of 30 nm is deposited on the surface of the substrate to wrap the gate electrode using the ultra-high K dielectric preparation process in step 5. Finally, acetone is used for stripping to remove the gate dielectric layer in the pad electrode area.

[0065] After the above process steps, a MOSHEMT device with an ultra-high-K dielectric wrapped gate was successfully prepared.

[0066] By simulating the device performance of Example 1 and Comparative Examples 1 and 2, it was found that after plasma and heat treatment, the surface roughness RMS was reduced from 0.8nm to 0.32nm. Compared with Comparative Example 1, the output current of Example 1 was increased by 10%, and the gate leakage was reduced by 2 orders of magnitude.

[0067] Example 1 threshold voltage 1.67V, transconductance 108.7mS / mm; Comparative Example 1 threshold voltage -0.36

[0068] V, transconductance 65.8mS / mm; comparative example 2 threshold voltage -2.94V, transconductance 133.7mS / mm.

[0069] After introducing the ultra-thin Al2O3 passivation layer, the reverse gate leakage is reduced by 1-2 orders of magnitude.

[0070] The breakdown voltage of the secondary covering ultra-high K dielectric layer is increased by 23%, and the breakdown voltage of Example 1 is increased by 52% compared with Comparative Example 1.

[0071] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any other changes, modifications, substitutions, combinations, and simplifications that do not deviate from the spirit and principle of the present invention shall be equivalent replacement methods and shall be included in the protection scope of the present invention. In order to better illustrate the embodiments, some parts in the drawings will be omitted or scaled, and do not represent the actual size of the device.

Claims

1. An enhancement-mode MOSHEMT device having an ultra-high-K dielectric wrapped recessed gate, characterized in that: Its structure includes: a substrate, a buffer layer, a channel layer and a barrier layer in sequence. A source and a drain are respectively arranged on both sides of the barrier layer. A groove is arranged in the middle of the barrier layer near the source. A passivation layer is arranged in the area of ​​the barrier layer other than the source and the drain. An ultra-high K gate dielectric layer is arranged on the passivation layer. A groove gate is arranged above the groove of the barrier layer corresponding to the ultra-high K gate dielectric layer. An ultra-high K dielectric layer is also arranged to cover the groove gate.

2. The enhancement mode MOSHEMT device according to claim 1, characterized in that: The dielectric constant of the ultra-high K gate dielectric layer and the ultra-high K dielectric layer is above 100, the material is selected from barium titanate, lead titanate, strontium titanate, and barium strontium titanate, and the thickness is 20-50nm.

3. The enhancement mode MOSHEMT device according to claim 2, characterized in that: The barrier layer is Al 0.25 Ga 0.75 N, the thickness is 15nm, and the depth of the groove is 9.5nm.

4. The enhancement mode MOSHEMT device according to any one of claims 1 to 3, characterized in that: The passivation layer is Al2O3, HfO2 or Y2O3, and has a thickness of 1-2nm.

5. The enhancement mode MOSHEMT device according to claim 4, characterized in that: The substrate is a silicon, SiC or sapphire substrate.

6. The enhancement mode MOSHEMT device according to claim 5, characterized in that: The buffer layer is a C-doped GaN buffer layer with a thickness of 4-5 um.

7. The enhancement mode MOSHEMT device according to claim 6, characterized in that: The channel layer is non-intentionally doped n-type GaN with a thickness of 300-1000nm.

8. The enhancement mode MOSHEMT device according to any one of claims 1 to 3, characterized in that: The source and drain are Ti / Al / Ni / Au multilayer metals with a thickness of 20 / 120 / 50 / 100 nm, and the gate is Ni / Au two-layer metal with a thickness of 50 / 100 nm.

9. The method for preparing an enhancement mode MOSHEMT device according to any one of claims 1 to 8, characterized in that: The steps include: (1) cleaning an epitaxial wafer, wherein the epitaxial wafer includes a buffer layer, a channel layer, and a barrier layer grown sequentially on a substrate; (2) Photolithography is performed on the surface of the epitaxial wafer to form source and drain electrode patterns, followed by metal evaporation and annealing to form ohmic contact source and drain electrodes; (3) performing photolithography on the surface of the epitaxial wafer to form a mesa isolation pattern; (4) performing photolithography on the surface of the barrier layer near the source region to form a groove; (5) depositing a passivation layer on the surface of the barrier layer; (6) depositing an ultra-high-K gate dielectric layer on the surface of the passivation layer; (7) evaporating metal in an area on the surface of the ultra-high-K gate dielectric layer corresponding to the groove of the barrier layer to form a groove gate; (8) Growing an ultra-high-K dielectric layer on the surface of the ultra-high-K gate dielectric layer to cover the recessed gate.

10. The method for preparing an enhancement mode MOSHEMT device according to claim 9, characterized in that: In step (4), after the grooves are formed by photolithography, the device is placed in a PECVD chamber and the Cl-based etching byproducts on the surface of the barrier layer are oxidized using N2O / N2 plasma, and then immersed in a dilute hydrochloric acid solution to remove the oxide, and finally annealed in a N2 atmosphere to repair the surface damage caused by plasma bombardment.

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