Method of forming semiconductor device

Abstract

The method includes forming a first lift-off structure over a first substrate, where forming the first lift-off structure includes: depositing a first lift-off layer over the first substrate; depositing a first silicon layer over the first release layer; depositing a second release layer over the first silicon layer; and depositing a second silicon layer over the second release layer; epitaxially growing a first multilayer stack over the first lift-off structure; bonding the first multilayer stack to the second multilayer stack; and performing a first laser annealing process to ablate the first silicon layer and portions of the first and second lift-off layers to lift off the first substrate from the first multilayer stack. The embodiment of the invention also relates to a method for forming the semiconductor device.

Description

Technical Field

[0001] Embodiments of the present application relate to methods of forming semiconductor devices. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

[0003] The semiconductor industry continues to improve the integration density of individual electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that should be addressed. Summary of the invention

[0004] Some embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first peeling structure above a first substrate, wherein forming the first peeling structure comprises: depositing a first peeling layer above the first substrate; depositing a first silicon layer above the first peeling layer; depositing a second peeling layer above the first silicon layer; and depositing a second silicon layer above the second peeling layer; epitaxially growing a first multilayer stack above the first peeling structure; bonding the first multilayer stack to a second multilayer stack; and performing a first laser annealing process to ablate the first silicon layer and portions of the first peeling layer and the second peeling layer to peel the first substrate from the first multilayer stack.

[0005] Some other embodiments of the present application provide a method for forming a semiconductor device, including: depositing a first peeling layer over a first substrate; depositing a first silicon layer over the first peeling layer; depositing a second peeling layer over the first silicon layer; depositing a second silicon layer over the second peeling layer; epitaxially growing a first semiconductor layer and a second semiconductor layer over the second silicon layer; epitaxially growing a third semiconductor layer and a fourth semiconductor layer over the second substrate; depositing a first bonding layer over the second semiconductor layer; depositing a second bonding layer over the fourth semiconductor layer; bonding the first bonding layer to the second bonding layer to form a bonding layer; and after bonding the first bonding layer to the second bonding layer, using a laser annealing process to ablate the first peeling layer, the first silicon layer and the second peeling layer to peel the first substrate from the second silicon layer, the first semiconductor layer and the second semiconductor layer.

[0006] Some other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a first peeling structure above a first substrate, wherein the first peeling structure includes a resonant cavity, and wherein the first peeling structure includes: a first peeling layer; a first semiconductor layer, located above the first peeling layer; and a second peeling layer, located above the first semiconductor layer; epitaxially growing a first multilayer stack above the first peeling structure; bonding the first multilayer stack to a second multilayer stack; and performing a first laser annealing process using a laser beam having a wavelength matching the resonant frequency of the resonant cavity to ablate the first semiconductor layer and portions of the first peeling layer and the second peeling layer, and wherein performing the first laser annealing process causes the first substrate to be peeled off from the first multilayer stack. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0008] Figure 1 An exemplary schematic diagram of stacked transistors, such as complementary field effect transistors (CFETs), in a three-dimensional view is shown in accordance with some embodiments.

[0009] Figures 2A to 11 Shown are varying views of an intermediate stage in the fabrication of a CFET according to some embodiments.

[0010] Figures 12 to 16 Variations of views of intermediate stages in the fabrication of a CFET according to other embodiments are shown.

[0011] Figures 17 to 20 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package in accordance with some embodiments. DETAILED DESCRIPTION

[0012] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0013] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0014] According to various embodiments, a stacked transistor, such as a CFET, is formed. The CFET includes an n-type nanostructure FET and a p-type nanostructure FET stacked vertically together. To form the CFET, a first superlattice (e.g., including an NFET channel region formed by a first semiconductor layer) is epitaxially grown over a first substrate (e.g., a first carrier wafer), and a second superlattice (e.g., including a PFET channel region formed by a second semiconductor layer) is epitaxially grown over a second substrate (e.g., a second carrier wafer). A peeling structure may be formed between the first substrate and the first superlattice or between the second substrate and the second superlattice. The first superlattice and the second superlattice are then joined together. The peeling structure may include a multilayer stack of alternating silicon layers and peeling layers formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The multilayer stack includes between 2 and 5 silicon layers and between 2 and 5 peeling layers. Each peeling layer may include germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), or the like. A laser annealing process may be performed to ablate portions of the lift-off structure to lift the first substrate from the first superlattice, or to lift the second substrate from the second superlattice.

[0015] Advantageous features of one or more embodiments disclosed herein may allow one or more resonant cavities to be formed in the lift-off structure that match the wavelength of the laser used during the laser annealing process. This allows an ablation threshold to be achieved within the lift-off structure, resulting in partial ablation of the lift-off structure. Ablation of a portion of the lift-off structure allows the first substrate to be lifted off from the first superlattice, or the second substrate to be lifted off from the second superlattice. This lift-off of the first substrate from the first superlattice or the lift-off of the second substrate from the second superlattice is achieved with minimal damage to the first substrate or the second substrate. In this way, the first substrate or the second substrate may be used for possible recycling and reuse (e.g., to form another CFET) in further semiconductor manufacturing operations. Thus, manufacturing costs may be reduced. In addition, using a multilayer stack of alternating silicon layers and lift-off layers formed using CVD or ALD to form a lift-off structure produces better film quality for the silicon layer and the lift-off layer, compared to if the silicon layer and the lift-off layer are formed using other processes (e.g., a plasma process that produces plasma damage to the silicon layer and the lift-off layer). Thus, the quality of the epitaxial layer of the first superlattice or the second superlattice formed above the lift-off structure is improved. In addition, the peeling structure includes materials selected based on their lattice parameters to achieve improved lattice matching with the first superlattice or the second superlattice. In this way, strain and defects at the interface between the first superlattice and the peeling structure or between the second superlattice and the peeling structure are reduced. This produces an improved bond between the first substrate and the first superlattice or between the second substrate and the second superlattice.

[0016] Figure 1 An example of a CFET schematic according to some embodiments is shown. Figure 1 is a three-dimensional view, in which some components of the CFET are omitted for clarity of illustration.

[0017] The CFET includes a plurality of vertically stacked nanostructure FETs (e.g., nanowire FETs, nanosheet FETs, multi-bridge channel (MBC) FETs, nanoribbon FETs, gate-all-around (GAA) FETs, etc.). For example, the CFET may include a lower nanostructure FET of a first device type (e.g., n-type / p-type) and an upper nanostructure FET of a second device type (e.g., p-type / n-type) opposite to the first device type. Specifically, the CFET may include a lower PMOS transistor and an upper NMOS transistor, or the CFET may include a lower NMOS transistor and an upper PMOS transistor. For simplicity, various embodiments may be described below in the context of manufacturing a CFET having a lower PMOS transistor and an upper NMOS transistor. However, it should be understood that various embodiments may also be applicable to a CFET having a lower NMOS transistor and an upper PMOS transistor.

[0018] Each of the nanostructure FETs includes a semiconductor nanostructure 66 (labeled as a lower semiconductor nanostructure 66L and an upper semiconductor nanostructure 66U), wherein the semiconductor nanostructure 66 serves as a channel region for the nanostructure FET. The semiconductor nanostructure 66 may be a nanosheet, a nanowire, etc. The lower semiconductor nanostructure 66L is used for the lower nanostructure FET, and the upper semiconductor nanostructure 66U is used for the upper nanostructure FET. A channel isolation material ( Figure 1 Not explicitly shown, see Fig.10 ) to separate and electrically isolate the upper semiconductor nanostructure 66U from the lower semiconductor nanostructure 66L.

[0019] The gate dielectric 130 is along the top surface, sidewalls and bottom surface of the semiconductor nanostructure 66. The gate electrode 134 (including the lower gate electrode 134L and the upper gate electrode 134U) is located above the gate dielectric 130 and around the semiconductor nanostructure 66. The source / drain region 108 (labeled as the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U) is disposed at opposite sides of the gate dielectric 130 and the gate electrode 134. The source / drain region 108 may refer to a source or a drain, individually or collectively depending on the context. Isolation features may be formed to separate the desired source / drain region 108 and / or the desired gate electrode 134. For example, the lower gate electrode 134L may be optionally separated from the upper gate electrode 134U. Optionally, the lower gate electrode 134L may be coupled to the upper gate electrode 134U. In addition, the upper epitaxial source / drain region 108U may be separated from the lower epitaxial source / drain region 108L by one or more dielectric layers ( Figure 1 Not explicitly shown, see Fig.11 ). Isolation features between the channel region, gate, and source / drain regions allow vertical stacking of transistors, thereby improving device density. Due to the vertical stacking nature of the CFET, the schematic diagram may also be referred to as a stacked transistor or a folded transistor.

[0020] Figure 1 Reference cross sections that may be used in subsequent figures are also shown. Cross section AA' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the CFET and in the direction of current flow, for example, between the source / drain regions 108 of the CFET. Cross section BB' is perpendicular to cross section AA' and along the longitudinal axis of the gate electrode 134 of the CFET. Cross section CC' is parallel to cross section BB' and extends through the source / drain regions 108 of the CFET. For clarity, subsequent figures may refer to these reference cross sections.

[0021] Figures 2A to 11 is a diagram of an intermediate stage in the fabrication of a CFET according to some embodiments.

[0022] Figure 2A , Figure 2B , Figure 3 , Figure 4 and Figure 7 is shown with Figure 1 Similar 3D views of the 3D view.

[0023] Figure 5 , Figure 6 , Figure 8 , Fig. 9 , Fig.10 and Fig.11 shows along with Figure 1 A cross-sectional view of a cross section similar to the reference cross section AA'.

[0024] exist Figure 2A and Figure 2B In the embodiment, two substrates 60L and 60U are provided respectively. Figure 2A A substrate 60L is shown, and Figure 2B Substrate 60U is shown. In a subsequent process, substrate 60U can be bonded onto substrate 60L (see Figure 3 ). Therefore, substrate 60L can be referred to as a lower substrate 60L, and substrate 60U can also be referred to as an upper substrate 60U. Each of substrates 60L and 60U can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. Substrates 60L and 60U can each be a wafer, such as a silicon wafer. Substrates 60L and 60U may also be subsequently referred to as carrier wafers. Typically, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on a substrate, which is typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrates 60L and 60U may include: silicon; germanium; compound semiconductors including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0025] refer to Figure 2B , forming a lift-off structure 50U over the substrate 60U. The lift-off structure 50U may include a multi-layer stack of alternating lift-off layers 51U and silicon layers 53U that may be formed using physical vapor deposition (PVD), plasma enhanced (ALD) PEALD, thermal ALD, microwave CVD (MWCVD), plasma enhanced CVD (PECVD), hybrid physical CVD (HPCVD), etc. Each lift-off layer 51U may include germanium (Ge), silicon germanium (e.g., Si 1-x Ge x, wherein x is in the range of from 0.7 to 1), silicon carbide (SiC), boron- or phosphorus-doped silicon, boron- or phosphorus-doped silicon germanium, yttrium oxide (Y 2 O 3 ), cerium oxide (CeO 2 ), boron nitride (BN), gallium phosphide (GaP), titanium nitride (TiN), etc. In an embodiment, the growth temperature during the formation of the peeling layer 51U is in a range from 100° C. to 1400° C. In an embodiment, the growth temperature during the formation of the peeling layer 51U is in a range from 400° C. to 800° C. In an embodiment, each peeling layer 51U may include a material having a crystal system that is cubic, hexagonal, tetragonal, orthorhombic, monoclinic, triclinic, etc. In an embodiment, the peeling layer 51U may include a material having a single crystal structure, a polycrystalline structure, an amorphous structure, etc.

[0026] Forming the peeling structure 50U may include forming a plurality of peeling stacks 55U over the substrate 60U. Each peeling stack 55U includes a peeling layer 51U and a corresponding silicon layer 53U over the peeling layer 51U. The peeling structure 50U may include 2 to 5 peeling stacks 55U. For example, Figure 2B In FIG. 5 , the peeling structure 50U is shown as including 2 peeling stacks 55U. In other embodiments, the peeling structure 50U may include up to 5 peeling stacks 55U. Figure 2B In the embodiment of the present invention, a first peeling layer 51U (e.g., also referred to as a bottom-most peeling layer) may be formed over a substrate 60U. A corresponding first silicon layer 53U (also referred to as a bottom-most silicon layer) is then formed over the first peeling layer 51U to form a first peeling stack 55U. More peeling stacks 55U (including pairs of peeling layers 51U and corresponding silicon layers 53U) are then formed over the first peeling stack 55U to form a peeling structure 50U. For example, in Figure 2B In the embodiment, a second peeling layer 51U (e.g., also referred to as the top peeling layer) and a corresponding second silicon layer 53U (e.g., also referred to as the top silicon layer) are then sequentially formed over the first peeling stack 55U to form a second peeling stack 55U. In an embodiment, the thickness T1 of each peeling layer 51U is in the range of 1 nm to 10 nm. In an embodiment, the thickness T2 of each silicon layer 53U may be in the range of 5 nm to 200 nm. In an embodiment, the top silicon layer (e.g., Figure 2B The thickness T3 of the second silicon layer 53U) is greater than 100 nm.

[0027] Return to reference Figure 2A and Figure 2B, a multilayer stack 52L (also referred to as a superlattice) and a multilayer stack 52U (also referred to as a superlattice) are formed over the substrate 60L and the substrate 60U, respectively. Specifically, the multilayer stack 52L is formed over and in contact with the substrate 60L, and the multilayer stack 52U is formed over and in contact with the peeling structure 50U. The multilayer stack 52L includes alternating dummy semiconductor layers 54L and semiconductor layers 56L, and the multilayer stack 52U includes alternating dummy semiconductor layers 54U and semiconductor layers 56U. The multilayer stacks 52U and 52L will subsequently be bonded together, and the dummy semiconductor layers 54L and the semiconductor layers 56L will be disposed under the dummy semiconductor layers 54U and the semiconductor layers 56U (see Figure 3 ). Therefore, layers 54L and 56L may also be referred to as lower dummy semiconductor layer 54L and lower semiconductor layer 56L, respectively, and layers 54U and 56U may also be referred to as upper dummy semiconductor layer 54U and upper semiconductor layer 56U, respectively. As described in more detail later, dummy semiconductor layers 54L and 54U will be removed, and semiconductor layers 56L and 56U will be patterned to form the channel region of the CFET. Specifically, lower semiconductor layer 56L will be patterned to form the channel region of the lower nanostructure FET of the CFET, and upper semiconductor layer 56U will be patterned to form the channel region of the upper nanostructure FET of the CFET.

[0028] The multilayer stacks 52L and 52U are each shown to include a specific number of dummy semiconductor layers 54L / 54U and semiconductor layers 56L / 56U. It should be understood that the multilayer stacks 52L and 52U can include any number of dummy semiconductor layers 54L / 54U and / or semiconductor layers 56L / 56U. Each layer of the multilayer stacks 52L and 52U can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc.

[0029] The dummy semiconductor layers 54U and 54L are formed of a first semiconductor material selected from the candidate semiconductor materials of the substrates 60U and 60L. The semiconductor layers 56U and 56L are formed of one or more second semiconductor materials. The second semiconductor material may be selected from the candidate semiconductor materials of the substrates 60U and 60L. The lower semiconductor layer 56L and the upper semiconductor layer 56U may be formed of the same semiconductor material, or may be formed of different semiconductor materials. In some embodiments, the lower semiconductor layer 56L and the upper semiconductor layer 56U are both formed of semiconductor materials suitable for p-type devices and n-type devices, such as silicon. In some embodiments, the lower semiconductor layer 56L is formed of a semiconductor material suitable for p-type devices, such as germanium or silicon germanium, and the upper semiconductor layer 56U is formed of a semiconductor material suitable for n-type devices, such as silicon or carbon-doped silicon.

[0030] The semiconductor material of the semiconductor layers 56U and 56L is different from the semiconductor material of the dummy semiconductor layers 54U and 54L, and has a high etching selectivity to the semiconductor material of the dummy semiconductor layers 54U and 54L. Therefore, in subsequent processing, the material of the dummy semiconductor layers 54U and 54L can be removed at a faster rate than the material of the semiconductor layers 56U and 56L. In some embodiments, the dummy semiconductor layers 54U and 54L are formed of silicon germanium, and the semiconductor layers 56U and 56L are formed of silicon. In this processing step, the silicon of the semiconductor layers 56U and 56L can be undoped or lightly doped.

[0031] Further references Figure 2A and Figure 2B , insulating bonding layers 58L and 58U are deposited on the multilayer stacks 52L and 52U, respectively. Figure 2A shows a perspective view of substrate 60L, multilayer stack 52L (including dummy semiconductor layer 54L and semiconductor layer 56L), and bonding layer 58L; and Figure 2B A perspective view of substrate 60U, peeling structure 50U, multilayer stack 52U (including dummy semiconductor layer 54U and semiconductor layer 56U), and bonding layer 58U are shown. Bonding layers 58L and 58U can be deposited by any suitable process, such as physical vapor deposition (PVD), CVD, ALD, etc. Bonding layers 58L and 58U can facilitate bonding of lower substrate 60L to upper substrate 60U in subsequent processes (see Figure 3 ). The bonding layers 58L and 58U may each include an insulating material suitable for a subsequent dielectric-to-dielectric bonding process. Exemplary materials for the bonding layers 58L and 58U include silicon oxide (e.g., SiO 2 ), silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon carbide, aluminum oxide, aluminum nitride, hafnium oxide, boron nitride, boron carbonitride, yttrium oxide, etc. The material composition of the bonding layer 58L may be the same as or different from the material composition of the bonding layer 58U. In an embodiment, each of the bonding layers 58L and 58U may have a thickness T4 in the range of from 0.5 nm to 50 nm.

[0032] exist Figure 3 In the embodiment, the upper substrate 60U on which the multilayer stack 52U is disposed is placed over and bonded to the lower substrate 60L on which the multilayer stack 52L is disposed to form the bonded structure 10. Figure 3As shown, the bonding structure 10 includes a lower substrate 60L; a lower multilayer stack 52L above the lower substrate 60L; bonding layers 58L and 58U above the lower multilayer stack 52L; an upper multilayer stack 52U above the bonding layers 58L and 58U; a peeling structure 50U above the multilayer stack 52U; and an upper substrate 60U above the peeling structure 50U. The upper substrate 60U can be bonded to the lower substrate 60L through the bonding layers 58L and 58U. Specifically, the bonding layers 58L and 58U can be bonded together using suitable techniques, such as dielectric to dielectric bonding, etc. The dielectric to dielectric bonding process may include surface treatment of one or more bonding surfaces of the bonding layer 58L or 58U. The surface treatment may include plasma treatment. After the surface treatment, the bonding layer 58U can be placed above the bonding layer 58L and aligned with the bonding layer 58L. Then, the two bonding layers 58L and 58U are pressed against each other to start the pre-bonding of the upper substrate 60U to the lower substrate 60L. The pre-bonding is performed at room temperature (e.g., in the range of 25°C to 26°C). After the pre-bonding, an annealing process can be applied by, for example, heating the substrates 60L and 60U to an elevated temperature. After bonding, the lower bonding layer 58L and the upper bonding layer 58U can be collectively referred to as a bonding layer 58. The bonding layer 58 may or may not have an interface where the bonding layer 58L and the bonding layer 58U meet.

[0033] exist Figure 4 In the embodiment, a laser annealing process 61 is performed using a laser to peel the upper substrate 60U from the topmost silicon layer (eg, the second silicon layer 53U), the multilayer stack 52U, and the rest of the bonded structure 10. The laser annealing process 61 includes Figure 3 A laser beam emitted from a laser is systematically moved (e.g., scanned) over the top surface of the bonding structure 10 shown in FIG. 1 (e.g., the top surface of the upper substrate 60U). In an embodiment, the laser may operate in the infrared region with a wavelength in the range of from 500 to 2500 nm. In an embodiment, the laser beam may have a power output in the range of from 500 mW to 5000 mW. In an embodiment, the laser may emit a pulse with a duration of picoseconds (1×10 -12 The laser beam may be able to penetrate the upper substrate 60U to reach the lift-off structure 50U.

[0034] The peeling structure 50U includes one or more resonant cavities 59. The resonant cavity 59 may be formed in each combination of the silicon layer 53U and the peeling layer 51U adjacent to (disposed above and below) the silicon layer 53U. Figure 4In the present invention, the resonance cavities 59 are formed in the first silicon layer 53U, the first peeling layer 51U, and the second peeling layer 51U. In this way, the number of resonance cavities 59 formed in the peeling structure 50U is equal to the number of silicon layers 53U having corresponding adjacent peeling layers 51U disposed above and below each of the silicon layers 53U.

[0035] During the laser annealing process 61, the laser interacts with each resonant cavity 59 in the silicon layer 53U and its corresponding adjacent peeling layer 51U. The wavelength of the laser beam emitted by the laser can be matched to the resonant frequency of the resonant cavity 59, and the resonant cavity 59 can capture the electromagnetic waves generated by the laser, allowing them to resonate back and forth within the resonant cavity 59. This resonance increases the energy density of the laser within the resonant cavity 59, which can produce more efficient heating during the laser annealing process 61. Therefore, an ablation threshold can be achieved within the peeling structure 50U, which allows for more efficient material removal (e.g., by ablation) of the silicon layer 53U and its corresponding adjacent peeling layer 51U. In this way, the upper substrate 60U is peeled away from the topmost silicon layer (e.g., the second silicon layer 53U), the multilayer stack 52U, and the rest of the bonded structure 10 (subsequently in Figure 5 ). It should be noted that no resonant cavity is formed in the topmost silicon layer (e.g., the second silicon layer 53U) of the lift-off structure 50U because it has only one lift-off layer 51U adjacent thereto. After the laser annealing process 61, the topmost silicon layer (e.g., the second silicon layer 53U) remains on the multilayer stack 52U. In an embodiment, the topmost silicon layer (e.g., the second silicon layer 53U) having a thickness T3 greater than 100 nm can help prevent destruction or damage to the multilayer stack 52U (also referred to as a superlattice) and the multilayer stack 52L (also referred to as a superlattice) during the laser annealing process 61.

[0036] Further references Figure 4 , the laser annealing process 61 is performed using a laser operating in the infrared region so that a void is generated at the interface between each silicon layer 53U and the adjacent peeling layer 51U disposed above and / or below the silicon layer 53U. Therefore, the bonding force between the silicon layer 53U and the adjacent peeling layer 51U is weakened without causing significant thermal effects or damage to the upper substrate 60U or the multilayer stack 52U. The generated void acts as a stress concentrator and helps to promote the peeling of the upper substrate 60U from the topmost silicon layer (e.g., the second silicon layer 53U) and the multilayer stack 52U during the laser annealing process 61.

[0037] Figure 5The upper substrate 60U and the bonded structure 10 are shown after a laser annealing process 61 is performed to peel the upper substrate 60U from the topmost silicon layer (e.g., the second silicon layer 53U), the multilayer stack 52U, and the rest of the bonded structure 10. Due to the laser annealing process 61, portions of the first silicon layer 53U and the peeling layers 51U (e.g., the first peeling layer 51U and the second peeling layer 51U) are ablated, which facilitates peeling of the upper substrate 60U from the topmost silicon layer (e.g., the second silicon layer 53U), the multilayer stack 52U, and the rest of the bonded structure 10.

[0038] exist Figure 6 In the embodiment, a wet etching process 63A is performed to remove the remaining portion of the lift-off layer 51U (e.g., the first lift-off layer 51U) on the first surface 65 of the upper substrate 60U. In addition, a wet etching process 63B is performed to remove the remaining portion of the lift-off layer 51U (e.g., the second lift-off layer 51U) on the first surface 67 of the topmost silicon layer (e.g., the second silicon layer 53U). The wet etching processes 63A and 63B may include using hydrogen peroxide (H 2 O 2 ), deionized water or hydrofluoric acid (HF) as an etchant to remove the remaining portion of the first peeling layer 51U on the first surface 65 of the upper substrate 60U and the second peeling layer 51U on the first surface 67 of the second silicon layer 53U. After performing the wet etching process 63A and the wet etching process 63B, a surface cleaning process may be performed on the surface of each of the upper substrate 60U and the bonding structure 10. The surface cleaning process may include exposing the surface of each of the upper substrate 60U and the bonding structure 10 to a solution including deionized water, ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 In an embodiment, the temperature of the solution during the surface cleaning process ranges from 40°C to 80°C.

[0039] Further references Figure 6 After the wet etching process 63A, the wet etching process 63B, and the surface cleaning process have been performed, a planarization process may be performed on each of the first surface 65 of the upper substrate 60U and the first surface 67 of the topmost silicon layer (e.g., the second silicon layer 53U). The planarization process may include a grinding process, chemical mechanical polishing (CMP), a combination thereof, etc. The planarization process may also be used to reduce the thickness of the topmost silicon layer (e.g., the second silicon layer 53U) to match the thickness of each of the semiconductor layers 56U and / or 56L.

[0040] Advantages can be achieved by forming a peeling structure 50U over a substrate 60U, the peeling structure 50U including a plurality of peeling stacks 55U. Each peeling stack 55U includes a peeling layer 51U and a corresponding silicon layer 53U over the peeling layer 51U, wherein the peeling structure 50U includes 2 to 5 peeling stacks 55U. For example, the peeling structure 50U may include a first peeling layer 51U over the substrate 60U, a first silicon layer 53U over the first peeling layer 51U, a second peeling layer 51U over the first silicon layer 53U, and a second silicon layer 53U over the second peeling layer 51U. Each peeling layer 51U may include germanium (Ge), silicon germanium (e.g., Si 1-x Ge x , wherein x is in the range of from 0.7 to 1), silicon carbide (SiC), boron- or phosphorus-doped silicon, boron- or phosphorus-doped silicon germanium, yttrium oxide (Y 2 O 3 ), cerium oxide (CeO 2 ), boron nitride (BN), gallium phosphide (GaP) or titanium nitride (TiN). Each peeling layer 51U has a thickness T1 in a range from 1 nm to 10 nm, and each silicon layer 53U has a thickness T2 in a range from 5 nm to 200 nm. The multilayer stack 52U is formed over the peeling structure 50U and in contact with the peeling structure 50U, and after the multilayer stack 52U is formed, the multilayer stack 52U is bonded to the multilayer stack 52L. Then, the laser annealing process 61 is implemented using a laser operating in an infrared region having a wavelength in a range from 500 to 2500 nm, and the laser emits a laser beam having a power output in a range from 500 mW to 5000 mW. The laser annealing process 61 causes ablation of the first silicon layer 53U and portions of the first peeling layer 51U and the second peeling layer 51U, and further causes the substrate 60U to be peeled off from the multilayer stack 52U.

[0041] These advantages include each peeling layer 51U having a thickness T1 in a range from 1 nm to 10 nm, and each silicon layer 53U having a thickness T2 in a range from 5 nm to 200 nm, allowing one or more resonant cavities 59 to be formed in the peeling structure 50U that match the wavelength of the infrared laser used during the laser annealing process 61. This allows for more efficient heating of the peeling structure 50U during the laser annealing process 61, which allows for ablation thresholds to be achieved within the peeling structure 50U, and enables more efficient material removal (e.g., by ablation) of portions of the first silicon layer 53U and the first and second peeling layers 51U, 51U. This further enables the substrate 60U to be peeled off from the multilayer stack 52U. This peeling of the substrate 60U from the multilayer stack 52U is achieved with minimal damage to the substrate 60U, since the need to perform a trimming or thinning process on the substrate 60U to remove it from the multilayer stack 52U is eliminated. In this way, the substrate 60U can be used for possible recycling and reuse (e.g., to form another CFET) in further semiconductor manufacturing operations. Therefore, manufacturing costs can be reduced. In addition, forming a peeling structure 50U using a plurality of peeling stacks 55U including alternating silicon layers 53U and peeling layers 51U formed using CVD or ALD produces better film quality of the silicon layers 53U and the peeling layers 51U, compared to if the silicon layers 53U and the peeling layers 51U are formed using other processes (e.g., a plasma process that produces plasma damage to the silicon layers 53U and the peeling layers 51U). Therefore, the quality of the epitaxial layer of the multilayer stack 52U formed above the peeling structure 50U is improved. In addition, the plurality of peeling stacks 55U include materials selected based on their lattice parameters to achieve an improved lattice that matches the multilayer stack 52U. In this way, strain and defects at the interface between the multilayer stack 52U and the peeling structure 50U are reduced. When the multilayer stack 52U is formed, this produces an improved bond between the substrate 60U and the multilayer stack 52U.

[0042] exist Figure 7, semiconductor fins 62 are formed in the lower substrate 60L. In addition, nanostructures 64, 66 (including pseudo nanostructures 64, lower semiconductor nanostructures 66L, intermediate semiconductor nanostructures 66M, and upper semiconductor nanostructures 66U) are formed in the topmost silicon layer (e.g., the second silicon layer 53U) and the multilayer stacks 52L and 52U, and the isolation material 100 is formed by the bonding layer 58. In some embodiments, the nanostructures 64, 66, the isolation material 100, and the semiconductor fins 62 are formed by etching trenches in the topmost silicon layer (e.g., the second silicon layer 53U), the upper multilayer stack 52U, the bonding layer 58, the lower multilayer stack 52L, and the lower substrate 60L. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. Etching can be anisotropic. Forming the nanostructures 64, 66 may define the pseudo nanostructure 64 from the lower pseudo semiconductor layer 54L and the upper pseudo semiconductor layer 54U, the lower semiconductor nanostructure 66L from some of the lower semiconductor layer 56L, the upper semiconductor nanostructure 66U from the topmost silicon layer (e.g., the second silicon layer 53U) and some of the upper semiconductor layer 56U, and the intermediate semiconductor nanostructure 66M from some of the lower semiconductor layer 56L and some of the upper semiconductor layer 56U. The lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U may be further collectively referred to as the semiconductor nanostructure 66.

[0043] The lower semiconductor nanostructure 66L will serve as the channel region of the lower nanostructure FET for the CFET. The upper semiconductor nanostructure 66U will serve as the channel region of the upper nanostructure FET for the CFET. The intermediate semiconductor nanostructure 66M is a semiconductor nanostructure 66 that is directly above / below the isolation material 100 (e.g., in contact with the isolation material 100). Depending on the height of the subsequently formed source / drain regions, the intermediate semiconductor nanostructure 66M may or may not be adjacent to any source / drain regions and may or may not serve as a functional channel region for the CFET. The isolation structure and the intermediate semiconductor nanostructure 66M may define the boundaries of the lower nanostructure FET and the upper nanostructure FET.

[0044] The semiconductor fins 62, nanostructures 64, 66, and isolation material 100 may be patterned by any suitable method. For example, the semiconductor fins 62, nanostructures 64, 66, and isolation material 100 may be patterned using one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a spacing that is less than that obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed above a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the semiconductor fins 62, nanostructures 64, 66, and isolation material 100. In some embodiments, a mask (or other layer) may remain on the nanostructures 64, 66.

[0045] Although each of the semiconductor fins 62, nanostructures 64, 66, and isolation material 100 are shown as having a constant width throughout, in other embodiments, the semiconductor fins 62, nanostructures 64, 66, and / or isolation material 100 may have tapered sidewalls such that the width of each of the semiconductor fins 62, nanostructures 64, 66, and / or isolation material 100 increases continuously in a direction toward the substrate 60L. In such embodiments, each of the nanostructures 64, 66, and isolation material 100 may have different widths and be trapezoidal in shape.

[0046] Further references Figure 7After forming the semiconductor fins 62, the nanostructures 64, 66 (including the pseudo nanostructures 64, the lower semiconductor nanostructures 66L, the middle semiconductor nanostructures 66M and the upper semiconductor nanostructures 66U) and the isolation material 100, an isolation region 70 is formed above the lower substrate 60L and between adjacent semiconductor fins 62. The isolation region 70 (hereinafter also referred to as a shallow trench isolation (STI) region) may include a dielectric liner and a dielectric material above the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof. The formation of the isolation region 70 may include: depositing a dielectric layer; and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, or the like, to remove excess portions of the dielectric material, such as portions above the nanostructures 64, 66. The deposition process may include ALD, high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, the isolation region 70 includes silicon oxide formed by a FCVD process, followed by an annealing process. Then, the dielectric layer is recessed to define the isolation region 70. The dielectric layer can be recessed so that the upper portion of the semiconductor fins 62, nanostructures 64, 66, and isolation material 100 extend higher than the remaining isolation region 70.

[0047] After forming the isolation region 70, a pseudo dielectric layer 72 is formed on the semiconductor fin 62, the nanostructure 64, 66 and / or the isolation material 100. The pseudo dielectric layer 72 may be, for example, silicon oxide, silicon nitride, a combination thereof, etc., and may be deposited or thermally grown according to acceptable techniques. A pseudo gate layer 74 is formed above the pseudo dielectric layer 72, and a mask layer 76 is formed above the pseudo gate layer 74. The pseudo gate layer 74 may be deposited above the pseudo dielectric layer 72, and then planarized such as by CMP. The mask layer 76 may be deposited above the pseudo gate layer 74. The pseudo gate layer 74 may be a conductive or non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly silicon), polycrystalline silicon germanium (poly-SiGe), metal nitride, metal silicide, metal oxide and metal. The pseudo gate layer 74 may be deposited by physical vapor deposition (PVD), CVD, sputtering deposition or other techniques for depositing selected materials. The pseudo gate layer 74 may be made of other materials having high etching selectivity relative to the etching of the isolation region. The mask layer 76 may include, for example, silicon nitride, silicon oxynitride, etc. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70, such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 only covers the semiconductor fins 62, the nanostructures 64, 66, and / or the isolation material 100.

[0048] exist Figure 8In the embodiment of the present invention, the mask layer 76 can be patterned using acceptable photolithography and etching techniques to form a mask 86. The pattern of the mask 86 can then be transferred to the dummy gate layer 74 and to the dummy dielectric layer 72 to form a dummy gate 84 and a dummy dielectric 82, respectively. The dummy gate 84 covers the corresponding channel region of the nanostructures 64, 66. The pattern of the mask 86 can be used to physically separate each of the dummy gates 84 from the adjacent dummy gates 84. The dummy gates 84 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the corresponding semiconductor fin 62. After patterning, the mask 86 can be optionally removed, such as by any acceptable etching technique.

[0049] After forming the dummy gate 84 and the dummy dielectric 82, a gate spacer 90 is formed over the nanostructures 64, 66 and on the exposed sidewalls of the mask 86 (if present), the dummy gate 84 and the dummy dielectric 82. The gate spacer 90 may be formed by conformally forming one or more dielectric materials and then etching the dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., which may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials formed by any acceptable process may be used. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be implemented to pattern the dielectric material. The etching may be anisotropic. The dielectric material (when etching) has a portion remaining on the sidewall of the dummy gate 84 (thus forming the gate spacer 90). In some embodiments, the dielectric material (when etching) may also have a portion remaining on the sidewalls of the semiconductor fin 62 and / or the nanostructure 64, 66.

[0050] Still reference Figure 8, after forming the gate spacer 90, source / drain recesses 94 are formed in the semiconductor fins 62, the nanostructures 64, 66, the isolation material 100, and the substrate 60L. An epitaxial source / drain region will then be formed in the source / drain recesses 94. The source / drain recesses 94 may extend through the nanostructures 64, 66, through the isolation material 100, and into the substrate 60L. The semiconductor fins 62 may be etched so that the bottom surface of the source / drain recesses 94 is disposed above, below, or flush with the top surface of the isolation region 70. The source / drain recesses 94 may be formed by etching the semiconductor fins 62, the nanostructures 64, 66, the isolation material 100, and the substrate 60L using an anisotropic etching process (such as RIE, NBE, etc.). The gate spacers 90 and the dummy gates 84 mask portions of the semiconductor fins 62, the nanostructures 64, 66, the isolation material 100, and the substrate 60L during the etching process used to form the source / drain recesses 94. A single etching process or multiple etching processes may be used to etch each layer of the nanostructures 64, 66, the isolation material 100, and / or the semiconductor fins 62. After the source / drain recesses 94 reach a desired depth, a timed etching process may be used to stop the etching of the source / drain recesses 94.

[0051] exist Fig. 9 In the embodiment of the present invention, an internal spacer 98 is formed on the sidewalls of the pseudo nanostructure 64 and the isolation material 100. In order to form the internal spacer 98, the sidewalls of the pseudo nanostructure 64 and the isolation material 100 exposed by the source / drain recess 94 are recessed to form a sidewall recess. The sidewall recess can be formed by recessing the sidewalls of the pseudo nanostructure 64 and the isolation material 100 using any acceptable etching process. The etching is selective to the material of the pseudo nanostructure 64 (e.g., the material of the pseudo nanostructure 64 is selectively etched at a faster rate than the material of the semiconductor nanostructure 66). The etching can also be selective to the material of the isolation material 100 (e.g., the material of the isolation material 100 is selectively etched at a faster rate than the material of the semiconductor nanostructure 66). The etching can be isotropic. Although the sidewalls of the pseudo nanostructure 64 and the isolation material 100 are shown as being straight after etching, the sidewalls can be concave or convex.

[0052] In some embodiments, the same etching process is used to recess the sidewalls of the pseudo-nanostructure 64 and the isolation material 100. Specifically, the etching process may be performed at a faster rate than the isolation material 100 (e.g., Fig. 9 ), the material of the pseudo nanostructure 64 is selectively etched at the same rate or at a slower rate. The etching rate produces different relative dimensions on the sidewalls of the pseudo nanostructure 64 compared to the isolation material 100. The relative etching rates of the pseudo nanostructure 64 and the isolation material 100 can be achieved, for example, by adjusting the etching parameters of the etching process.

[0053] Then, an internal spacer 98 is formed in the sidewall recess of the pseudo nanostructure 64 and the isolation material 100. As described in more detail later, a source / drain region will be formed in the source / drain recess 94, and the pseudo nanostructure 64 will be replaced with a corresponding gate structure. The internal spacer 98 serves as an isolation member between the subsequently formed source / drain region and the subsequently formed gate structure. In addition, the internal spacer 98 can be used to prevent damage to the subsequently formed source / drain region by a subsequent etching process (such as an etching process for forming a gate structure).

[0054] The internal spacer 98 can be formed by conformally forming an insulating material in the source / drain recess 94 and then subsequently etching the insulating material. The insulating material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon oxynitride, silicon oxycarbon, silicon oxynitride, etc. In an embodiment, the insulating material may include silicon oxynitride with a carbon atomic percentage of less than 6%. Other low dielectric constant (low-k) materials with a k value of less than about 3.5 can be utilized. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etch, such as RIE, NBE, etc. The insulating material (when etched) has a portion that remains in the sidewall recess of the pseudo nanostructure 64 and the isolation material 100 (thus forming the internal spacer 98).

[0055] Although the outer sidewalls of the inner spacers 98 are shown flush with the sidewalls of the semiconductor nanostructures 66, the outer sidewalls of the inner spacers 98 may extend beyond or be recessed from the sidewalls of the semiconductor nanostructures 66. In other words, the inner spacers 98 may partially fill, completely fill, or overfill the sidewall recesses of the dummy nanostructures 64 and the isolation material 100. Furthermore, although the sidewalls of the inner spacers 98 are shown as being straight, those sidewalls may be concave or convex.

[0056] Due to the difference in size between the sidewall recesses of the pseudo nanostructure 64 and the isolation material 100, the internal spacers 98 on the isolation material 100 may also have different sizes (e.g., width) than the internal spacers 98 on the pseudo nanostructure 64. For example, in the illustrated embodiment, the internal spacers 98 on the isolation material 100 are not as wide as the internal spacers 98 on the pseudo nanostructure 64. In other embodiments, the internal spacers 98 on the isolation material 100 may be wider than the internal spacers 98 on the pseudo nanostructure 64 or have the same width as the internal spacers 98 on the pseudo nanostructure 64.

[0057] Further references Fig. 9, after forming the inner spacer 98, the lower epitaxial source / drain region 108L and the upper epitaxial source / drain region 108U are formed. The lower epitaxial source / drain region 108L is formed in the lower portion of the source / drain recess 94. The lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L and does not contact the upper semiconductor nanostructure 66U. The inner spacer 98 electrically insulates the lower epitaxial source / drain region 108L from the dummy nanostructure 64, which will be replaced with a replacement gate in a subsequent process.

[0058] The lower epitaxial source / drain region 108L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 108L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 108L is a p-type source / drain region, the corresponding material may include silicon or silicon germanium doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain region 108L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopant. During the epitaxy of the lower epitaxial source / drain region 108L, the upper semiconductor nanostructure 66U may be masked to prevent undesired epitaxial growth on the upper semiconductor nanostructure 66U. After growing the lower epitaxial source / drain regions 108L, the mask over the upper semiconductor nanostructures 66U may then be removed.

[0059] As a result of the epitaxial process used to form the lower epitaxial source / drain regions 108L, the upper surfaces of the lower epitaxial source / drain regions 108L have facets that extend laterally outward beyond the sidewalls of the semiconductor fins 62. In some embodiments, adjacent lower epitaxial source / drain regions 108L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 108L of the same FET to merge.

[0060] A first contact etch stop layer (CESL) 112 and a first ILD 114 are formed over the lower epitaxial source / drain regions 108L. The first CESL 112 may be formed of a dielectric material having a high etch selectivity relative to the etching of the first ILD 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 114 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 114 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

[0061] The formation process may include: depositing a conformal CESL layer; depositing a material for the first ILD 114; and a subsequent planarization process and then an etch-back process. In some embodiments, the first ILD 114 is first etched, leaving the first CESL 112 unetched. An anisotropic etching process is then performed to remove the portion of the first CESL 112 that is above the recessed first ILD 114. After the recess, the sidewalls of the upper semiconductor nanostructure 66U are exposed.

[0062] An upper epitaxial source / drain region 108U is then formed in the upper portion of the source / drain recess 94. The upper epitaxial source / drain region 108U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 66U. The material of the upper epitaxial source / drain region 108U may be selected from the same candidate material group used to form the lower epitaxial source / drain region 108L, depending on the desired conductivity type of the upper epitaxial source / drain region 108U. The conductivity type of the upper epitaxial source / drain region 108U may be opposite to the conductivity type of the lower epitaxial source / drain region 108L. For example, the upper epitaxial source / drain region 108U may be doped opposite to the lower epitaxial source / drain region 108L. The upper epitaxial source / drain region 108U may be in-situ doped with n-type or p-type dopants and / or may be implanted with n-type or p-type dopants. In an embodiment, the upper epitaxial source / drain region 108U includes silicon doped with phosphorus or the like, wherein the doping concentration of the upper epitaxial source / drain region 108U is greater than 1×10 21 cm -3 The adjacent upper epitaxial source / drain regions 108U may remain separated after the epitaxial process, or may merge.

[0063] After forming the upper epitaxial source / drain regions 108U, the second CESL 122 and the second ILD 124 are formed. The materials and formation methods may be similar to those of the first CESL 112 and the first ILD 114, respectively, and are not discussed in detail herein. The formation process may include: depositing layers for the second CESL 122 and the second ILD 124; and performing a planarization process to remove excess portions of the corresponding layers. After the planarization process, the top surfaces of the second ILD 124, the gate spacers 90, and the dummy gate stacks 82 / 84 are coplanar (within process variations). The planarization process may remove the mask 86, or leave the mask 86 unremoved.

[0064] Fig.10 A replacement gate process is shown in which the pseudo gate stack 82 / 84 and the pseudo nanostructure 64 are replaced with the gate stack 136. The replacement gate process includes first removing the remaining portions of the pseudo gate stack 82 / 84 and the pseudo nanostructure 64. The mask 86 (if present) may also be removed. The pseudo gate stack 82 / 84 is removed in one or more etching processes, thereby defining a groove between the gate spacers 90 and exposing the semiconductor nanostructure 66 / pseudo nanostructure 64. The remaining portion of the pseudo nanostructure 64 is then removed by etching so that the groove extends between the semiconductor nanostructures 66. In the etching process, the pseudo nanostructure 64 is etched at a faster rate than the semiconductor nanostructure 66, the isolation material 100, and the internal spacer 98. The etching may be isotropic. For example, when the pseudo nanostructure 64 is formed of silicon germanium and the semiconductor nanostructure 66 is formed of silicon, the etching process may include using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH) and other wet etching processes.

[0065] Then, a gate dielectric 130 is deposited in the grooves between the gate spacers 90 and on the exposed semiconductor nanostructures 66. The gate dielectric 130 is conformally formed on the exposed surface of the grooves (the removed gate stack 82 / 84 and the dummy nanostructure 64) including the semiconductor nanostructures 66, the isolation material 100, and the gate spacers 90. In some embodiments, the gate dielectric 130 wraps all (e.g., four) sides of the semiconductor nanostructures 66 and the isolation material 100. Specifically, the gate dielectric 130 may be formed on the top surface of the semiconductor fin 62; the top surface, sidewalls, and bottom surface of the semiconductor nanostructures 66U, 66L; the exposed lateral surfaces and sidewalls of the semiconductor nanostructure 66M; the sidewalls of the isolation material 100; and the sidewalls of the gate spacers 90. The gate dielectric 130 may include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, and the like. The gate dielectric 130 may include a high dielectric constant (high-k) material having a k value greater than about 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation method of the gate dielectric 130 may include molecular beam deposition (MBD), ALD, PECVD, etc. Although a single layer of gate dielectric 130 is shown, the gate dielectric 130 may include multiple layers, such as an interface layer and an upper high-k dielectric layer.

[0066] A lower gate electrode 134L is formed on the gate dielectric 130 around the lower semiconductor nanostructure 66L. For example, the lower gate electrode 134L wraps around the lower semiconductor nanostructure 66L. The lower gate electrode 134L may be formed of a metal-containing material such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 134L may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filler materials.

[0067] The lower gate electrode 134L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 134L may include one or more work function adjustment layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, and the like. Additionally or alternatively, the lower gate electrode 134L may include a dipole-inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, molybdenum, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0068] The lower gate electrode 134L may be formed by conformally depositing one or more gate electrode layers and then recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be implemented to recess the gate electrode layer 134L to a desired level (e.g., at or below the level of the isolation material 100). The etching may be isotropic. Etching the lower gate electrode 134L may expose the upper semiconductor nanostructure 66U.

[0069] In some embodiments, an isolation layer (not explicitly shown) may be optionally formed on the lower gate electrode 134L. The isolation layer serves as an isolation member between the lower gate electrode 134L and the subsequently formed upper gate electrode 134U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, combinations thereof, etc.) and then recessing the dielectric material to expose the upper semiconductor nanostructure 66U.

[0070] Then, an upper gate electrode 134U is formed on the isolation layer (if present) or the lower gate electrode 134L described above. The upper gate electrode 134U is disposed between the upper semiconductor nanostructures 66U. In some embodiments, the upper gate electrode 134U wraps the upper semiconductor nanostructure 66U. The upper gate electrode 134U can be formed of the same candidate material and candidate process used to form the lower gate electrode 134L. The upper gate electrode 134U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 134U may include one or more work function adjustment layers formed of a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 134U is shown, the upper gate electrode 134U may include any number of work function adjustment layers, any number of barrier layers, any number of glue layers, and filling materials.

[0071] In addition, one or more removal processes are performed to make the top surfaces of the upper gate electrode 134U and the gate dielectric 130 flush with the second ILD 124. The removal process used to form the gate dielectric 130 can be the same removal process as the removal process used to form the upper gate electrode 134U. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. can be utilized. After the planarization process, the top surfaces of the upper gate electrode 134U, the gate dielectric 130, the second ILD 124, and the gate spacer 90 are substantially coplanar (within process variations). Each corresponding pair of the gate dielectric 130 and the gate electrode 134 (including the upper gate electrode 134U and / or the lower gate electrode 134L) can be collectively referred to as a "gate stack" 136 (including an upper gate stack 136U and a lower gate stack 136L). Each gate stack 136 extends along three sides (e.g., a top surface, a sidewall, and a bottom surface) of the channel region of the semiconductor nanostructure 66 (see Figure 1 ). The lower gate stack 136L may also extend along the sidewalls and / or top surfaces of the semiconductor fin 62 .

[0072] Likewise Fig.10 As shown in , a gate mask 138 is formed over the gate stack 136. The formation process may include: recessing the gate stack 136; filling the resulting recess with a dielectric material such as silicon nitride, silicon carbonitride, silicon oxynitride, silicon carbon oxynitride, etc.; and performing a planarization process to remove excess portions of the dielectric material over the second ILD 124.

[0073] exist Fig.11 In the embodiment, a silicide region 142 and a source / drain contact 144 are formed through the second ILD 124 to electrically couple to the upper epitaxial source / drain region 108U and / or the lower epitaxial source / drain region 108L. As an example of forming the source / drain contact 144, an opening is formed through the second ILD 124 and the second CESL 122 using acceptable photolithography and etching techniques. A liner (not shown separately) (such as a diffusion barrier layer, an adhesion layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process may be performed to remove excess material from the top surface of the gate spacer 90 and the second ILD 124. The remaining liner and conductive material form a source / drain contact 144 in the opening. In some embodiments, a planarization process such as CMP, an etch-back process, a combination thereof, etc. is utilized. After the planarization process, top surfaces of the gate spacers 90 , the second ILD 124 , and the source / drain contacts 144 are substantially coplanar (within process variations).

[0074] Optionally, a metal-semiconductor alloy region 142 is formed at the interface between the source / drain region 108 and the source / drain contact 144. The metal-semiconductor alloy region 142 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanide region formed of a metal silicide and a metal germanide, etc. The metal-semiconductor alloy region 142 may be formed before the material of the source / drain contact 144 by depositing a metal in an opening for the source / drain contact 144 and then performing a thermal annealing process. The metal may be any metal that can react with the semiconductor material (e.g., silicon, silicon germanium, germanium, etc.) of the source / drain region 108 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process such as a wet clean may be performed to remove any remaining metal from the openings for the source / drain contacts 144 (such as from the surface of the metal-semiconductor alloy region 142). The material of the source / drain contacts 144 may then be formed on the metal-semiconductor alloy region 142. The active devices shown are collectively referred to as device layers 170.

[0075] Further references Fig.11 , and then an etch stop layer (ESL) 152 and a third ILD 154 are formed. In some embodiments, the ESL 152 may include a dielectric material having a high etch selectivity relative to the etching of the third ILD 154, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 154 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

[0076] Subsequently, a gate contact 156 and a source / drain via 158 are formed to contact the upper gate stack 136U and the source / drain contact 144, respectively. As an example of forming a gate contact 156 and a source / drain via 158, an opening for the gate contact 156 and the source / drain via 158 is formed through the third ILD 154, the ESL 152 and the gate mask 138. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown separately) (such as a diffusion barrier layer, an adhesive layer, etc.) and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, may be implemented to remove excess material from the top surface of the third ILD 154. The remaining liner and conductive material form a gate contact 156 and a source / drain via 158 in the opening. The gate contact 156 and the source / drain vias 158 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 156 and the source / drain vias 158 may be formed in different cross sections, which may avoid shorting the contacts. In some embodiments, contacts to the lower gate stack 136L and the lower epitaxial source / drain regions 108L may be made through the back side of the device layer 170 (e.g., the side opposite the source / drain contact 144).

[0077] Then, a front side interconnect structure 176 is formed on the device layer 170, the gate contact 156, the source / drain vias 158, and the third ILD 154. The front side interconnect structure 176 includes a dielectric layer 174 and a layer of conductive features 172 in the dielectric layer 174. The dielectric layer 174 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 174 may also include a passivation layer formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc., or a combination thereof, over the low-k dielectric material. The dielectric layer 174 may also include a polymer layer.

[0078] Conductive component 172 may include conductive lines and vias, which may be formed using a damascene process. Conductive component 172 may include metal lines and metal vias, which include a diffusion barrier layer and a copper-containing material above the diffusion barrier layer. There may also be aluminum pads located above and electrically connected to the metal lines and vias. Conductive component 172 may be electrically connected to gate contact 156 and source / drain vias 158. Front side interconnect structure 176, gate contact 156, source / drain vias 158, and third ILD 154 may be collectively referred to as structure 180.

[0079] Figures 12 to 16Unless otherwise indicated, the same reference numerals in this embodiment (and the embodiments discussed subsequently) refer to Figures 1 to 11 The same components in the embodiments shown in the drawings are formed by the same process. Therefore, the process steps and applicable materials may not be repeated here. Fig.12 The engagement structure 20 is shown and may be similar to Figure 3 The joining structure 10, unless otherwise stated. Fig.12 The bonding structure 20 and Figure 3 The difference between the bonding structure 10 and the bonding structure 20 is that the bonding structure 20 may also include a peeling structure 50L disposed between the substrate 60L and the multilayer stack 52L. The peeling structure 50L may be used in the same manner as previously described for Figure 2B The peeling structure 50U is formed using similar materials and similar processes as those described above.

[0080] Forming the peeling structure 50L may include forming a plurality of peeling stacks 55L over the substrate 60L. Each peeling stack 55L includes a peeling layer 51L and a corresponding silicon layer 53L over the peeling layer 51L. The peeling structure 50L may include 2 to 5 peeling stacks 55L. For example, Fig.12 In FIG. 5 , the peeling structure 50L is shown as including 2 peeling stacks 55L. In other embodiments, the peeling structure 50L may include up to 5 peeling stacks 55L. Fig.12 In the embodiment of the present invention, a first peeling layer 51L (e.g., also referred to as a bottom-most peeling layer) may be formed over a substrate 60L. A corresponding first silicon layer 53L (also referred to as a bottom-most silicon layer) is then formed over the first peeling layer 51L to form a first peeling stack 55L. More peeling stacks 55L (including a pair of peeling layers 51L and corresponding silicon layers 53L) are then formed over the first peeling stack 55L to form a peeling structure 50L. For example, in Fig.12 In the embodiment, a second peeling layer 51L (e.g., also referred to as the top peeling layer) and a corresponding second silicon layer 53L (e.g., also referred to as the top silicon layer) are then sequentially formed over the first peeling stack 55L to form a second peeling stack 55L. In an embodiment, a thickness T5 of each peeling layer 51L is in a range from 1 nm to 10 nm. In an embodiment, a thickness T6 of each silicon layer 53L may be in a range from 5 nm to 200 nm. In an embodiment, the top silicon layer (e.g., Fig.12 The thickness T7 of the second silicon layer 53L in the lift-off layer 51L is greater than 100 nm. The lift-off layer 51L and the silicon layer 53L can be formed using processes and materials similar to those of the lift-off layer 51U and the silicon layer 53U, respectively. Figure 2B After forming the peeling structure 50L, the multilayer stack 52L is formed in the same manner as previously described in Figure 2BMultilayer stack 52U is formed over and in contact with debonding structure 50L in a manner similar to the multilayer stack 52U formed over and in contact with debonding structure 50U described in .

[0081] exist Fig.13 In the implementation Figures 4 to 11 The same steps as shown in , to sequentially form a device layer 170 (previously in Fig.11 ) and structure 180 (previously shown in Fig.11 ).

[0082] After forming device layer 170 and structure 180, substrate 184 (e.g., silicon substrate, silicon wafer, etc.) is bonded to the top surface of structure 180 using a suitable technique such as fusion bonding. For example, in various embodiments, substrate 184 can be bonded to structure 180 using bonding layers 182 / 183 on the surfaces of structure 180 and substrate 184, respectively. In some embodiments, bonding layers 182 / 183 can each include silicon oxide formed on the surfaces of structure 180 and substrate 184, respectively, by a deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. In other embodiments, bonding layer 183 can be formed by thermal oxidation of the silicon surface on substrate 184.

[0083] Before bonding, at least one of the bonding layers 182 / 183 may be subjected to surface treatment. The surface treatment may include plasma treatment. The plasma treatment may be implemented in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsed with deionized water, etc.) that may be applied to one or both bonding layers 182 / 183. Then, the substrate 184 is aligned with the structure 180, and the two of them are pressed against each other at room temperature (between about 21 degrees and about 25 degrees) to bond them together. The bonding process can be strengthened by a subsequent annealing step. For example, this can be accomplished by heating the substrate 184 and the structure 180 to a temperature in the range of from 140°C to 500°C.

[0084] exist Fig.14 In the Fig.13 , so that the lower substrate 60L is disposed above the substrate 184. A laser annealing process 186 is then performed using a laser to peel the lower substrate 60L from the topmost silicon layer (e.g., the second silicon layer 53L), the device layer 170, and the structure 180. The laser annealing process 186 may be similar to that previously described in Figure 4 The laser annealing process 186 may include the following steps: Fig.14180. The laser beam emitted from the laser is systematically moved (e.g., scanned) over the top surface of the lower substrate 60L shown in FIG. 186. Due to the laser annealing process 186, an ablation threshold can be achieved within the lift-off structure 50L, which allows for effective material removal (e.g., by ablation) of the first silicon layer 53L (also referred to as the bottommost silicon layer) and portions of the first lift-off layer 51L and the second lift-off layer 51L. In this manner, the lower substrate 60L is lifted off from the topmost silicon layer (e.g., the second silicon layer 53L), the device layer 170, and the structure 180.

[0085] exist Fig.15 In the embodiment, a wet etching process 188A is performed to remove the remaining portion of the lift-off layer 51L (e.g., the first lift-off layer 51L) on the first surface 187 of the lower substrate 60L. In addition, a wet etching process 188B is performed to remove the remaining portion of the lift-off layer 51L (e.g., the second lift-off layer 51L) on the first surface 189 of the topmost silicon layer (e.g., the second silicon layer 53L). The wet etching processes 188A and 188B may include using hydrogen peroxide (H 2 O 2 ), deionized water or hydrofluoric acid (HF) as an etchant to remove the remaining portion of the lift-off layer 51L (e.g., the first lift-off layer 51L) on the first surface 187 of the lower substrate 60L and the lift-off layer 51L (e.g., the second lift-off layer 51L) on the first surface 189 of the topmost silicon layer (e.g., the second silicon layer 53L). After performing the wet etching process 188A and the wet etching process 188B, a surface cleaning process may be performed on the surface of each of the lower substrate 60L and the topmost silicon layer (e.g., the second silicon layer 53L). The surface cleaning process may include exposing the surface of each of the lower substrate 60L and the topmost silicon layer (e.g., the second silicon layer 53L) to a solution including deionized water, ammonium hydroxide (NH OH), and / or HF. 4 OH) and hydrogen peroxide (H 2 O 2 In an embodiment, the temperature of the solution during the surface cleaning process ranges from 40°C to 80°C.

[0086] Further references Fig.15 After the wet etching process 188A, the wet etching process 188B, and the surface cleaning process have been performed, a planarization process may be performed on each of the first surface 187 of the lower substrate 60L and the first surface 189 of the topmost silicon layer (e.g., the second silicon layer 53L). The planarization process may include a grinding process, chemical mechanical polishing (CMP), a combination thereof, and the like.

[0087] Advantages can be achieved by forming a lift-off structure 50L over a substrate 60L, the lift-off structure 50L including a plurality of lift-off stacks 55L. Each lift-off stack 55L includes a lift-off layer 51L and a corresponding silicon layer 53L over the lift-off layer 51L, wherein the lift-off structure 50L includes 2 to 5 lift-off stacks 55L. For example, the lift-off structure 50L may include a first lift-off layer 51L over the substrate 60L, a first silicon layer 53L over the first lift-off layer 51L, a second lift-off layer 51L over the first silicon layer 53L, and a second silicon layer 53L over the second lift-off layer 51L. Each lift-off layer 51L may include germanium (Ge), silicon germanium (e.g., Si 1-x Ge x , wherein x is in the range of from 0.7 to 1), silicon carbide (SiC), boron- or phosphorus-doped silicon, boron- or phosphorus-doped silicon germanium, yttrium oxide (Y 2 O 3 ), cerium oxide (CeO 2 ), boron nitride (BN), gallium phosphide (GaP) or titanium nitride (TiN). Each peeling layer 51L has a thickness T5 in a range from 1 nm to 10 nm, and each silicon layer 53L has a thickness T6 in a range from 5 nm to 200 nm. The multilayer stack 52L is formed over and in contact with the peeling structure 50L, and after the multilayer stack 52L is formed, the multilayer stack 52L is bonded to the multilayer stack 52U. Then, the laser annealing process 186 is implemented using a laser operating in an infrared region having a wavelength in a range from 500 to 2500 nm, and the laser emits a laser beam having a power output in a range from 500 mW to 5000 mW. The laser annealing process 186 causes ablation of the first silicon layer 53L and portions of the first and second peeling layers 51L and further causes the substrate 60L to be peeled off from the multilayer stack 52L.

[0088] These advantages include each lift-off layer 51L having a thickness T5 in a range from 1 nm to 10 nm, and each silicon layer 53L having a thickness T6 in a range from 5 nm to 200 nm, allowing one or more resonant cavities to be formed in the lift-off structure 50L (e.g., in the first silicon layer 53L, the first lift-off layer 51L, and the second lift-off layer 51L) that match the wavelength of the infrared laser used during the laser annealing process 186 (e.g., similar to the previously described Figure 459 described in the resonant cavity 59). This allows for more efficient heating of the peeling structure 50L during the laser annealing process 186, which allows for achieving an ablation threshold within the peeling structure 50L and enables more efficient material removal (e.g., by ablation) of portions of the first silicon layer 53L and the first and second peeling layers 51L, 51L. This further enables the substrate 60L to be peeled off from the multilayer stack 52L. This peeling of the substrate 60L from the multilayer stack 52L is achieved with minimal damage to the substrate 60L because the need to perform a trimming or thinning process on the substrate 60L to remove it from the multilayer stack 52L is eliminated. In this way, the substrate 60L can be used for possible recycling and reuse in further semiconductor manufacturing operations (e.g., to form another CFET). Therefore, manufacturing costs can be reduced. In addition, forming the peeling structure 50L using a plurality of peeling stacks 55L including alternating silicon layers 53L and peeling layers 51L formed using CVD or ALD results in better film quality of the silicon layers 53L and the peeling layers 51L than if the silicon layers 53L and the peeling layers 51L were formed using other processes (e.g., a plasma process that produces plasma damage to the silicon layers 53L and the peeling layers 51L). Thus, the quality of the epitaxial layers of the multilayer stack 52L formed over the peeling structure 50L is improved. In addition, the plurality of peeling stacks 55L include materials selected based on their lattice parameters to achieve an improved lattice that matches the multilayer stack 52L. In this way, strain and defects at the interface between the multilayer stack 52L and the peeling structure 50L are reduced. This results in an improved bond between the substrate 60L and the multilayer stack 52L when the multilayer stack 52L is formed.

[0089] exist Fig.16 In the process, a further thinning process is applied to the planarized first surface 189 (previously Fig.15 ) to remove the topmost silicon layer (e.g., the second silicon layer 53L) and the semiconductor fins 62. The thinning process may include a grinding process, a chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. After the thinning process, the lower epitaxial source / drain region 108L of the device layer 170 (e.g., previously Fig.11 ) can be exposed.

[0090] After performing a thinning process to remove the topmost silicon layer (e.g., the second silicon layer 53L) and the semiconductor fins 62, a structure 190 is formed over the device layer 170. The structure 190 may include a fourth ILD disposed over the device layer and a plurality of ILDs extending through the fourth ILD to contact the lower gate stacks 136L (e.g., previously formed in the device layer). Fig.11 ) and the lower epitaxial source / drain region 108L (e.g., previously shown in Fig.11The structure 190 may also include a backside interconnect structure disposed over the device layer 170, the gate contact plug, the source / drain vias, and the fourth ILD. The backside interconnect structure includes a layer of dielectric layers and conductive features in the dielectric layers. The conductive features may be electrically connected to the gate contact plug and the source / drain vias. The structure 190 may use the same techniques as previously described. Fig.11 For example, the processes and materials used to form the fourth ILD, the gate contact plug, and the source / drain vias can be similar to those previously described in Fig.11 154, the gate contact 156, and the source / drain vias 158. In addition, the processes and materials used to form the backside interconnect structure can be similar to those previously described in Fig.11 Those described in for forming the front side interconnect structure 176.

[0091] Figures 17 to 20 Unless otherwise indicated, the same reference numerals in this embodiment (and the embodiments discussed subsequently) refer to Figures 1 to 16 The same components in the embodiments shown in the drawings are formed by the same process. Therefore, the process steps and applicable materials may not be repeated here. Figures 17 to 20 is a cross-sectional view of an intermediate step during a process for forming an integrated circuit package 30 (eg, a system on an integrated chip (SoIC) device, etc.) in accordance with some embodiments.

[0092] Fig.17 It is shown that wafer 200 (e.g., top die, etc.) is bonded to wafer 300 (e.g., bottom die, etc.) according to an embodiment. Each of wafer 200 or wafer 300 may include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a microcontroller, etc.), a memory die (e.g., a dynamic random access memory (DRAM) die, a static random access memory (SRAM) die, etc.), a power management die (e.g., a power management integrated circuit (PMIC) die), a radio frequency (RF) die, an interface die, a sensor die, a microelectromechanical system (MEMS) die, a signal processing die (e.g., a digital signal processing (DSP) die), a front-end die (e.g., an analog front-end (AFE) die), etc. or a combination thereof (e.g., a system on chip (SoC) die). Each of wafer 200 and wafer 300 may include different die regions that are segmented in a subsequent step to form a plurality of die regions.

[0093] Further references Fig.17, wafer 200 includes a substrate 252 and a lift-off structure 210 formed on the substrate 252. Substrate 252 (which may also be referred to as a carrier substrate or carrier wafer) may be a doped or undoped silicon substrate or an active layer of a semiconductor on insulator (SOI) substrate. Substrate 252 may include: other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof. Other substrates, such as multilayer or gradient substrates, may also be used.

[0094] The lift-off structure 210 of the wafer 200 is formed over the substrate 252. The lift-off structure 210 may be formed using the same method as previously described for forming the lift-off structure 210. Figure 2B The peeling structure 50U and Fig.12 The peeling structure 210 may be formed by similar materials and similar processes as those described in the peeling structure 50L in FIG. For example, forming the peeling structure 210 may include forming a plurality of peeling stacks 211 above the substrate 252. Each peeling stack 211 includes a peeling layer 212 and a corresponding silicon layer 214 above the peeling layer 212. The peeling structure 210 may include 2 to 5 peeling stacks 211. For example, in Fig.17 In FIG. 2 , the peeling structure 210 is shown as including two peeling stacks 211. In other embodiments, the peeling structure 210 may include up to five peeling stacks 211. Fig.17 In the embodiment of the present invention, a first peeling layer 212 (e.g., also referred to as a bottom-most peeling layer) may be formed over a substrate 252. A corresponding first silicon layer 214 (also referred to as a bottom-most silicon layer) is then formed over the first peeling layer 212 to form a first peeling stack 211. More peeling stacks 211 (including peeling layers 212 and corresponding silicon layers 214) are then formed over the first peeling stack 211 to form a peeling structure 210. For example, in Fig.17 In the embodiment, a second peeling layer 212 (e.g., also referred to as the topmost peeling layer) and a corresponding second silicon layer 214 (also referred to as the topmost silicon layer) are then sequentially formed over the first peeling stack 211 to form the second peeling stack 211. In an embodiment, a thickness T8 of each peeling layer 212 is in a range from 1 nm to 10 nm. In an embodiment, a thickness T9 of each silicon layer 214 may be in a range from 5 nm to 200 nm. In an embodiment, a thickness T10 of the topmost silicon layer (e.g., the second silicon layer 214) is greater than 100 nm. The peeling layer 212 and the silicon layer 214 may be formed using the same method as previously described. Figure 2B The peeling layer 51U and the silicon layer 53U are formed by processes and materials similar to those described in , respectively.

[0095] After forming the lift-off structure 210, an active device layer 253 is formed in / on the topmost silicon layer (e.g., the second silicon layer 214). The active device layer 253 may include active devices (e.g., transistors, diodes, etc.), capacitors, resistors, etc. The interconnect structure 254 of the wafer 200 is disposed above the active device layer 253 and is used to electrically connect the devices of the active device layer 253 to form an integrated circuit. The interconnect structure 254 may include one or more dielectric layers and corresponding metallization layers in the dielectric layer. Acceptable dielectric materials for the dielectric layer include: oxides, such as silicon oxide or aluminum oxide; nitrides, such as silicon nitride; carbides, such as silicon carbide; etc.; or combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, silicon carbon nitride, etc. Other dielectric materials may also be used, such as polymers, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymers, etc. The metallization layer may include conductive vias and / or conductive lines to interconnect the devices of the active device layer 253. The metallization layer may be formed of a conductive material, such as a metal, such as copper, cobalt, aluminum, gold, combinations thereof, etc. The interconnect structure 254 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0096] Conductive connectors 256 are shown, which may be located in and / or on the interconnect structure 254 of the wafer 200. For example, the conductive connectors 256 may be part of an upper metallization layer of the interconnect structure 254. The conductive connectors 256 may be formed of a metal such as copper, aluminum, etc., and may be formed by, for example, plating, etc. The conductive connectors 256 may be conductive posts, pads, etc. that make external connections.

[0097] The dielectric layer 258 is located in and / or on the interconnect structure 254. For example, the dielectric layer 258 can be an upper dielectric layer of the interconnect structure 254. The dielectric layer 258 laterally seals the conductive connector 256. The dielectric layer 258 can be an oxide, a nitride, a carbide, a polymer, etc., or a combination thereof. The dielectric layer 258 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. Initially, the dielectric layer 258 can bury the conductive connector 256 so that the top surface of the dielectric layer 258 is located above the top surface of the conductive connector 256. The conductive connector 256 can be exposed through the dielectric layer 258 by a removal process, which can be applied to various layers to remove excess material above the conductive connector 256. The removal process can be a planarization process, such as chemical mechanical polishing (CMP), etch back, a combination thereof, etc.

[0098] Wafer 300 may have a structure similar to that described for wafer 200, and the details are not repeated here. The materials of the components in wafer 300 may be found by referring to the same components in wafer 200, where the same components in wafer 200 begin with the number "2", which components correspond to the components in wafer 300 and have reference numbers beginning with the number "3". Conductive vias 362 may be formed through wafer 300 to allow external connections to be made to subsequently formed integrated circuit packages 30. Conductive vias 362 may be through-substrate vias (TSVs), such as through-silicon vias, etc. Conductive vias 362 extend through a substrate 352 of wafer 300 to be physically and electrically connected to a metallization layer of an interconnect structure 354 of wafer 300. Interconnect structure 354 is disposed above substrate 352 and an active device layer 353 formed in / or on substrate 352.

[0099] Further references Fig.17 , wafer 200 and wafer 300 are bonded so that the active device layers 253 / 353 face each other (e.g., are "face-to-face" bonded). The dielectric layer 258 of wafer 200 is bonded to the dielectric layer 358 of wafer 300 by dielectric-to-dielectric bonding without using any adhesive material (e.g., a die attach film), and the conductive connector 256 of wafer 200 is bonded to the conductive connector 356 of wafer 300 by metal-to-metal bonding without using any eutectic material (e.g., solder). Bonding may include pre-bonding and annealing. During pre-bonding, a small pressure is applied to press wafer 200 against wafer 300. Pre-bonding is performed at low temperature, such as room temperature, such as a temperature in the range of 15°C to 30°C, and after pre-bonding, dielectric layer 258 and dielectric layer 358 are bonded to each other. The bonding strength is then improved in a subsequent annealing step, wherein the dielectric layer 258 and the dielectric layer 358 are annealed at a high temperature, such as a temperature in the range of 140° C. to 500° C. After annealing, a bond, such as a molten bond, is formed that bonds the dielectric layer 258 and the dielectric layer 358. For example, the bond may be a covalent bond between the material of the dielectric layer 258 and the material of the dielectric layer 358. The conductive connector 256 and the conductive connector 356 are connected to each other in a one-to-one correspondence. The conductive connector 256 and the conductive connector 356 may be in physical contact after pre-bonding, or may be expanded to make physical contact during annealing. In addition, during annealing, the materials (e.g., copper) of the conductive connector 256 and the conductive connector 356 are mixed so that a metal-to-metal bond is also formed. Therefore, the resulting bond between the wafer 200 and the wafer 300 is a mixed bond including a dielectric-to-dielectric bond and a metal-to-metal bond.

[0100] exist Fig.18 In, previously in Fig.17The structure shown in FIG. 2 can be positioned so that wafer 200 is disposed above wafer 300. A laser annealing process 216 is then performed using a laser to peel substrate 252 from the topmost silicon layer (e.g., second silicon layer 214), interconnect structure 254, and wafer 300. Laser annealing process 216 can be similar to that previously described in Figure 4 The laser annealing process described in 61 and previously in Fig.14 The laser annealing process 216 may include the laser annealing process 186 described in Fig.18 The laser beam emitted from the laser is systematically moved (e.g., scanned) over the top surface of the substrate 252 shown. Due to the laser annealing process 216, an ablation threshold can be achieved within the peeling structure 210, which allows for effective material removal (e.g., by ablation) of the first silicon layer 214 (also referred to as the bottommost silicon layer) and portions of the first peeling layer 212 and the second peeling layer 212. In this manner, the substrate 252 is peeled away from the topmost silicon layer (e.g., the second silicon layer 214), the interconnect structure 254, and the wafer 300.

[0101] exist Fig.19 In the embodiment, a wet etching process 218A is performed to remove the remaining portion of the lift-off layer 212 (e.g., the first lift-off layer 212) on the first surface 219 of the substrate 252. In addition, a wet etching process 218B is performed to remove the remaining portion of the lift-off layer 212 (e.g., the second lift-off layer 212) on the first surface 220 of the topmost silicon layer (e.g., the second silicon layer 214). The wet etching processes 218A and 218B may include using hydrogen peroxide (H 2 O 2 ), deionized water or hydrofluoric acid (HF) as an etchant to remove the remaining portion of the lift-off layer 212 (e.g., the first lift-off layer 212) on the first surface 219 of the substrate 252 and the lift-off layer 212 (e.g., the second lift-off layer 212) on the first surface 220 of the topmost silicon layer (e.g., the second silicon layer 214). After performing the wet etching process 218A and the wet etching process 218B, a surface cleaning process may be performed on the surface of each of the substrate 252 and the topmost silicon layer (e.g., the second silicon layer 214). The surface cleaning process may include exposing the surface of each of the substrate 252 and the topmost silicon layer (e.g., the second silicon layer 214) to a solution including deionized water, ammonium hydroxide (NH 2 4 OH) and hydrogen peroxide (H 2 O 2 In an embodiment, the temperature of the solution during the surface cleaning process ranges from 40°C to 80°C.

[0102] Further references Fig.19After the wet etching process 218A, the wet etching process 218B, and the surface cleaning process have been performed, a first planarization process such as CMP may then be performed on the bottom surface of the substrate 352 to expose the conductive vias 362 of the wafer 300. A second planarization process may be performed on each of the first surface 219 of the substrate 252 and the first surface 220 of the topmost silicon layer (e.g., the second silicon layer 214). The second planarization process may include a grinding process, chemical mechanical polishing (CMP), a combination thereof, and the like.

[0103] Advantages can be achieved by forming a peeling structure 210 above a substrate 252 of a wafer 200, the peeling structure 210 including a plurality of peeling stacks 211. Each peeling stack 211 includes a peeling layer 212 and a corresponding silicon layer 214 above the peeling layer 212, wherein the peeling structure 210 includes 2 to 5 peeling stacks 211. For example, the peeling structure 210 may include a first peeling layer 212 above the substrate 252, a first silicon layer 214 above the first peeling layer 212, a second peeling layer 212 above the first silicon layer 214, and a second silicon layer 214 above the second peeling layer 212. Each peeling layer 212 may include germanium (Ge), silicon germanium (e.g., Si), or a plurality of other peeling layers. 1- x Ge x , wherein x is in the range of from 0.7 to 1), silicon carbide (SiC), boron- or phosphorus-doped silicon, boron- or phosphorus-doped silicon germanium, yttrium oxide (Y 2 O 3 ), cerium oxide (CeO 2 ), boron nitride (BN), gallium phosphide (GaP) or titanium nitride (TiN). Each peeling layer 212 has a thickness T8 in a range from 1 nm to 10 nm, and each silicon layer 214 has a thickness T9 in a range from 5 nm to 200 nm. After the wafer 200 is bonded to the wafer 300, a laser annealing process 216 is then performed using a laser, the laser operating in an infrared region having a wavelength in a range from 500 to 2500 nm, and the laser emitting a laser beam having a power output in a range from 500 mW to 5000 mW. The laser annealing process 216 causes ablation of the first silicon layer 214 and portions of the first peeling layer 212 and the second peeling layer 212, and further causes the substrate 252 to be peeled off from the topmost silicon layer (e.g., the second silicon layer 214), the interconnect structure 254 of the wafer 200, and the wafer 300.

[0104] These advantages include each lift-off layer 212 having a thickness T8 in a range from 1 nm to 10 nm, and each silicon layer 214 having a thickness T9 in a range from 5 nm to 200 nm, allowing one or more resonant cavities to be formed in the lift-off structure 210 (e.g., in the first silicon layer 214, the first lift-off layer 212, and the second lift-off layer 212) that match the wavelength of the infrared laser used during the laser annealing process 216 (e.g., similar to the previously described Figure 4 214 ). This allows for more efficient heating of the lift-off structure 210 during the laser annealing process 216, which allows for an ablation threshold to be achieved within the lift-off structure 210 and enables more efficient material removal (e.g., by ablation) of the first silicon layer 214 and portions of the first and second lift-off layers 212 and 212. This further enables the substrate 252 to be peeled off from the topmost silicon layer (e.g., the second silicon layer 214), the interconnect structure 254 of the wafer 200, and the wafer 300. This peeling of the substrate 252 from the topmost silicon layer (e.g., the second silicon layer 214), the interconnect structure 254 of the wafer 200, and the wafer 300 is achieved with minimal damage to the substrate 252 because the need to perform a trimming or thinning process on the substrate 252 to remove it from the wafers 200 and 300 is eliminated. In this way, the substrate 252 can be used for possible recycling and reuse in further semiconductor manufacturing operations (e.g., to form another CFET). Therefore, manufacturing costs can be reduced.

[0105] Fig. 20A contact pad 382 and a dielectric layer 380 are shown formed on the planarized bottom surface of the substrate 352 and the exposed conductive vias 362 of the wafer 300. The dielectric layer 380 may be an oxide, such as silicon oxide, PSG, BSG, BPSG, etc.; a nitride, such as silicon nitride, etc.; a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB)-based polymer, etc.; or a combination thereof. The dielectric layer 380 may be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD), etc. The contact pad 382 may be used to connect to other devices. In some embodiments, the contact pad 382 is a conductive bump suitable for use with a reflowable connector (such as a microbump) extending through the dielectric layer 380. In the illustrated embodiment, the contact pad 382 is formed to pass through the dielectric layer 380. As an example of forming contact pad 382, ​​an opening is formed in dielectric layer 380, and a seed layer is formed above and in the opening of dielectric layer 380. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including multiple sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, PVD, etc. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to contact pad 382. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating, etc. The conductive material can include metals, such as copper, nickel, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as using oxygen plasma, etc. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining portion of the seed layer and the conductive material form a contact pad 382.

[0106] After forming the contact pad 382, ​​a conductive connector 384 is formed on the contact pad 382. The conductive connector 384 can be a ball grid array (BGA) connector, a solder ball, a metal column, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), etc. The conductive connector 384 can include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 384 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 384 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on the top of the metal column. The metal cover layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process. The conductive connector 384 is electrically connected to the interconnect structure 254 of the wafer 200 through the conductive via 362 of the wafer 300 and the interconnect structure 354. The conductive connector 384 may be used to electrically connect the integrated circuit package 30 to an external device, such as a package substrate, etc.

[0107] Embodiments of the present disclosure have some advantageous features. Embodiments include forming a CFET, wherein, to form the CFET, a first superlattice (e.g., including an NFET channel region formed by a first semiconductor layer) is epitaxially grown over a first substrate (e.g., a first carrier wafer), and a second superlattice (e.g., including a PFET channel region formed by a second semiconductor layer) is epitaxially grown over a second substrate (e.g., a second carrier wafer). A peeling structure may be formed between the first substrate and the first superlattice or between the second substrate and the second superlattice. The first superlattice and the second superlattice are then bonded together. The peeling structure may include a multilayer stack of alternating silicon layers and peeling layers formed using chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The multilayer stack includes between 2 and 5 silicon layers and between 2 and 5 peeling layers. Each peeling layer may include germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), or the like. A laser annealing process may be performed to ablate portions of the peeling structure to peel the first substrate from the first superlattice, or to peel the second substrate from the second superlattice.

[0108] One or more embodiments disclosed herein may allow one or more resonant cavities to be formed in a peeling structure that match the wavelength of an infrared laser used during a laser annealing process. This allows an ablation threshold to be achieved within the peeling structure, resulting in partial ablation of the peeling structure. Ablation of a portion of the peeling structure allows the first substrate to be peeled from the first superlattice, or the second substrate to be peeled from the second superlattice. This peeling of the first substrate from the first superlattice or the peeling of the second substrate from the second superlattice is achieved with minimal damage to the first substrate or the second substrate. In this way, the first substrate or the second substrate can be used for possible recycling and reuse in further semiconductor manufacturing operations (e.g., to form another CFET). Therefore, manufacturing costs can be reduced. In addition, using a multilayer stack of alternating silicon layers and peeling layers formed using CVD or ALD to form a peeling structure produces better film quality for the silicon layer and the peeling layer, compared to if the silicon layer and the peeling layer are formed using other processes (e.g., a plasma process that produces plasma damage to the silicon layer and the peeling layer). Therefore, the quality of the epitaxial layer of the first superlattice or the second superlattice formed above the peeling structure is improved. In addition, the peeling structure includes materials selected based on their lattice parameters to achieve improved lattice matching with the first superlattice or the second superlattice. In this way, strain and defects at the interface between the first superlattice and the peeling structure or between the second superlattice and the peeling structure are reduced. This produces an improved bond between the first substrate and the first superlattice or between the second substrate and the second superlattice.

[0109] According to an embodiment, a method includes: forming a first lift-off structure over a first substrate, wherein forming the first lift-off structure includes: depositing a first lift-off layer over the first substrate; depositing a first silicon layer over the first lift-off layer; depositing a second lift-off layer over the first silicon layer; and depositing a second silicon layer over the second lift-off layer; epitaxially growing a first multilayer stack over the first lift-off structure; bonding the first multilayer stack to the second multilayer stack; and performing a first laser annealing process to ablate the first silicon layer and portions of the first lift-off layer and the second lift-off layer to lift the first substrate off the first multilayer stack. In an embodiment, the method also includes: patterning the second silicon layer, the first multilayer stack, and the second multilayer stack to form a fin, the fin including a plurality of lower nanostructures alternately stacked with the first pseudo nanostructure and a plurality of upper nanostructures located above the plurality of lower nanostructures, the plurality of upper nanostructures alternately stacked with the second pseudo nanostructure. In an embodiment, the method also includes: replacing the first pseudo nanostructure with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second pseudo nanostructure with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures. In an embodiment, performing the first laser annealing process includes scanning a laser beam emitted by a laser over a top surface of the first substrate, wherein the laser operates in an infrared region having a wavelength in a range from 500 to 2500 nm. In an embodiment, during the implementation of the first laser annealing process, the laser beam has a power output in a range from 500 mW to 5000 mW. In an embodiment, a resonant cavity is formed in a combination of the first silicon layer, the first peeling layer, and the second peeling layer, and wherein, during the implementation of the first laser annealing process, the laser interacts with the resonant cavity. In an embodiment, the thickness of each of the first peeling layer and the second peeling layer is in a range from 1 nm to 10 nm. In an embodiment, the thickness of the first silicon layer is in a range from 5 nm to 200 nm. In an embodiment, each of the first peeling layer and the second peeling layer includes germanium, silicon germanium, silicon carbide, boron or phosphorus doped silicon, boron or phosphorus doped silicon germanium, yttrium oxide, cerium oxide, boron nitride, gallium phosphide, or titanium nitride.

[0110] According to an embodiment, the method includes: depositing a first peeling layer over a first substrate; depositing a first silicon layer over the first peeling layer; depositing a second peeling layer over the first silicon layer; depositing a second silicon layer over the second peeling layer; epitaxially growing a first semiconductor layer and a second semiconductor layer over the second silicon layer; epitaxially growing a third semiconductor layer and a fourth semiconductor layer over the second substrate; depositing a first bonding layer over the second semiconductor layer; depositing a second bonding layer over the fourth semiconductor layer; bonding the first bonding layer to the second bonding layer to form a bonding layer; and after bonding the first bonding layer to the second bonding layer, ablating the first peeling layer, the first silicon layer, and the second peeling layer using a laser annealing process to peel the first substrate from the second silicon layer, the first semiconductor layer, and the second semiconductor layer. In an embodiment, the method also includes: patterning the third semiconductor layer, the fourth semiconductor layer, the bonding layer, the second semiconductor layer, and the first semiconductor layer to define a fin extending upward from the first substrate. In an embodiment, the method further includes: patterning a source / drain recess in the fin; forming a first source / drain in the source / drain recess; depositing a first isolation layer over the first source / drain; and forming a second source / drain in the source / drain recess over the first isolation layer. In an embodiment, a thickness of each of the first peeling layer and the second peeling layer is in a range from 1 nm to 10 nm. In an embodiment, the laser annealing process includes heating the first peeling layer, the first silicon layer, and the second peeling layer using a laser beam emitted from a laser. In an embodiment, the laser operates in an infrared region having a wavelength in a range from 500 to 2500 nm.

[0111] According to an embodiment, a method includes: forming a first lift-off structure over a first substrate, wherein the first lift-off structure includes a resonant cavity, and wherein the first lift-off structure includes: a first lift-off layer; a first semiconductor layer located over the first lift-off layer; and a second lift-off layer located over the first semiconductor layer; epitaxially growing a first multilayer stack over the first lift-off structure; bonding the first multilayer stack to the second multilayer stack; and performing a first laser annealing process using a laser beam having a wavelength matching a resonant frequency of the resonant cavity to ablate the first semiconductor layer and portions of the first lift-off layer and the second lift-off layer, and wherein performing the first laser annealing process causes the first substrate to be lifted off from the first multilayer stack. In an embodiment, the method also includes: patterning the first multilayer stack and the second multilayer stack to form a fin, the fin including a plurality of lower nanostructures alternately stacked with the first pseudo nanostructure and a plurality of upper nanostructures located over the plurality of lower nanostructures, the plurality of upper nanostructures alternately stacked with the second pseudo nanostructure; replacing the first pseudo nanostructure with a first gate stack, the first gate stack surrounding each of the plurality of lower nanostructures; and replacing the second pseudo nanostructure with a second gate stack, the second gate stack surrounding each of the plurality of upper nanostructures. In an embodiment, the first semiconductor layer comprises silicon, and wherein the thickness of the first semiconductor layer is in a range from 5 nm to 200 nm. In an embodiment, the first semiconductor layer comprises silicon, and wherein the thickness of the first semiconductor layer is in a range from 5 nm to 200 nm. In an embodiment, the thickness of each of the first peeling layer and the second peeling layer is in a range from 1 nm to 10 nm.

[0112] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: A first peeling structure is formed on the first substrate, wherein forming the first peeling structure comprises: depositing a first lift-off layer over the first substrate; depositing a first silicon layer over the first peeling layer; depositing a second lift-off layer over the first silicon layer; and depositing a second silicon layer over the second peeling layer; epitaxially growing a first multilayer stack over the first lift-off structure; bonding the first multilayer stack to a second multilayer stack; and A first laser annealing process is performed to ablate the first silicon layer and portions of the first and second lift-off layers to lift the first substrate off the first multi-layer stack.

2. The method according to claim 1, further comprising: The second silicon layer, the first multilayer stack, and the second multilayer stack are patterned to form a fin, the fin including a plurality of lower nanostructures alternately stacked with first pseudo-nanostructures and a plurality of upper nanostructures located above the plurality of lower nanostructures, the plurality of upper nanostructures alternately stacked with second pseudo-nanostructures.

3. The method according to claim 2, further comprising: replacing the first dummy nanostructure with a first gate stack surrounding each of the plurality of lower nanostructures; as well as The second dummy nanostructure is replaced with a second gate stack surrounding each of the plurality of upper nanostructures.

4. The method according to claim 1, wherein: Performing the first laser annealing process includes scanning a laser beam emitted by a laser over a top surface of the first substrate, wherein the laser operates in an infrared region having a wavelength in a range from 500 to 2500 nm.

5. The method according to claim 4, wherein: During the performing of the first laser annealing process, the laser beam has a power output ranging from 500 mW to 5000 mW.

6. The method according to claim 5, wherein: A resonant cavity is formed in a combination of the first silicon layer, the first exfoliation layer, and the second exfoliation layer, and wherein the laser interacts with the resonant cavity during the first laser annealing process.

7. The method according to claim 1, wherein: The thickness of each of the first peeling layer and the second peeling layer ranges from 1 nm to 10 nm.

8. The method according to claim 1, wherein: The thickness of the first silicon layer is in the range from 5 nm to 200 nm.

9. A method of forming a semiconductor device, comprising: depositing a first lift-off layer over the first substrate; depositing a first silicon layer over the first peeling layer; depositing a second lift-off layer over the first silicon layer; depositing a second silicon layer over the second peeling layer; epitaxially growing a first semiconductor layer and a second semiconductor layer on the second silicon layer; epitaxially growing a third semiconductor layer and a fourth semiconductor layer on the second substrate; depositing a first bonding layer over the second semiconductor layer; depositing a second bonding layer over the fourth semiconductor layer; bonding the first bonding layer to the second bonding layer to form a bonding layer; as well as After bonding the first bonding layer to the second bonding layer, the first lift-off layer, the first silicon layer, and the second lift-off layer are ablated using a laser annealing process to lift the first substrate off the second silicon layer, the first semiconductor layer, and the second semiconductor layer.

10. A method of forming a semiconductor device, comprising: A first lift-off structure is formed over a first substrate, wherein the first lift-off structure comprises a resonant cavity, and wherein the first lift-off structure comprises: first peeling layer; A first semiconductor layer located above the first peeling layer; and a second peeling layer, located above the first semiconductor layer; epitaxially growing a first multilayer stack over the first lift-off structure; bonding the first multilayer stack to a second multilayer stack; and A first laser annealing process is performed using a laser beam having a wavelength matched to a resonant frequency of the resonant cavity to ablate the first semiconductor layer and portions of the first and second peeling layers, and wherein the first laser annealing process is performed such that the first substrate is peeled off from the first multilayer stack.

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