Semiconductor device

Abstract

A semiconductor device includes: a semiconductor stack having a first surface and a second surface and including semiconductor layers having different compositions stacked therein, in which the semiconductor stack has a recess in the second surface and a through hole penetrating the semiconductor stack; a plurality of passive gate structures, wherein the plurality of passive gate structures are arranged on the second surface of the semiconductor stack body; a first conductivity type epitaxial pattern disposed in the through hole and connected to a first impurity region in the semiconductor stack; a second conductivity type epitaxial pattern disposed in the recess and connected to a second impurity region in the semiconductor stack; a first contact connected to the first conductivity type epitaxial pattern; and a second contact connected to the second conductivity type epitaxial pattern.

Description

Technical Field

[0001] Example embodiments of the present disclosure relate to a semiconductor device. Background Art

[0002] As the demand for high performance, speed and / or multifunctionality in semiconductor devices increases, the integration density of semiconductor devices also increases. In order to overcome the limitation of operating characteristics caused by the size reduction of planar metal oxide semiconductor field effect transistors (MOSFETs), efforts have been made to develop semiconductor devices including FinFETs, which include fin-shaped channels and gate-all-around type field effect transistors including nanosheets surrounded by gates. Summary of the invention

[0003] Example embodiments of the present disclosure provide a semiconductor device having improved electrical characteristics and reliability.

[0004] According to an example embodiment of the present disclosure, a semiconductor device includes: a semiconductor stack having a first surface and a second surface opposite to each other, including semiconductor layers with different components stacked in the semiconductor stack, and including at least one of a first conductive type impurity region and a second conductive type impurity region, wherein the semiconductor stack has a recess formed in the second surface and a through hole penetrating the semiconductor stack; a plurality of passive gate structures, the plurality of passive gate structures are arranged on the second surface of the semiconductor stack and spaced apart from each other, wherein each of the recess and the through hole is arranged between the plurality of passive gate structures; a first conductive type epitaxial pattern, the first conductive type epitaxial pattern is arranged in the through hole a first conductive type epitaxial pattern, the second conductive type epitaxial pattern being arranged in the recess and connected to the semiconductor stack; a first gap-filling insulating layer, the first gap-filling insulating layer being arranged on the first conductive type epitaxial pattern adjacent to the first surface of the semiconductor stack in the through hole; a second gap-filling insulating layer, the second gap-filling insulating layer being arranged between the multiple passive gate structures on the second surface of the semiconductor stack; a first contact, the first contact penetrating the first gap-filling insulating layer and connected to the first conductive type epitaxial pattern; and a second contact, the second contact penetrating the second gap-filling insulating layer and connected to the second conductive type epitaxial pattern.

[0005] According to an example embodiment of the present disclosure, a semiconductor device includes: a semiconductor stack, the semiconductor stack including: an intermediate semiconductor layer; an upper stack, the upper stack having a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on an upper surface of the intermediate semiconductor layer; a lower stack, the lower stack having a first lower semiconductor layer and a second lower semiconductor layer alternately stacked on a lower surface of the intermediate semiconductor layer; and a first conductive type impurity region and a second conductive type impurity region arranged horizontally; a plurality of passive gate structures, the plurality of passive gate structures being arranged at a certain interval on the lower surface of the semiconductor stack; at least one recess, the at least one recess being arranged in the plurality of between at least one pair of adjacent passive gate structures among the multiple passive gate structures, and penetrating the lower stack from the lower surface of the semiconductor stack; at least one through hole, the at least one through hole is arranged between at least one pair of adjacent passive gate structures among the multiple passive gate structures, and penetrates the semiconductor stack; at least one first conductive type epitaxial pattern, the at least one first conductive type epitaxial pattern is arranged in the at least one through hole and connected to the upper stack of the semiconductor stack; and at least one second conductive type epitaxial pattern, the at least one second conductive type epitaxial pattern is arranged in the at least one recess and connected to the lower stack of the semiconductor stack.

[0006] According to an example embodiment of the present disclosure, a semiconductor device includes a first device region and a second device region that are horizontally arranged, wherein the first device region includes: a channel structure, the channel structure includes an insulating isolation pattern, a first semiconductor pattern, and a second semiconductor pattern, the first semiconductor pattern is vertically stacked and spaced apart from each other on an upper surface of the insulating isolation pattern, and the second semiconductor pattern is vertically stacked and spaced apart from each other on a lower surface of the insulating isolation pattern; a pair of first source / drain patterns, the pair of first source / drain patterns are arranged on both sides of the channel structure in a first direction and are respectively connected to both sides of the first semiconductor pattern; a pair of second source / drain patterns, the pair of second source / drain patterns are arranged on both sides of the channel structure in the first direction and are respectively connected to both sides of the second semiconductor pattern; a first gate structure, the first gate structure extends in a second direction intersecting the first direction and surrounds the first semiconductor pattern; and a second gate structure, the second gate structure intersects with the lower surface of the channel structure, extends in the second direction, and surrounds the second semiconductor pattern, and Wherein, the second device area includes: a semiconductor stack, which is arranged at a height corresponding to the height of the channel structure, and includes an upper stack and a lower stack, the upper stack has a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on the upper surface of the middle semiconductor layer, and the lower stack has a first lower semiconductor layer and a second lower semiconductor layer alternately stacked on the lower surface of the middle semiconductor layer, wherein the semiconductor stack includes a first conductive type impurity region and a second conductive type impurity region arranged in a horizontal direction; a plurality of passive gate structures, wherein the plurality of passive gate structures are arranged on the lower surface of the semiconductor stack; a first conductive type epitaxial pattern, wherein the first conductive type epitaxial pattern is arranged in a through hole of the semiconductor stack penetrating between adjacent passive gate structures among the plurality of passive gate structures, and is connected to the upper stack; and a second conductive type epitaxial pattern, wherein the second conductive type epitaxial pattern is arranged in a recess and is connected to the lower stack, wherein the recess is formed on the lower surface of the semiconductor stack between other adjacent passive gate structures among the plurality of passive gate structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects, features and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a plan view showing a semiconductor device according to an example embodiment of the present disclosure;

[0009] FIG. 2A to FIG. 2CThe diagrams are respectively taken along lines II', II1-II1' and II2-II2'. Figure 1 A cross-sectional view of a first device region A of a semiconductor device in FIG.

[0010] Figure 3A and Figure 3B The diagrams are taken along lines III-III' and IV-IV', respectively. Figure 1 A cross-sectional view of a second device region B of a semiconductor device in FIG.

[0011] Figure 4A is a cross-sectional view showing a first device region of a semiconductor device taken along line II' according to an example embodiment of the present disclosure;

[0012] Figure 4B is a cross-sectional view showing a second device region of a semiconductor device taken along line III-III' according to an example embodiment of the present disclosure;

[0013] Figure 5A and Figure 5B are a plan view and a lateral cross-sectional view respectively showing a semiconductor device (eg, a circuit device) according to an example embodiment of the present disclosure;

[0014] Fig. 6A and Figure 6B is a cross-sectional view showing a semiconductor device (eg, a circuit device) according to an example embodiment of the present disclosure;

[0015] Fig. 7A and Figure 7B are a plan view and a lateral cross-sectional view respectively showing a semiconductor device (eg, a circuit device) according to an example embodiment of the present disclosure;

[0016] Figure 8 is a lateral cross-sectional view showing a semiconductor device (eg, a circuit device) according to an example embodiment of the present disclosure;

[0017] Fig. 9A and Fig. 9B are a plan view and a lateral cross-sectional view respectively showing a semiconductor device (eg, a capacitor) according to an example embodiment of the present disclosure;

[0018] Fig.10 is a lateral cross-sectional view showing a semiconductor device (eg, a capacitor) according to an example embodiment of the present disclosure;

[0019] FIG. 11A to FIG. 11I is a cross-sectional view showing a part of a process of a method of manufacturing a semiconductor device according to an example embodiment of the present disclosure;

[0020] FIG. 12A to FIG. 12Gis a cross-sectional view showing another part of the process of the method of manufacturing a semiconductor device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0021] Hereinafter, embodiments of the present disclosure will be described below with reference to the accompanying drawings. The same reference numerals refer to the same elements throughout.

[0022] It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on another element," it can be directly connected or coupled to another element or directly on another element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "contacting" or "in contact with" another element (or any form of the word "contacting"), there are no intervening elements at the point of contact.

[0023] Terms such as "same," "equal," "planar," or "coplanar" as used herein when referring to orientation, layout, position, shape, size, quantity, or other measurement do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measurement, but are intended to cover nearly the same orientation, layout, position, shape, size, quantity, or other measurement within an acceptable range of variation that may occur, for example, due to manufacturing processes. The term "substantially" may be used herein to emphasize this meaning unless the context or other statements indicate otherwise.

[0024] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," "on," and the like may be used herein to describe the relationship of one element or feature to other elements or features as shown. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is flipped, an element described as being "below" or "beneath" other elements or features will be oriented as being "above" the other elements or features. Thus, the term "below" may include both above and below orientations.

[0025] Figure 1 is a plan view illustrating a semiconductor device according to example embodiments. FIG. 2A to FIG. 2C The diagrams are respectively taken along lines II', II1-II1' and II2-II2'. Figure 1 sectional view of a first device region A of a semiconductor device in FIG. Figure 3A and Figure 3B The diagrams are taken along lines III-III' and IV-IV', respectively. Figure 1 sectional view of a second device region B of a semiconductor device in FIG.

[0026] refer to Figure 1 , the semiconductor device in the example embodiment may include a first device region A and a second device region B arranged in a horizontal direction (e.g., an X direction or a Y direction). Herein, the first device region A may also be referred to as a "logic region" implementing the logic device 100A, and the second device region B may also be referred to as a "peripheral circuit region" implementing the circuit device 100B.

[0027] refer to Figure 1 and FIG. 2A to FIG. 2C The logic device 100A of the semiconductor device 100 in the example embodiment may include a channel structure CS extending longitudinally in a first direction (e.g., X direction), and a first gate structure GS1 and a second gate structure GS2 intersecting a region of the channel structure CS and extending longitudinally in a second direction (e.g., Y direction) intersecting the first direction (e.g., X direction).

[0028] Specifically, refer to Figure 2A , the channel structure CS may include an insulating isolation pattern 160, first semiconductor patterns 131 stacked and spaced apart from each other in a third direction (e.g., Z direction) on an upper surface of the insulating isolation pattern 160, and second semiconductor patterns 132 stacked and spaced apart from each other in a third direction (e.g., Z direction) on a lower surface of the insulating isolation pattern 160. Among the second semiconductor patterns 132, the insulating isolation pattern 160 may be disposed on the uppermost semiconductor pattern, and the first semiconductor patterns 131 may be stacked and spaced apart from each other on the insulating isolation pattern 160. The insulating isolation pattern 160 may be arranged to overlap the first channel layer 131 and the second channel layer 132 in a third direction (e.g., Z direction), i.e., a vertical direction. Hereinafter, the terms "first semiconductor pattern 131" and "first channel layer 131" may be used interchangeably, and the terms "second semiconductor pattern 132" and "second channel layer 132" may be used interchangeably.

[0029] As described above, the first semiconductor pattern 131 and the second semiconductor pattern 132 may be isolated from each other by the insulating isolation pattern 160, and each of the first semiconductor pattern 131 and the second semiconductor pattern 132 may be provided as an independent channel structure. For example, the first semiconductor pattern 131 may be included in the first channel structure CS1, and the second semiconductor pattern 132 may be included in the second channel structure CS2.

[0030] In some example embodiments, a plurality of first semiconductor patterns 131 (e.g., two or three first semiconductor patterns) may be provided. For example, the first semiconductor pattern 131 may be formed of, or include, silicon (Si) or silicon germanium (SiGe). Similarly, a plurality of second semiconductor patterns 132 (e.g., two or three second semiconductor patterns) may be provided. For example, the second semiconductor pattern 132 may be formed of, or include silicon (Si) or silicon germanium (SiGe). In some example embodiments, the first semiconductor pattern 131 and the second semiconductor pattern 132 may be silicon semiconductor patterns.

[0031] The insulating isolation pattern 160 may include an insulating material and may be formed of, for example, at least one of silicon nitride, silicon oxynitride, or silicon carbonitride, or include at least one of silicon nitride, silicon oxynitride, or silicon carbonitride. The insulating isolation pattern 160 may be a single insulating material layer, but in some example embodiments, the insulating isolation pattern 160 may include a plurality of insulating material layers.

[0032] The gate structure employed in example embodiments may include a first gate structure GS1 for the first channel structure CS1 and a second gate structure GS2 for the second channel structure CS2 .

[0033] refer to Figure 1 , Figure 2A and Figure 2C The first gate structure GS1 may intersect a region of the first channel structure CS1, may extend longitudinally in the second direction (e.g., the Y direction), and may respectively surround the first semiconductor patterns 131. Similarly, the second gate structure GS2 may intersect a region of the second channel structure CS2, may extend longitudinally in the second direction (e.g., the Y direction), and may surround each of the second semiconductor patterns 132.

[0034] Specifically, refer to Figure 2A and Figure 2C, the first gate structure GS1 adopted in the example embodiment may include a first gate electrode 145A surrounding the first semiconductor pattern 131 and a first gate insulating layer 142A disposed between the first semiconductor pattern 131 and the first gate electrode 145A. In addition, the first gate structure GS1 may include: a first gate spacer 141A disposed on the uppermost first semiconductor pattern 131 and disposed on both sidewalls of the upper portion of the first gate electrode 145A; and a first gate capping layer 147A disposed on the upper portion between the first gate spacers 141A. The first gate capping layer 147A may contact the upper surface of the first gate electrode 145A, and the first gate electrode 145A may surround and contact the surface of the first gate insulating layer 142A. In some example embodiments, the first gate insulating layer 142A may be formed between the first semiconductor pattern 131 and the first gate electrode 145A, may also extend in the second direction (e.g., the Y direction) along the upper surface of the insulating isolation pattern 160, and may be formed on the inner sidewall of the first gate spacer 141A.

[0035] Similarly, the second gate structure GS2 employed in the example embodiment may include a second gate electrode 145B surrounding the second semiconductor pattern 132, a second gate insulating layer 142B disposed between the second semiconductor pattern 132 and the second gate electrode 145B, a second gate spacer 141B disposed on both sidewalls of the second gate electrode 145B, and a second gate capping layer 147B disposed on an electrode portion between the second gate spacers 141 B. The second gate capping layer 147B may contact a lower surface of the second gate electrode 145B, and the second gate electrode 145B may surround and contact a surface of the second gate insulating layer 142B.

[0036] In example embodiments, similar to the process of forming the second gate structure GS2, the first gate structure GS1 may be configured to be formed in a backside process (eg, Fig.12F and Figure 12G ). That is, Figure 2A As shown, the first gate structure GS1 may have a structure similar to the second gate structure GS2 (eg, a vertically symmetrical structure). Alternatively, in another exemplary embodiment, when the front process (eg, Fig.12D and Fig.12E ), when forming the first gate structure GS1 in the embodiment of the present invention, the portion disposed on the uppermost first semiconductor pattern 131 (for example, the upper portion of the first gate electrode 145A, the portion of the first gate insulating layer 142A, and the first gate spacer 141A) may not be provided (see Figure 5A ).

[0037] The first gate electrode 145A and the second gate electrode 145B employed in the example embodiments may include different conductive materials. For example, the first gate electrode 145A and the second gate electrode 145B may be formed of at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC, or include at least one of W, Ti, Ta, Mo, TiN, TaN, WN, TiON, TiAlC, TiAlN, and TaAlC. In some example embodiments, the first gate electrode 145A and the second gate electrode 145B may be formed of a semiconductor material such as doped polysilicon, or include a semiconductor material such as doped polysilicon. At least one of the first gate electrode 145A and the second gate electrode 145B may include a multilayer structure formed of different materials.

[0038] The first gate insulating layer 142A and the second gate insulating layer 142B may include different dielectric materials. For example, the first gate insulating layer 142A and the second gate insulating layer 142B may be formed of or include oxide, nitride, or high-κ material. High-κ material may refer to a dielectric constant higher than that of silicon oxide (SiO 2 ) dielectric material with a dielectric constant of . The high-κ material can be, for example, aluminum oxide (Al 2 O 3 ), Tantalum Oxide (Ta 2 O 3 ), titanium oxide (TiO 2 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), zirconium oxide silicon (ZrSi x O y ), hafnium oxide (HfO 2 ), Hafnium Silicon Oxide (HfSi x O y ), lanthanum oxide (La 2 O 3 ), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), Hafnium Aluminum Oxide (HfAl x O y ) and praseodymium oxide (Pr 2 O 3 ).

[0039] The first gate spacer 141A and the second gate spacer 141B may include the same insulating material or partially different insulating materials. For example, the first gate spacer 141A and the second gate spacer 141B may be formed of at least one of silicon oxide, silicon nitride and silicon oxynitride, or include at least one of silicon oxide, silicon nitride and silicon oxynitride. In some example embodiments, at least one of the first gate spacer 141A and the second gate spacer 141B may include a multilayer structure formed of different materials. The first gate capping layer 147A and the second gate capping layer 147B may be formed of, for example, silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbon nitride, or include, for example, silicon nitride, silicon oxynitride, silicon carbonitride or silicon carbon nitride.

[0040] The logic device 100A in the example embodiment may include a pair of first source / drain patterns 150A disposed on both sides of the first channel structure CS1 in the first direction (e.g., X direction), and a pair of second source / drain patterns 150B disposed on both sides of the second channel structure CS2 in the first direction (e.g., X direction). The pair of first source / drain patterns 150A may be connected to both sides of the first semiconductor pattern 131, and the pair of second source / drain patterns 150B may be connected to both sides of the second semiconductor pattern 132. The first source / drain patterns 150A and the second source / drain patterns 150B may be arranged to overlap each other in a vertical third direction (e.g., Z direction).

[0041] The first source / drain pattern 150A may include epitaxial growth from both side surfaces of the first channel layer 131. Similarly, the second source / drain pattern 150B may include epitaxial growth from both side surfaces of the second channel layer 132.

[0042] The first source / drain pattern 150A and the second source / drain pattern 150B may include a semiconductor epitaxial layer such as silicon (Si). The first source / drain pattern 150A and the second source / drain pattern 150B may include impurities of different types and / or concentrations. In some example embodiments, the first source / drain pattern 150A may include an epitaxial layer doped with first conductive type impurities, and the second source / drain pattern 150B may include an epitaxial layer doped with second conductive type impurities.

[0043] For example, the first source / drain pattern 150A may be formed of silicon (Si) doped with N-type impurities, or include silicon (Si) doped with N-type impurities. The second source / drain pattern 150B may be formed of silicon or silicon germanium (SiGe) doped with P-type impurities, or include silicon or silicon germanium (SiGe) doped with P-type impurities. Therefore, the cross-sectional surfaces of the first source / drain pattern 150A and the second source / drain pattern 150B in the second direction (e.g., the Y direction) may have different shapes. For example, the cross-sectional surface of the first source / drain pattern 150A may have a polygonal shape with a gentle angle. The cross-sectional surface of the second source / drain pattern 150B may have a pentagonal shape (see Figure 2B ).

[0044] The logic device 100A in the example embodiment may include a multi-layer insulation structure in a space in which the first source / drain pattern 150A and the second source / drain pattern 150B are disposed. Figure 2B As shown, the multi-layer insulation structure may include a first gap-filling insulation layer 180 and a second gap-filling insulation layer 190, and an isolation insulation layer 170 disposed between the first gap-filling insulation layer 180 and the second gap-filling insulation layer 190. FIG. 11A to FIG. 11I and FIG. 12A to FIG. 12G ),exist Figure 2B In a state where the cross-sectional surface in FIG. 1 is reversed, a first gap-filling insulating layer 180, an isolation insulating layer 170, and a second gap-filling insulating layer 190 may be sequentially formed. The first gap-filling insulating layer 180 may have a surface substantially coplanar with an upper surface of the first source / drain pattern 150A. The isolation insulating layer 170 may be formed to cover the first source / drain pattern 150A located on the first gap-filling insulating layer 180. The second gap-filling insulating layer 190 may be formed to cover the second source / drain pattern 150B located on the isolation insulating layer 170. In example embodiments, the isolation insulating layer 170 may contact the first gap-filling insulating layer 180 and the second gap-filling insulating layer 190.

[0045] The first gap-filling insulating layer 180 and the second gap-filling insulating layer 190 may be silicon oxide. For example, the first gap-filling insulating layer 180 and the second gap-filling insulating layer 190 may be spin-on hardmask (SOH), flowable oxide (FOX), tonn silazen (TOSZ), undoped silica glass (USG), borosilica glass (BSG), phosphosilaca glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetra ethyl ortho silicate (PETEOS), fluoride silicate glass (FSG), high density plasma (HDP) oxide, plasma enhanced oxide (PEOX), flowable CVD (FCVD), or a combination thereof. The first gap-filling insulating layer 180 and the second gap-filling insulating layer 190 may be formed using a chemical vapor deposition (CVD), a flowable CVD (FCVD) process, or a spin coating process.

[0046] The isolation insulating layer 170 is provided to isolate the first source / drain pattern 150A and the second source / drain pattern 150B, and may include an insulating material that may be the same as or similar to the first gap-filling insulating layer 180 and the second gap-filling insulating layer 190. For example, the isolation insulating layer 170 may include silicon oxide, silicon oxynitride, silicon carbonitride, or silicon nitride.

[0047] In some example embodiments, the isolation insulating layer 170 may be relatively conformally formed using a process such as atomic layer deposition (ALD). In this case, the isolation insulating layer 170 may be relatively conformally formed on an upper surface of the first gap-filling insulating layer 180 along a surface of the first source / drain pattern 150A.

[0048] The logic device 100A in example embodiments may further include a first upper contact 210A connected to the first source / drain pattern 150A and a first lower contact 220A connected to the second source / drain pattern 150B. The logic device 100A may further include a contact (not shown) connected to the first gate electrode 145A or the second gate electrode 145B.

[0049] The first upper contact 210A may penetrate the first gap-filling insulating layer 180 and may be connected to the first source / drain pattern 150A, and the first lower contact 220A may penetrate the second gap-filling insulating layer 190 and may be connected to the second source / drain pattern 150B. For example, the first upper contact 210A may contact the first source / drain pattern 150A, and the first lower contact 220A may contact the second source / drain pattern 150B. In example embodiments, the first upper contact 210A and the first lower contact 220A may include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru), and molybdenum (Mo).

[0050] Thus, the logic device 100A in the example embodiment may include a stacked upper transistor and a lower transistor. The upper transistor may include a first channel structure CS1, a first gate structure GS1, and a first source / drain pattern 150A, and the lower transistor may include a second channel structure CS2, a second gate structure GS2, and a second source / drain pattern 150B. Each of the upper transistor and the lower transistor may be a multi-bridge channel FET (MBCFET). TM ). The upper transistor may be configured as one of an N-type MOSFET and a P-type MOSFET, and the lower transistor may be the other of a P-type MOSFET and an N-type MOSFET. In an example embodiment, each of the upper transistors may be an N-type MOSFET, and each of the lower transistors may be a P-type MOSFET.

[0051] As described above, the semiconductor device 100 in the example embodiment may include a first device region A and a second device region B disposed in different regions in a horizontal direction. The second device region B may include a circuit device 100B included in a peripheral circuit. Since the circuit device 100B in the example embodiment is formed by a series of processes combined with the process of forming the logic device 100A described above, these components may be interrelated. FIG. 11A to FIG. 11I and FIG. 12A to FIG. 12G The manufacturing process is described in more detail.

[0052] refer to Figure 1 , Figure 3A and Figure 3B, the circuit device 100B of the semiconductor device 100 in the example embodiment may include: a semiconductor stack body SL in which semiconductor layers of different compositions are stacked; and a plurality of passive gate structures NG disposed on a lower surface of the semiconductor stack body SL and spaced apart from each other.

[0053] The semiconductor stack SL may be provided as a semiconductor bulk structure to form the circuit device 100B. The semiconductor stack SL may include at least one of a first conductive type impurity region W1 and a second conductive type impurity region W2. In example embodiments, the semiconductor stack SL may include a first conductive type impurity region W1 and a second conductive type impurity region W2 surrounding the first conductive type impurity region W1. For example, in a plan view, the second conductive type impurity region W2 may surround a side surface of the first conductive type impurity region W1.

[0054] In an example embodiment, each of the plurality of passive gate structures NG may correspond to the second gate structure GS2, but may be understood as a dummy structure that does not participate in driving. The plurality of passive gate structures NG employed in the example embodiment may have a structure similar to a portion of the second gate structure GS2 (a portion disposed below the second channel structure CS2), and may be formed of the same material. Specifically, each of the plurality of passive gate structures NG may include: a second gate electrode 145B extending in a second direction (e.g., Y direction) on the lower surface of the semiconductor stack SL; a second gate insulating layer 142B disposed between the lower surface of the semiconductor stack SL and the second gate electrode 145B; a second gate spacer 141B disposed on both side walls of the second gate electrode 145B; and a second gate covering layer 147B disposed on the second gate electrode 145B between the second gate spacers 141B.

[0055] The semiconductor stacked body SL employed in example embodiments may have a semiconductor stacked body ( Fig.11A The structure corresponding to SL in .

[0056] like Figure 3A and Figure 3BAs shown, the semiconductor layer may include: an intermediate semiconductor layer 125L; an upper stack SL1 including a first upper semiconductor layer 121L and a second upper semiconductor layer 131L alternately stacked on an upper surface of the intermediate semiconductor layer 125L; and a lower stack SL2 including a first lower semiconductor layer 122L and a second lower semiconductor layer 132L alternately stacked on a lower surface of the intermediate semiconductor layer 125L. The first upper semiconductor layer 121L may include an uppermost first upper semiconductor layer 121L'.

[0057] Each of the second upper semiconductor layers 131L may correspond to the first semiconductor pattern 131 included in the channel of the logic device 100A. That is, each of the second upper semiconductor layers 131L may include a material layer substantially the same as that of the first semiconductor pattern 131, and may have substantially the same thickness. Similarly, the second lower semiconductor layers 132L may correspond to the second semiconductor patterns 132 included in the channel of the logic device 100A, respectively. For example, each of the second lower semiconductor layers 132L may include a material layer substantially the same as that of the second semiconductor pattern 132, and may have substantially the same thickness. However, in a semiconductor stack, a portion of the components (e.g., Ge) may diffuse during a process, so that the boundaries of the semiconductor layers and the distribution of the portion of the components may change.

[0058] In addition, the first upper semiconductor layer 121L and the first lower semiconductor layer 122L may correspond to the first sacrificial pattern and the second sacrificial pattern (eg, Fig.11A and Fig. 11B The first sacrificial layer 121L and the second sacrificial layer 122L in the middle semiconductor layer 125L may correspond to the middle sacrificial layer (eg, Fig.11A and Fig. 11B The middle sacrificial layer 125L in the channel structure CS1 is formed to form insulating isolation patterns 160 between the first channel structure CS1 and the second channel structure CS2, respectively.

[0059] In some example embodiments, the thickness t1 of the intermediate semiconductor layer 125 may be greater than the thickness of each of the first and second upper semiconductor layers 121L and 131L or each of the first and second lower semiconductor layers 122L and 132L.

[0060] In some example embodiments, the lower stack SL2 may be disposed such that the first lower semiconductor layer 122L and the second lower semiconductor layer 132L may be disposed at least as the uppermost layer (ie, a layer in contact with the intermediate semiconductor layer 125) and the lowermost layer of the lower stack SL2, respectively.

[0061] Alternatively, the upper stack SL1 may be arranged so that the first upper semiconductor layers 121L' and 121L may be at least set as the uppermost layer and the lowermost layer of the upper stack SL1. Here, the thickness t2 of the first upper semiconductor layer 121L' as the uppermost layer may be greater than each of the thicknesses of the other first upper semiconductor layers 121L.

[0062] In example embodiments, the lower surface of the semiconductor stacked body SL may have a channel structure (eg, Figure 2A The height of the lower surface of the channel structure CS in the semiconductor stack SL may substantially correspond to the height of the lower surface of the channel structure CS in the semiconductor stack SL. Figure 2A The height of the upper surface of the channel structure CS in the semiconductor stack SL is higher than the thickness t2 of the first upper semiconductor layer 121' (ie, the uppermost layer). In other words, the thickness T of the semiconductor stack SL may be greater than the channel structure (eg, Figure 2A The height H of the channel structure CS in FIG. 1 is greater than the thickness t2 of the first upper semiconductor layer 121 ′ (ie, the uppermost layer).

[0063] In example embodiments, semiconductor layers of different compositions may have different germanium composition ratios (e.g., 0 to 60%). For example, the second upper semiconductor layer 131L and the second lower semiconductor layer 132L may include silicon, and the first upper semiconductor layer 121L, the first lower semiconductor layer 122L, and the intermediate semiconductor layer 125L may include silicon germanium. The germanium concentration of the intermediate semiconductor layer 125L may be greater than the germanium concentration of each of the first upper semiconductor layer 121L and the first lower semiconductor layer 122L.

[0064] In example embodiments, the germanium concentration of the first lower semiconductor layer 122L may be greater than the germanium concentration of each of the first upper semiconductor layers 121L. However, example embodiments thereof are not limited thereto, and the first upper semiconductor layer 121L and the first lower semiconductor layer 122L may have the same germanium concentration (eg, see Figure 5A and Figure 5B ).

[0065] The semiconductor stack SL may have at least one recess R1 and R2 formed on the lower surface and at least one through hole TH penetrating the semiconductor stack SL. The at least one recess R1 and R2 may be disposed between at least one pair of adjacent passive gate structures among the plurality of passive gate structures NG, and may be formed to a depth penetrating the lower stack SL2. The at least one through hole TH may be disposed between at least one pair of other adjacent passive gate structures among the plurality of passive gate structures NG. In example embodiments, the semiconductor stack SL may include two recesses R1 and R2 and a single through hole TH.

[0066] refer to Figure 3A and Figure 3B , the circuit device 100B in example embodiments may be configured as a PNP device having the semiconductor stacked body SL, the first conductive type epitaxial pattern 150E1 , and the two second conductive type epitaxial patterns 150E2 a and 150E2 b .

[0067] As described above, the semiconductor stack SL may include a first conductive type impurity region W1 and a second conductive type impurity region W2 surrounding the first conductive type impurity region W1. The first conductive type impurity region W1 may be configured as an N-type impurity region, and the second conductive type impurity region W2 may be configured as a P-type impurity region.

[0068] The first conductive type epitaxial pattern 150E1 and the second conductive type epitaxial patterns 150E2 a and 150E2 b may be epitaxial layers grown in the same process as forming the first source / drain pattern 150A and the second source / drain pattern 150B of the logic device 100A, respectively.

[0069] Specifically, the first conductive type epitaxial pattern 150E1 may be formed together with the first source / drain pattern 150A of the logic device 100A, and may include an epitaxial layer of the same material. In addition, the first conductive type epitaxial pattern 150E1 and the first source / drain pattern 150A may be disposed at substantially the same height. Similarly, each of the second conductive type epitaxial patterns 150E2a and 150E2b may be formed together with the second source / drain pattern 150B of the logic device 100A, and may include an epitaxial layer of the same material. In addition, the second conductive type epitaxial patterns 150E2a and 150E2b and the second source / drain pattern 150B may be disposed at substantially the same height.

[0070] The first and second recesses R1 and R2 and the through hole TH may define a region in which one first conductive type epitaxial pattern 150E1 and two second conductive type epitaxial patterns 150E2a and 150E2b are formed. In example embodiments, the first and second recesses R1 and R2 may be disposed in the first conductive type impurity region W1 and the second conductive type impurity region W2, respectively, and the through hole TH may be disposed in the first conductive type impurity region W1 between the first and second recesses R1 and R2.

[0071] The first conductive type epitaxial pattern 150E1 may be disposed in the through hole TH, and the second conductive type epitaxial patterns 150E2a and 150Eb may be disposed in the first recess R1 and the second recess R2, respectively. The first conductive type epitaxial pattern 150E1 may be disposed in the through hole TH at a height higher than that of the second conductive type epitaxial patterns 150E2a and 150E2b.

[0072] In example embodiments, the first conductive type epitaxial pattern 150E1 may be an N-type semiconductor pattern similar to the first source / drain pattern 150A, and the second conductive type epitaxial patterns 150E2a and 150E2b may be P-type semiconductor patterns similar to the second source / drain pattern 150B.

[0073] With this arrangement, Figure 3A As shown, the circuit device 100B in the example embodiment may be implemented as a PNP bipolar transistor including a second conductivity type epitaxial pattern 150E2a as an emitter, a first conductivity type epitaxial pattern 150E1 as a base, and a second conductivity type epitaxial pattern 150E2b as a collector.

[0074] As described above, the recesses R1 and R2 and the through hole TH may define an area in which the first conductive type epitaxial pattern 150E1 and the second conductive type epitaxial patterns 150E2a and 150E2b are formed. In addition to designing the impurity regions of the semiconductor stack SL, various circuit devices may be implemented by configuring the positions of the first and second recesses R1 and R2 and the through hole TH.

[0075] refer to Figure 3A and Figure 3B , the circuit device 100B in example embodiments may include an isolation insulating layer 170 , a first gap-filling insulating layer 180 , and a second gap-filling insulating layer 190 .

[0076] The isolation insulating layer 170 may be disposed between the bottom surfaces of the first recess R1 and the second recess R2 and the second conductive type epitaxial patterns 150E2a and 150E2b. The isolation insulating layer 170 may contact the second conductive type epitaxial patterns 150E2a and 150E2b. The isolation insulating layer 170 may be formed by the same process as the process of forming the isolation insulating layer 170 of the logic device 100A (see Fig.11H ). The first gap-filling insulating layer 180 may be disposed on the first conductive type epitaxial pattern 150E1 in the through hole TH. The first gap-filling insulating layer 180 may contact the first conductive type epitaxial pattern 150E1. For example, the first gap-filling insulating layer 180 may be disposed on the first conductive type epitaxial pattern 150E1 adjacent to the upper surface of the semiconductor stack SL in the through hole TH. The second gap-filling insulating layer 190 may be disposed between the plurality of passive gate structures NG on the lower surface of the semiconductor stack SL. In example embodiments, the second gap-filling insulating layer 190 may partially fill the through hole TH from the lower surface of the semiconductor stack SL to the first conductive type epitaxial pattern 150E1. The second gap-filling insulating layer 190 may contact the first conductive type epitaxial pattern 150E1.

[0077] The circuit device 100B in example embodiments may include a cover structure including an electrode material layer 145L and an insulating cover layer 147L sequentially disposed on an upper surface of the semiconductor stacked body SL.

[0078] The electrode material layer 145L and the insulating cover layer 147L may be provided as a layer structure, but may be formed together in a process of forming the first gate electrode 145A and the first gate cover layer 147A of the logic device 100A. The electrode material layer 145L may include the same material as that of the first gate electrode 145A. In addition, the insulating cover layer 147L may include the same material as that of the first gate cover layer 147A.

[0079] In example embodiments, the second gate spacer 141A' and the second gate insulating layer 142A' may be disposed between the capping structure and the first gap-filling insulating layer 180. The second gate spacer 141A' and the second gate insulating layer 142A' of the circuit device 100B may be formed together in a process of forming the second gate spacer 141A and the second gate insulating layer 142A of the logic device 100A. The second gate spacer 141A' may include the same material as that of the second gate spacer 141A. In addition, the second gate insulating layer 142A may include the same material as that of the second gate insulating layer 142A'. In some example embodiments, a portion of the components associated with the first gate structure GS1 may not be included in the circuit device. For example, in a process of forming the second gate insulating layer 142A, the second gate insulating layer 142A' may not be provided by masking the second device region B (see Fig. 9B ).

[0080] The circuit device 100B in example embodiments may further include a second upper contact 210B connected to the first conductive type epitaxial pattern 150E1 , and second lower contacts 220B1 and 220B2 connected to the second conductive type epitaxial patterns 150E2 a and 150E2 b , respectively.

[0081] The second upper contact 210B may penetrate the first gap-filling insulating layer 180 and may be connected to the first conductive type epitaxial pattern 150E1, and the second lower contacts 220B1 and 220B2 may penetrate the second gap-filling insulating layer 190 and may be connected to the second conductive type epitaxial patterns 150E2a and 150E2b, respectively. For example, the second upper contact 210B may contact the first conductive type epitaxial pattern 150E1, and the second lower contacts 220B1 and 220B2 may contact the second conductive type epitaxial patterns 150E2a and 150E2b, respectively. For example, the second upper contact 210B and the second lower contacts 220B1 and 220B2 may be formed of at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru) and molybdenum (Mo), or include at least one of titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), tungsten carbonitride (WCN), titanium (Ti), tantalum (Ta), tungsten (W), copper (Cu), aluminum (Al), cobalt (Co), ruthenium (Ru) and molybdenum (Mo).

[0082] The semiconductor device 100 in the example embodiment may have a double-sided interconnect structure including a first interconnect structure 280 and a second interconnect structure 290. The double-sided interconnect structure may be applied to both the first device region A and the second device region B, and may be configured to electrically connect the logic device 100A to the circuit device 100B. The first interconnect structure 280 may be disposed on the upper surface of the semiconductor device 100, and the second interconnect structure 290 may be disposed on the lower surface of the semiconductor device 100.

[0083] refer to FIG. 2A to FIG. 2C as well as Figure 3A and Figure 3B , the first interconnect structure 280 may include: first interconnect insulating layers 281 and 282, and first upper interconnect lines M1a and second upper interconnect lines M1b disposed in the first interconnect insulating layers 281 and 282. For example, in the logic device 100A, the first upper interconnect line M1a may be connected to the first upper contact 210A through a metal via V1a. In the circuit device 100B, the second upper interconnect line M1b may be connected to the second upper contact 210B through a metal via V1b.

[0084] Similarly, the second interconnect structure 290 may include: second interconnect insulating layers 291 and 292, and first to third lower interconnect lines M2a, M2b, and M2c disposed in the second interconnect insulating layers 291 and 292. For example, in the logic device 100A, the first lower interconnect line M2a may be connected to the first lower contact 220A through a metal via V2a. In the circuit device 100B, the second lower interconnect line M2b may be connected to the second lower contact 220B1 through a metal via V2b, and the third lower interconnect line M2c may be connected to the second lower contact 220B2 through a metal via V2c.

[0085] For example, the first interconnect insulating layers 281 and 282 and the second interconnect insulating layers 291 and 292 may be formed of or include silicon oxide, silicon oxynitride, SiOC, SiCOH, or a combination thereof. For example, the upper interconnects M1a, M1b and the lower interconnects M2a, M2b, M2c and the metal paths V1a, V1b and V2a, V2b, V2c may be formed of or include copper or a copper-containing alloy. In some example embodiments, the interconnects and the corresponding metal paths may be formed together using a dual damascene process.

[0086] Figure 4A is a cross-sectional view illustrating a first device region of a semiconductor device taken along line II′ according to example embodiments. Figure 4B is a cross-sectional view illustrating a second device region of a semiconductor device taken along line III-III′ according to example embodiments.

[0087] refer to Figure 4A and Figure 4B , except that the configuration of the process of the first gate structure and the first gate structure GS1 of the logic device is changed and the configuration of the semiconductor stack SL and the upper surface structure of the circuit device is changed, the semiconductor device in the example embodiment may be similar to Figures 1 to 3B 1. In addition, unless otherwise specified, the components in the example embodiments may refer to Figures 1 to 3B 1 and 10. The description of the same components of the semiconductor device 100 shown in FIG. 1 is to be understood.

[0088] Unlike the aforementioned example embodiments, the process for forming the second gate structure GS2 (eg, Fig.12D and Fig.12E The semiconductor device in the exemplary embodiment, in particular, the logic device 100A', is formed by a similar process as in the process of forming the second gate structure GS2 (see Fig.12DBefore the process in the process), a process of forming the first gate structure GS1 may be performed. The first sacrificial pattern (eg, Fig. 12C A first sacrificial pattern 121 in the embodiment of the present invention is formed, and a first gate insulating layer 142A and a first gate electrode 145A may be formed.

[0089] Therefore, in the logic device 100A' in the example embodiment, except for the gate structure portion surrounding the uppermost first semiconductor pattern 131, an upper structure portion such as the first gate electrode portion and the first gate capping layer disposed on the first channel structure CS1 may not be provided. Figure 4A In addition, Figure 4A , the logic device 100A′ may include an insulating portion 185 on an upper surface of the first channel structure CS1.

[0090] like Figure 4B As shown, unlike the aforementioned example embodiments, the circuit device in the example embodiments may not include an electrode material layer (eg, Figure 3A The electrode material layer 145L in the embodiment of the present invention and the insulating cover layer (e.g., Figure 3A In contrast, the circuit device 100B′ may include an insulating portion 185 located on the upper surface of the semiconductor stack SL. Fig.12F ) and then forming the insulating portion 185. In addition, in the semiconductor stack SL employed in the circuit device 100B', unlike the aforementioned example embodiments, the thickness of the first upper semiconductor layer 121L as the uppermost layer of the upper stack may be substantially the same as the thickness of the other semiconductor layers.

[0091] Figure 5A and Figure 5B 1 are plan views and lateral cross-sectional views illustrating a semiconductor device (eg, a circuit device) according to example embodiments.

[0092] refer to Figure 5A and Figure 5B , except that the spacer ISO is further included between the second conductive type epitaxial pattern 150E2a disposed in the first conductive type impurity region W1 and the first conductive type epitaxial pattern 150E1, the circuit device 100C in the example embodiment may be similar to Figure 3A and Figure 3B In addition, unless otherwise specified, the components in the exemplary embodiments may refer to the circuit device 100B shown in FIG. Figure 3A and Figure 3B 100B shown in the figure.

[0093] The circuit device 100C in the example embodiment may further include an isolation spacer ISO between the second conductivity type epitaxial pattern 150E2a as an emitter and the first conductivity type epitaxial pattern 150E1 as a base. The second conductivity type epitaxial pattern 150E2a and the first conductivity type epitaxial pattern 150E1 may be disposed in the same first conductivity type impurity region W1.

[0094] In the circuit device 100C in the example embodiment, the spacer ISO may be provided as a dielectric barrier for dispersing the current flowing from the emitter to the base. The spacer ISO employed in the example embodiment may be configured as a through-hole structure and may be provided by filling the through-hole structure with a dielectric material. Such a spacer ISO may be used as a dielectric barrier to prevent current concentration in various circuit devices.

[0095] Fig. 6A and Figure 6B 1 is a cross-sectional view showing a semiconductor device (eg, circuit device) according to an example embodiment. The circuit devices 100B, 100B' and 100C according to the aforementioned example embodiment are shown as PNP bipolar devices, and the circuit devices 100D and 100E in the example embodiment may be implemented as NPN bipolar devices.

[0096] refer to Fig. 6A , except that the configuration of the impurity regions of the semiconductor stacked body SL and the configuration of the upper and lower positions of the first conductive type epitaxial patterns 150E1a and 150E1b and the second conductive type epitaxial pattern 150E2 are changed, the circuit device 100D in the example embodiment may be similar to Figure 3A and Figure 3B The circuit device 100B shown in FIG. 10B is shown in FIG. 10B. In addition, unless otherwise specified, the components in the exemplary embodiments may refer to Figure 3A and Figure 3B 100B shown in the figure.

[0097] Unlike the aforementioned example embodiments, the circuit device 100D in the example embodiments may have a first conductive type impurity region W1 surrounding a second conductive type impurity region W2. For example, the first conductive type impurity region W1 may be configured as an N-type region, and the second conductive type impurity region W2 may be configured as a P-type region.

[0098] The circuit device 100D in example embodiments may include two first conductivity-type epitaxial patterns 150E1 a and 150E1 b and a second conductivity-type epitaxial pattern 150E2 .

[0099] The semiconductor stack SL may include two recesses in the lower surface and a single through hole penetrating the semiconductor stack SL. Unlike the aforementioned example embodiments, in the example embodiments, two first conductive type epitaxial patterns 150E1a and 150E1b may be formed in the two recesses, respectively, and a second conductive type epitaxial pattern 150E2 may be formed to be disposed within the through hole at a height higher than that of the two first conductive type epitaxial patterns 150E1a and 150E1b.

[0100] The first conductive type epitaxial pattern 150E1a and the second conductive type epitaxial pattern 150E2 may be disposed in the second conductive type impurity region W2, and the other first conductive type epitaxial pattern 150E1b may be disposed in the first conductive type impurity region W1. In example embodiments, the two first conductive type epitaxial patterns 150E1a and 150E1b may be configured as N-type semiconductor patterns, and the second conductive type epitaxial pattern 150E2 may be configured as P-type semiconductor patterns. Similarly, the logic device (see Figure 2A )'s first source / drain pattern 150A and the second source / drain pattern 150B may also be changed.

[0101] With this arrangement, Fig. 6A As shown, the circuit device 100D in the example embodiment may be implemented as an NPN bipolar transistor including a first conductivity type epitaxial pattern 150E1a as an emitter, a second conductivity type epitaxial pattern 150E2 as a base, and a first conductivity type epitaxial pattern 150E1b as a collector.

[0102] refer to Figure 6B , except that the configuration of the impurity regions W1 and W2 of the semiconductor stack SL is changed and the positions of the first conductive type epitaxial patterns 150E1a and 150E1b and the second conductive type epitaxial pattern 150E2 are changed, the circuit device 100E in the example embodiment may be similar to Figure 3A and Figure 3B The circuit device 100B shown in FIG. 10B is shown in FIG. 10B. In addition, unless otherwise specified, the components in the exemplary embodiments may refer to Figure 3A and Figure 3B 100B shown in the figure.

[0103] The circuit device 100E in the example embodiment may have the first conductive type impurity region W1 surrounding the second conductive type impurity region W2, similar to Fig. 6A The circuit device 100D shown. For example, the first conductive type impurity region W1 may be configured as an N-type region, and the second conductive type impurity region W2 may be configured as a P-type region.

[0104] The circuit device 100E in example embodiments may include two first conductivity-type epitaxial patterns 150E1 a and 150E1 b and a second conductivity-type epitaxial pattern 150E2 .

[0105] The semiconductor stack SL may include a recess in the lower surface and two through holes penetrating the semiconductor stack SL. Unlike the aforementioned example embodiments, in the example embodiments, two first conductive type epitaxial patterns 150E1a and 150E1b may be formed in the two through holes, respectively, and the two first conductive type epitaxial patterns 150E1a and 150E1b may be disposed within the through holes at a height higher than that of the second conductive type epitaxial pattern 150E2.

[0106] The first conductive type epitaxial pattern 150E1a and the second conductive type epitaxial pattern 150E2 may be disposed in the second conductive type impurity region W2, and the other first conductive type epitaxial pattern 150E1b may be disposed in the first conductive type impurity region W1. In example embodiments, the two first conductive type epitaxial patterns 150E1a and 150E1b may be configured as N-type semiconductor patterns, and the second conductive type epitaxial pattern 150E2 may be configured as a P-type semiconductor pattern.

[0107] With this arrangement, Figure 6B As shown, the circuit device 100E in the example embodiment may be implemented as an NPN bipolar transistor including a first conductivity type epitaxial pattern 150E1a as an emitter, a second conductivity type epitaxial pattern 150E2 as a base, and a first conductivity type epitaxial pattern 150E1b as a collector.

[0108] Fig. 7A and Figure 7B 1 are plan views and lateral cross-sectional views illustrating a semiconductor device (eg, a circuit device) according to example embodiments.

[0109] refer to Fig. 7A and Figure 7B , except that the semiconductor stacked body SL has a configuration in which a single impurity region W1 and a single first conductivity type epitaxial pattern 150E1 and a single second conductivity type epitaxial pattern 150E2 are formed, the circuit device 100F in the example embodiment may be similar to Figure 3A and Figure 3B The circuit device 100B shown in FIG. 10B is shown in FIG. 10B. In addition, unless otherwise specified, the components in the exemplary embodiments may refer to Figure 3A and Figure 3B 100B shown in the figure.

[0110] The circuit device 100F in the example embodiment may be configured as a PN diode. The semiconductor stack SL may have a first conductive type impurity region W1. For example, the first conductive type impurity region W1 may be configured as an N-type well. A first conductive type epitaxial pattern 150E1 and a second conductive type epitaxial pattern 150E2 may be formed in the first conductive type impurity region W1. The second conductive type epitaxial pattern 150E2 may be disposed in a recess formed in the lower surface of the semiconductor stack. The first conductive type epitaxial pattern 150E1 may be disposed in a through hole penetrating the semiconductor stack SL. The first conductive type epitaxial pattern 150E1 may be disposed in the through hole at a height higher than that of the second conductive type epitaxial pattern 150E2.

[0111] Figure 8 is a lateral cross-sectional view illustrating a semiconductor device (eg, a circuit device) according to example embodiments.

[0112] refer to Figure 8 , except that a configuration in which the conductivity type of the impurity regions of the single semiconductor stack SL is changed is provided, the circuit device 100F′ in the example embodiment may be similar to Fig. 7A and Figure 7B The circuit device 100F shown in FIG. 100F is shown in FIG. 100F. In addition, unless otherwise specified, the components in the exemplary embodiments may refer to Fig. 7A and Figure 7B 100F shown in the figure.

[0113] The circuit device 100F' in the example embodiment may be configured as a PN diode. Different from the example embodiments mentioned above, the semiconductor stack SL may have a second conductive type impurity region W2. For example, the second conductive type impurity region W2 may be configured as a P-type well. The first conductive type epitaxial pattern 150E1 and the second conductive type epitaxial pattern 150E2 may be formed in the second conductive type impurity region W2. Similar to the example embodiments mentioned above, the second conductive type epitaxial pattern 150E2 may be disposed in a recess formed in the lower surface of the semiconductor stack. The first conductive type epitaxial pattern 150E1 may be disposed in a through hole penetrating the semiconductor stack SL.

[0114] The circuit device in the example embodiment may be implemented as a capacitor. For example, the circuit device may be implemented as a capacitor (eg, an N-type capacitor) using a semiconductor of a specific conductivity type as a capacitance material.

[0115] Fig. 9A and Fig. 9B 1 and 2 are a plan view and a lateral cross-sectional view respectively illustrating a semiconductor device (eg, a capacitor) according to example embodiments.

[0116] refer to Fig. 9A and Fig. 9B , except for a configuration including a third upper contact 210C connected to an electrode material layer 145L disposed on the semiconductor stack SL and a configuration including other interconnection lines M1b and M1c for implementing a capacitor, the circuit device 100G in the example embodiment may be similar to Figure 3A and Figure 3B The circuit device 100B shown in FIG. 10B is shown in FIG. 10B. In addition, unless otherwise specified, the components in the exemplary embodiments may refer to Figure 3A and Figure 3B 100B shown in the figure.

[0117] The circuit device 100G in the example embodiment may be configured as a capacitor device and may include a first conductive type impurity region W1 of a semiconductor stack SL and a plurality of first conductive type epitaxial patterns 150E1 each disposed in a plurality of through holes and connected to the semiconductor stack SL (specifically, the upper stack SL1). As described above, the first conductive type impurity region W1 may be provided as a capacitor structure.

[0118] As described above, the plurality of second upper contacts 210B may penetrate the first gap-filling insulating layer and be connected to the first conductive type epitaxial pattern 150E1. In addition to including the plurality of second upper contacts 210B, the circuit device 100F in the example embodiment may further include a plurality of third upper contacts 210C penetrating the insulating capping layer 147L and connected to the electrode material layer 145L. The plurality of third upper contacts 210C may be electrically connected to the first conductive type impurity region W1 through the electrode material layer 145L. In addition, Figure 3A Unlike the example embodiment shown in FIG. 1 , the circuit device 100F in the example embodiment may not include the first gate insulating layer 142A′.

[0119] refer to Fig. 9A , the plurality of second upper contacts 210B may be connected to the interconnection line M1b through the plurality of metal vias V1b, and the plurality of third upper contacts 210C may be connected to the interconnection line M1c through the plurality of metal vias V1c.

[0120] Fig.10 is a lateral cross-sectional view illustrating a semiconductor device (eg, a capacitor) according to example embodiments.

[0121] refer to Fig.10 The circuit device 100G′ in the example embodiment may be configured as a capacitor device and may include a device having Figure 2A. However, in example embodiments, structures corresponding to the first gate structure and the second gate structure may be provided as a first passive gate structure NG1 and a second passive gate structure NG2, respectively, which are not used as gates of active transistors. However, the first passive gate structure NG1 may be provided as an electrode structure on one side of a capacitor. In addition, a first conductive type impurity region W1 of the semiconductor stack SL and a plurality of first conductive type epitaxial patterns 150E1 disposed in a plurality of through holes and connected to the semiconductor stack SL (specifically, the upper stack SL1) may be included.

[0122] The circuit device 100G′ in example embodiments may include a first semiconductor pattern 131 ′ operating as a capacitive material and a plurality of first conductive type epitaxial patterns 150E1 .

[0123] In addition to including the upper contacts 210B, the circuit device 100G' in example embodiments may further include a plurality of third upper contacts 210C connected to the first gate electrode 145A through the first gate capping layer 147A. The plurality of third upper contacts 210C may be electrically connected to the first semiconductor pattern 131' through the first gate electrode 145A.

[0124] Similar to the aforementioned example embodiment, the plurality of second upper contacts 210B may be connected to the interconnection line M1b through the plurality of metal vias V1b, and the plurality of third upper contacts 210C may be connected to the interconnection line M1c through the plurality of metal vias V1c (see Fig. 9A ).

[0125] FIG. 11A to FIG. 11I is a cross-sectional view showing a part of the process of a method for manufacturing a semiconductor device according to an example embodiment. The manufacturing method in the example embodiment can be understood as manufacturing Figure 1 The process of the semiconductor device 100 is shown in FIG. 1 , and each process cross-sectional view may include Figure 2A The logic devices and Figure 3A The cross-sectional view corresponding to the circuit device in .

[0126] refer to Fig.11A , a semiconductor stacked body SL may be formed on the substrate 101 , that is, in the first device region A and the second device region B.

[0127] The substrate 101 may include a semiconductor material, such as a Group IV semiconductor, a Group III-V compound semiconductor, or a Group II-VI compound semiconductor. For example, the Group IV semiconductor may include silicon (Si), germanium (Ge), or silicon germanium (SiGe). The substrate 101 may include a bulk wafer, an epitaxial layer, or a silicon-on-insulator (SOI) layer.

[0128] The semiconductor stack SL can be formed by alternately stacking semiconductor layers of different components on a substrate. The semiconductor layer includes: an intermediate semiconductor layer 125L (also referred to as an "intermediate sacrificial layer 125L"); an upper stack SL1 (also referred to as a "first stack") having a first sacrificial layer 121L (also referred to as a "first upper semiconductor layer") and a first semiconductor layer 131L (also referred to as a "second upper semiconductor layer") alternately stacked on the upper surface of the intermediate semiconductor layer 125L; and a lower stack SL2 (also referred to as a "second stack") having a second sacrificial layer 122L (also referred to as a "first lower semiconductor layer") and a second semiconductor layer 132L (also referred to as a "second lower semiconductor layer") alternately stacked on the lower surface of the intermediate semiconductor layer 125L. Semiconductor layers of different components can be implemented by different germanium component ratios (e.g., 0 to 60%).

[0129] The first semiconductor layer 131L and the second semiconductor layer 132L may be used to configure the channel of the logic device 100A. For example, the first semiconductor layer 131L and the second semiconductor layer 132L may include silicon. The first sacrificial layer 121L, the second sacrificial layer 122L, and the intermediate semiconductor layer 125L may be used as selectively removable sacrificial layers, and may include silicon germanium having a relatively high germanium concentration (e.g., 15% or more). Depending on the process sequence of removing the sacrificial layers, the first sacrificial layer 121L, the second sacrificial layer 122L, and the intermediate semiconductor layer 125L may also be configured to have different germanium concentrations. In an example embodiment, in the process of forming the logic device 100A, the germanium concentration of the intermediate semiconductor layer 125L that may be preferentially removed may be greater than the germanium concentration of each of the first sacrificial layer 121L and the second sacrificial layer 122L. In addition, the germanium concentration of the second sacrificial layer 122L may be greater than the germanium concentration of each of the first sacrificial layer 121L. However, example embodiments thereof are not limited thereto, and the first sacrificial layer 121L and the second sacrificial layer 122L may have the same germanium concentration.

[0130] In some example embodiments, the thickness t1 of the intermediate semiconductor layer 125 may be greater than the thickness of each of the first semiconductor layer 121L and the second semiconductor layer 131L or each of the first semiconductor layer 122L and the second semiconductor layer 132L. In some example embodiments, the second stack SL2 may be arranged so that the second sacrificial layer 122L and the second semiconductor layer 132L may be at least respectively set as the lowermost layer (i.e., the layer in contact with the intermediate semiconductor layer 125) and the uppermost layer of the second stack SL2. The first stack SL1 may be arranged so that the first sacrificial layers 121L' and 121L may be at least set as the lowermost layer and the uppermost layer of the first stack SL1. Here, the thickness t2 of the first sacrificial layer 121L' as the lowermost layer may be greater than the respective thicknesses of the other first sacrificial layers 121L.

[0131] Afterwards, refer to Fig. 11B , in the first device region A, the semiconductor stacked body SL may be patterned to form a fin structure FS, and in the second device region B, desired impurity regions W1 and W2 may be formed in the semiconductor stacked body SL.

[0132] The process of forming the fin structure may be selectively performed only on the first device region A, and during the process of forming the fin structure, the second device region B may be covered with a mask (not shown). In the first device region A, the fin structure FS may extend longitudinally in a first direction (e.g., X direction) on the substrate 101, and a plurality of fin structures FS may be formed and arranged in parallel in a second direction (e.g., Y direction).

[0133] In the second device region B, an ion implantation process may be used to form impurity regions W1 and W2 in the semiconductor stack SL to form a circuit device. The ion implantation process may be selectively performed only on the second device region B, and during the ion implantation process, the first device region A may be covered with a mask (not shown). Figure 1 In the illustrated example, in a plan view, the semiconductor stack SL may include a first conductive type impurity region W1 and a second conductive type impurity region W2 surrounding the first conductive type impurity region W1 .

[0134] Afterwards, refer to Fig. 11C , a plurality of dummy gate structures DG may be formed in the first device region and the second device region (eg, the first device region A and the second device region B).

[0135] The plurality of dummy gate structures DG may extend longitudinally in the second direction (e.g., the Y direction) and may be arranged in parallel in the first direction (e.g., the X direction). In example embodiments, the plurality of dummy gate structures DG may be arranged at a first pitch P1 in the first device region A, and may be arranged at a second pitch P2 in the second device region B. The first pitch P1 and the second pitch P2 may be the same, but example embodiments thereof are not limited thereto.

[0136] The plurality of dummy gate structures DG in the first device region A may be formed to intersect with the fin structure FS (see Figure 1 ), and a plurality of dummy gate structures DG in the second device region B may be formed on a flat surface of the semiconductor stack SL.

[0137] In this process, gate spacers 141 may be formed on both sides of the dummy gate structure DG. Each of the dummy gate structures DS may be provided as a sacrificial structure that provides a space for forming a gate structure GS to be formed in a subsequent process. The dummy gate structure DS may include a dummy material layer 245 and a mask pattern layer 247. The mask pattern layer 247 may be used to pattern the dummy material layer 245. The dummy material layer 245 may be an insulating layer and a conductive layer, respectively, but in some example embodiments, the dummy material layer 245 may include polysilicon. The mask pattern layer 247 may include silicon oxide and / or silicon nitride. However, example embodiments thereof are not limited thereto, and the dummy material layer 245 may include a plurality of different material layers. For example, the dummy material layer 245 may also include an insulating film, such as silicon oxide, below the polysilicon.

[0138] The gate spacer 141 may be formed on both sidewalls of the dummy gate structure DS. The gate spacer 141 may be formed by forming a film of uniform thickness along the upper surface and side surfaces of the substrate on which the dummy gate structure DS is formed and performing anisotropic etching. The gate spacer 141 may be formed of a low-κ material and may include, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN.

[0139] Afterwards, refer to Fig.11D In the first device region, a portion of the fin structure FS between the dummy gate structures DS may be removed to form a first recess RS1 .

[0140] In some embodiments, the process may be selectively performed only on the first device region A, and during the process, the second device region B may be covered with a mask (not shown).

[0141] In example embodiments, the first recess RS1 may be formed sufficiently deep in the substrate 101. In this process, the process may be performed by removing the exposed region of the fin structure FS using the dummy gate structure DS and the gate spacer 141 as a mask. Through this process, the first semiconductor pattern 131 and the second semiconductor pattern 132 may have a desired channel length in a first direction (e.g., X direction). The side portion of the first semiconductor pattern 131 exposed by the first recess RS1 may be provided as a region for forming a first source / drain pattern, and the side portion of the second semiconductor pattern 132 may be provided as a region for forming a second source / drain pattern.

[0142] Afterwards, refer to Fig.11E , in the second device region B, a second recess RS2 and a third recess RS3 may be formed in the semiconductor stacked body SL.

[0143] The process may be selectively performed only on the second device region B, and during the process, the first device region A may be covered with a mask (not shown).

[0144] In an example embodiment, the second recess RS2 may be formed to a depth penetrating the second stack SL2, and the third recess RS3 may be formed similar to the first recess RS1 to be sufficiently deep into the substrate 101. The process may also be performed by removing the exposed area of ​​the semiconductor stack SL using the dummy gate structure DS and the gate spacer 141 as a mask. The second recess RS2 may be set as a space for a second conductive type epitaxial pattern, and the third recess RS3 may be set as a space for a first conductive type epitaxial pattern. After removing the substrate, the third recess RS3 may be set as a through hole.

[0145] Afterwards, refer to Fig.11F In the first device region A and the second device region B, a first gap-filling insulating layer 180' and a second gap-filling insulating layer 190' may be formed in the space between the dummy gate structures DG to fill the first to third recesses RS1, RS2, and RS3, and thereafter, the first gap-filling insulating layer 180' of the first recess RS1 and the third recess RS3 may be selectively recessed (for example, a first recess RS1' and a third recess RS3' may be formed), and a blocking insulating layer 260 may be formed.

[0146] For ease of description, the portion filled with the same insulating material may be divided into a first gap-filling insulating layer 180' and a second gap-filling insulating layer 190'. The insulating material portion filled in the first recess RS1 and the third recess RS3 may be referred to as the first gap-filling insulating layer 180, and the insulating material portion filled in the space between the second recess RS2 and the dummy gate structure DG may be referred to as the second gap-filling insulating layer 190.

[0147] The process of forming the first gap filling insulating layer 180' and the second gap filling insulating layer 190' may be performed by depositing a first insulating material to fill the space between the dummy gate structures DS and performing planarization such as chemical mechanical polishing (CMP). For example, the first gap filling insulating layer 180' and the second gap filling insulating layer 190' may be silicon oxide, such as a spin-on hard mask (SOH). The process of optionally recessing the first gap filling insulating layer 180' may be performed by a process such as etching back. The first gap filling insulating layer 180' of the first recess RS1 may be formed to have an upper surface height that covers at least the side surface of the first semiconductor pattern 131. The first gap filling insulating layer 180' of the third recess RS3 may also have the same height as the height of the first gap filling insulating layer 180' of the first recess RS1. In an example embodiment, the upper surface height of the recessed first gap filling insulating layer 180' may be formed to overlap with the intermediate semiconductor layer 125 in a horizontal direction.

[0148] Thereafter, the blocking insulating layer 260 may conformally form a second insulating material over the entire region. Specifically, the second insulating material may be formed on the sidewalls of the dummy gate structure DS in addition to being formed on the upper surface of the dummy gate structure DS and the upper surface of the first gap-filling insulating layer 180'. The second insulating material may include a dielectric material that inhibits epitaxial growth. For example, the second insulating material may include silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbonitride (SiCN).

[0149] Afterwards, refer to Fig.11G , the first gap-filling insulating layer 180 ′ may be exposed on bottom surfaces of the first and third recesses RS1 and RS3 , and the exposed first gap-filling insulating layer 180 ′ may be further recessed, thereby exposing the first semiconductor pattern 131 .

[0150] The process of exposing the first gap-filling insulating layer 180' may be performed by an anisotropic etching process such as dry etching. Specifically, by the anisotropic etching process, portions disposed on the upper surfaces of the dummy gate structure DS and the second gap-filling insulating layer 190' and the upper surface of the first gap-filling insulating layer 180' may be removed from the blocking insulating layer 260. Therefore, the blocking insulating layer 260' may remain on the exposed sidewall portions of the dummy gate structure DS. The blocking insulating layer 260' may be disposed to cover the sidewall portions of the dummy gate structure DS and the side surfaces of the second semiconductor pattern layer 132.

[0151] Thereafter, the first gap filling insulating layer 180' may be partially recessed so that the side surface of the first semiconductor pattern 131 may be opened. Thereafter, a desired first source / drain pattern 150A may be formed by epitaxially growing from the side surface of the first semiconductor pattern 131. During the epitaxial growth process, the epitaxial layer growth may be suppressed in the portion where the blocking insulating layer 260 is formed. Simultaneously with the process of forming the first source / drain pattern 150A, a first conductive type epitaxial pattern 150E1 may be formed in the third recess RS3. The first conductive type epitaxial pattern 150E1 may be grown from the side surface of the opening of the first semiconductor layer 131L by an additional recess process in the third recess RS3. Thus, in example embodiments, the first source / drain pattern 150A and the first conductive type epitaxial pattern 150E1 may be formed by the same epitaxial growth process. The first source / drain pattern 150A and the first conductive type epitaxial pattern 150E1 may include the same conductive type semiconductor material and may be disposed at the same height.

[0152] Afterwards, refer to Fig.11H , the blocking insulating layer 260 may be removed, a third insulating material may be deposited, and a selective etch-back process may be performed so that the first recess RS1 ′ and the second recess RS2 ′ may be formed again. In this process, the isolation insulating layer 170 may be formed.

[0153] This process can be performed by a process of depositing a third insulating material to fill the first recess RS1 and the third recess RS3 and a planarization process such as CMP. The third insulating material can be a material similar to the first insulating material. For example, the material can be silicon oxide such as SOH. Thereafter, an isolation insulating layer 170 can be formed in the first recess RS1' and the second recess RS2' by performing a process such as selective etching back to form the first recess RS1' and the second recess RS2'. The isolation insulating layer 170 can cover the bottom surface of the first source / drain pattern 150A in the first recess RS1' and the second recess RS2'. In addition, in the process of forming the isolation insulating layer 170, the space above the first conductive type epitaxial pattern 150E1 of the third recess can also be filled.

[0154] Afterwards, refer to Fig.11I In the first device region A and the second device region B, the second source / drain pattern 150B and the second conductive type epitaxial patterns 150E2a and 150E2b may be simultaneously formed.

[0155] In the first recess RS1', a second source / drain pattern 150B may be formed from the side surface of the exposed second semiconductor pattern 132, and in the second recess RS2', second conductive type epitaxial patterns 150E2a and 150E2b may be formed from the side surface of the exposed second semiconductor layer 132L. Thus, in example embodiments, the second source / drain pattern 150B and the second conductive type epitaxial patterns 150E2a and 150E2b may be formed by the same epitaxial growth process. The second source / drain pattern 150B and the second conductive type epitaxial patterns 150E2a and 150E2a may include semiconductor materials of the same conductive type.

[0156] FIG. 12A to FIG. 12G 2 is a cross-sectional view illustrating other parts of processes of a method of manufacturing a semiconductor device according to example embodiments.

[0157] refer to Fig. 12A , a process of partially removing the dummy gate structure DG may be performed. Fig. 12A In the example shown in FIG. 2 , an insulating layer may be formed to fill the space between the dummy gate structures DG, and a CMP process may be performed to remove the insulating layer until the mask pattern layer 247 (eg, until the PL line). In the dummy gate structure DG, the dummy material layer 245 may be exposed.

[0158] Afterwards, refer to Fig. 12B , in the first device region A, the dummy material layer 245 and the mask pattern layer 247 may be removed, and the intermediate semiconductor layer 125 may be removed by applying a selective etching process through the removed space DH1. Thus, the first space O1 from which the intermediate semiconductor layer 125 is removed may be obtained. Fig. 12C , in the first device region A, an insulating material may be filled in the first space O1 to form an insulating isolation pattern 160 .

[0159] Afterwards, refer to Fig.12D , a space DH2 between the gap-filling insulating layers 190 may be formed by selectively removing the dummy material layer 245 and the mask pattern layer 247 from the second device region B, and thereafter, a second space O2 between the second semiconductor patterns 132 may be formed by selectively removing the second sacrificial pattern 122 from the first device region A. Even when the dummy material layer 245 is removed from the second device region B and the semiconductor stack SL is exposed, unlike the first device region A, the component may not have a fin-type structure, so that only the upper surface of the semiconductor stack SL (i.e., the second semiconductor layer 132L) may be exposed. Therefore, even in the process of selectively removing the second sacrificial pattern 122 in the first device region A, the semiconductor stack SL in the second device region B may not be etched.

[0160] Afterwards, refer to Fig.12E , a second gate structure GS2 may be formed, and a first lower contact 220A and second lower contacts 220B1 and 220B2 may be formed.

[0161] The process of forming the second gate structure GS2 may be performed by conformally forming a second gate insulating layer 142B to surround the exposed second semiconductor pattern 132. Thereafter, a second gate electrode 145B may be formed to be buried in the spaces DH1 and DH2 from which the dummy material layer is removed, and may be recessed to a predetermined depth. Thereafter, a second gate structure GS2 may be formed in the first device region A by forming a second gate capping layer 147B on the second gate electrode 145B and performing a CMP process. In this same process, a passive gate structure NG having the same structure as that of the second gate structure GS2 may be formed in the second device region B. In the first device region A, the first lower contact 220A may penetrate the second gap-filling insulating layer 190 and may be connected to the second source / drain pattern 150B, and in the second device region B, the second lower contacts 220B1 and 220B2 may penetrate the second gap-filling insulating layer 190 and may be connected to the second conductive type epitaxial patterns 150E2a and 150E2b, respectively. In some example embodiments, a second gate structure GS2 may also be formed. Figure 2A and Figure 3A The second interconnect structure 290 described in .

[0162] Afterwards, refer to Fig.12F , the substrate 101 may be removed, and the first sacrificial patterns 121 may be selectively removed, thereby forming a third space O3 between the first semiconductor patterns 131 .

[0163] The removal of the substrate 101 may be performed through a wet etching process. During the wet etching process, the first semiconductor pattern 131 provided as a channel may be protected by the first sacrificial pattern 121, which is an uppermost portion having a relatively large thickness.

[0164] After removing the substrate 101, a first opening region OP1 may be provided to the first device region A, and a second opening region OP2 may be provided to the second device region B. In some example embodiments, the first opening region and the second opening region may be formed, and a first gate spacer 141A may be formed. The spacer material may be conformally deposited, and an anisotropic etching process may be applied to remain only on the sidewalls of the first gap-filling insulating layer 190.

[0165] Thereafter, the first sacrificial pattern 121 may be selectively removed from the first device region A so that a third space O3 may be formed between the first semiconductor patterns 131. In this process, the first sacrificial pattern 121, which is the uppermost portion having a relatively large thickness, may also be removed. Even when the substrate 101 is removed from the second device region B and the semiconductor stack SL is exposed, unlike the first device region A, the component may not have a fin structure, so that only the upper surface of the semiconductor stack SL (i.e., the uppermost first sacrificial layer 121L) may be exposed, and a portion or all of it may be removed. After the uppermost first sacrificial layer 121L is removed, the component may be protected by the second uppermost first semiconductor layer 131L. Therefore, even in the process of selectively removing the first sacrificial pattern 121 in the second device region A, the semiconductor stack SL in the second device region B may not be further etched.

[0166] Afterwards, refer to Figure 12G , a first gate structure GS1 may be formed in the first device region A, and at the same time, an electrode material layer 145L and an insulating capping layer 147L may be formed in the second device region B. Thereafter, a first upper contact 210A and a second upper contact 210B may be formed.

[0167] In the first device area A, the process of forming the first gate structure GS1 may be performed as a process of conformally forming the first gate insulating layer 142A to surround the exposed first semiconductor pattern 131. Thereafter, the first gate electrode 145A may be formed to be buried in the space OP1 from which the substrate 101 is removed, and may be recessed to a predetermined depth. Thereafter, a second gate structure GS2 may be formed in the first device area A by forming a second gate capping layer 147B on the second gate electrode 145B and performing a CMP process. In this same process, in the second device area B, a layer identical to the second gate structure GS2 may be formed in the space OP2 from which the substrate 101 has been removed. For example, a second gate insulating layer 142A' may be formed on the inner sidewall of the second gate spacer 141A'. Subsequently, in the process of forming the first gate structure, an electrode material layer 145L and an insulating capping layer 147L may be sequentially formed in the second device area. The electrode material layer 145L may include the same electrode material as that of the first gate electrode 145A, and the insulating capping layer 147L may include the same insulating material as that of the first gate capping layer 147A. In the first device region A, the first upper contact 210A may penetrate the first gap-filling insulating layer 180 and may be connected to the first source / drain pattern 150A, and in the second device region B, the second upper contact 210B may penetrate the first gap-filling insulating layer 180 and may be connected to the first conductive type epitaxial pattern 150E1. In some example embodiments, a first conductive type epitaxial pattern 150E1 may be further formed. Figure 2A and Figure 3A The first interconnect structure 280 described in .

[0168] According to the aforementioned example embodiments, in a semiconductor device without a bulk substrate, various circuit devices may be implemented to form a peripheral circuit using a semiconductor stack to form a channel layer and an epitaxial pattern corresponding to a source / drain pattern.

[0169] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: A semiconductor stack having a first surface and a second surface opposite to each other, including semiconductor layers having different compositions stacked in the semiconductor stack, and including at least one of a first conductivity type impurity region and a second conductivity type impurity region, wherein the semiconductor stack has a recess formed in the second surface and a through hole penetrating the semiconductor stack; a plurality of passive gate structures disposed on the second surface of the semiconductor stack and spaced apart from each other, wherein each of the recess and the through hole is disposed between the plurality of passive gate structures; a first conductive type epitaxial pattern disposed in the through hole and connected to the semiconductor stack; a second conductive type epitaxial pattern disposed in the recess and connected to the semiconductor stack; a first gap-filling insulating layer disposed on the first conductive type epitaxial pattern in the through hole adjacent to the first surface of the semiconductor stack; a second gap-filling insulating layer, the second gap-filling insulating layer being disposed between the plurality of passive gate structures on the second surface of the semiconductor stack; a first contact penetrating the first gap-filling insulating layer and connected to the first conductive type epitaxial pattern; and A second contact penetrates the second gap-filling insulating layer and is connected to the second conductive type epitaxial pattern.

2. The semiconductor device according to claim 1, wherein The first conductive type epitaxial pattern is disposed in the through hole at a height higher than that of the second conductive type epitaxial pattern.

3. The semiconductor device according to claim 1, wherein The semiconductor stack includes the first conductivity type impurity region and the second conductivity type impurity region arranged in a horizontal direction.

4. The semiconductor device according to claim 3, in, The second conductive type epitaxial pattern includes two second conductive type epitaxial patterns, and the recess includes a first recess located in the first conductive type impurity region and a second recess located in the second conductive type impurity region, The two second conductive type epitaxial patterns are respectively arranged in the first concave portion and the second concave portion, and The first conductive type epitaxial pattern is disposed between the two second conductive type epitaxial patterns in one of the first conductive type impurity region and the second conductive type impurity region.

5. The semiconductor device according to claim 4, wherein: The semiconductor stack includes an isolation hole located between the first conductive type epitaxial pattern and one of the two second conductive type epitaxial patterns that is disposed in the same conductive type impurity region as the first conductive type epitaxial pattern.

6. The semiconductor device according to claim 3, in, The first conductive type epitaxial pattern includes two first conductive type epitaxial patterns, and the through hole includes a first through hole located in the first conductive type impurity region and a second through hole located in the second conductive type impurity region, The two first conductive type epitaxial patterns are respectively arranged in the first through hole and the second through hole, and The second conductive type epitaxial pattern is disposed between the two first conductive type epitaxial patterns in one of the first conductive type impurity region and the second conductive type impurity region.

7. The semiconductor device according to claim 1, in, The semiconductor stack includes one of the first conductivity type impurity region and the second conductivity type impurity region, and The first conductive type epitaxial pattern and the second conductive type epitaxial pattern are spaced apart from each other and are disposed in the one impurity region.

8. The semiconductor device according to claim 1, further comprising: an electrode material layer, the electrode material layer being disposed on the first surface of the semiconductor stack, and An insulating covering layer is disposed on the electrode material layer.

9. A semiconductor device, comprising: A semiconductor stack, the semiconductor stack comprising: an intermediate semiconductor layer; an upper stack having a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on an upper surface of the intermediate semiconductor layer; a lower stack having a first lower semiconductor layer and a second lower semiconductor layer alternately stacked on a lower surface of the intermediate semiconductor layer; and a first conductive type impurity region and a second conductive type impurity region arranged horizontally; a plurality of passive gate structures, the plurality of passive gate structures being arranged on a lower surface of the semiconductor stack at a certain interval; at least one recess, the at least one recess being disposed between at least one pair of adjacent passive gate structures among the plurality of passive gate structures and penetrating the lower stack from the lower surface of the semiconductor stack; at least one through hole, the at least one through hole being disposed between at least one pair of adjacent passive gate structures among the plurality of passive gate structures and penetrating the semiconductor stack; at least one first conductive type epitaxial pattern disposed in the at least one through hole and connected to the upper stack of the semiconductor stack; and At least one second conductive type epitaxial pattern is disposed in the at least one recess and connected to the lower stack of the semiconductor stack.

10. The semiconductor device according to claim 9, wherein The first upper semiconductor layers are at least respectively arranged as the topmost first upper semiconductor layer and the bottommost first upper semiconductor layer of the upper stack, and the thickness of the topmost first upper semiconductor layer as the topmost layer among the first upper semiconductor layers is greater than that of the other first upper semiconductor layers.

11. The semiconductor device according to claim 10, further comprising: an electrode material layer disposed on the upper surface of the semiconductor stack, and An insulating covering layer covers the electrode material layer.

12. The semiconductor device according to claim 9, wherein The thickness of the middle semiconductor layer is greater than the thickness of each of the first upper semiconductor layer and the second upper semiconductor layer or each of the first lower semiconductor layer and the second lower semiconductor layer.

13. The semiconductor device according to claim 9, in, The second upper semiconductor layer and the second lower semiconductor layer include silicon, and Wherein, the first upper semiconductor layer, the first lower semiconductor layer and the middle semiconductor layer include silicon germanium.

14. The semiconductor device according to claim 13, wherein: The germanium concentration of the middle semiconductor layer is greater than the germanium concentration of each of the first upper semiconductor layer and the first lower semiconductor layer.

15. The semiconductor device according to claim 13, wherein: The first upper semiconductor layer and the first lower semiconductor layer have the same germanium concentration.

16. A semiconductor device, comprising a first device region and a second device region arranged horizontally, in, The first device region comprises: a channel structure including an insulating isolation pattern, a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern being vertically stacked on an upper surface of the insulating isolation pattern and spaced apart from each other, and the second semiconductor pattern being vertically stacked on a lower surface of the insulating isolation pattern and spaced apart from each other; a pair of first source / drain patterns, the pair of first source / drain patterns being disposed on both sides of the channel structure in a first direction and respectively connected to both sides of the first semiconductor pattern; a pair of second source / drain patterns, the pair of second source / drain patterns being disposed on both sides of the channel structure in the first direction and respectively connected to both sides of the second semiconductor pattern; a first gate structure extending in a second direction crossing the first direction and surrounding the first semiconductor pattern; and a second gate structure intersecting a lower surface of the channel structure, extending in the second direction, and surrounding the second semiconductor pattern, and Wherein, the second device area includes: A semiconductor stack, the semiconductor stack being disposed at a height corresponding to the height of the channel structure and comprising an upper stack having a first upper semiconductor layer and a second upper semiconductor layer alternately stacked on an upper surface of an intermediate semiconductor layer, and a lower stack having a first lower semiconductor layer and a second lower semiconductor layer alternately stacked on a lower surface of the intermediate semiconductor layer, wherein the semiconductor stack comprises a first conductive type impurity region and a second conductive type impurity region disposed in a horizontal direction; A plurality of passive gate structures, the plurality of passive gate structures being arranged on a lower surface of the semiconductor stack; a first conductive type epitaxial pattern, the first conductive type epitaxial pattern being disposed in a through hole penetrating the semiconductor stack between adjacent passive gate structures among the plurality of passive gate structures and connected to the upper stack; and A second conductive type epitaxial pattern is disposed in a recess and connected to the lower stack, wherein the recess is formed on a lower surface of the semiconductor stack between other adjacent passive gate structures among the plurality of passive gate structures.

17. The semiconductor device according to claim 16, in, The first conductive type epitaxial pattern includes the same material as that of the pair of first source / drain patterns, and The second conductive type epitaxial pattern includes a material that is the same as a material of the pair of second source / drain patterns.

18. The semiconductor device according to claim 16, wherein: The semiconductor stack has a thickness corresponding to a height of the channel structure.

19. The semiconductor device according to claim 16, in, The first upper semiconductor layers are at least respectively arranged as the uppermost first upper semiconductor layer and the lowermost first upper semiconductor layer of the upper stack, and the thickness of the uppermost first upper semiconductor layer as the uppermost layer among the first upper semiconductor layers is greater than the thickness of the other first upper semiconductor layers, and The height of the upper surface of the semiconductor stack is higher than the height of the upper surface of the channel structure by the thickness of the uppermost first upper semiconductor layer.

20. The semiconductor device according to claim 16, in, The second device region further includes: an electrode material layer, the electrode material layer being disposed on the upper surface of the semiconductor stack, and an insulating cover layer, the insulating cover layer covering the electrode material layer, and The electrode material layer includes a material that is the same as a material of the gate electrode of the first gate structure.

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