Topcon battery structure and preparation method thereof

Abstract

The invention provides a Topcon battery structure and a preparation method thereof, and relates to the technical field of solar cells, and the Topcon battery structure comprises a semiconductor substrate, one surface of the semiconductor substrate is provided with a second conductive type semiconductor region, and one side, away from the semiconductor substrate, of the second conductive type semiconductor region is provided with a second passivation layer A; a second passivation layer B is arranged on one side of the second passivation layer A away from the second conductive type semiconductor region, an ultrathin amorphous silicon layer is arranged on one side of the semiconductor substrate away from the second conductive type semiconductor region, and a tunneling layer is arranged on one side of the ultrathin amorphous silicon layer away from the semiconductor substrate. A first conductive type semiconductor region is arranged on one side, far away from the ultrathin amorphous silicon layer, of the tunneling layer; and a first passivation layer is arranged on one side, far away from the tunneling layer, of the first conductive type semiconductor region. According to the Topcon cell, the ultrathin amorphous silicon layer is arranged, so that the problem of lattice mismatch between the semiconductor substrate and the tunneling layer can be relieved, interface defects are reduced, and the performance and reliability of the Topcon cell are improved.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cells, and in particular to a Topcon cell structure and a preparation method thereof. Background Art

[0002] The back structure of the Topcon cell is mainly composed of an ultra-thin silicon oxide layer and a doped polysilicon layer, which together form a passivation contact structure.

[0003] For example, a Chinese patent with the authorization announcement number CN117542915B discloses a TOPCon solar cell, including a cell, which is composed of a front anti-reflection layer, a front passivation layer, an emitter, a silicon substrate layer, an ultra-thin tunneling silicon dioxide layer, a polysilicon layer, a back passivation layer, and a back anti-reflection layer from top to bottom. The TOPCon solar cell device designed by the present invention can use an insulating heat-conducting layer and a heat-conducting support layer to quickly transfer heat to the heat-conducting plate, and then use the heat-conducting plate and the heat-exchanging plate to exchange heat with external water flow to quickly dissipate heat and cool down. At the same time, it can also use the light-transmitting plate and the water flow sprayed on the light-transmitting plate to cool down, so that the temperature of the cell can be quickly stabilized within an ideal temperature range, effectively ensuring the conversion efficiency of the cell.

[0004] Among them, a silicon dioxide layer is deposited on the back of the silicon substrate layer, but the above structure has the following defects: during the deposition of silicon oxide, stress may be generated between the silicon oxide and the silicon substrate layer due to differences in thermal expansion coefficients and lattice mismatch. This stress may cause the silicon substrate to deform and bend, and may even cause defects such as cracks in the silicon oxide layer, affecting the performance and reliability of the device. Summary of the invention

[0005] The present invention provides a Topcon battery structure and a preparation method thereof, which are used to solve at least one technical problem raised in the above background technology.

[0006] To solve the above technical problems, the present invention discloses a Topcon battery structure, comprising: a semiconductor substrate, a second conductive type semiconductor region is arranged on one side of the semiconductor substrate, a second passivation layer A is arranged on the side of the second conductive type semiconductor region away from the semiconductor substrate, a second passivation layer B is arranged on the side of the second passivation layer A away from the second conductive type semiconductor region, an ultra-thin amorphous silicon layer is arranged on the side of the semiconductor substrate away from the second conductive type semiconductor region, a tunneling layer is arranged on the side of the ultra-thin amorphous silicon layer away from the semiconductor substrate, a first conductive type semiconductor region is arranged on the side of the tunneling layer away from the ultra-thin amorphous silicon layer, and a first passivation layer is arranged on the side of the first conductive type semiconductor region away from the tunneling layer.

[0007] Preferably, the thickness of the ultra-thin amorphous silicon layer is 0.1-5 nm, more preferably 0.1-3 nm.

[0008] Preferably, the thickness of the tunneling layer is 0.1-5 nm, more preferably 0.1-2.5 nm.

[0009] The present invention also discloses a method for preparing a Topcon battery structure, which is used to prepare the Topcon battery structure, comprising the following steps:

[0010] Step 1: Prepare a single-sided polished wafer that has undergone texturing, boron diffusion, and etching processes as a semiconductor substrate;

[0011] Step 2: placing the semiconductor substrate into the reaction chamber;

[0012] Step 3: introducing silicon source gas and carrier gas into the reaction chamber to prepare an ultra-thin amorphous silicon layer;

[0013] Step 4: preparing a tunneling layer on the side of the ultra-thin amorphous silicon layer away from the semiconductor substrate;

[0014] Step 5: preparing a first conductive type semiconductor region on a side of the tunneling layer away from the ultra-thin amorphous silicon layer;

[0015] Step 6: preparing a first passivation layer on a side of the first conductive type semiconductor region away from the tunneling layer, and then manufacturing a first electrode, wherein the first electrode passes through the first passivation layer and contacts the first conductive type semiconductor region;

[0016] Step 7: preparing a second conductive type semiconductor region on a side of the semiconductor substrate away from the first conductive type semiconductor region;

[0017] Step 8: preparing a second passivation layer A on a side of the second conductive type semiconductor region away from the semiconductor substrate;

[0018] Step 9: Prepare a second passivation layer B and a second electrode, the second electrode passes through the second passivation layer B and the second passivation layer A to contact the second conductive type semiconductor region.

[0019] Preferably, in step 2, nitrogen is first introduced into the reaction chamber to make the pressure inside the reaction chamber consistent with that outside, and the temperature of the reaction chamber is set within a preset temperature range. Then, the semiconductor substrate is placed in the reaction chamber, the introduction of nitrogen is stopped, and the reaction chamber is vacuumed.

[0020] Preferably, after the vacuum treatment, the reaction chamber is inspected for airtightness, and the air leakage of the reaction chamber does not exceed 120 mTorr per minute.

[0021] Preferably, after the airtightness check is completed, the temperature of the reaction chamber is increased so that the temperature inside the reaction chamber reaches the deposition target temperature.

[0022] Preferably, preparing the first conductive type semiconductor region comprises:

[0023] A mixed gas containing a silicon source gas, a doping gas and a carrier gas is introduced into the reaction chamber to prepare an amorphous silicon layer A;

[0024] A mixed gas containing a silicon source gas, a doping gas and a carrier gas is introduced into the reaction chamber to prepare an amorphous silicon layer B;

[0025] Finally, doped amorphous silicon is obtained, and the doped amorphous silicon is crystallized into doped polycrystalline silicon to obtain a first conductive type semiconductor region.

[0026] Preferably, the sum of the thicknesses of the amorphous silicon layer A and the amorphous silicon layer B is 30-170 nm.

[0027] Preferably, preparing the first conductive type semiconductor region includes: depositing polysilicon on the surface of the tunneling layer, performing a doping process on the polysilicon to form doped polysilicon, and preparing the first conductive type semiconductor region.

[0028] The technical solution of the present invention has the following advantages: The present invention provides a Topcon battery structure and a preparation method thereof, which relates to the technical field of solar cells, including a semiconductor substrate, a second conductive type semiconductor region is arranged on one side of the semiconductor substrate, a second passivation layer A is arranged on the side of the second conductive type semiconductor region away from the semiconductor substrate, a second passivation layer B is arranged on the side of the second passivation layer A away from the second conductive type semiconductor region, an ultra-thin amorphous silicon layer is arranged on the side of the semiconductor substrate away from the second conductive type semiconductor region, a tunneling layer is arranged on the side of the ultra-thin amorphous silicon layer away from the semiconductor substrate, a first conductive type semiconductor region is arranged on the side of the tunneling layer away from the ultra-thin amorphous silicon layer, and a first passivation layer is arranged on the side of the first conductive type semiconductor region away from the tunneling layer. In the present invention, by arranging an ultra-thin amorphous silicon layer, the lattice mismatch problem between the semiconductor substrate and the tunneling layer can be alleviated, the generation of interface defects can be reduced, and thus the performance and reliability of the Topcon battery can be improved.

[0029] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention can be realized and obtained by the devices particularly pointed out in the written description and the drawings of the description.

[0030] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0032] Figure 1 A schematic diagram of the structure of a Topcon battery of the present invention;

[0033] Figure 2 It is a schematic diagram of the structure of the ventilation device in the present invention;

[0034] Figure 3 It is a schematic diagram of the internal structure of the air intake box in the present invention;

[0035] Figure 4 This is a schematic diagram of the internal structure of the gas injection pipe in the present invention;

[0036] Figure 5 It is a schematic diagram of the structure of the rotating cylinder in the present invention.

[0037] In the figure: 1. semiconductor substrate; 2. second conductive type semiconductor region; 3. second passivation layer A; 4. second passivation layer B; 5. ultra-thin amorphous silicon layer; 6. tunneling layer; 7. first conductive type semiconductor region; 8. first passivation layer; 9. air inlet box; 10. air injection pipe; 11. injection pipe; 12. reaction chamber; 13. rotating disk; 14. sliding frame; 15. sliding column; 16. driving rod; 17. piston block; 18. air inlet cavity; 19. first air inlet pipe; 20. second air inlet pipe; 21. air outlet pipe; 22. rotating shaft; 23. blades; 24. rotating column; 25. spiral guide groove; 26. rotating cylinder; 27. connecting hole; 28. driving plate; 29. ​​sliding block; 30. reciprocating screw; 31. filter. DETAILED DESCRIPTION

[0038] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0039] In addition, in the present invention, the descriptions of "first", "second", etc. are only used for descriptive purposes, and do not specifically refer to the order or sequence, nor are they used to limit the present invention. They are only used to distinguish components or operations described with the same technical terms, and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions and technical features between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0040] The embodiment of the present invention provides a Topcon battery structure, such as Figure 1As shown, it includes: a semiconductor substrate 1, a second conductive type semiconductor region 2 is arranged on one side of the semiconductor substrate 1, a second passivation layer A3 is arranged on the side of the second conductive type semiconductor region 2 away from the semiconductor substrate 1, a second passivation layer B4 is arranged on the side of the second passivation layer A3 away from the second conductive type semiconductor region 2, an ultra-thin amorphous silicon layer 5 is arranged on the side of the semiconductor substrate 1 away from the second conductive type semiconductor region 2, a tunneling layer 6 is arranged on the side of the ultra-thin amorphous silicon layer 5 away from the semiconductor substrate 1, a first conductive type semiconductor region 7 is arranged on the side of the tunneling layer 6 away from the ultra-thin amorphous silicon layer 5, and a first passivation layer 8 is arranged on the side of the first conductive type semiconductor region 7 away from the tunneling layer 6;

[0041] The thickness of the ultra-thin amorphous silicon layer 5 is 0.1-5 nm, preferably, the thickness of the ultra-thin amorphous silicon layer 5 is 0.1-3 nm; the thickness of the tunneling layer 6 is 0.1-5 nm, preferably, the thickness of the tunneling layer 6 is 0.1-2.5 nm;

[0042] The second passivation layer A3, the second passivation layer B4, and the first passivation layer 8 may have a single film selected from the group consisting of a silicon nitride film, a silicon nitride film containing hydrogen, a silicon oxide film, and a silicon nitride oxide; the film may be an aluminum oxide film, magnesium fluoride MgF2, zinc sulfide ZnS, titanium dioxide TiO2, and cerium oxide CeO2, or may have a multilayer structure in which two or more films selected from the group are combined;

[0043] The semiconductor substrate 1 may be a silicon substrate;

[0044] The first conductive type semiconductor region 7 is doped with a fifth main group element, such as phosphorus (P), arsenic (As), antimony (Sb) and bismuth (Bi);

[0045] The second conductive type semiconductor region 2 is doped with a third main group element, such as boron (B), aluminum (Al), gallium (Ga) and indium (In);

[0046] The tunneling layer 6 may be any one of oxide, nitride, semiconductor and conductive polymer.

[0047] The existing Topcon cell structure deposits silicon oxide on the back of the silicon substrate, which has the following defects:

[0048] 1) During the deposition of silicon oxide, stress may be generated between silicon oxide and the silicon substrate due to differences in thermal expansion coefficients and lattice mismatch. This stress may cause the silicon substrate to deform and bend, and may even cause defects such as cracks in the tunneling layer, affecting the performance and reliability of the device;

[0049] 2) There are some interface states at the interface between the silicon substrate and the tunneling layer. These interface states will capture carriers, increase the recombination probability of carriers, and reduce the electrical performance of the device. For example, interface states may shorten the lifetime of carriers, thereby affecting the photoelectric conversion efficiency of solar cells;

[0050] 3) Silicon oxide itself is an insulator, and electrons need to overcome a high potential barrier to tunnel through it. Although the quantum tunneling effect can be used to achieve electron transmission in ultra-thin cases, the thickness control of the tunneling layer is extremely strict. If the thickness is too thick, the probability of electron tunneling will drop sharply, affecting the collection of current, thereby reducing the photoelectric conversion efficiency of the battery; if the thickness is too thin, it may produce too many defects such as pinholes, reduce the passivation effect, and increase the recombination of carriers.

[0051] The Topcon battery structure of the present application is provided with an ultra-thin amorphous silicon layer 5 between the tunneling layer 6 and the semiconductor substrate 1. The ultra-thin amorphous silicon layer 5 has an energy band, and the band gap difference between the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 is less than the band gap difference between the semiconductor substrate 1 and the tunneling layer 6. When the thickness of the ultra-thin amorphous silicon layer 5 is extremely thin, the tunneling layer formed by the combination of the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 can utilize the quantum tunneling effect, so that electrons can cross the potential barrier with a higher probability.

[0052] In addition, the ultra-thin amorphous silicon layer 5 can alleviate the lattice mismatch problem between the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, reduce the generation of interface defects, and improve the performance and reliability of the Topcon battery. The structure of the ultra-thin amorphous silicon layer 5 is relatively flexible and can adapt to the lattice structure of the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, thereby reducing the stress and defect density at the interface.

[0053] The present invention also discloses a method for preparing a Topcon battery structure, which is used to prepare the Topcon battery structure, comprising the following steps:

[0054] Step 1: preparing a single-sided polished wafer that has undergone texturing, boron diffusion, and etching processes as a semiconductor substrate 1;

[0055] Step 2: placing the semiconductor substrate 1 into the reaction chamber 12;

[0056] Step 3: introducing silicon source gas and carrier gas into the reaction chamber 12 to prepare an ultra-thin amorphous silicon layer 5;

[0057] Step 4: preparing a tunneling layer 6 on the side of the ultra-thin amorphous silicon layer 5 away from the semiconductor substrate 1;

[0058] Step 5: preparing a first conductive type semiconductor region 7 on a side of the tunneling layer 6 away from the ultra-thin amorphous silicon layer 5;

[0059] Step 6: preparing a first passivation layer 8 on the side of the first conductive type semiconductor region 7 away from the tunneling layer 6, and then manufacturing a first electrode, wherein the first electrode passes through the first passivation layer and contacts the first conductive type semiconductor region;

[0060] Step 7: preparing a second conductive type semiconductor region 2 on a side of the semiconductor substrate 1 away from the first conductive type semiconductor region;

[0061] Step 8: preparing a second passivation layer A3 on a side of the second conductive type semiconductor region 2 away from the semiconductor substrate 1;

[0062] Step 9: Prepare a second passivation layer B and a second electrode, the second electrode passes through the second passivation layer B and the second passivation layer A to contact the second conductive type semiconductor region.

[0063] The working principle and beneficial effects of the above technical solution are as follows: first prepare a semiconductor substrate 1, the semiconductor substrate 1 is a single-sided polished wafer 1 that has undergone texturing, boron diffusion, and etching processes in sequence, and the semiconductor substrate 1 can be a silicon substrate; put the semiconductor substrate 1 into a reaction chamber 12; introduce silicon source gas and carrier gas (hydrogen can be selected as the carrier gas) into the reaction chamber 12 to prepare an ultra-thin amorphous silicon layer 5; prepare a tunneling layer 6 on the side of the ultra-thin amorphous silicon layer 5 away from the semiconductor substrate 1; prepare a first conductive type semiconductor region 7 on the side of the tunneling layer 6 away from the ultra-thin amorphous silicon layer 5; and A first passivation layer 8 is prepared on the side of the semiconductor region 7 away from the tunneling layer 6, and then a first electrode is made. The first electrode passes through the first passivation layer and contacts the first conductive type semiconductor region; a second conductive type semiconductor region 2 is prepared on the side of the semiconductor substrate 1 away from the first conductive type semiconductor region; a second passivation layer A3 is prepared on the side of the second conductive type semiconductor region 2 away from the semiconductor substrate 1; finally, a second passivation layer B4 and a second electrode are prepared according to the existing preparation process, and the second electrode passes through the second passivation layer B and the second passivation layer A and contacts the second conductive type semiconductor region.

[0064] The above scheme has the following advantages:

[0065] (1) By arranging an ultra-thin amorphous silicon layer 5 between the tunneling layer 6 and the semiconductor substrate 1, the ultra-thin amorphous silicon layer 5 has an energy band, and the band gap difference between the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 is less than the band gap difference between the semiconductor substrate 1 and the tunneling layer 6. When the thickness of the ultra-thin amorphous silicon layer 5 is extremely thin, the tunneling layer formed by the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 can utilize the quantum tunneling effect, so that electrons can pass through the potential barrier with a higher probability;

[0066] (2) The ultra-thin amorphous silicon layer 5 can alleviate the lattice mismatch problem between the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, and reduce the generation of interface defects. The structure of the ultra-thin amorphous silicon layer 5 is relatively flexible and can adapt to the lattice structure of the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, thereby reducing the stress and defect density at the interface. Specifically,

[0067] A. The lattice constant of silicon is about 5.43 angstroms. The structure of silicon oxide is relatively complex, and there is no single value that directly corresponds to the lattice constant of silicon. This lattice constant mismatch is more obvious between the silicon substrate and silicon oxide, because the structure and properties of silicon oxide are quite different from those of the silicon substrate;

[0068] B. Although ultra-thin amorphous silicon does not have a clear single lattice constant, the disorder of its atomic arrangement can be inferred that its average lattice constant is different from the lattice constant of the silicon substrate. However, due to the structural characteristics of amorphous silicon, it can alleviate the impact of lattice constant mismatch to a certain extent through its own structural adjustment;

[0069] C. Lattice matching of ultra-thin amorphous silicon: Although amorphous silicon lacks long-range order, it still has a certain degree of short-range order. Within a short distance, the atomic arrangement of amorphous silicon has a certain regularity, similar to the local structure of crystalline silicon. This short-range order enables amorphous silicon to form a certain match with the lattice structure of the silicon substrate in a local area when it contacts the silicon substrate.

[0070] (3) The performance of the tunneling layer can be precisely controlled by adjusting the thickness and doping concentration of the ultra-thin amorphous silicon layer 5 and the preparation process of the tunneling layer 6. This enables engineers to customize the optimal tunneling layer structure according to different application requirements to meet the performance requirements of various electronic devices.

[0071] Further, such as Figure 1-Figure 5 As shown, in step 3, silicon source gas and carrier gas are introduced into the reaction chamber 12 through a ventilation device, the ventilation device includes an air inlet box 9 and an air injection pipe 10, the air inlet box 9 is connected to the air injection pipe 10 through an air outlet pipe 21, and an injection pipe 11 is arranged at the output end of the air injection pipe 10, and one end of the injection pipe 11 extends into the reaction chamber 12;

[0072] An air intake assembly is arranged in the air intake box 9, and the air intake assembly includes a driving motor, which is arranged at the center of the air intake box 9, and is connected to the inner wall of the air intake box 9. A rotating disk 13 is arranged at the output end of the driving motor, and a sliding frame 14 is arranged in front of the rotating disk 13. The left and right sides of the sliding frame 14 are slidably connected to the inner wall of the air intake box 9 up and down, a sliding column 15 is arranged in the sliding frame 14, and the sliding column 15 is slidably connected to the inner wall of the sliding frame 14, and one end of the sliding column 15 is rotatably connected to the eccentric position of the rotating disk 13, and driving rods 16 are symmetrically arranged on the upper and lower sides of the sliding frame 14, and a piston block 17 is arranged at one end of the driving rod 16 away from the sliding frame 14, and an air intake cavity 18 is arranged on the side of the piston block 17 away from the driving motor. The first air inlet pipe 19 and the second air inlet pipe 20 are connected to the cavity 18, and the first air inlet pipe 19 and the second air inlet pipe 20 are both provided with a first one-way valve and a flow control valve. One end of the air outlet pipe 21 is connected to the air inlet cavity 18, and a second one-way valve is provided in the air outlet pipe 21. A rotating shaft 22 is provided on the side of the piston block 17 away from the driving motor. The rotating shaft 22 is rotatably connected to the piston block 17, and a blade 23 is provided on the rotating shaft 22. A rotating column 24 is rotatably provided on the side wall of the rotating shaft 22. The rotating column 24 is perpendicular to the rotating shaft 22, and the rotating column 24 is rotatably connected to the side wall of the rotating shaft 22. A spiral guide groove 25 is provided on the inner wall of the air inlet box 9, and the rotating column 24 extends into the spiral guide groove 25 away from one end of the rotating shaft 22 and is slidably connected to the inner wall of the spiral guide groove 25.

[0073] The working principle and beneficial effects of the above technical solution are as follows: the first air inlet pipe 19 is used to transport silicon source gas into the air inlet box 9, and the second air inlet pipe 20 is used to transport carrier gas into the air inlet box 9. When ventilation is introduced into the reaction chamber 12, the driving motor is started, and the rotation of the driving motor drives the rotating disk 13 to rotate, and the rotation of the rotating disk 13 drives the sliding column 15 to move, and the sliding column 15 drives the sliding frame 14 to reciprocate up and down in the air inlet box 9. When the sliding frame 14 moves, it can drive the piston block 17 to slide up and down in the air inlet box 9 through the driving rod 16. When the piston block 17 slides toward the direction close to the driving motor, the gas in the first air inlet pipe 19 and the second air inlet pipe 20 enters the air inlet chamber 18, and the silicon source gas and the carrier gas are mixed in the air inlet chamber 18 to form a mixed gas. When the piston block 17 slides toward the direction away from the driving motor, the piston block 17 presses the mixed gas into the air inlet chamber 18. Inlet and outlet pipes 21, the mixed gas enters the gas injection pipe 10 through the gas outlet pipe 21, and then is injected into the reaction chamber 12 through the injection pipe 11. The mixed gas can be compressed by the piston block 17, so that precise jetting can be achieved through the injection pipe 11 to improve the ventilation efficiency. The two air inlet chambers 18 can alternately supply gas to the gas injection pipe 10 to avoid interruption in the ventilation process, thereby ensuring the ventilation effect into the reaction chamber 12. In addition, during the sliding process of the piston block 17, the piston block 17 drives the rotating shaft 22 to move, and the rotating column 24 on the side wall of the rotating shaft 22 slides along the spiral guide groove 25 and drives the rotating shaft 22 to rotate. The rotation of the rotating shaft 22 drives the blade 23 to rotate. The rotation of the blade 23 can stir the mixed gas, improve the mixing efficiency of the silicon source gas and the carrier gas, and enhance the mixing effect of the silicon source gas and the carrier gas, thereby improving the preparation quality of the ultra-thin amorphous silicon layer 5.

[0074] Further, such as Figure 4 , Figure 5 As shown, a gas injection assembly is arranged in the gas injection pipe 10, and the gas injection assembly includes a rotating cylinder 26, the central axis of the rotating cylinder 26 is in the same straight line with the central axis of the gas injection pipe 10, and the two ends of the rotating cylinder 26 are respectively rotatably connected to the inner wall of the gas injection pipe 10, a plurality of connecting holes 27 are arranged on the side wall of the rotating cylinder 26, and a driving plate 28 is arranged on the outer wall of the rotating cylinder 26, and the driving plate 28 is W-shaped, and the driving plate 28 is in contact with the inner wall of the gas injection pipe 10 away from the side of the rotating cylinder 26, and a sliding block 29 is arranged in the rotating cylinder 26, and the sliding block 29 is slidably connected to the inner wall of the rotating cylinder 26 left and right, and a connecting hole is arranged in the center of the sliding block 29, and the sliding block 29 is transmission-connected to the outer wall of the reciprocating screw 30 through the connecting hole, and the reciprocating screw 30 is arranged in the rotating cylinder 26, and one end of the reciprocating screw 30 is fixedly connected to the inner wall of the gas injection pipe 10, and a filter screen 31 and a third one-way valve are arranged in the injection pipe 11.

[0075] The working principle and beneficial effects of the above technical solution are as follows: after the mixed gas enters the gas injection tube 10 through the gas outlet pipe 21, part of the mixed gas can push the driving plate 28 to move, and the driving plate 28 drives the rotating cylinder 26 to rotate in the gas injection tube 10. By rotating the driving plate 28, the mixed gas is stirred to further improve the mixing effect of the mixed gas. The sliding block 29 can rotate synchronously with the rotating cylinder 26. During the rotation process, the sliding block 29 reciprocates left and right along the reciprocating screw 30, and part of the mixed gas enters the rotating cylinder 26 through the connecting hole 27. The reciprocating sliding block 29 can push the mixed gas in the rotating cylinder 26, so that the mixed gas further collides and mixes with each other, thereby enhancing the mixing effect. Finally, the evenly mixed mixed gas passes through the filter 31 into the reaction chamber 12, thereby ensuring the smooth preparation of the ultra-thin amorphous silicon layer 5.

[0076] Example 1

[0077] A method for preparing a Topcon battery structure includes:

[0078] 1. Preparation

[0079] A single-side polished wafer that has undergone texturing, boron diffusion, and etching processes in sequence is used as a semiconductor substrate 1.

[0080] (II) Sedimentation process

[0081] 1. Introduce 5000-10000 sccm of nitrogen into the LPCVD / PECVD reaction chamber 12 to make the pressure inside the reaction chamber 12 consistent with the external pressure, and set the temperature of the reaction chamber 12 at 300-500°C;

[0082] 2. Grab the carrier carrying the polishing sheet into the reaction chamber 12 with a robot, set the gas flow rate to 0, and evacuate the reaction chamber 12 for 80-200 seconds;

[0083] 3. Raise the temperature of the reaction chamber 12 to 300-380°C;

[0084] 4. Set the pressure to 0 at the process temperature and perform a tightness check on the reaction chamber 12, requiring that the air leakage does not exceed 120 mTorr per minute;

[0085] 5. Raise the temperature of the reaction chamber 12 to reach the target deposition temperature, preferably 350-380°C;

[0086] 6. A silicon source gas of 1000-3000 sccm (such as silane) and a carrier gas of 5000-15000 sccm (such as hydrogen) are introduced into the reaction chamber 12 for a reaction time of 5-50 seconds to prepare an ultra-thin amorphous silicon layer 5 with a thickness of 0.1-5 nm, more preferably 0.1-3 nm;

[0087] 7. Introduce 8000-20000sccm of oxygen source gas (such as laughing gas) and 800-5000sccm of silicon source gas (such as silane) into the reaction chamber 12 for 50-300s to prepare a tunneling layer 6 having a thickness of 0.1-5nm, more preferably 0.1-2.5nm;

[0088] 8. Raise the temperature of the reaction chamber 12 to 420-500°C;

[0089] 9. A mixed gas containing 1000-5000 sccm of silicon source gas (such as silane), 100-1000 sccm of doping gas (the doping gas is a first conductive type impurity gas containing a 5th main group element, such as phosphine, etc., for controlling the conductivity type and doping concentration of the first conductive type semiconductor region) and 5000-20000 sccm of hydrogen is introduced into the reaction chamber 12 to prepare an amorphous silicon layer A, wherein the ratio of silane to phosphine is 3-8, the reaction time is 300-800 S, and the thickness is 10-80 nm, more preferably 20-30 nm;

[0090] 10. A mixed gas containing 1000-5000 sccm of silicon source gas (such as silane), 1500-5000 sccm of doping gas (the doping gas is a first conductive type impurity gas containing a 5th main group element, such as phosphine, etc., for controlling the conductive type and doping concentration of the first conductive type semiconductor region) and 3000-15000 sccm of hydrogen is introduced into the reaction chamber 12 to prepare an amorphous silicon layer B, wherein the ratio of silane to phosphine is 0.8-5, the reaction time is 500-2000 S, and the thickness is 20-90 nm, more preferably 60-80 nm;

[0091] 11. The sum of the thickness of the amorphous silicon layer A and the amorphous silicon layer B is 30-170 nm;

[0092] 12. 5000-10000sccm of oxygen source gas (such as laughing gas) and 800-5000sccm of silicon source gas (such as silane) are introduced into the reaction chamber 12 for 50-200s to prepare a tunneling layer 6 to protect the internal first conductive type semiconductor region (which will be washed away in the subsequent cleaning process);

[0093] 13. Annealing process: using a quartz tube as a reaction chamber 12 to crystallize the poly post-doped amorphous silicon into doped polysilicon; introducing nitrogen gas at 5000-10000 sccm into the reaction chamber 12 to make the pressure inside the reaction chamber 12 consistent with the external pressure, and setting the temperature of the reaction chamber 12 at 600-1200°C;

[0094] 14. Grab the carrier carrying the poly-coated semiconductor substrate 1 into the reaction chamber 12 with a robot, set the gas flow rate to 0, and perform vacuum treatment in the reaction chamber 12 for 80-200 seconds;

[0095] 15. Raise the temperature of the reaction chamber 12 to 800-2000°C;

[0096] 16. Introduce nitrogen gas into the reaction chamber 12 at a flow rate of 6000-20000 sccm, while maintaining a constant temperature treatment for 500-1500 seconds;

[0097] 17. Based on the previous step, the temperature of the reaction chamber 12 is raised by 15-50°C;

[0098] 18. Introduce nitrogen gas into the reaction chamber 12 at a flow rate of 6000-20000 sccm, while maintaining a constant temperature treatment for 2000-5000 seconds;

[0099] 19. The total constant temperature time is 2500-8000S to allow for full crystallization;

[0100] (III) Post-processing

[0101] According to the existing Topcon preparation process, the first passivation layer 8, the first electrode, the second passivation layer A3, the second passivation layer B4, and the second electrode are prepared respectively, and finally a Topcon battery structure is manufactured.

[0102] Example 2

[0103] Another method for preparing the Topcon battery structure includes:

[0104] 1. Preparation

[0105] A single-side polished wafer that has undergone texturing, boron diffusion, and etching processes in sequence is used as a semiconductor substrate 1.

[0106] (II) Sedimentation process

[0107] 1. Introduce nitrogen gas at 1000-10000 sccm into the LPCVD / PECVD reaction chamber 12 to make the pressure inside the reaction chamber 12 consistent with the external pressure, and set the temperature of the reaction chamber 12 at 400-800°C;

[0108] 2. Grab the carrier carrying the polishing sheet into the reaction chamber 12 with a robot, set the gas flow rate to 0, and evacuate the reaction chamber 12 for 120-300 seconds;

[0109] 3. Set the pressure to 0 at the process temperature and perform a tightness check on the reaction chamber 12, requiring that the air leakage does not exceed 120 mTorr per minute;

[0110] 4. Raise the temperature of the reaction chamber 12 to reach the target deposition temperature, preferably 400-1000° C.;

[0111] 5. Maintain the above temperature, constant temperature 200-800S;

[0112] 6. A silicon source gas of 1000-3000 sccm (such as silane) and a carrier gas of 500-2000 sccm (such as hydrogen) are introduced into the reaction chamber 12 for a reaction time of 5-50 seconds to prepare an ultra-thin amorphous silicon layer 5 with a thickness of 0.1-5 nm, more preferably 0.1-3 nm;

[0113] 7. Introduce 10000-50000 sccm of oxygen source gas (such as oxygen) into the reaction chamber 12 for 200-800 s to prepare a tunneling layer 6 with a thickness of 0.1-5 nm, more preferably 0.1-2.5 nm;

[0114] 8. Maintain the above temperature and pressure, constant temperature 200-600S;

[0115] 9. Evacuate the air to gradually reduce the pressure to the limit;

[0116] 10. Introduce silane at 200-2000 sccm to purge the reaction chamber 12 for 30-200 seconds;

[0117] 11. Introduce silane at 2000-20000sccm and keep the temperature constant for 30-300S;

[0118] 12. Set the pressure to 0 at the process temperature and perform a tightness check on the reaction chamber 12, requiring that the air leakage does not exceed 120 mTorr per minute;

[0119] 13. Introduce silane 1000-10000sccm and nitrogen 100-1000sccm to control the pressure at 100-2000 and the time at 10-60S;

[0120] 14. Maintain the above conditions at constant temperature and pressure for 800-3000S, and utilize the thermal decomposition of silane to generate SiH2 and hydrogen to deposit the poly layer;

[0121] 15. Evacuate the pressure to the limit, then introduce nitrogen at 300-3000sccm to clean the furnace tube;

[0122] 16. Evacuate the chamber to reduce the pressure to the limit, clear the environment in the reaction chamber 12, and reduce the temperature by 500-800°C;

[0123] 17. Introduce nitrogen gas at 800-8000 sccm to break the vacuum so that the pressure inside and outside the reaction chamber 12 is balanced before leaving the boat;

[0124] 18. Phosphorus diffusion process (doping): using a quartz tube as a reaction chamber 12 to dope the polysilicon of the poly layer to become doped polysilicon; introducing nitrogen gas at 2000-10000 sccm into the reaction chamber 12 to make the pressure inside the reaction chamber 12 consistent with that outside, and setting the temperature of the reaction chamber 12 at 600-1200°C;

[0125] 19. Grab the carrier carrying the poly-coated semiconductor substrate 1 into the reaction chamber 12 with a robot, set the gas flow rate to 0, and evacuate the reaction chamber 12, with the pressure controlled at 50-500 for 60-200 seconds;

[0126] 20. Raise the temperature of the reaction chamber 12 to 700-1500° C.;

[0127] 21. Introduce source (phosphorus oxychloride) gas (nitrogen) 800-3000sccm, oxygen 200-2000sccm, nitrogen 300-3000sccm into the reaction chamber 12, the pressure is controlled at 50-500, and the time is 400-2000S;

[0128] 22. The reaction chamber 12 is heated to a temperature of 800-2000°C;

[0129] 23. Introduce source (phosphorus oxychloride) gas (nitrogen) 500-2500sccm and nitrogen 800-5000sccm into the reaction chamber 12, the pressure is controlled at 50-500, and the time is 600-2000S;

[0130] 24. Introduce source (phosphorus oxychloride) gas (nitrogen) 500-2500sccm, oxygen 500-5000sccm, nitrogen 800-5000sccm into the reaction chamber 12, the pressure is controlled at 100-800, and the time is 300-1000S;

[0131] 25. Introduce 200-5000sccm of source (phosphorus oxychloride) gas (nitrogen), 500-5000sccm of oxygen, and 500-5000sccm of nitrogen into the reaction chamber 12, control the pressure at 300-2000, and gradually reduce the temperature to 600-1200°C for 500-5000S;

[0132] 26. Introduce a source gas (which may be phosphorus oxychloride) (which may be nitrogen) at 1000-5000 sccm and nitrogen at 800-5000 sccm into the reaction chamber 12, and control the pressure at 50-500 for 30-600 seconds;

[0133] 27. Introduce nitrogen gas at 2000-10000 sccm into the reaction chamber 12 to make the pressure inside the reaction chamber 12 consistent with the external pressure. At the same time, set the temperature of the reaction chamber 12 at 600-1200°C to make the pressure inside and outside the reaction chamber 12 balanced before leaving the boat;

[0134] (III) Post-processing

[0135] According to the existing Topcon preparation process, the first passivation layer 8, the first electrode, the second passivation layer A3, the second passivation layer B4, and the second electrode are prepared respectively, and finally a Topcon battery structure is manufactured.

[0136] In the above scheme, by arranging the ultra-thin amorphous silicon layer 5 between the tunneling layer 6 and the semiconductor substrate 1, the ultra-thin amorphous silicon layer 5 has an energy band, and the band gap difference between the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 is less than the band gap difference between the semiconductor substrate 1 and the tunneling layer 6. When the thickness of the ultra-thin amorphous silicon layer 5 is extremely thin, the tunneling layer formed by the combination of the ultra-thin amorphous silicon layer 5 and the tunneling layer 6 can utilize the quantum tunneling effect, so that electrons can pass through the potential barrier with a higher probability;

[0137] In addition, the ultra-thin amorphous silicon layer 5 can alleviate the lattice mismatch problem between the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, and reduce the generation of interface defects. The structure of the ultra-thin amorphous silicon layer 5 is relatively flexible and can adapt to the lattice structure of the semiconductor substrate 1 and the tunneling layer 6 to a certain extent, thereby reducing the stress and defect density at the interface.

[0138] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0139] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0140] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and the implementation methods. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A Topcon battery structure, characterized in that: include: A semiconductor substrate, a second conductive type semiconductor region is arranged on one side of the semiconductor substrate, a second passivation layer A is arranged on the side of the second conductive type semiconductor region away from the semiconductor substrate, a second passivation layer B is arranged on the side of the second passivation layer A away from the second conductive type semiconductor region, an ultra-thin amorphous silicon layer is arranged on the side of the semiconductor substrate away from the second conductive type semiconductor region, a tunneling layer is arranged on the side of the ultra-thin amorphous silicon layer away from the semiconductor substrate, a first conductive type semiconductor region is arranged on the side of the tunneling layer away from the ultra-thin amorphous silicon layer, and a first passivation layer is arranged on the side of the first conductive type semiconductor region away from the tunneling layer.

2. A Topcon battery structure according to claim 1, characterized in that: The thickness of the ultra-thin amorphous silicon layer is 0.1-5 nm.

3. A Topcon battery structure according to claim 1, characterized in that: The thickness of the tunneling layer is 0.1-5 nm.

4. A method for preparing a Topcon battery structure, for preparing a Topcon battery structure as claimed in any one of claims 1 to 3, characterized in that: The following steps are involved: Step 1: Prepare a single-sided polished wafer that has undergone texturing, boron diffusion, and etching processes as a semiconductor substrate; Step 2: placing the semiconductor substrate into the reaction chamber; Step 3: introducing silicon source gas and carrier gas into the reaction chamber to prepare an ultra-thin amorphous silicon layer; Step 4: preparing a tunneling layer on the side of the ultra-thin amorphous silicon layer away from the semiconductor substrate; Step 5: preparing a first conductivity type semiconductor region on a side of the tunneling layer away from the ultra-thin amorphous silicon layer; Step 6: preparing a first passivation layer on a side of the first conductive type semiconductor region away from the tunneling layer, and then manufacturing a first electrode, wherein the first electrode passes through the first passivation layer and contacts the first conductive type semiconductor region; Step 7: preparing a second conductive type semiconductor region on a side of the semiconductor substrate away from the first conductive type semiconductor region; Step 8: preparing a second passivation layer A on a side of the second conductive type semiconductor region away from the semiconductor substrate; Step 9: Prepare a second passivation layer B and a second electrode, the second electrode passes through the second passivation layer B and the second passivation layer A to contact the second conductive type semiconductor region.

5. A method for preparing a Topcon battery structure according to claim 4, characterized in that: In step 2, nitrogen is first introduced into the reaction chamber to make the pressure inside the reaction chamber consistent with that outside, and the temperature of the reaction chamber is set within a preset temperature range. Then, the semiconductor substrate is placed in the reaction chamber, the introduction of nitrogen is stopped, and the reaction chamber is vacuumed.

6. A method for preparing a Topcon battery structure according to claim 5, characterized in that: After the vacuum treatment, the reaction chamber is checked for tightness, and the air leakage in the reaction chamber does not exceed 120mTorr per minute.

7. A method for preparing a Topcon battery structure according to claim 6, characterized in that: After the airtightness check is completed, the temperature of the reaction chamber is increased to make the temperature inside the reaction chamber reach the deposition target temperature.

8. A method for preparing a Topcon battery structure according to claim 4, characterized in that: Preparing a first conductive type semiconductor region includes: A mixed gas containing a silicon source gas, a doping gas and a carrier gas is introduced into the reaction chamber to prepare an amorphous silicon layer A; A mixed gas containing a silicon source gas, a doping gas and a carrier gas is introduced into the reaction chamber to prepare an amorphous silicon layer B; Finally, doped amorphous silicon is obtained, and the doped amorphous silicon is crystallized into doped polysilicon to obtain a first conductive type semiconductor region.

9. A method for preparing a Topcon battery structure according to claim 8, characterized in that: The sum of the thicknesses of the amorphous silicon layer A and the amorphous silicon layer B is 30-170 nm.

10. A method for preparing a Topcon battery structure according to claim 4, characterized in that: The preparation of the first conductive type semiconductor region includes: depositing polysilicon on the surface of the tunneling layer, performing a doping process on the polysilicon to form doped polysilicon, and preparing the first conductive type semiconductor region.

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