Hall sensor and preparation method thereof

Abstract

The invention discloses a Hall sensor and a preparation method thereof. The preparation method of the Hall sensor comprises the following steps: providing a P-type substrate, and forming a P-type deep trap, a low-doped N trap and a shallow trench isolation layer on the P-type substrate; preparing an active layer on the low-doped N well; preparing a first deep groove and a second deep groove on the P-type substrate and the shallow groove isolation layer; the first deep groove and the second deep groove are filled with N-type doped polycrystalline silicon; and preparing four N + contact layers. According to the embodiment of the invention, the Hall sensor which is higher in sensitivity and measurement precision and stronger in anti-interference capability is prepared through the steps.

Description

Technical Field

[0001] The present invention relates to the technical field of sensors, and in particular to a Hall sensor and a preparation method thereof. Background Art

[0002] Hall sensors are widely used in various magnetic field measurement, current measurement, position detection, speed measurement and other occasions due to their high sensitivity, good stability and wide measurement range.

[0003] The Hall sensor is a sensor that uses the Hall effect to measure parameters such as magnetic fields. When the magnetic field passes vertically through the Hall disk, the electrons flowing in the Hall disk are affected by the Lorentz force of the magnetic field and turn. At this time, the voltage can be measured at the other end of the intersection. By measuring this voltage, the detection of parameters such as magnetic fields can be achieved.

[0004] The existing Hall sensor has a high bias voltage and contains more non-magnetic field noise in the output voltage due to the sensitivity of the structure, size, N-well injection concentration and other reasons, which affects the sensitivity and measurement accuracy of the Hall sensor. Summary of the invention

[0005] The present invention provides a Hall sensor and a method for manufacturing the same, so as to reduce the noise introduced by the bias voltage in the Hall sensor, thereby improving the sensitivity and measurement accuracy of the Hall sensor. According to one aspect of the present invention, a Hall sensor is provided, comprising:

[0006] P-type substrate;

[0007] The P-type deep well, low-doped N-well and active layer are stacked on the P-type substrate in sequence.

[0008] In the orthographic projection of the plane where the P-type substrate is located, the P-type deep well, the low-doped N-well and the active layer are all in a cross shape, and the P-type deep well and the active layer are all located in the low-doped N-well, the active layer includes a central area and four branch arm areas connected to the central area, the four branch arm areas include a first branch arm area, a second branch arm area, a third branch arm area and a fourth branch arm area, the first branch arm area and the second branch arm area are located on two sides of the central area that are away from each other in a first direction, the third branch arm area and the fourth branch arm area are located on two sides of the central area that are away from each other in a second direction, the first direction and the second direction are orthogonal and parallel to the plane where the P-type substrate is located;

[0009] Four N+ contact layers, including a first N+ contact layer, a second N+ contact layer, a third N+ contact layer and a fourth N+ contact layer, wherein the first N+ contact layer and the second N+ contact layer are respectively located at a side of the first arm region and the second arm region away from the central region in the first direction, and the third N+ contact layer and the fourth N+ contact layer are respectively located at a side of the third arm region and the fourth arm region away from the central region in the first direction; there is a gap between the N+ contact layer and the corresponding arm region;

[0010] The first deep trench and the second deep trench are both filled with N-type doped polysilicon and are both located above the P-type substrate; in the orthographic projection of the plane where the P-type substrate is located, the first deep trench is respectively adjacent to and extends in parallel with the edges of the first arm region and the second arm region extending in the first direction and the edges of the third arm region and the fourth arm region extending in the second direction; the second deep trench is located below the four N+ contact layers; the N-type doped polysilicon in the second deep trench is respectively in contact with the low-doped N well and the N+ contact layer, and there is a gap between the second deep trench and the P-type deep well and the active layer;

[0011] The shallow trench isolation layer is located above the P-type substrate and is located in a region of the P-type substrate excluding the active layer, the first deep trench and the N+ contact layer.

[0012] Optionally, the first deep trench includes a first sub-deep trench, a second sub-deep trench, a third sub-deep trench and a fourth sub-deep trench;

[0013] The orthographic projections of the first sub-deep trench, the second sub-deep trench, the third sub-deep trench and the fourth sub-deep trench on the plane where the P-type substrate is located are all L-shaped;

[0014] In the orthographic projection of the plane where the P-type substrate is located, the first sub-deep trench is adjacent to and extends in parallel with the edge of the first arm region extending along the first direction and the edge of the third arm region extending along the second direction, the second sub-deep trench is adjacent to and extends in parallel with the edge of the second arm region extending along the first direction and the edge of the third arm region extending along the second direction, the third sub-deep trench is adjacent to and extends in parallel with the edge of the first arm region extending along the first direction and the edge of the fourth arm region extending along the second direction, and the fourth sub-deep trench is adjacent to and extends in parallel with the edge of the second arm region extending along the first direction and the edge of the fourth arm region extending along the second direction.

[0015] Optionally, the bottom surfaces of the first deep trench and the second deep trench have the same height, and are lower than or equal to the height of the bottom surface of the low-doped N-well.

[0016] Optionally, a depth H of the first deep groove satisfies: 10 μm≤H≤80 μm.

[0017] Optionally, in the orthographic projection of the plane where the P-type substrate is located, a width D of the first deep trench in a vertical extension direction satisfies: 0<D≤10 μm.

[0018] Optionally, in the orthographic projection of the plane where the P-type substrate is located, a gap L between the first deep trench and the active layer satisfies: 0≤L≤10 μm.

[0019] Optionally, the doping concentration of the low-doped N-well is 1*e15 to 1*e17 cells / cm 3 .

[0020] According to another aspect of the present invention, there is provided a method for preparing a Hall sensor, for preparing the Hall sensor according to the first aspect, the method comprising:

[0021] A P-type substrate is provided, and a P-type deep well, a low-doped N-well and a shallow trench isolation layer are formed on the P-type substrate; wherein the P-type deep well and the low-doped N-well are stacked in sequence; in the orthographic projection of the plane where the P-type substrate is located, the P-type deep well and the low-doped N-well are both in a cross shape, and the P-type deep well is located in the low-doped N-well, and the shallow trench isolation layer overlaps with the low-doped N-well at most in part;

[0022] An active layer is prepared on a low-doped N-well; wherein, in an orthographic projection of a plane where a P-type substrate is located, the active layer is in a cross shape, and the active layer is located in the low-doped N-well, the active layer does not overlap with a shallow trench isolation layer, the active layer includes a central region and four arm regions connected to the central region, the four arm regions include a first arm region, a second arm region, a third arm region, and a fourth arm region, the first arm region and the second arm region are located on two sides of the central region that are away from each other in a first direction, the third arm region and the fourth arm region are located on two sides of the central region that are away from each other in a second direction, the first direction and the second direction are orthogonal and parallel to the plane where the P-type substrate is located;

[0023] A first deep trench and a second deep trench are formed on the P-type substrate and the shallow trench isolation layer; wherein, in the orthographic projection of the plane where the P-type substrate is located, the first deep trench is adjacent to and extends in parallel with the edges of the first arm region and the second arm region extending in the first direction and the edges of the third arm region and the fourth arm region extending in the second direction;

[0024] The second deep trench is located below the four N+ contact layers; the N-type doped polysilicon in the second deep trench is in contact with the low-doped N well and the N+ contact layer respectively, and there is a gap between the P-type deep well and the active layer;

[0025] Filling N-type doped polysilicon in the first deep trench and the second deep trench; the N-type doped polysilicon in the second deep trench is in contact with the low-doped N-well and has a gap with the P-type deep well and the active layer;

[0026] Four N+ contact layers are prepared; the four N+ contact layers include a first N+ contact layer, a second N+ contact layer, a third N+ contact layer and a fourth N+ contact layer, the first N+ contact layer and the second N+ contact layer are respectively located on the side of the first arm region and the second arm region away from the central region in the first direction, the third N+ contact layer and the fourth N+ contact layer are respectively located on the side of the third arm region and the fourth arm region away from the central region in the first direction; there is a gap between the N+ contact layer and the corresponding arm region; the four N+ contact layers are located above the second deep trench and in contact with the N-type doped polysilicon in the second deep trench.

[0027] Optionally, filling the first deep trench and the second deep trench with N-type doped polysilicon includes:

[0028] Depositing N-type doped polysilicon so that the first deep trench and the second deep trench are filled with N-type doped polysilicon, and a polysilicon layer is formed on the shallow trench isolation layer;

[0029] The polysilicon layer on the shallow trench isolation layer is removed.

[0030] Optionally, a P-type substrate is provided, and a P-type deep well, a low-doped N-well, and a shallow trench isolation layer are formed on the P-type substrate, including:

[0031] Providing a P-type substrate;

[0032] sequentially forming a P-type deep well and a low-doped N-well in a P-type substrate;

[0033] A shallow trench isolation region is formed on the surface of the P-type substrate.

[0034] The technical solution of the embodiment of the present invention solves the problem that the bias voltage of the traditional Hall sensor is high and the output voltage contains more non-magnetic field noise by setting an isolation structure of N-type polysilicon, effectively reduces the deviation of drift electrons in the N-well resistor, and at the same time fully isolates the interference of free electrons in the P-type region, reduces the bias voltage and non-magnetic field noise, and thus improves the sensitivity and measurement accuracy of the Hall sensor.

[0035] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0037] Figure 1 is a schematic structural diagram of a Hall sensor provided by an embodiment of the present invention;

[0038] Figure 2 is a longitudinal cross-sectional view of a Hall sensor provided by an embodiment of the present invention;

[0039] Figure 3 is a longitudinal cross-sectional view of another Hall sensor provided by an embodiment of the present invention;

[0040] Figure 4 is a schematic structural diagram of another Hall sensor provided by an embodiment of the present invention;

[0041] Figure 5 is a flow chart of a method for preparing a Hall sensor provided by an embodiment of the present invention;

[0042] Figure 6-Figure 20 A schematic diagram of the structures of five Hall sensors provided in an embodiment of the present invention;

[0043] Fig.21 is a flow chart of another method for preparing a Hall sensor provided by an embodiment of the present invention;

[0044] Fig. 22 It is a flow chart of another method for preparing a Hall sensor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0045] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0047] Figure 1 is a schematic diagram of the structure of a Hall sensor provided by an embodiment of the present invention, Figure 2 is a longitudinal cross-sectional view of a Hall sensor provided by an embodiment of the present invention, Figure 3 is a longitudinal cross-sectional view of another Hall sensor provided by an embodiment of the present invention, Figure 2 The longitudinal section view shown corresponds to Figure 1 The blue arrow position, Figure 3 The longitudinal section view shown corresponds to Figure 1 The red arrow position.

[0048] like Figure 1 , Figure 2 and Figure 3As shown, in some embodiments, the Hall sensor includes: a P-type substrate 10, a P-type deep well 20, a low-doped N-well 30 and an active layer 40. Figure 2 and Figure 3 As shown, the P-type deep well 20, the low-doped N-well 30 and the active layer 40 are sequentially stacked on the P-type substrate 10. Figure 1 As shown, in the orthographic projection of the plane where the P-type substrate 10 is located, the P-type deep well 20, the low-doped N-well 30 and the active layer 40 are all distributed in a cross shape. The P-type deep well 20 is located at the center of the low-doped N-well 30, and the active layer 40 is further located at the center of the P-type deep well 20. Figure 1 As shown, the active layer 40 includes a central region 45 and four arm regions connected to the central region 45, namely, a first arm region 41, a second arm region 42, a third arm region 43 and a fourth arm region 44. Figure 1 , the first direction is the positive direction of the x-axis, the second direction is the positive direction of the y-axis, the first arm region 41 and the second arm region 42 are located on two sides of the central region 45 that are away from each other in the first direction, the first arm region 41 is located in the positive direction of the x-axis compared to the central region 45, and the second arm region 42 is located in the negative direction of the x-axis compared to the central region 45. The third arm region 43 and the fourth arm region 44 are located on two sides of the central region 45 that are away from each other in the second direction, the third arm region 43 is located in the positive direction of the y-axis compared to the central region 45, and the fourth arm region 44 is located in the negative direction of the y-axis compared to the central region 45. The first direction and the second direction are orthogonal and parallel to the plane where the P-type substrate 10 is located. Among them, the P-type substrate 10 can be understood as a semiconductor substrate in which the majority of carriers are holes (positive charge); the P-type deep well 20 can be understood as a deeper P-type region formed in the P-type substrate 10; the low-doped N-well 30 can be understood as an N-type region formed in the P-type deep well 20, but with a lower doping concentration; the active layer 40 can be understood as a region in the semiconductor structure for current conduction and signal processing. In the Hall sensor, the active layer 40 is used to detect changes in the magnetic field.

[0049] like Figure 1 and Figure 3 As shown, four N+ contact layers 50 include a first N+ contact layer 51, a second N+ contact layer 52, a third N+ contact layer 53 and a fourth N+ contact layer 54. The first N+ contact layer 51 and the second N+ contact layer 52 are respectively located on the first arm region 41 and the second arm region 42 on the side away from the central region 45 in the first direction, and the third N+ contact layer 53 and the fourth N+ contact layer 54 are respectively located on the third arm region 43 and the fourth arm region 44 on the side away from the central region 45 in the first direction. Figure 3As shown, there is a gap between the N+ contact layer 50 and the corresponding arm region. The N+ contact layer 50 can be understood as a high-doping concentration N-type region for forming a loop with an external circuit, and current flows from the external circuit into or out of the active layer 40 through the N+ contact layer 50.

[0050] like Figure 1 , Figure 2 and Figure 3 As shown, the first deep trench 60 and the second deep trench 70 are both filled with N-type doped polysilicon and are both located above the P-type substrate 10. Figure 1 As shown, in the orthographic projection of the plane where the P-type substrate 10 is located, the first deep groove 60 is adjacent to and extends in parallel with the edges of the first arm region 41 and the second arm region 42 extending along the first direction and the edges of the third arm region 43 and the fourth arm region 44 extending along the second direction; the second deep groove 70 is located below the four N+ contact layers 50. Figure 3 As shown, the N-type doped polysilicon in the second deep trench 70 is in contact with the low-doped N well 30 and the N+ contact layer 50, respectively, and there is a gap between the P-type deep well 20 and the active layer 40. The deep trench can be understood as a deep groove etched in the semiconductor substrate; the N-type doped polysilicon can be understood as a polysilicon material doped with N-type impurities (such as phosphorus), which is used as a filling material for the first deep trench 60 and the second deep trench 70.

[0051] like Figure 1 , Figure 2 and Figure 3 As shown, the shallow trench isolation layer 80 is located above the P-type substrate 10 and is located on the P-type substrate 10 except the active layer 40, the first deep trench 60 and the N+ contact layer 50. The shallow trench isolation layer 80 can be understood as being filled with insulating material to prevent current from flowing between different circuit regions. The shallow trench isolation layer 80 helps to protect the active layer 40 from interference from the external environment, plays a further electrical isolation role, and improves the stability and reliability of the Hall sensor.

[0052] In the embodiment of the present invention, the P-type substrate 10 provides a semiconductor platform; the P-type deep well 20 is located above the P-type substrate 10 to provide electrical isolation from the low-doped N-well 30; the low-doped N-well 30 is located above the P-type deep well 20 to form a low-doped N-well region of the Hall sensor; the active layer 40 is located above the P-type deep well 20, and the cross-shaped distribution of the active layer 40 structure helps to achieve more accurate and stable magnetic field measurement; the first deep groove 60 and the second deep groove 70 filled with N-type polysilicon are located on the periphery of the Hall disk structure, on the one hand, as an isolation member of the Hall device, providing an electrical isolation effect, blocking the drifting electrons deviated in the Hall disk, and reducing the influence of the free electrons in the P-type substrate 10 on the Hall disk. On the other hand, the N-type polysilicon in the second deep groove 70 connects the low-doped N-well 30 layer and the N+ contact layer 50, which enhances the magnetic field detection sensitivity of the Hall sensor and reduces the bias voltage and noise.

[0053] In an optional embodiment, the bottom surface heights of the first deep trench 60 and the second deep trench 70 are the same, and are lower than or equal to the bottom surface height of the low-doped N-well 30. By setting the first deep trench 60 and the second deep trench 70 to the same depth, it is helpful to reduce process steps, reduce production costs, and improve production efficiency. In addition, designing the bottom surface of the deep trench below the N-well can enhance the isolation effect and reduce the mutual influence between different functional areas. Exemplarily, the depth of the first deep trench 60 and the second deep trench 70 can be set to 0.5-60μm.

[0054] In an optional embodiment, the depth H of the first deep trench 60 satisfies: 10 μm ≤ H ≤ 80 μm. One of the main functions of the first deep trench is to isolate different functional areas, such as the low-doped N-well 30 of the Hall disk and the adjacent P-type substrate 10. The total depth of the three layers of the P-type deep well 20, the low-doped N-well 30 and the active layer 40 is about 1 μm. A deeper deep trench can provide better isolation effect, reduce signal interference and noise, and thus improve the sensitivity of the Hall sensor.

[0055] In an optional embodiment, in the orthographic projection of the plane where the P-type substrate 10 is located, the width D of the first deep trench 60 in the vertical extension direction satisfies: 0<D≤10μm. The main function of the first deep trench 60 is to provide electrical isolation to reduce signal interference and noise between different functional areas. By controlling its width D, it can be ensured that the deep trench has sufficient isolation capability while avoiding unnecessary process complexity and cost increase that may be caused by an overly wide deep trench.

[0056] In an optional embodiment, in the orthographic projection of the plane where the P-type substrate 10 is located, the gap L between the first deep groove 60 and the active layer 40 satisfies: 0≤L≤10μm. The main function of the first deep groove 60 is to provide electrical isolation to reduce signal interference and noise between different functional areas. By controlling the gap L between it and the active layer 40, it can be ensured that an effective isolation barrier is formed around the active layer, thereby protecting the active layer from interference from the external environment. When the gap L is 0, the Hall element is completely isolated from the P-type substrate 10, and the isolation effect is the best; as the gap increases, the isolation effect declines slightly. When L=10μm, the isolation effect drops to a critical value. If L continues to increase, the isolation effect will not be achieved. Therefore, considering the tolerance problem in the semiconductor manufacturing process, controlling the gap L within a certain range can ensure that the Hall sensor has good performance and will not have too high manufacturing difficulty, which not only improves the overall performance of the Hall sensor, but also effectively reduces the production cost.

[0057] In an optional embodiment, the doping concentration of the low-doped N well 30 is 1*e15 to 1*e17 cells / cm 3 The doping concentration of the low-doped N-well 30 refers to the number of impurity atoms doped per unit volume. Specifically, the doping concentration of the low-doped N-well 30 is set to 1*e15 to 1*e17 atoms / cm 3 Ensure that the N-well has appropriate conductivity and carrier concentration. Within this concentration range, the linear relationship between the Hall voltage and the magnetic field strength is more significant, thereby improving the sensitivity of the sensor.

[0058] Figure 4 is a schematic diagram of the structure of another Hall sensor provided by an embodiment of the present invention, such as Figure 2 As shown, in some embodiments, the first deep trench 60 includes a first sub-deep trench 61, a second sub-deep trench 62, a third sub-deep trench 63 and a fourth sub-deep trench 64;

[0059] The orthographic projections of the first sub-trench 61, the second sub-trench 62, the third sub-trench 63 and the fourth sub-trench 64 on the plane where the P-type substrate 10 is located are all L-shaped;

[0060] In the orthographic projection of the plane where the P-type substrate 10 is located, the first sub-deep groove 61 is adjacent to and extends in parallel with the edge of the first arm area 41 extending along the first direction and the edge of the third arm area 43 extending along the second direction, the second sub-deep groove 62 is adjacent to and extends in parallel with the edge of the second arm area 42 extending along the first direction and the edge of the third arm area 43 extending along the second direction, the third sub-deep groove 63 is adjacent to and extends in parallel with the edge of the first arm area 41 extending along the first direction and the edge of the fourth arm area 44 extending along the second direction, and the fourth sub-deep groove 64 is adjacent to and extends in parallel with the edge of the second arm area 52 extending along the first direction and the edge of the fourth arm area 44 extending along the second direction.

[0061] Specifically, the first deep groove 60 is subdivided into four sub-deep grooves: a first sub-deep groove 61, a second sub-deep groove 62, a third sub-deep groove 63 and a fourth sub-deep groove 64. The orthographic projections of the four sub-deep grooves on the plane where the P-type substrate 10 is located are all L-shaped, and they have a specific adjacent and parallel relationship with the four arm regions (the first arm region 41, the second arm region 42, the third arm region 43 and the fourth arm region 44). The independently arranged sub-deep grooves can be adjusted separately when the Hall element is in the interference of other circuit elements or certain specific spatial layouts without affecting other sub-grooves.

[0062] The embodiment of the present invention subdivides the first deep trench 60 into four sub-deep trenches: a first sub-deep trench 61 , a second sub-deep trench 62 , a third sub-deep trench 63 and a fourth sub-deep trench 64 , which helps to more accurately control the electrical isolation between different functional areas and reduce signal interference and noise.

[0063] Based on the Hall sensor of the above embodiment, an embodiment of the present invention further provides a method for preparing a Hall sensor. Figure 5 It is a flow chart of a method for preparing a Hall sensor provided in an embodiment of the present invention, which is used to prepare the Hall sensor shown in the above embodiment. Figure 6-Figure 20 The schematic diagram of the structure of five Hall sensors provided in the embodiments of the present invention is as follows: Figure 6-Figure 20 The structural diagram of the Hall sensor shown in the figure corresponds to Figure 5 The top view of each step in the process diagram of a preparation method of a Hall sensor, the blue line longitudinal section in the top view, and the red line longitudinal section in the top view. Figure 5 , the preparation method comprises:

[0064] S110 , providing a P-type substrate, and forming a P-type deep well, a low-doped N-well, and a shallow trench isolation layer on the P-type substrate.

[0065] Among them, Figure 6 , Figure 7 and Figure 8 As shown, the P-type deep well and the low-doped N-well are stacked in sequence; in the orthographic projection of the plane where the P-type substrate is located, the P-type deep well and the low-doped N-well are both cross-shaped, and the P-type deep well is located in the low-doped N-well, and the shallow trench isolation layer overlaps with the low-doped N-well at most.

[0066] Specifically, a P-type deep well and a low-doped N-well are formed on a P-type substrate through specific process steps (such as ion implantation, etc.). After the above steps, a shallow trench is formed through process steps such as photolithography and etching. Then, an isolation material (such as silicon oxide, etc.) is used to fill the shallow trench to form a shallow trench isolation layer to achieve effective circuit element isolation.

[0067] S120, preparing an active layer on the low-doped N-well.

[0068] Among them, Fig. 9 , Fig.10 and Fig.11 As shown, in the orthographic projection of the plane where the P-type substrate is located, the active layer is cross-shaped, and the active layer is located in the low-doped N-well, the active layer does not overlap with the shallow trench isolation layer, the active layer includes a central area and four branch arm areas connected to the central area, the four branch arm areas include a first branch arm area, a second branch arm area, a third branch arm area and a fourth branch arm area, the first branch arm area and the second branch arm area are located on both sides of the central area that are away from each other in a first direction, the third branch arm area and the fourth branch arm area are located on both sides of the central area that are away from each other in a second direction, and the first direction and the second direction are orthogonal and parallel to the plane where the P-type substrate is located.

[0069] Specifically, first, the low-doped N-well is cleaned to remove impurities and contaminants on the surface. Then, an active layer with a specific doping concentration and thickness is prepared on the low-doped N-well by epitaxial growth or other methods. Finally, annealing treatment, surface treatment, etc. are performed to further improve its quality and stability.

[0070] S130, preparing a first deep trench and a second deep trench on the P-type substrate and the shallow trench isolation layer.

[0071] Among them, Fig.12 , Fig.13 and Fig.14 As shown, in the orthographic projection of the plane where the P-type substrate is located, the first deep groove is respectively adjacent to and extends in parallel with the edges of the first arm region and the second arm region extending in the first direction and the edges of the third arm region and the fourth arm region extending in the second direction; the second deep groove is located below the four N+ contact layers; the N-type doped polysilicon in the second deep groove is respectively in contact with the low-doped N well and the N+ contact layer, and there is a gap with the P-type deep well and the active layer;

[0072] Specifically, a photoresist layer with a specific pattern is formed on the P-type substrate and the shallow trench isolation layer using a photolithography technique, and an etching technique (such as wet etching or dry etching) is used to remove the P-type substrate and the shallow trench isolation layer material below the photoresist layer to form a first deep trench and a second deep trench. The preparation of the first deep trench and the second deep trench helps to achieve electrical isolation between different functional areas and prevent unnecessary interference or leakage of current or signals between different areas.

[0073] S140 , filling N-type doped polysilicon in the first deep trench and the second deep trench.

[0074] Among them, Fig.15 , Fig.16 and Fig.17 As shown, the N-type doped polysilicon in the second deep trench is in contact with the low-doped N-well, and there is a gap between the P-type deep well and the active layer.

[0075] Specifically, chemical vapor deposition, physical vapor deposition or other techniques are used to deposit N-type doped polysilicon in the first deep trench and the second deep trench. After the deposition is completed, annealing is performed to eliminate stress and defects in the deposited layer, while promoting the diffusion and activation of dopants. Finally, excess deposited layer material is removed by chemical etching and / or mechanical grinding. There is a gap between the first deep trench and the P-type deep well, the low-doped N-well and the active layer, which shields the free charges in the P-type substrate and blocks the overflow of charges in the Hall element. In the second deep trench, it is in contact with the low-doped N-well, and there is a gap between it and the P-type deep well and the active layer, forming an effective conductive channel with the low-doped N-well.

[0076] S150, preparing four N+ contact layers.

[0077] Among them, Fig.18 , Fig.19 and Fig. 20 As shown, the four N+ contact layers include a first N+ contact layer, a second N+ contact layer, a third N+ contact layer and a fourth N+ contact layer. The first N+ contact layer and the second N+ contact layer are respectively located on the side of the first arm region and the second arm region away from the central region in the first direction, and the third N+ contact layer and the fourth N+ contact layer are respectively located on the side of the third arm region and the fourth arm region away from the central region in the first direction; there is a gap between the N+ contact layer and the corresponding arm region; the four N+ contact layers are located above the second deep trench and in contact with the N-type doped polysilicon in the second deep trench.

[0078] Specifically, a high-concentration N+ contact layer is formed in the area above the second deep groove at the end of the four arm regions of the Hall sensor by ion implantation or epitaxial growth. The main function of the N+ contact layer is to provide electrical connection with the Hall element so as to transmit the signal generated by the Hall element to the external circuit.

[0079] The embodiment of the present invention first prepares the basic structure of the Hall element by forming a P-type deep well, a low-doped N-well, a shallow trench isolation layer and an active layer on a P-type substrate. Then, by preparing the first deep trench and the second deep trench and filling them with N-type doped polysilicon, the free charges in the P-type substrate are shielded, the overflow of charges in the Hall element is blocked, and an effective conductive channel is formed with the low-doped N-well. Finally, four N+ contact layers are prepared to provide electrical connection with the Hall element. The embodiment of the present invention prepares a Hall sensor with higher sensitivity and measurement accuracy and stronger anti-interference ability through the above steps.

[0080] Fig.21 is a schematic flow chart of another method for preparing a Hall sensor provided by an embodiment of the present invention, with reference to Fig.21, the preparation method of the Hall sensor based on the above embodiment is refined or optimized. Specifically, filling the first deep trench and the second deep trench with N-type doped polysilicon includes: depositing N-type doped polysilicon to fill the first deep trench and the second deep trench with N-type doped polysilicon, and forming a polysilicon layer on the shallow trench isolation layer; removing the polysilicon layer on the shallow trench isolation layer.

[0081] For details not yet provided in this embodiment, please refer to the previous embodiment.

[0082] like Fig.21 As shown, a schematic flow chart of another method for preparing a Hall sensor provided by an embodiment of the present invention includes the following steps:

[0083] S210 , providing a P-type substrate, and forming a P-type deep well, a low-doped N-well, and a shallow trench isolation layer on the P-type substrate.

[0084] S220 , preparing an active layer on the low-doped N-well.

[0085] S230 , preparing a first deep trench and a second deep trench on the P-type substrate and the shallow trench isolation layer.

[0086] S240 , depositing N-type doped polysilicon to fill the first deep trench and the second deep trench with N-type doped polysilicon, and forming a polysilicon layer on the shallow trench isolation layer.

[0087] Specifically, chemical vapor deposition or physical vapor deposition technology is used to deposit N-type doped polysilicon on the first deep trench, the second deep trench and the shallow trench isolation layer. During the deposition process, the deposition rate and thickness need to be precisely controlled to obtain the desired filling effect and surface quality.

[0088] S250, removing the polysilicon layer on the shallow trench isolation layer.

[0089] Specifically, the excess polysilicon layer on the shallow trench isolation layer may form unnecessary electrical connections with other parts of the Hall element. Therefore, according to the thickness, material properties and process requirements of the polysilicon layer on the shallow trench isolation layer, an appropriate removal method is selected, such as chemical etching, physical grinding or ion beam etching, to ensure that only the excess polysilicon layer is removed without affecting other parts of the Hall element.

[0090] S260, prepare four N+ contact layers.

[0091] The embodiment of the present invention provides a method for preparing a Hall sensor, wherein N-type doped polysilicon is deposited on a first deep trench, a second deep trench, and a shallow trench isolation layer by precisely controlling the deposition rate and thickness, thereby ensuring the desired filling effect and surface quality. The excess polysilicon layer on the shallow trench isolation layer is removed to avoid unnecessary electrical connections, thereby ensuring the performance and stability of the Hall element. The above steps jointly ensure the structural stability, electrical connection quality, and process compatibility of the Hall element, thereby improving the performance and reliability of the sensor.

[0092] Fig. 22 is a schematic flow chart of another method for preparing a Hall sensor provided by an embodiment of the present invention, with reference to Fig. 22 , the preparation method of the Hall sensor based on the above embodiment is refined or optimized. Specifically, a P-type substrate is provided, and a P-type deep well, a low-doped N-well and a shallow trench isolation layer are formed on the P-type substrate, including: providing a P-type substrate; sequentially forming a P-type deep well and a low-doped N-well in the P-type substrate; and forming a shallow trench isolation region on the surface of the P-type substrate.

[0093] For details not yet provided in this embodiment, please refer to the previous embodiment.

[0094] like Fig. 22 As shown, a schematic flow chart of another method for preparing a Hall sensor provided by an embodiment of the present invention includes the following steps:

[0095] S310 , providing a P-type substrate.

[0096] Specifically, a semiconductor substrate with a P-type conductivity and holes as the majority carrier is prepared, and necessary cleaning and pretreatment are performed to ensure that its surface is clean and free of defects.

[0097] S320 , sequentially forming a P-type deep well and a low-doped N-well in the P-type substrate.

[0098] Specifically, a specific mask and ion implantation equipment are used to implant P-type or N-type impurity ions into the substrate, and the impurity ions are uniformly distributed in the substrate through a diffusion process.

[0099] S330, forming a shallow trench isolation region on the surface of the P-type substrate.

[0100] Specifically, a shallow groove with a specific shape and size is formed on the surface of the substrate using photolithography and etching methods, and then filled with a suitable isolation material (such as silicon dioxide) and cured.

[0101] S340, preparing an active layer on the low-doped N-well.

[0102] S350, preparing a first deep trench and a second deep trench on the P-type substrate and the shallow trench isolation layer.

[0103] S360 , filling N-type doped polysilicon in the first deep trench and the second deep trench.

[0104] S370, prepare four N+ contact layers.

[0105] The embodiment of the present invention can ensure that the Hall element has a stable structure and good electrical isolation performance by forming a P-type deep well, a low-doped N-well and a shallow trench isolation region, thereby improving the stability and reliability of the sensor.

[0106] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0107] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A Hall sensor, characterized in that: P-type substrate; A P-type deep well, a low-doped N-well and an active layer are sequentially stacked on the P-type substrate. In the orthographic projection of the plane where the P-type substrate is located, the P-type deep well, the low-doped N-well and the active layer are all in a cross shape, and the P-type deep well and the active layer are both located in the low-doped N-well, the active layer includes a central area and four branch arm areas connected to the central area, the four branch arm areas include a first branch arm area, a second branch arm area, a third branch arm area and a fourth branch arm area, the first branch arm area and the second branch arm area are located on two sides of the central area that are away from each other in a first direction, the third branch arm area and the fourth branch arm area are located on two sides of the central area that are away from each other in a second direction, the first direction and the second direction are orthogonal and parallel to the plane where the P-type substrate is located; Four N+ contact layers, including a first N+ contact layer, a second N+ contact layer, a third N+ contact layer and a fourth N+ contact layer, wherein the first N+ contact layer and the second N+ contact layer are respectively located at a side of the first arm region and the second arm region away from the central region in the first direction, and the third N+ contact layer and the fourth N+ contact layer are respectively located at a side of the third arm region and the fourth arm region away from the central region in the first direction; there is a gap between the N+ contact layer and the corresponding arm region; The first deep trench and the second deep trench are both filled with N-type doped polysilicon and are both located above the P-type substrate; in the orthographic projection of the plane where the P-type substrate is located, the first deep trench is respectively adjacent to and extends in parallel with the edges of the first branch arm region and the second branch arm region extending along the first direction and the edges of the third branch arm region and the fourth branch arm region extending along the second direction; The second deep trench is located below the four N+ contact layers; the N-type doped polysilicon in the second deep trench is in contact with the low-doped N well and the N+ contact layer respectively, and there is a gap between the second deep trench and the P-type deep well and the active layer; A shallow trench isolation layer is located above the P-type substrate and in a region of the P-type substrate excluding the active layer, the first deep trench and the N+ contact layer.

2. The Hall sensor according to claim 1, characterized in that: The first deep trench includes a first sub-deep trench, a second sub-deep trench, a third sub-deep trench and a fourth sub-deep trench; The orthographic projections of the first sub-deep trench, the second sub-deep trench, the third sub-deep trench and the fourth sub-deep trench on the plane where the P-type substrate is located are all L-shaped; In the orthographic projection of the plane where the P-type substrate is located, the first sub-deep groove is adjacent to and extends in parallel with the edge of the first branch arm area extending along the first direction and the edge of the third branch arm area extending along the second direction, the second sub-deep groove is adjacent to and extends in parallel with the edge of the second branch arm area extending along the first direction and the edge of the third branch arm area extending along the second direction, the third sub-deep groove is adjacent to and extends in parallel with the edge of the first branch arm area extending along the first direction and the edge of the fourth branch arm area extending along the second direction, and the fourth sub-deep groove is adjacent to and extends in parallel with the edge of the second branch arm area extending along the first direction and the edge of the fourth branch arm area extending along the second direction.

3. The Hall sensor according to claim 1, characterized in that: The bottom surfaces of the first deep trench and the second deep trench have the same height, and are lower than or equal to the height of the bottom surface of the low-doped N-well.

4. The Hall sensor according to claim 3, characterized in that: The depth H of the first deep groove satisfies: 10 μm≤H≤80 μm.

5. The Hall sensor according to claim 1, characterized in that: In the orthographic projection of the plane where the P-type substrate is located, the width D of the first deep trench in the vertical extension direction satisfies: 0<D≤10μm.

6. The Hall sensor according to claim 1, characterized in that: In the orthographic projection of the plane where the P-type substrate is located, a gap L between the first deep trench and the active layer satisfies: 0≤L≤10 μm.

7. The Hall sensor according to claim 1, characterized in that: The doping concentration of the low-doped N well is 1*e15 to 1*e17 per cm 3 .

8. A method for preparing a Hall sensor, characterized in that: For preparing the Hall sensor according to any one of claims 1 to 7, the preparation method comprises: A P-type substrate is provided, and a P-type deep well, a low-doped N-well and a shallow trench isolation layer are formed on the P-type substrate; wherein the P-type deep well and the low-doped N-well are stacked in sequence; in the orthographic projection of the plane where the P-type substrate is located, the P-type deep well and the low-doped N-well are both in a cross shape, and the P-type deep well is located in the low-doped N-well, and the shallow trench isolation layer overlaps with the low-doped N-well at most in part; An active layer is prepared on the low-doped N-well; wherein, in the orthographic projection of the plane where the P-type substrate is located, the active layer is in a cross shape, and the active layer is located in the low-doped N-well, the active layer does not overlap with the shallow trench isolation layer, the active layer includes a central area and four arm areas connected to the central area, the four arm areas include a first arm area, a second arm area, a third arm area and a fourth arm area, the first arm area and the second arm area are located on two sides of the central area that are away from each other in a first direction, the third arm area and the fourth arm area are located on two sides of the central area that are away from each other in a second direction, the first direction and the second direction are orthogonal and parallel to the plane where the P-type substrate is located; A first deep trench and a second deep trench are formed on the P-type substrate and the shallow trench isolation layer; wherein, in the orthographic projection of the plane where the P-type substrate is located, the first deep trench is adjacent to and extends in parallel with the edges of the first arm region and the second arm region extending along the first direction and the edges of the third arm region and the fourth arm region extending along the second direction, respectively; The second deep trench is located below the four N+ contact layers; the N-type doped polysilicon in the second deep trench is in contact with the low-doped N well and the N+ contact layer respectively, and there is a gap between the second deep trench and the P-type deep well and the active layer; Filling N-type doped polysilicon in the first deep trench and the second deep trench; the N-type doped polysilicon in the second deep trench is in contact with the low-doped N-well, and there is a gap between the N-type doped polysilicon and the P-type deep well and the active layer; Prepare four N+ contact layers; the four N+ contact layers include a first N+ contact layer, a second N+ contact layer, a third N+ contact layer and a fourth N+ contact layer, the first N+ contact layer and the second N+ contact layer are respectively located on the side of the first arm region and the second arm region away from the central region in the first direction, the third N+ contact layer and the fourth N+ contact layer are respectively located on the side of the third arm region and the fourth arm region away from the central region in the first direction; there is a gap between the N+ contact layer and the corresponding arm region; the four N+ contact layers are located above the second deep trench and in contact with the N-type doped polysilicon in the second deep trench.

9. The preparation method according to claim 8, characterized in that: Filling N-type doped polysilicon in the first deep trench and the second deep trench comprises: Depositing N-type doped polysilicon so that the first deep trench and the second deep trench are filled with N-type doped polysilicon, and a polysilicon layer is formed on the shallow trench isolation layer; The polysilicon layer on the shallow trench isolation layer is removed.

10. The preparation method according to claim 8, characterized in that: Providing a P-type substrate, and forming a P-type deep well, a low-doped N-well, and a shallow trench isolation layer on the P-type substrate, including: Providing a P-type substrate; Sequentially forming the P-type deep well and the low-doped N-well in the P-type substrate; The shallow trench isolation region is formed on the surface of the P-type substrate.

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