Patch antenna in package

Abstract

In an example, a semiconductor package (300) includes a semiconductor substrate (1039) including a device side having circuitry formed therein. The package further comprises: a conductive layer (1000) positioned over the semiconductor substrate; a patch antenna (112) coupled to the conductive layer and the device side of the semiconductor substrate; and a molding compound (304) covering the patch antenna. The molding compound has a relative dielectric constant in the range of 3.4 to 3.5 and a loss tangent in the range of 0.0025 to 0.013.

Description

Background Art

[0001] A device participating in wireless communications may include one or more antennas. Such antennas may be incorporated into a wireless device in various configurations. In some configurations, an antenna may be included on a semiconductor die as well as circuitry configured to operate the antenna for wireless communications. Such an antenna may be referred to as an "on-die antenna" because it is on the semiconductor die or because it is co-located with the semiconductor die in the same semiconductor package. Summary of the invention

[0002] In an example, a semiconductor package includes a semiconductor substrate including a device side having a circuit system formed therein. The package also includes: a conductive layer positioned above the semiconductor substrate; a patch antenna coupled to the conductive layer and the device side of the semiconductor substrate; and a molding compound covering the patch antenna. The molding compound has a relative dielectric constant in a range of 3.4 to 3.5 and a loss tangent in a range of 0.0025 to 0.013.

[0003] In an example, a method for manufacturing a semiconductor package includes: coupling a first conductive layer to a semiconductor substrate; coupling a second conductive layer to the first conductive layer using a through hole, the through hole extending through an insulating layer between the first conductive layer and the second conductive layer, the second conductive layer being farther from the semiconductor substrate than the first conductive layer; forming a cavity in a surface of the second conductive layer facing away from the semiconductor substrate, the cavity having a metal base plate and a plurality of metal walls, the base plate and the plurality of walls being coupled to a ground connection of the semiconductor substrate through the through hole; positioning a patch antenna in the cavity; and covering the patch antenna with a molding compound. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A is a perspective view of a patch antenna semiconductor die configured to efficiently radiate wireless signals according to various examples.

[0005] Figure 1B A top-down view of a patch antenna semiconductor die configured to efficiently radiate wireless signals according to various examples.

[0006] Figure 1C is a cross-sectional view of a patch antenna semiconductor die configured to efficiently radiate wireless signals according to various examples.

[0007] Figure 2A is a perspective view of a patch antenna configured to efficiently radiate wireless signals according to various examples.

[0008] Figure 2B is a top-down view of a patch antenna configured to efficiently radiate wireless signals according to various examples.

[0009] Figure 3A is a perspective view of a patch antenna semiconductor package configured to effectively radiate wireless signals according to various examples.

[0010] Figure 3B A top-down view of a patch antenna semiconductor package configured to efficiently radiate wireless signals according to various examples.

[0011] Figure 3C is a cross-sectional view of a patch antenna semiconductor package configured to effectively radiate wireless signals according to various examples.

[0012] Figure 4 is a graph depicting radiation efficiency as a function of thickness of various molding compounds in a patch antenna semiconductor package according to various examples.

[0013] Figure 5A is a perspective view of a patch antenna semiconductor package according to various examples and a radiation gain pattern that effectively radiates a wireless signal.

[0014] Figure 5B A first cross-sectional view of a patch antenna semiconductor package and a radiation gain pattern for effectively radiating a wireless signal according to various examples.

[0015] Figure 5C FIG. 4 is a second cross-sectional view of a patch antenna semiconductor package and a radiation gain pattern for effectively radiating a wireless signal according to various examples.

[0016] Figure 6 is a 3-D polar plot of the gain of a wireless signal effectively radiated by a patch antenna semiconductor package according to various examples.

[0017] Figure 7 Graphs depicting gain and return loss as a function of frequency of a signal radiated by a patch antenna semiconductor package according to various examples.

[0018] Figure 8 is a graph depicting radiation efficiency as a function of signal frequency for a range of different relative dielectric constants of patch antenna semiconductor package molding compounds according to various examples.

[0019] Fig. 9 is a graph depicting radiation efficiency as a function of signal frequency for a range of different loss tangents of patch antenna semiconductor package molding compounds according to various examples.

[0020] Fig.10 is a cutaway cross-sectional view of a patch antenna semiconductor die configured to efficiently radiate wireless signals according to various examples.

[0021] Fig.11is a flow chart of a method for manufacturing a chip antenna semiconductor package according to various examples.

[0022] Figures 12A to 12J 1 is a process flow of a method for manufacturing a chip antenna semiconductor package according to various examples. DETAILED DESCRIPTION

[0023] On-chip antennas suffer from multiple disadvantages that reduce operational radiation efficiency. These disadvantages are particularly problematic in the millimeter wave range, such as in the range of 30 GHz to 300 GHz. For example, in some configurations of semiconductor packages, the on-chip patch antenna (i.e., an antenna comprising a planar metal sheet coupled to a ground plane or positioned adjacent to a ground plane) is positioned at an unfavorable distance from the ground plane, and thus this configuration of two metal plates (antenna and ground plane) separated by a dielectric exhibits capacitive behavior, tending to store energy rather than radiate energy. This reduces operational efficiency. In addition, the molding compound used to cover the components of the semiconductor package containing the patch antenna has an inherent property of causing significant dielectric losses to the energy to be radiated. In addition, structures adjacent to the patch antenna and the semiconductor package containing the antenna can reflect or absorb the radiated energy, thereby reducing the radiation efficiency. When a wireless signal is radiated with poor directivity (i.e., the radiated energy is not focused in a specific direction), the signal is likely to encounter these adjacent structures, which will reduce the total amount of energy that can reach the intended wireless communication target.

[0024] The present disclosure describes various examples of patch antenna semiconductor packages that reduce the challenges described above. Specifically, an example package includes a semiconductor die having a ground structure that extends through the die from the device (i.e., circuit system) side of the silicon near the bottom of the die to the patch antenna near the top of the die. The ground structure may, for example, include four walls, each of which includes a series of metal layers and vias coupled in a chain configuration that extends vertically through the die by coupling to the silicon at one end (e.g., at the ground node of the silicon) and extending to a cavity that accommodates the patch antenna at the other end. In addition, in some examples, the cavity at the top of the package may contain a patch antenna and may have a bottom plate and walls covered by or composed of metal that are coupled to the metal layers and via chains described above. During operation, the ground structure directs radiated energy vertically and outwardly away from the die, and the ground structure prevents energy from radiating horizontally. In this way, the ground structure promotes radiation of energy in the desired direction, rather than dissipating energy in horizontal (lateral) or other undesirable directions. The ground structure is described as having four walls, but the ground structure may have a different number of walls (eg, three or five walls).

[0025] In addition, in an example, the semiconductor package described herein includes a molding compound covering the components of the package, such as a semiconductor die, a patch antenna, etc. The molding compound has specific properties that are critical to improving radiation efficiency and directivity. For optimal performance, experimental simulation data indicate that it is critical that the molding compound of the semiconductor package has a dielectric constant of 2.36 to 3.4 and a loss tangent of 0.013 to 0.0025. The molding compound may have other features that also improve radiation efficiency, such as a thickness of approximately one-quarter of the wavelength of the radiated signal (between the patch antenna and the top of the molding compound) (a molding compound thickness of one-quarter of the signal wavelength used, because in wave theory, this thickness contributes to constructive interference and therefore contributes to radiation efficiency, such as when a wave incident from an antenna traverses a 1 / 4 wavelength molding compound thickness, it is reflected back from the media interface toward the antenna and therefore traverses the 1 / 4 wavelength distance again, and combines with the wave incident from the antenna). These and other features are now described with reference to the drawings.

[0026] Figure 1A 1 is a perspective view of a patch antenna semiconductor die 100 configured to effectively radiate wireless signals according to various examples. The die 100 may be included as part of a semiconductor package, as described below. The die 100 includes a component 102 and a component 104. In the example, the component 104 is part of the component 102, but is shown as a separate component for ease of understanding. The component 102 may include various components, such as a silicon substrate including a device side in which a circuit system is formed. The component 102 may also include a back-end process (BEOL), which includes metal layers, insulating materials that separate the metal layers from each other, and through holes connecting the metal layers. Some of the metal layers may form a network to facilitate communication between various circuit systems on the device side of the silicon. These features are described below. The component 104 may include the final or topmost metal layer of the BEOL. Therefore, the BEOL extends across both components 102 and 104. Some of the metal layers may form a network to facilitate communication between various circuit systems on the device side of the silicon and the bonding pads 306 on the component 104.

[0027] Component 104 includes a cavity 106. Cavity 106 has a floor 108 and a plurality of walls 110. As explained, cavity 106 and floor 108 may cover the metal layers of component 104, or they may be formed by the metal layers of component 104. The cavity houses a patch antenna 112 (e.g., a 45 nm complementary metal oxide semiconductor (CMOS) process). Cavity 106 may have any suitable size and shape to accommodate patch antenna 112. Patch antenna 112 includes a radiating element 114 and a feed line 116 coupled to radiating element 114. Radiating element 114 may be appropriately shaped and sized to radiate energy (signal) outward and away from component 104. As shown, feed line 116 extends horizontally from radiating element 114, and at a point away from radiating element 114, feed line 116 couples vertically downward to the BEOL in component 102. Feed line 116 supplies a signal between the BEOL in component 102 and radiating element 114.

[0028] The floor 108 and / or walls 110 of the cavity 106 include metal that is coupled to a ground node in the die 100. In some examples, the floor 108 and / or walls 110 are separate from the component 104, but coupled to or in contact with the component, which itself may be a topmost metal layer. In other examples, the floor 108 and / or walls 110 are part of the component 104 (e.g., a topmost metal layer). In some examples, the BEOL of components 102 and 104 (as mentioned, described in more detail below) are connected to a ground node on the silicon in component 102, and through a series of connections in the BEOL of component 102, the ground node extends from the silicon all the way to the component 104, the floor 108, and the walls 110. This forms one wall of the aforementioned ground structure. Additionally, similar walls may be formed in the die 100, and these walls may be coupled to each other, similar to the way the walls of a rectangular prism may be coupled to each other. The ground structure prevents or blocks energy from being radiated horizontally. Figure 1B is a top-down view of a die 100 according to various examples. Figure 1C is a cross-sectional view of a die 100 according to various examples.

[0029] Figure 2A and 2B supply Figures 1A to 1C A more detailed view of the patch antenna 112 is shown in FIG. 1 . Specifically, Figure 2A is a perspective view of a patch antenna 112 configured to efficiently radiate wireless signals according to various examples. Figure 2B1 is a top-down view of a patch antenna 112 configured to efficiently radiate wireless signals according to various examples. The cavity 106 has specific dimensions to promote radiation efficiency, and these dimensions are shown relative to the patch antenna 112. The distance 118 between any point on the wall 110 and the closest point on the patch antenna 112 should be in the range of 20 microns to 30 microns, wherein a distance 118 below this range is unfavorable due to increased coupling between the patch and the grounded wall, and wherein a distance above this range is unfavorable because it will increase surface wave modes. The length of the patch antenna 112 is approximately half the wavelength of the signal transmitted from or received by the patch antenna 112, and the width of the patch antenna 112 is tuned to produce a wide bandwidth as required. The patch antenna 112 receives communications from the circuit system in the tube core 100 by means of the feed line 116 and receives radiated energy accordingly, and likewise, the patch antenna 112 receives wireless communications and provides corresponding signals to the feed line 116 to provide to the circuit system. In an example, feed line 116 is a microstrip. In an example, feed line 116 is a 50 ohm microstrip having a width of approximately 17 microns. In an example, patch antenna 112 is configured to operate in the millimeter wave range (e.g., 30 GHz to 300 GHz). Circuitry in communication with patch antenna 112 may be located on silicon, in the BEOL of die 100, on substrate 108, or any combination thereof.

[0030] Figure 3A 3 is a perspective view of a patch antenna semiconductor package 300 configured to effectively radiate wireless signals according to various examples. In an example, the package 300 includes a substrate 302 on which a semiconductor die 100 is placed. For example, the die 100 can be placed on the substrate 302 with the aid of a die attach film. A molding compound 304 can be applied to cover the die 100 and the substrate 302. The circuit system within the die 100 (e.g., the circuit system formed on silicon) can communicate with electronic components outside the package 300 through wire bonds 310 that couple bonding pads 306 to conductive terminals 308. The conductive terminals 308 are exposed to the outside of the molding compound 304, thereby allowing the conductive terminals 308 to be coupled (e.g., soldered) to metal contacts on a printed circuit board or other device. Figure 3B for Figure 3A A top-down view of the structure of Figure 3C for Figure 3A A cross-sectional view of the structure.

[0031] The molding compound 304 has specific properties that promote radiation efficiency. The thickness of the molding compound 304 measured from the top surface of the patch antenna 112 to the top surface of the molding compound 304 is approximately one-quarter of the wavelength of the signal that the patch antenna 112 is configured to radiate. Experimental data indicates that the molding compound 304 with this thickness (i.e., one-quarter of the wavelength of the signal that the patch antenna 112 is configured to radiate) improves the radiation efficiency by 20% compared to the molding compound that does not have this specific thickness. Therefore, this molding compound thickness is critical to achieving an approximately 20% improvement in excellent radiation efficiency, and molding compounds that are thinner or thicker than this thickness will produce poor radiation efficiency results. In addition to the thickness of the molding compound 304, the composition of the molding compound 304 affects the radiation efficiency. Table 1 provides experimental data on the critical material properties of the actual molding compound 304 to achieve excellent radiation efficiency, especially with respect to the relative dielectric constant and loss tangent of the molding compound 304. Materials 1 to 5 listed in Table 1 are epoxy-based molding compounds including silica filler particles.

[0032] Table 1. Experimental data showing critical material properties of molding compound 304 for achieving good radiation efficiency.

[0033] Material Relative dielectric constant Loss tangent Material 1 2.36 0.013 Material 2 3.4 0.0025 Material 3 3.5 0.013 Material 4 3.55 0.0095 Material 5 3.86 0.011

[0034] Figure 4 The properties of materials 1 to 5 are depicted in Table 1. Specifically, Figure 4 is a graph depicting radiation efficiency as a function of the thickness of the molding compound 304 at a frequency of 300 GHz. The thickness of the molding compound 304 is defined as the distance from the top surface of the patch antenna 112 to the top surface of the molding compound 304. The frequency of 300 GHz is the frequency at which the patch antenna 112 radiates energy. Figure 4 The behavior depicted in holds for frequencies in the millimeter wave band, not just for 300 GHz. Figure 4In graph 400 of FIG. 400 , curve 402 depicts the performance of material 1; curve 404 depicts the performance of material 2; curve 406 depicts the performance of material 3; curve 408 depicts the performance of material 4; and curve 410 depicts the performance of material 5. The lower the loss tangent of a given material, the higher the radiation efficiency of the material. This is true for the propagation of electromagnetic waves through any dielectric medium. However, the radiation efficiency of materials with different dielectric constants is not easily predicted. As described below, experiments indicate that the particular process (e.g., a radio frequency (RF) CMOS process) used to form the back end of line (BEOL) metal layers of the semiconductor die in a given package, the properties of the intermetallic dielectric materials used for the BEOL metal layers, and the manner in which these materials interact with the dielectric constant of the molding compound 304 contribute to the radiation efficiency of the molding compound 304. The molding compound 304 thickness is plotted on the x-axis of graph 400, while the y-axis plots the radiation efficiency. Curve 402 shows that material 1 performs particularly poorly relative to materials 2 to 5 in the 0.0 mm to 0.18 mm molding compound thickness range, and that it performs relatively well in the 0.2 mm to 0.3 mm and 0.5 mm to 0.6 mm molding compound thickness ranges. Curve 404 shows that material 2 consistently outperforms materials 1 and 3 to 5, or at least material 2 is not outperformed by any of materials 1 and 3 to 5. Therefore, material 2 is a good candidate for improving radiation efficiency. Curve 406 shows that material 3 is generally outperformed by one or more of materials 1, 2, 4, and 5 in most molding compound thickness ranges, and therefore material 3 is not a good candidate for inclusion in molding compound 304. Curve 408 shows that material 4 outperforms most materials in the 1.2 mm to 1.8 mm and 0.4 mm to 0.46 mm molding compound thickness ranges, but material 4 does not outperform material 2 at any thickness. Finally, curve 410 shows that material 5 is generally the worst performing of materials 1 to 5. Comparing the relative performance of materials 1 to 5, material 2 is significantly better than the remaining materials, and material 1 is also better than materials 3 to 5, and is comparable to material 2 in the molding compound thickness ranges of 0.2 mm to 0.3 mm and 0.5 mm to 0.6 mm.

[0035] based on Figure 4 Based on the results shown in FIG. 1 , when using material 2, the thickness of the molding compound 304 may be in the range of 0.13 mm to 0.25 mm or 0.4 mm to 0.53 mm to achieve the best performance. Figure 4 According to the results shown in , when material 3 is used, the thickness of the molding compound 304 may be in the range of 0 mm to 0.16 mm, 0.16 mm to 0.3 mm, or 0.425 mm to 0.56 mm to obtain the best performance.

[0036] Figure 5A 3 is a perspective view of a semiconductor package 300 according to various examples and a radiation gain pattern for effectively radiating a wireless signal. Specifically, Figure 5AThe radiation gain (radiation) pattern is shown in the Φ=0° plane 500 and the Φ=90° plane 502. As shown, the radiation pattern is directional, meaning that it extends primarily from the patch antenna 112 in a direction orthogonal to the patch antenna 112. The radiation pattern assumes that the molding compound 304 is Material 3 (Table 1), has a thickness of 140 microns, and an operating frequency of 300 GHz (although similar radiation patterns will result from other operating frequencies in the millimeter wave range). Figure 5B and 5C Provides Figure 5A An alternative cross-sectional view of the radiation pattern shown in .

[0037] Figure 6 Another depiction of the gain (radiation) pattern provided by semiconductor package 300 is provided. Figure 6 The illustration is a 3-D polar plot of the gain at 300 GHz, although similar radiation patterns will be produced by other operating frequencies in the millimeter wave frequency range. Figure 6 Assume that the molding compound 304 is material 3 (Table 1) and has a thickness of 140 microns. Figure 6 As shown, the peak gain is approximately 4.363 dB. Importantly, the peak gain level exists in the orthogonal direction relative to the patch antenna 112 ( Figure 5A ), for example, along a vertical axis extending from the patch antenna 112 in an orthogonal direction, as indicated by numeral 602, and a minimum gain level exists in a direction perpendicular to such vertical axis, as indicated by numeral 604.

[0038] Figure 7 7 is a graph 700 depicting gain and return loss (in dB) as a function of frequency (in GHz) of a signal radiated by a patch antenna semiconductor package 300 according to various examples. Graph 700 includes curves 702 (return loss with molding compound 304 present in semiconductor package 300), 704 (return loss without molding compound 304 present in semiconductor package 300), 706 (peak gain with molding compound 304 not present in semiconductor package 300), and 708 (peak gain with molding compound 304 present in semiconductor package 300). As indicated by curves 702 and 704, the presence of molding compound 304 in package 300 results in wider impedance bandwidth performance across the swept frequency range of operating frequencies from 270 GHz to 330 GHz. As indicated by curves 706 and 708 , across the swept frequency range of operating frequencies from 270 GHz to 330 GHz, the presence of molding compound 304 in package 300 consistently produces superior gain compared to the absence of molding compound 304 in package 300 .

[0039] Figure 8800 is a graph depicting radiation efficiency as a function of signal frequency for a range of relative dielectric constant values ​​of different molding compounds according to various examples. Graph 800 includes curves 802, 804, 806, 808, 810, 812, 814, 816, and 818 for relative dielectric constant values ​​of 1, 1.5, 2, 2.5, 3, 3.5, 3.55, 4, and 5, respectively. The molding compound loss tangent is kept constant at 0.013 to facilitate a fair comparison of the range of relative dielectric constant values. As shown, for the frequency sweep range of 270 GHz to 330 GHz, curve 814 (relative dielectric constant of 3.55) has the highest area under the curve (AUC), and therefore has the best overall performance among the various molding compound relative dielectric constants.

[0040] Fig. 9 900 is a graph of radiation efficiency as a function of signal frequency for a range of different molding compound loss tangent values ​​according to various examples. Graph 900 includes curves 902, 904, 906, 908, 910, 912, and 914 for loss tangent values ​​of 0.0095, 0.008, 0.0065, 0.005, 0.0035, 0.002, and 0.0005, respectively. The relative dielectric constant of the molding compound is kept constant at 3.55 to facilitate a fair comparison of the range of loss tangent values. As shown in the figure, for the frequency sweep range of 270 GHz to 330 GHz, the curve representing the lowest loss tangent (in this case, the curve 914 corresponding to the loss tangent of 0.0005) produces the maximum radiation efficiency. These experimental data are used to determine the molding compound relative dielectric constant and loss tangent value combination with the maximum radiation efficiency, as shown in Table 1.

[0041] Fig.101 is a cross-sectional view of a patch antenna semiconductor die 100 configured to effectively radiate wireless signals according to various examples. Die 100 includes a silicon substrate 1039 (also referred to herein as silicon 1039, although other types of semiconductors may be substituted for silicon), the silicon substrate having a device side including circuitry and a non-device side opposite the device side. The device side surface faces upward toward the rest of the structure of die 100. Die 100 includes a plurality of metal layers 1000 to 1008. Die 100 also includes component 104, which is the topmost metal layer. Metal layer 1000 is coupled to silicon 1039 (e.g., coupled to a ground node on the device side of silicon 1039) by means of vias 1009. Metal layers 1001 to 1008 are coupled to metal layers 1000 to 1007, respectively, by means of vias 1010 to 1017, respectively. 1036. The via 1037 couples the metal layer 1027 to the component 104 (e.g., the topmost metal layer of the BEOL) and / or the floor 108 and / or the wall 110. The metal layers 1000 to 1008, the vias 1009 to 1018, the component 102, and the floor 108 and the wall 110 of the cavity 106 form a grounded wall as described above. The die 100 also includes metal layers 1019 to 1027 and vias 1028 to 1037. The metal layers 1020 to 1027 are coupled to the metal layers 1019 to 1026, respectively, by means of vias 1029 to 1036. In an example, the via 1037 couples the metal layer 1027 to the component 104 (e.g., the topmost metal layer of the BEOL) and / or the floor 108 and / or the wall 110. Fig.10 The view thus depicts two ground walls. The die 100 is contained in Fig.10 Two additional ground walls that are not visible in the plan view of the die 100. In summary, these four ground walls form the ground structure described herein. The space between the ground walls is vertically aligned with the patch antenna 112. Therefore, during operation, the energy radiated by the patch antenna 112 propagates vertically, and the ground structure composed of the aforementioned ground walls prevents or at least reduces radiation in the horizontal / lateral direction. This imparts directionality to the energy radiation, so that more energy is radiated vertically and especially upward and away from the tube core 100, thereby increasing the radiation efficiency. Alternative configurations are covered and included within the scope of the present disclosure. Insulating material 1038 (e.g., polyimide) covers the various metal layers and through holes within the tube core 100, as shown.

[0042] exist Fig.10 , the metal layers in component 102 are depicted as having a combined thickness that is greater than the thickness of silicon 1039. However, in an example, the thickness of silicon 1039 may substantially exceed the combined thickness of the metal layers in component 102.

[0043] Fig.11 is a flow chart of a method 1100 for fabricating a patch antenna semiconductor package, such as package 300 , according to various examples. Figures 12A to 12J FIG. 1 is a process flow diagram of a method for manufacturing a semiconductor package of a patch antenna such as package 300 according to various examples. Fig.11 and 12A To 12J. The method 1100 begins by coupling a first conductive layer to a silicon substrate (1102). Fig. 12A Shown is silicon 1039 and vias 1028 and 1009 formed on the device side of silicon 1039. Vias 1028 and 1009, as well as the remaining vias and conductive / metal layers described herein, may be formed by any suitable technique, such as electroplating techniques using appropriate seed layers and / or other materials. Fig. 12B Insulating material 1038 is shown applied to silicon 1039 and vias 1028 and 1009 . Fig. 12C The formation of conductive layers 1019 and 1000 coupled to vias 1028 and 1009, respectively, is shown.

[0044] The method 1100 includes coupling a second conductive layer to a first conductive layer using a first via extending through an insulating layer between the first conductive layer and the second conductive layer, the second conductive layer being further from the silicon than the first conductive layer (1104). Fig.12D Vias 1029 and 1010 are shown formed in conductive layers 1019 and 1000, respectively. Fig.12E Insulating material 1038 is shown applied to vias 1029 and 1010 and conductive layers 1019 and 1000 . Fig.12F The formation of conductive layers 1020 and 1001 coupled to vias 1029 and 1010, respectively, is shown.

[0045] The method 1100 also includes coupling the third conductive layer to the second conductive layer via a second via extending through the insulating material (1106). The method 1100 further includes forming a cavity in a surface of the third conductive layer facing away from the silicon, the cavity having a floor and a plurality of walls (1108). The method 1100 includes forming a metal layer in the cavity, the metal layer included in at least one of the floor and the walls of the cavity (e.g., the floor and at least one wall are formed of the metal layer), the metal layer coupled to a ground connection of the silicon via the first conductive layer and the second conductive layer and the first via and the second via (1110). Figure 12G The formation of vias 1030 and 1011 and the application of additional insulating material 1038 are shown. Fig.12HThe formation of the third conductive layer 104 and the cavity 106 in the top surface of the third conductive layer 104 is shown. In an example, the cavity is formed in the third conductive layer 104 by suitable photolithography and electroplating techniques. In some examples, a metal layer is formed on the floor 108 and one or more walls 110 of the cavity 106, and the metal layer on the floor 108 contacts the via 1011 and the via 1030. In some examples, the floor 108 and the walls 110 are part of the third conductive layer 104, and the vias 1030, 1011 are coupled to the third conductive layer 104, the floor 108, and / or the walls 110.

[0046] The method 1100 includes positioning a patch antenna in a cavity (1112). Fig.12I Patch antenna 112 is shown positioned in cavity 106. In an example, patch antenna 112 is part of a metal layer (not explicitly shown) in component 102. In addition to coupling to circuitry on silicon 1039, feed line 116 may also be coupled to circuitry formed in a metal layer of component 102, circuitry formed on backplane 108, or a combination thereof. Method 1100 includes coupling a semiconductor die to a substrate (e.g., a printed circuit board), wire bonding bond pads on the die to conductive terminals, and covering the patch antenna and various conductive and insulating layers, the cavity, the conductive terminals, and the substrate with a molding compound (1114). Fig.12J An example package 300 is shown including a substrate 302 and a molding compound 304 covering the various components of the package 300. Fig.12J The package 300 has the Fig.10 The die 100 in FIG. 1 may have different numbers of conductive layers and vias, but any suitable number of conductive layers and / or vias may be useful.

[0047] In this description, the term "coupled" may encompass a functional relationship that enables connection, communication, or signal path consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in the first instance, device A is coupled to device B through a direct connection; or (b) in the second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0048] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configured (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0049] Circuits or devices described herein as including certain components may alternatively be coupled to those components to form the described circuit systems or devices. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0050] The use of the term "ground" and variations thereof in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise stated, "approximately," "substantially," or "substantially" preceding a parameter means within a + / -10% range of the parameter. Modifications may be made in the described examples, and other examples may be made within the scope of the claims.

Claims

1. A semiconductor package, comprising: a semiconductor substrate including a device side having circuitry formed therein; a conductive layer positioned over the semiconductor substrate; a patch antenna coupled to the conductive layer and the device side of the semiconductor substrate; and A molding compound covers the patch antenna, the molding compound having a relative dielectric constant in a range of 3.4 to 3.5 and a loss tangent in a range of 0.0025 to 0.

013. 2 . The package of claim 1 , wherein the molding compound has a relative dielectric constant of approximately 3.4 and a loss tangent of approximately 0.0025. 3 . The package of claim 2 , wherein the molding compound has a vertical thickness in the range of 0.13 mm to 0.25 mm. The package of claim 2 , wherein the molding compound has a vertical thickness in the range of 0.4 mm to 0.53 mm. 5 . The package of claim 1 , wherein the molding compound has a relative dielectric constant of approximately 3.5 and a loss tangent of approximately 0.

013. The package of claim 5 , wherein the molding compound has a vertical thickness in the range of 0 mm to 0.16 mm. 7 . The package of claim 5 , wherein the molding compound has a vertical thickness in the range of 0.16 mm to 0.3 mm.

8. The package of claim 5, wherein the molding compound has a vertical thickness in a range of 0.425 mm to 0.56 mm. 9 . The package of claim 1 , wherein the molding compound has a vertical thickness of one quarter of a wavelength of a signal that the patch antenna is configured to radiate.

10. A semiconductor package, comprising: a semiconductor substrate including a device side having circuitry formed therein; a plurality of conductive layers positioned above the semiconductor substrate, each of the plurality of conductive layers coupled to another of the plurality of conductive layers through a different via, the plurality of conductive layers including a top conductive layer positioned farthest from the semiconductor substrate; a ground member located in the cavity of the top conductive layer, the ground member being coupled to a ground connection in the circuitry by means of the via; a patch antenna located in the cavity; and A molding compound covering the patch antenna, the molding compound having a relative dielectric constant in the range of 3.4 to 3.5 and a thickness from the patch antenna to a top surface of the molding compound, the thickness being approximately one quarter of a wavelength of a wireless signal to be transmitted by the patch antenna. The package of claim 10 , wherein the grounding member is contained in a floor of the cavity.

12. The package of claim 10, wherein the ground member covers a plurality of walls of the cavity.

13. The package of claim 10, wherein the molding compound has a relative dielectric constant of approximately 3.

4.

14. The package of claim 10, wherein the molding compound has a loss tangent of approximately 0.0025.

15. A semiconductor package, comprising: a semiconductor substrate including a device side having circuitry formed therein; a plurality of conductive layers positioned above the semiconductor substrate, each of the plurality of conductive layers coupled to another of the plurality of conductive layers through a different via, the plurality of conductive layers including a top conductive layer positioned farthest from the semiconductor substrate; a ground member located in the cavity of the top conductive layer, the ground member coupled to a ground connection in the circuit system by means of the via, the ground member being contained in a floor of the cavity and a wall of the cavity; a patch antenna located in the cavity; and A molding compound covers the patch antenna, the molding compound having a relative dielectric constant in a range of 3.4 to 3.5 and a loss tangent in a range of 0.0025 to 0.

013. The package of claim 15 , wherein the grounding member covers all walls of the cavity.

17. The package of claim 16, wherein the distance between the edge of the patch antenna and the nearest wall of the cavity is between 20 and 30 microns.

18. The package of claim 15, wherein the molding compound has a relative dielectric constant of approximately 3.4 and a loss tangent of approximately 0.0025.

19. The package of claim 18, wherein the molding compound has a vertical thickness in the range of 0.13 mm to 0.25 mm.

20. The package of claim 18, wherein the molding compound has a relative dielectric constant of approximately 3.5 and a loss tangent of approximately 0.

013.

21. A method for manufacturing a semiconductor package, comprising: coupling the first conductive layer to the semiconductor substrate; coupling a second conductive layer to the first conductive layer using a via, the via extending through an insulating layer between the first conductive layer and the second conductive layer, the second conductive layer being further from the semiconductor substrate than the first conductive layer; forming a cavity in a surface of the second conductive layer facing away from the semiconductor substrate, the cavity having a metal floor and a plurality of metal walls, the floor and the plurality of walls being coupled to a ground connection of the semiconductor substrate through the through hole; positioning a patch antenna in the cavity; and The patch antenna is covered with a molding compound.

22. The method of claim 21, wherein the molding compound has a relative dielectric constant in the range of 3.4 to 3.

5.

23. The method of claim 21, wherein the molding compound has a loss tangent of approximately 0.0025.

24. The method of claim 21, wherein the molding compound has a loss tangent of approximately 0.013.

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