Input / output interface, signal amplifier and integrated circuit

Abstract

An input / output interface (100) includes an IO terminal, a gate device (110), and an electrostatic discharge prevention device. The gate device (110) is configured to control reading of data from the IO terminal. The gate device (110) comprises: a first switching device (112); an input terminal of the first switching device (112) is connected to an IO terminal. The anti-electrostatic discharge device is configured to increase a breakdown voltage at the first switching device (112).

Description

Input and output interfaces, signal amplifiers and integrated circuits Technical Field

[0001] The present disclosure generally relates to an input / output (IO) interface, and in particular to an IO interface with improved anti-electrostatic discharge performance. Background Art

[0002] The input and output interfaces of a device can read and write data, but they also face the problem of electrostatic discharge from the input and output interfaces. For example, as MOS technology continues to evolve, the gate oxide layer voltage of MOS devices continues to decrease, and the requirements for electrostatic discharge (ESD) protection design are becoming increasingly stringent. In some cases, such as for fin-type MOS devices, the gate oxide layer of the chip's MOS device has dropped to 0.8V, which poses great difficulties for electrostatic discharge at the device's interface. Traditional electrostatic discharge measures increase the risk of damage to the device's internal components.

[0003] Summary of the Invention

[0004] The present disclosure provides an input-output interface, a signal amplifier, and an integrated circuit, aiming to solve or alleviate one or more of the above-mentioned problems.

[0005] According to a first aspect of the present disclosure, an input / output (IO) interface is provided. The IO interface includes: an IO terminal; and a gate device configured to control the reading of data from the IO terminal, and includes: a first switching device, the input end of which is connected to the IO terminal; and an anti-static discharge device configured to increase the breakdown voltage at the first switching device. According to an embodiment of the present disclosure, the IO interface can increase the breakdown voltage at the first switching device by providing the anti-static discharge device, thereby enhancing the first switching device's ability to withstand the electrostatic discharge breakdown voltage of the IO terminal, thereby significantly improving the electrostatic discharge protection capability of the gate device.

[0006] In some embodiments, the input end of the first switching device may be directly connected to the IO terminal. Thus, since no resistive device is provided between the input end of the first switching device and the IO terminal, the noise performance of the IO interface is significantly improved.

[0007] In some embodiments, the anti-ESD device may include a second switching device, the output of which is connected to the gate of the first switching device. Thus, the provision of the second switching device enhances the ESD protection capability of the gate device. Furthermore, because the anti-ESD device is implemented using the second switching device, the on / off state of the first switching device can be conveniently controlled.

[0008] In some embodiments, the gate device may further include an inverter connected to the input terminal of the second switch device, thereby conveniently and flexibly controlling the on and off of the first switch device as needed through the inverter.

[0009] In some embodiments, the gate of the second switching device and the input terminal of the inverter can be controlled synchronously, thereby conveniently realizing the switching state of the first switching device through synchronous control.

[0010] In some embodiments, the first switching device and the second switching device may include MOS FETs.

[0011] In some embodiments, the first switching device may include a MOS transistor, and the input end may include a source or a drain of the MOS transistor.

[0012] In some embodiments, the second switching device may include a MOS transistor, and the output end may include a source or a drain of the MOS transistor.

[0013] In some embodiments, the IO interface may further include: a positive terminal; a ground terminal; and a discharge bridge connected between the positive terminal and the ground terminal and having a smaller current resistance than that of the first switching device, so as to allow static electricity from the IO terminal to be discharged via the discharge bridge. Thus, when a large amount of static electricity accumulates at the IO terminal, current is discharged through the discharge bridge.

[0014] In some embodiments, the discharge bridge may include a first unidirectional conductive element connected between the IO terminal and the positive terminal and a second unidirectional conductive element connected between the IO terminal and the ground terminal, wherein the first unidirectional conductive element is configured to only allow current to flow from the IO terminal to the positive terminal, and the second unidirectional conductive element is configured to only allow current to flow from the ground terminal to the IO terminal. Thus, the discharge of electrostatic charge at the IO terminal can be achieved using a simplified discharge bridge structure.

[0015] In some embodiments, the first unidirectional conducting element and the second unidirectional conducting element may include diodes or MOS transistors.

[0016] In some embodiments, the IO interface may further include a clamping circuit disposed between the positive terminal and the ground terminal, so that discharge from the IO terminal can be absorbed by the clamping circuit.

[0017] According to a second aspect of the present disclosure, a signal amplifier is provided. The signal amplifier includes the IO interface according to the first aspect. The amplifier according to an embodiment of the present disclosure has good anti-noise performance.

[0018] According to a third aspect of the present disclosure, an integrated circuit is provided, comprising the IO interface according to the first aspect.

[0019] It should be understood that the contents described in the Summary of the Invention are not intended to define the key or important features of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The above and other objects, features and advantages of the embodiments of the present disclosure will become readily understood by reading the following detailed description with reference to the accompanying drawings, in which several embodiments of the present disclosure are shown in an illustrative and non-limiting manner.

[0021] FIG1 shows a circuit diagram of an exemplary IO interface according to a first embodiment of the present disclosure.

[0022] FIG2 shows a circuit diagram of an example IO interface according to a second embodiment of the present disclosure.

[0023] FIG3 is a schematic diagram showing an increase in withstand voltage of a switching device of an exemplary IO interface according to a third embodiment of the present disclosure.

[0024] FIG4 shows a circuit diagram of an exemplary IO interface according to a fourth embodiment of the present disclosure.

[0025] Throughout the drawings, the same or similar reference numerals are used to designate the same or similar components. DETAILED DESCRIPTION

[0026] The principles and spirit of the present disclosure will be described below with reference to several exemplary embodiments shown in the accompanying drawings. It should be understood that the description of these specific embodiments is only intended to enable those skilled in the art to better understand and implement the present disclosure, and is not intended to limit the scope of the present disclosure in any way. In the following description and claims, unless otherwise defined, all technical and scientific terms used herein have the same meanings as commonly understood by those of ordinary skill in the art.

[0027] As used herein, the term "including" and similar terms should be understood as open inclusion, i.e., "including but not limited to." The term "based on" should be understood as "based at least in part on." The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment." The terms "first," "second," etc. may refer to different or the same objects and are only used to distinguish the objects referred to, and do not imply a specific spatial order, temporal order, order of importance, etc. of the objects referred to.

[0028] In the application scenario of integrated circuits, the integrated circuits usually include an IO interface, through which signals from external devices can be received to further process the signals accordingly and realize various functions. As an example, in some radio frequency high-speed application scenarios (such as 6GHz), the integrated circuit may include a signal amplifier. The communication signal received by the antenna can be input through the IO interface of the signal amplifier and input into the signal amplifier. The signal amplifier can read the communication signal, amplify the communication signal, and then output the amplified signal. The signal amplifier may include a gate device, and the gate device may include a MOS tube, which performs signal reading by controlling the MOS tube. It is worth noting that although the embodiment of the present disclosure uses a signal amplifier as an example to illustrate the application scenario of the IO interface; this is merely exemplary, and the IO interface of the embodiment of the present disclosure can be applied to any other integrated circuit, chip or semiconductor device.

[0029] As previously mentioned, as MOS transistor processes continue to evolve, the gate oxide layer of MOS transistors continues to decrease. For example, for Fin-type MOS transistors, the gate oxide layer of MOS transistors has been reduced to 0.8V. On the other hand, the IO terminal pads of the IO interface accumulate electrostatic charge during use, and the discharge of this accumulated electrostatic charge increases the risk of damage to the MOS transistor. To address this issue, according to an embodiment of the present disclosure, an IO interface is provided that provides electrostatic discharge protection between the gate device and the IO terminal pad, preventing static electricity from the IO terminal pad from discharging through the gate device and damaging the gate device.

[0030] FIG1 shows a circuit diagram of an example IO interface 100 according to a first embodiment of the present disclosure. As shown in FIG1 , IO interface 100 includes an IO terminal, a positive terminal VDD, and a ground terminal GND. The positive terminal VDD and the ground terminal GND can be connected to the positive and negative poles of a DC voltage and used to power IO interface 100. The IO terminal can be adapted to receive external signals. IO interface 100 also includes a gate device 110. Gate device 110 can be configured to control the reading of data from the IO terminal. In some embodiments, gate device 110 may include a first switching device 112 that can receive control instructions to selectively read signals from the IO terminal. In the illustrated embodiment, first switching device 112 is shown as a PMOS transistor, but this is merely exemplary; first switching device 112 may be any other type of MOS transistor. In some embodiments, gate device 110 also includes an inverter 114 connected to the input of the first switching device. Inverter 114 allows for flexible and convenient control of the on and off states of first switching device 112 as needed. In some embodiments, the input terminal of the first switching device 112 may include a source or a drain of a MOS transistor.

[0031] The gate device 110 can implement input and output control for the IO terminal through the first switch device 112 and the inverter 114. For example, in some cases, the input end of the inverter 114 can be connected to the controller of the IO interface 100 and can receive instructions from the controller, and the output end of the inverter 114 can be connected to the gate of the first switch device 112. In turn, the first switch device 112 can be controlled to be turned on and off by the instructions of the inverter 114.

[0032] As shown in FIG1 , the IO interface 100 may further include a discharge bridge 120. Discharge bridge 120 is connected between the positive terminal VDD and the ground terminal GND and may include two discharge branches 122 and 124, and a discharge resistor R connected in series between the two discharge branches. As shown in FIG1 , each discharge branch 122 may include a first diode 125 a connected between the IO terminal and the positive terminal VDD, and a second diode 125 b connected between the IO terminal and the ground terminal. The first diode 125 a is configured to allow current to flow only from the IO terminal to the positive terminal, and the second diode 125 b is configured to allow current to flow only from the ground terminal to the IO terminal.

[0033] The ESD protection principle of the IO interface 100 shown in Figure 1 is as follows. When a large amount of electrostatic charge accumulates on an IO terminal, it will be discharged through the circuit of the IO interface 100 when the electrostatic charge reaches a certain level. Because current will follow the path of least resistance, when the IO terminal discharges through the circuit of the IO interface 100, the current will be discharged through the first-stage discharge branch 122 and the second-stage discharge branch 124 of the discharge bridge 120.

[0034] A resistor R is connected in series between the first-stage discharge branch 122 and the first-stage discharge branch 124. Resistor R divides the current voltage, and the current after voltage division by R is then discharged through the second-stage discharge branch 124. The first-stage discharge branch 122 and the first-stage discharge branch 124 ensure that the electrostatic discharge circuit bypasses the first switching device 112 and flows into the VDD branch, thereby preventing the current from flowing into the first switching device 112. Furthermore, the provision of resistor R reduces the voltage applied to the first switching device 112 of the gate device 110, thereby effectively preventing electrostatic discharge at the IO terminal from damaging the first switching device 112.

[0035] In some embodiments, as shown in FIG1 , the IO interface 100 may further include a clamping circuit 140 disposed between the positive terminal VDD and the ground terminal GND. The clamping circuit can be configured to absorb electrostatic discharge from the IO terminal to effectively protect the components of the IO interface. The clamping circuit 140 is a well-known clamping circuit in the art, and the form of the clamping circuit 140 is not limited, as long as it can achieve potential clamping.

[0036] Although the resistor R reduces the voltage on the first switch device 112 of the gate device 110, it degrades the performance of the system including the IO interface, particularly because the presence of the resistor R increases system noise and power consumption.

[0037] FIG2 shows a circuit diagram of an example IO interface 200 according to a second embodiment of the present disclosure. As shown in FIG2 , IO interface 200 includes an IO terminal, a positive terminal VDD, and a ground terminal GND. The positive terminal VDD and the ground terminal GND can be connected to the positive and negative poles of a DC voltage and used to power IO interface 200. The IO terminal can be adapted to receive external signals. IO interface 200 can also include a gate device 210. The gate device 210 can be configured to control the reading of data from the IO terminal.

[0038] In some embodiments, the gate device 210 may include a first switch device 212. The first switch device 212 may receive a control instruction to selectively read a signal from an IO terminal. In the illustrated embodiment, the first switch device 212 is exemplarily shown as a PMOS transistor. This is merely exemplary, and the first switch device 212 may be any other type of MOS transistor.

[0039] As shown in FIG2 , the input end of the first switching device 212 is directly connected to the IO terminal. Unlike the embodiment shown in FIG1 , the input end of the first switching device 212 is directly connected to the IO terminal without an additional resistor, thereby avoiding system noise caused by the presence of the R resistor. This significantly improves the performance of RF signal processing (e.g., 6G communication signals).

[0040] As shown in FIG2 , gate device 210 further includes an inverter 214. Inverter 214 allows for flexible and convenient control of the on / off state of first switching device 212 as needed. As shown in FIG2 , gate device 210 further includes an anti-ESD device. The anti-ESD device can be configured to increase the breakdown voltage at first switching device 212. The anti-ESD device can be connected in series with the branch where first switching device 212 and inverter 214 are located. The anti-ESD device can enhance the first switching device 212's ability to withstand the electrostatic discharge breakdown voltage of the IO terminal, thereby significantly improving the electrostatic discharge protection capability of gate device 210.

[0041] In some embodiments, the anti-electrostatic discharge device may include a second switching device 216. The output of the second switching device 216 is connected to the gate of the first switching device 212. The input of the second switching device 216 may be connected to the output of the inverter 214. Thus, the provision of the second switching device 216 can enhance the electrostatic discharge protection capability of the gate device 210. Furthermore, because the anti-electrostatic discharge device is implemented using the second switching device 216, the switching state of the first switching device 212 can be conveniently controlled by synchronously controlling the second switching device 216 and the inverter 214.

[0042] In some embodiments, the gate device 210 can implement input and output control for the IO terminal through the first switch device 212, the second switch device 216, and the inverter 214. For example, in some cases, the input of the inverter 214 can be connected to the controller of the IO interface 200 and can receive instructions from the controller, the output of the inverter 214 can be connected to the input of the second switch device 216, and the output of the second switch device 216 can be connected to the gate of the first switch device 212. The gate of the second switch device 216 can also receive instructions from the controller of the IO interface 200 to implement coordinated control of the inverter 214 and the second switch device 216. As a result, the inverter 214 and the second switch device 216 are controlled in a coordinated (particularly synchronous) manner, ensuring that the first switch device 212 is turned on and off in response to the instructions of the inverter 214 and the second switch device 216.

[0043] It is worth noting that, although the second switching device 216 is shown as the same type of switching device as the first switching device 212 (i.e., a PMOS transistor) in the embodiment of FIG2 , this is merely exemplary. The second switching device 216 may be implemented as any other suitable switching device, as long as it can achieve coordinated control of the inverter 214 and the second switching device 216. The output end of the first switching device 212 may include the source or drain of a MOS transistor. The output end of the second switching device 216 may include the source or drain of a MOS transistor.

[0044] As shown in Figure 2, the IO interface 200 may also include a discharge bridge 220. The discharge bridge 220 is connected between the positive terminal VDD and the ground terminal GND, and may include a primary discharge branch. As shown in Figure 2, the discharge branch may include a first diode 225a connected between the IO terminal and the positive terminal VDD, and a second diode 225b connected between the IO terminal and the ground terminal. The first diode 225a is configured to allow current to flow only from the IO terminal to the positive terminal, and the second diode 225b is configured to allow current to flow only from the ground terminal to the IO terminal. Compared to the embodiment shown in Figure 1, the second-stage discharge branch is reduced, further improving circuit noise performance. In addition, the number of parts is reduced, further reducing circuit cost.

[0045] The ESD protection principle of IO interface 200 shown in Figure 2 is as follows. When a large amount of electrostatic charge accumulates on an IO terminal, it will be discharged through the circuit of IO interface 200 when the electrostatic charge reaches a certain level. Because current follows the path of least resistance, when the IO terminal discharges through the circuit of IO interface 200, the current is discharged through the discharge branch of discharge bridge 220 rather than through gate device 410, thereby preventing damage to the gate device.

[0046] At this time, the IO terminal is directly connected to the input of the first switching device 212 and is exposed to the electrostatic load at the IO terminal. Because the gate device 210 can increase the breakdown voltage of the first switching device 212 by the additional second switching device 216, the first switching device 212 will not be damaged by the electrostatic discharge breakdown of the IO terminal.

[0047] In some embodiments, as shown in FIG2 , IO interface 200 may further include a clamping circuit 240 disposed between the positive terminal VDD and the ground terminal GND. Clamping circuit 240 may be configured to absorb electrostatic discharge from the IO terminal, effectively protecting components of the IO interface. Clamping circuit 240 is a type of clamping circuit well known in the art, and the form of clamping circuit 240 is not limited, as long as it can achieve potential clamping.

[0048] It is worth noting that, although in the illustrated embodiment, only one second switching device 216 is shown on the control branch of the first switching device 212 of the gate device 210, this is merely exemplary, and multiple second switching devices 216 may be provided as needed to further enhance the first switching device 212's ability to withstand electrostatic discharge voltage.

[0049] Figure 3 shows a schematic diagram of the withstand voltage increase of the switching device of the example IO 300 according to the third embodiment of the present disclosure. The cross-sectional view shown in Figure 3 shows a schematic diagram of the voltage increase on the branch from the IO terminal to the positive terminal VDD.

[0050] 3 , the gate device 310 includes a first switch device 312, a second switch device 316, and an inverter 314 arranged in series from the IO terminal to the positive terminal VDD. In the illustrated embodiment, the first switch device 312 and the second switch device 316 are shown as NMOS transistors, which is merely exemplary.

[0051] As shown in FIG3 , the electrostatic voltage accumulated at the IO terminal must sequentially break down the first NP node of the first switching device 312 (i.e., the left NP node of the first switching device 312 in the figure), the first NP node of the second switching device 316 (i.e., the left NP node of the second switching device 316 in the figure), the second NP node of the second switching device 316 (i.e., the right NP node of the second switching device 316 in the figure), the first PN node of the inverter 314 (i.e., the right NP node of the inverter 314 in the figure), and the first PN node of the inverter 314 (i.e., the right NP node of the inverter 314 in the figure) before reaching the power supply terminal VDD. Providing the second switching device 316 significantly enhances the electrostatic discharge voltage tolerance of the gate device 310 (particularly the first switching device 312).

[0052] FIG4 shows a circuit diagram of an example IO interface 400 according to a fourth embodiment of the present disclosure. As shown in FIG4 , IO interface 400 includes an IO terminal, a positive terminal VDD, and a ground terminal GND. The positive terminal VDD and the ground terminal GND can be connected to the positive and negative poles of a DC voltage and used to power IO interface 400. The IO terminal can be adapted to receive external signals. IO interface 400 can also include a gate device 410. Gate device 410 can be configured to control the reading of data from the IO terminal.

[0053] In some embodiments, gate device 410 may include a first switching device 412. First switching device 412 may receive a control instruction to selectively read a signal from an IO terminal. An input terminal of first switching device 412 is directly connected to the IO terminal. Gate device 410 may also include an inverter 414. Inverter 414 may be used to conveniently and flexibly control the on and off states of first switching device 412 as needed.

[0054] As shown in FIG4 , gate device 410 may further include an anti-electrostatic discharge (ESD) device. The anti-electrostatic discharge (ESD) device may include a second switching device 416. The output of second switching device 416 is connected to the gate of first switching device 412. The input of second switching device 416 may be connected to the output of inverter 414. Thus, the provision of second switching device 416 enhances the ESD protection capability of gate device 410. Furthermore, since the ESD device is implemented via second switching device 416, the switching state of first switching device 412 can be conveniently controlled by synchronously controlling second switching device 416 and inverter 414.

[0055] In some embodiments, gate device 410 can implement input and output control for an IO terminal through a first switch device 412, a second switch device 416, and an inverter 414. For example, in some cases, the input of inverter 414 can be connected to a controller of IO interface 400 and can receive instructions from the controller, the output of inverter 414 can be connected to the input of second switch device 416, and the output of second switch device 416 can be connected to the gate of first switch device 412. The gate of second switch device 416 can also receive instructions from the controller of IO interface 400 to implement coordinated control of inverter 414 and second switch device 416. Thus, inverter 414 and second switch device 416 are controlled in a coordinated (particularly synchronous) manner, ensuring that first switch device 412 is turned on and off in response to the instructions of inverter 414 and second switch device 416.

[0056] As shown in FIG4 , the IO interface 400 may also include a discharge bridge 420. The discharge bridge 420 is connected between the positive terminal VDD and the ground terminal GND, and may include a primary discharge branch. As shown in FIG4 , the discharge branch 412 may include a first MOS transistor 425a connected between the IO terminal and the positive terminal VDD, and a second MOS transistor 425b connected between the IO terminal and the ground terminal. The first MOS transistor 425a is configured to allow current to flow only from the IO terminal to the positive terminal, and the second MOS transistor 425b is configured to allow current to flow only from the ground terminal to the IO terminal. Compared to the embodiment shown in FIG1 , the second-stage discharge branch is eliminated, further improving circuit noise performance. Furthermore, the number of components is reduced, further reducing circuit cost. It is worth noting that in the illustrated embodiment, the switching device of the discharge branch is shown as a MOS transistor. This is merely exemplary. In the embodiments of the present disclosure, any other suitable unidirectional switching device may be used to form an electrostatic discharge path.

[0057] The electrostatic discharge protection principle of the IO interface 400 shown in Figure 4 is as follows. When a large amount of electrostatic charge accumulates at the IO terminal, when the electrostatic charge accumulates to a certain level, it will be discharged through the circuit of the IO interface 400. Since the current will follow the path of least resistance to discharge, when the IO terminal is discharged through the circuit of the IO interface 400, the current will be discharged through the discharge branch of the discharge bridge 220, and will not pass through the gate device 410, thereby avoiding damage to the gate device. In particular, the IO terminal is directly connected to the input end of the first switching device 412 and is exposed to the electrostatic load at the IO terminal. Because the gate device 410 can increase the breakdown voltage at the first switching device 412 by the additional second switching device 416, the first switching device 412 will not be damaged by the electrostatic discharge breakdown of the IO terminal.

[0058] As shown in FIG4 , IO interface 400 may further include a clamping circuit 240 disposed between the positive terminal VDD and the ground terminal GND. Clamping circuit 240 may be configured to absorb electrostatic discharge from the IO terminal, effectively protecting the components of the IO interface. Clamping circuit 240 is a type of clamping circuit well known in the art, and the form of clamping circuit 240 is not limited, as long as it can achieve potential clamping.

[0059] According to an embodiment of the present disclosure, a signal amplifier is also provided, comprising an IO interface according to any one of the above aspects. Due to the provision of an anti-electrostatic discharge device (especially a second switching device), not only is the electrostatic discharge of the IO terminal of the IO interface effectively prevented from damaging the functional components of the signal amplifier; but the circuit noise of the signal amplifier can also be significantly enhanced, thereby improving the noise performance of the amplifier. It is worth noting that although the application scenario of the IO interface according to the embodiment of the present disclosure is illustrated by taking a signal amplifier as an example, the IO of this application can be applied to other integrated circuits or chips.

[0060] According to an embodiment of the present disclosure, an integrated circuit is further provided, comprising the IO interface according to any one of the above aspects. The integrated circuit according to an embodiment of the present disclosure can effectively prevent electrostatic discharge of IO terminals of the IO interface from damaging functional devices of the integrated circuit.

[0061] In addition, although operations are depicted in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in a sequential order, or that all illustrated operations be performed to obtain the desired result. In some cases, multitasking or parallel processing can be beneficial. Similarly, although the above discussion contains certain specific implementation details, this should not be interpreted as limiting the scope of any invention or claim, but rather as a description of a specific embodiment that can be directed to a specific invention. Certain features described in this specification in the context of separate embodiments may also be integrated and implemented in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately in multiple embodiments or in any suitable subcombination.

[0062] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. An input / output (IO) interface, characterized in that: include: IO terminals; and A gate device is configured to control reading of data from the IO terminal and includes: a first switching device, an input terminal of the first switching device being connected to the IO terminal; and The anti-electrostatic discharge device is configured to increase the breakdown voltage of the first switching device.

2. The IO interface according to claim 1, wherein: An input terminal of the first switching device is directly connected to the IO terminal.

3. The IO interface according to claim 1, wherein: The anti-static discharge device includes a second switching device, wherein an output end of the second switching device is connected to a gate of the first switching device.

4. The IO interface according to claim 3, characterized in that: The gate device further includes an inverter connected to an input terminal of the second switching device.

5. The IO interface according to claim 4, characterized in that: The gate of the second switching device is synchronously controlled with the input terminal of the inverter.

6. The IO interface according to any one of claims 3 to 5, characterized in that: The first switching device and the second switching device include MOS FETs.

7. The IO interface according to any one of claims 2 to 5, characterized in that: The first switching device includes a MOS transistor, and the input end includes a source or a drain of the MOS transistor.

8. The IO interface according to any one of claims 3 to 5, characterized in that: The second switching device includes a MOS transistor, and the output end includes a source or a drain of the MOS transistor.

9. The IO interface according to any one of claims 1 to 4, characterized in that: Also includes positive extreme; Ground terminal; as well as A discharge bridge is connected between the positive terminal and the ground terminal and includes a current resistance smaller than that of the first switching device to allow static electricity from the IO terminal to be discharged via the discharge bridge.

10. The IO interface according to claim 9, characterized in that: The discharge bridge includes a first unidirectional conductive element connected between the IO terminal and the positive terminal and a second unidirectional conductive element connected between the IO terminal and the ground terminal, wherein the first unidirectional conductive element is configured to only allow current to flow from the IO terminal to the positive terminal, and the second unidirectional conductive element is configured to only allow current to flow from the ground terminal to the IO terminal.

11. The IO interface according to claim 10, characterized in that: The first unidirectional conducting element and the second unidirectional conducting element include diodes or MOS transistors.

12. The IO interface according to claim 9, wherein: Also included is a clamping circuit disposed between the positive terminal and the ground terminal.

13. A signal amplifier, characterized in that: The method comprises the IO interface according to any one of claims 1 to 12.

14. An integrated circuit, characterized in that: The method comprises the IO interface according to any one of claims 1 to 12.

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