Multi-level converter system

Abstract

The invention relates to a multi-level converter system comprising a plurality of energy storage modules and transistors wherein each energy storage module can be connected in parallel with a respective adjacent energy storage module, can be connected in series with a respective adjacent energy storage module, and / or can be bridged, each energy storage module is provided with at least one energy storage unit, at least two adjacent NPN transistors share an N-type region, and / or at least two adjacent PNP transistors share a P-type region.

Description

Technical Field

[0001] The present invention relates to a multilevel converter system, which comprises a plurality of energy storage modules and transistors, wherein each energy storage module can be connected in parallel with a corresponding adjacent energy storage module, can be connected in series with a corresponding adjacent energy storage module, and / or can be bridged, and each energy storage module has at least one energy storage unit. Background Art

[0002] Previous energy storage devices were usually loaded with a DC voltage (DC). This is due to the structure of conventional converter systems, which attempt to keep AC voltage components (i.e., harmonic oscillations) away from the energy storage device.

[0003] Since many energy storage devices must be connected in series or parallel in this case, a battery management system (BMS) is required. For example, a DC link capacitor can be connected downstream of the energy storage device. This serves to further smooth the three-phase current of the converter and keep high-frequency oscillations away from the energy storage device and intercept switching overshoots, because the inductance of the energy storage device will continue to drive the current. The purpose of this procedure is to load the energy storage device with DC, because it is assumed that in this case it will help the resistance of the battery cell and reduce losses.

[0004] For example, in a conventional electric vehicle, a converter can be provided on the DC bus, which transfers energy to the electric motor and during braking energy recovery (regeneration) transfers energy again to the battery. For example, a charging device that can be operated with AC voltage (AC) or DC voltage (DC) can also be connected to this bus.

[0005] These converters are usually in the form of two-point converters, for example in the case of a three-phase design in the form of a B6 bridge, or, in particular in the field of solar plants, in the form of a three-point converter.

[0006] As an alternative to bridge circuits as converters, so-called multilevel converter systems are known.

[0007] Batteries (e.g. rechargeable batteries) can be used, for example, as energy storage devices or energy sources. The energy storage devices are not hard-wired to one another, but are combined together as individual submodules. This structure is required for each phase. The energy storage devices are thus divided between the phases and can, for example, be permanently connected in series or in parallel.

[0008] For example, lithium-ion battery cells are often used in electric vehicles.

[0009] Most current transistors are designed as NPN semiconductors. Thus, a region is negatively doped, then positively doped, and then negatively doped again. Such semiconductors with their three connections (drain, gate and source) are produced in a factory.

[0010] First, a silicon wafer is used, which is then turned into many individual semiconductors using different process steps. These semiconductors are then tested for their functionality and cut into individual discrete components. Each semiconductor - unless it is used directly as a so-called "bare die" - is then given a housing for contact with the outside.

[0011] The procedure is particularly advantageous for current semiconductors, such as silicon MOSFETs, ie silicon metal oxide semiconductor field effect transistors, because in power MOSFETs used for multi-level applications the gate is usually planar.

[0012] Due to the better switching and on-state behavior, power MOSFETs are often constructed as so-called "superjunction MOSFETs".

[0013] However, the market for power semiconductors has been disrupted for years by so-called “wide bandgap devices” (WBG).

[0014] Two of them are particularly noteworthy, namely silicon carbide (SiC) and gallium nitride (GaN).

[0015] According to current situation, in the lower voltage range, for example below 650 V, GaN is expected to dominate. This is because GaN is more cost-effective and more powerful than silicon components. However, currently these new switches are not constructed as planar components, but as lateral components.

[0016] Conventional multilevel converter systems are still quite expensive. This is due, for example, to the relatively large number of transistors. The transistors also require a relatively large amount of space, and therefore the chips used are relatively large, which has a negative impact on production costs. Summary of the invention

[0017] It is therefore an object of the present invention to provide a multilevel converter system, a method for producing a multilevel converter system, and a wafer for producing a multilevel converter system, wherein the production costs of the multilevel converter system are reduced.

[0018] This object is achieved by the subject matter of the independent claims and by a method.

[0019] According to the invention, the preferably modular multilevel converter system comprises a plurality of energy storage modules and transistors.

[0020] A multi-level converter system describes a type of arrangement or wiring of multiple energy storage modules and / or transistors.

[0021] Each energy storage module can have at least one battery or exactly one battery, for example a rechargeable battery.

[0022] For example, the transistor is used as a switch, which can be used to select a path for a current and / or voltage, for example. As a result, for example, an energy storage module can be incorporated into a desired configuration, or an energy storage module can be excluded from a desired configuration.

[0023] Preferably, at least or exactly two, three, four, five, six, seven, eight, nine, ten or more transistors are assigned to each energy storage module.

[0024] The transistor may be designed for a voltage of, for example, less than 500 V, 400 V, 300 V, 200 V, 100 V, 50 V, 40 V, 30 V, 20 V or 10 V. Preferably, the transistor may be designed for a voltage between 2 V and 8 V, for example 3 V, 4 V, 5 V, 6 V or 7 V.

[0025] For example, the transistor can be a lateral, planar or trench transistor. In principle, however, any type of configuration is conceivable.

[0026] Preferably, the transistor is designed as a MOSFET or comprises a MOSFET.

[0027] MOSFETs can be switched at high frequencies.

[0028] For example, at least one transistor may have a switching frequency of at least 1 Hz.

[0029] For example, silicon, gallium nitride, gallium arsenide and / or silicon carbide may be provided as semiconductor material.

[0030] Each energy storage module can be connected in parallel with a corresponding adjacent energy storage module, can be connected in series with a corresponding adjacent energy storage module, and / or can be bridged. Preferably, each energy storage module can be connected in series with a corresponding adjacent energy storage module. The possibility of parallel connection is advantageous, but not necessary.

[0031] In each case, adjacent energy storage modules are preferably connected to one another via two current and / or voltage paths. A transistor can be assigned to each path.

[0032] For example, three transistors are arranged between two adjacent energy storage modules. As a result, for example, the energy storage modules can be connected in parallel or in series.

[0033] Each energy storage module has at least one energy storage cell.

[0034] For example, an energy storage module may have exactly one energy storage unit. However, preferably, each energy storage module has a plurality of energy storage units, for example at least 10, 20, 30, 40, 50, 60, 70, 80, 90 or 100. For example, at least 100 energy storage units, for example 140 energy storage units, may be provided in the energy storage module.

[0035] Preferably, the energy storage units of the energy storage module can be connected in parallel with each other. Preferably, the energy storage units of the energy storage module are selected so that the same charge as that applied to the power grid, for example 230V, is applied.

[0036] Multilevel converter systems are more versatile than bridge circuits. This allows the creation of almost any configuration. For example, energy storage modules can be connected to each other in any way, such as in parallel or in series. Individual energy storage modules can also be incorporated into the desired configuration or excluded from the desired configuration.

[0037] At least two adjacent NPN transistors share an N-type region.Alternatively or additionally, at least two adjacent PNP transistors share a P-type region.

[0038] The N-type regions or P-type regions of adjacent transistors are thereby combined.

[0039] Instead of two adjacent NPN transistors, this effectively results in an NPNPN transistor; or, instead of two adjacent PNP transistors, this effectively results in a PNPNP transistor.

[0040] Independently of the multilevel converter system, protection of such transistors is also required.

[0041] Due to the fact that N-type or P-type regions are saved, there are advantages in the amount of semiconductor material required in the case of adjacent switches, as is usually the case in multi-level converter systems. On the one hand, this advantage is directly reflected in the price. On the other hand, the area of ​​the chip is reduced, which also has a positive effect on costs.

[0042] Surprisingly, a saving and / or shared use of adjacent areas can be achieved in multi-level converter systems and leads to a significant reduction in costs therein.

[0043] Developments of the invention can also be gathered from the dependent claims, the description and the accompanying drawings.

[0044] According to one embodiment, at least three NPN transistors are provided, wherein each of adjacent NPN transistors shares an N-type region.

[0045] Alternatively or additionally, at least three PNP transistors are provided, wherein each of adjacent PNP transistors shares a P-type region.

[0046] In principle, any number of transistors may be provided, each of which shares area with neighboring transistors.

[0047] For example, three NPN transistors may be combined to form an NPNPNPN transistor, or three PNP transistors may be combined to form a PNPNPNP transistor.

[0048] According to another embodiment, adjacent NPN transistors and / or PNP transistors are arranged side by side.

[0049] Preferably, the transistors are arranged in a rectilinear manner, ie in a row and, for example, without any angles.

[0050] According to another embodiment, adjacent NPN transistors and / or PNP transistors are not arranged linearly with respect to each other.

[0051] For example, adjacent transistors may be oriented at right angles or tilted to each other.

[0052] Preferably, adjacent transistors may comprise an angle greater than 0°.

[0053] Preferably, adjacent transistors may extend in different spatial directions (eg, along the X-axis, the Y-axis or the Z-axis).

[0054] According to a further embodiment, the multilevel converter system is designed as PECIN, MMSPC, M2B or BM3.

[0055] In this case, the topology PECIN stands for "Parallel Enhanced Commutation Integrated Nested", MMSPC stands for "Modular Multilevel Series Parallel Converter", and M2B stands for "Modular Multilevel Battery".

[0056] BM3, which is also known as the Marx topology, stands for "Battery Modular Multilevel Management".

[0057] In principle, other topologies are also conceivable, such as half-bridge, forward half-bridge, cross-switched, cascaded cross-switched, CEBS, full-bridge or ECIN.

[0058] For example, the mentioned topology is a potential candidate for installation in electric vehicles.

[0059] The present invention relates to a method for producing a multilevel converter system according to the invention, wherein N conductive layers and P conductive layers are produced in a wafer such that the N conductive layers and the P conductive layers are always arranged alternately, and / or wherein P conductive layers and N conductive layers are produced in a wafer such that the P conductive layers and the N conductive layers are always arranged alternately.

[0060] In this way, at least two adjacent NPN transistors share an N-type region, or two adjacent PNP transistors share a P-type region.

[0061] According to one embodiment, the wafer having the N conductive layer is covered with a first non-conductive protective layer.

[0062] For example, a single crystal silicon wafer or a single crystal gallium wafer may be used as a starting point.

[0063] For example, the first protective layer and / or the further protective layer may comprise or consist of silicon dioxide and / or gallium oxide.

[0064] A first window is inserted into the first protective layer to produce a P conductive layer.

[0065] The first window is covered with a second non-conductive protective layer.

[0066] A second window is inserted into the second protective layer to produce an N conductive layer.

[0067] The second window is covered with a third non-conductive protective layer.

[0068] A third window is inserted into the third protective layer to produce a P conductive layer.

[0069] The third window is covered with a fourth non-conductive protective layer.

[0070] A fourth window is inserted into the fourth protective layer to produce an N conductive layer.

[0071] For example, NPNPN transistors can be produced in this way.

[0072] The method can essentially continue as long as desired.

[0073] Preferably, the other windows are eventually inserted and the metal connections are attached, for example vaporized.

[0074] Corresponding production methods are also referred to as planar technologies. For example, windows can be inserted, preferably etched, by means of so-called mask technology.

[0075] According to another embodiment, the wafer having the P conductive layer is covered with a first non-conductive protective layer.

[0076] For example, a single crystal silicon wafer or a single crystal gallium wafer may be used as a starting point.

[0077] For example, the first protective layer and / or the further protective layer may comprise or consist of silicon dioxide and / or gallium oxide.

[0078] A first window is inserted into the first protective layer to produce an N conductive layer.

[0079] The first window is covered with a second non-conductive protective layer.

[0080] A second window is inserted into the second protective layer to produce a P conductive layer.

[0081] The second window is covered with a third non-conductive protective layer.

[0082] A third window is inserted into the third protective layer to produce an N conductive layer.

[0083] The third window is covered with a fourth non-conductive protective layer.

[0084] A fourth window is inserted into the fourth protective layer to produce a P conductive layer.

[0085] For example, PNPNP transistors can be produced in this way.

[0086] The method can essentially continue as long as desired.

[0087] Preferably, the other windows are eventually inserted and the metal connections are attached, for example vaporized.

[0088] Corresponding production methods are also referred to as planar technologies. For example, windows can be inserted, preferably etched, by means of so-called mask technology.

[0089] The invention further relates to a wafer for producing a multilevel converter system, in which N-conducting layers and P-conducting layers are always arranged alternately.

[0090] For example, an N conductive layer and a P conductive layer may be arranged to obtain an NPNPN structure.

[0091] Finally, the invention relates to a wafer for producing a multilevel converter system, in which P-conducting layers and N-conducting layers are always arranged alternately.

[0092] For example, the P conductive layer and the N conductive layer may be arranged to obtain a PNPNP structure.

[0093] All embodiments and components of the device described herein are preferably designed to be produced according to one or more methods described herein. In addition, all embodiments of the device described herein and all embodiments of the method described herein can be combined with each other, preferably also in a manner separate from the specific configuration mentioned. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] The present invention is described below by way of example with reference to the accompanying drawings, in which:

[0095] Figure 1 An embodiment of a multilevel converter system according to the prior art is shown;

[0096] Figure 2 shows a schematic diagram of three NPN transistors according to the prior art;

[0097] Figure 3 A schematic diagram of an NPNPNPN transistor is shown;

[0098] Figure 4 shows a schematic diagram of a PECIN according to the prior art; and

[0099] Figure 5 A schematic diagram of a PECIN according to the present invention is shown. DETAILED DESCRIPTION

[0100] First of all, it should be noted that the illustrated embodiments are purely exemplary. Therefore, the individual features can be implemented not only in the combinations shown, but also individually or in other technically useful combinations. For example, features of one embodiment can be combined with features of another embodiment in any desired manner. The configuration and / or number of energy storage modules, paths and transistors shown are purely exemplary and are essentially arbitrary.

[0101] If a figure contains reference numerals which are not explained in the directly related text of the specification, reference is made to the corresponding previous or subsequent explanation in the figure description. Therefore, the same reference numerals are used for the same or comparable components in the figures and are not explained again.

[0102] Figure 1 A multilevel converter system having energy storage modules 10 , 12 , 14 , 16 is shown.

[0103] Each of the adjacent energy storage modules 10 , 12 , 14 , 16 is connected via a plurality of paths.

[0104] A switch in the form of a transistor 18 is provided in each path.

[0105] Thus, adjacent energy storage modules 10, 12, 14, 16 can be connected in series or in parallel with one another. If necessary, individual energy storage modules 10, 12, 14, 16 can also be bridged, for example by closing the upper switch 18, and thus can be excluded from the configuration.

[0106] like Figure 2 and Figure 3 As shown, according to the present invention, three NPN transistors are effectively combined to form an NPNPNPN transistor.

[0107] Each of the adjacent NPN transistors shares an N-type region.

[0108] Thus, N-type regions can be combined here. Although this increases the scrap rate to some extent, it makes the semiconductor smaller and cheaper. For example, this can now be inserted into a housing.

[0109] This can be implemented for all topologies. However, the effect is greatest for topologies that also allow parallel connections and therefore have more switches.

[0110] The NPNPNPN transistor is preferably inserted into the housing as a whole, which can also reduce packaging costs.

[0111] Figure 4 and Figure 5 The combination of adjacent areas is shown using the PECIN topology as an example.

[0112] The two upper horizontally arranged NPN transistors share an N-type region and form an NPNPN transistor.

[0113] Likewise, the two lower horizontally arranged NPN transistors share the N-type region and form an NPNPN transistor.

[0114] The N-type regions of the two inclined NPN transistors are ultimately formed by the outer N-type region of the horizontal NPNPN transistor. In this case, the dashed lines represent the NPN connections, respectively.

[0115] Between the two horizontal NPNPN transistors, the NPN transistor thus extends from the left end of the upper NPNPN transistor to the right end of the lower NPNPN transistor, wherein the external N-type region is shared. Another NPN transistor extends from the right end of the upper NPNPN transistor to the left end of the lower NPNPN transistor, wherein the external N-type region is shared.

[0116] Similarly, PNP transistors may also be provided, wherein adjacent PNP transistors share a P-type region.

[0117] By virtue of each shared area among adjacent transistors, cost savings can be achieved. List of reference numerals 10 Energy storage module 12 Energy storage module 14 Energy storage module 16 Energy storage module 18 Transistor, switch.

Claims

1. A multi-level converter system, comprising: A plurality of energy storage modules (10, 12, 14, 16) and a transistor (18), wherein each energy storage module (10, 12, 14, 16) can be connected in parallel with a corresponding adjacent energy storage module (10, 12, 14, 16), can be connected in series with a corresponding adjacent energy storage module, and / or can be bridged, and each energy storage module has at least one energy storage unit, wherein at least two adjacent NPN transistors (18) share an N-type region, and / or At least two adjacent PNP transistors (18) share a P-type region.

2. The multilevel converter system according to claim 1, characterized in that providing at least three NPN transistors (18), wherein each of adjacent NPN transistors (18) shares an N-type region, and / or At least three PNP transistors (18) are provided, wherein each of adjacent PNP transistors (18) shares a P-type region.

3. The multilevel converter system according to claim 1 or 2, characterized in that: Adjacent NPN transistors (18) and / or PNP transistors (18) are arranged side by side.

4. The multilevel converter system according to any one of the preceding claims, characterized in that Adjacent NPN transistors (18) and / or PNP transistors (18) are not arranged linearly relative to each other.

5. The multilevel converter system according to any one of the preceding claims, characterized in that The multilevel converter system is designed as PECIN, MMSPC, M2B or BM3.

6. A method for producing a multilevel converter system according to any of the preceding claims, in, Producing N conductive layers and P conductive layers in a wafer so that the N conductive layers and the P conductive layers are always arranged alternately, and / or Therein, the P conductive layers and the N conductive layers are produced in a wafer such that the P conductive layers and the N conductive layers are always arranged alternately.

7. The method according to claim 6, characterized in that Covering the wafer having the N conductive layer with a first non-conductive protective layer, inserting a first window into the first protective layer to produce a P conductive layer, Covering the first window with a second non-conductive protective layer, inserting a second window into the second protective layer to produce an N conductive layer, Covering the second window with a third non-conductive protective layer, inserting a third window into the third protective layer to produce a P conductive layer, covering the third window with a fourth non-conductive protective layer, and A fourth window is inserted into the fourth protective layer to produce an N conductive layer.

8. The method according to claim 6, characterized in that Covering the wafer having the P conductive layer with a first non-conductive protective layer, inserting a first window into the first protective layer to produce an N conductive layer, Covering the first window with a second non-conductive protective layer, inserting a second window into the second protective layer to produce a P conductive layer, Covering the second window with a third non-conductive protective layer, inserting a third window into the third protective layer to produce an N conductive layer, covering the third window with a fourth non-conductive protective layer, and A fourth window is inserted into the fourth protective layer to produce a P conductive layer.

9. A wafer for producing a multilevel converter system, preferably a multilevel converter system according to any one of claims 1 to 5, wherein: N conductive layers and P conductive layers are always arranged alternately.

10. A wafer for producing a multilevel converter system, preferably a multilevel converter system according to any one of claims 1 to 5, wherein: P conductive layers and N conductive layers are always arranged alternately.

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