Tracking amplifier for inductive load

Abstract

The present invention generally relates to amplifier circuits for coupling and / or driving inductive loads with time-continuous current. Exemplary embodiments of the amplifier circuits disclosed herein may be used, for example, to drive, for example, an electrodynamic force converter that generates sound pressure, which may be in the form of a system-on-chip (SoC) or a system-in-package (SiP).

Description

Technical Field

[0001] Embodiments of the invention generally relate to amplifier circuits for coupling and / or driving inductive loads. Exemplary embodiments of the amplifier circuits disclosed herein can be used, for example, to drive an electrodynamic converter that generates, for example, sound pressure, which can be in the form of a system on chip (SoC) or a system in package (SiP). Background Art

[0002] Amplifier circuits are generally divided into two categories. One type of amplifier is a voltage amplifier, which is used to convert an input signal with a small input amplitude into an output signal with a large voltage amplitude. This type of amplifier is generally referred to as a small signal amplifier in the literature. For example, when used with an exemplary sensor element, the small output amplitude of the voltage amplifier can be processed for the next functional block in the signal processing chain. Other types of amplifiers are current amplifiers that focus on and provide high output currents. Optionally, current amplifiers are also called power amplifiers. When used in conjunction with a sound pressure generating (electrodynamic) device, a power amplifier can, for example, be used to provide a control signal for an actuator of the sound pressure generating (electrodynamic) device. Of course, hybrid forms of these two categories can also be found in technical applications, also involving the processing of time and value-continuous (= analog) or time and value-discrete (= digital) signals.

[0003] Due to the technical importance, the following description will focus on the amplification of analog voltages and currents. In principle, electrical amplifiers are an indispensable component in today's technology. Regardless of the chosen implementation, the power required for amplification is usually supplied by an electrical power supply device or element (e.g., a battery). Depending on how this power is handled, amplifiers are usually divided into different categories.

[0004] The amplifier topologies most commonly used today are known as Class AB, Class D, Class G, or Class H amplifiers.

[0005] A class AB amplifier usually has an output stage formed by n-type and p-type transistors driven via an operational amplifier input stage. Both transistors are driven continuously, i.e. no on-off scheme is used (e.g. in class D amplifiers, see below). The entire circuit is usually designed as a non-inverting amplifier. Since a class AB amplifier with a corresponding amplification factor has a time-continuous input signal at its output, no additional filter stage is required in the feedback path. However, since the output stage conducts current continuously, the power consumption of class AB amplifiers is often considered problematic, especially at higher output voltages.

[0006] The output stage of a class D amplifier is usually controlled by pulse width modulation (PWM), which reduces the power consumption of the current at the instant of switching. To generate the PWM signal, a comparator is usually used to sample the analog input signal to be amplified with a sawtooth voltage. After the output stage, a low-pass filter with sufficiently steep edges is usually required to filter out the analog fundamental component on the input side from the high-frequency digital signal.

[0007] A further improvement of the Class D amplifier is the Class G amplifier. Class G amplifiers usually have fixed and switchable supply voltage levels for their output-side push-pull stages. This switching of the supply voltage level can be achieved dynamically or by external control signals and results in better energy efficiency compared to Class D amplifiers, because for smaller output amplitudes, the energy that needs to be filtered by the output filter can be reduced.

[0008] Class H amplifiers try to minimize the power loss of Class AB amplifiers by regulating the supply voltage of the output stage. Regulation of the supply rail is usually achieved using an external feed with a boost and buck converter that requires a coil that cannot usually be integrated into an integrated circuit (IC) due to its size. In addition to the space required for external components in the IC implementation, the high complexity of Class H amplifiers is also a disadvantage. However, with proper design, Class H amplifiers may not require an output filter for filtering the signal on the output side.

[0009] The important properties for the design and implementation of amplifier circuits can be derived from the technical requirements of electronic amplifiers. The first thing to mention here is linearity, which directly translates into an amplified output signal free from distortion. Therefore, an ideal amplifier does not cause deviations from the input signal or, depending on the gain factor, does not cause deviations of multiples of the input signal. In addition, when selecting an amplifier design so that as much of the supplied power as possible is used for the actual useful output signal, the efficiency of the amplifier is also generally of decisive importance. On the contrary, a practical amplifier will consume additional energy at its output stage or through a downstream filter stage. From a system point of view, the complexity of the amplifier also plays an important role. Complexity cannot be summarized in a single key figure. However, important factors for the complexity of the amplifier design are usually the number of transistors, the area on the die, the use of external components (such as coils, capacitors and resistors) or additional functional blocks (such as voltage converters and active filters). In addition, in the case of reactive elements such as coils and capacitors, the load on the output side defines the required output voltage and output current and their frequency-dependent behavior.

[0010] The amplifier classes presented in the prior art have different advantages and disadvantages according to the described criteria. In terms of energy efficiency, the power and the filter stage at the output side are usually decisive. The class H amplifier is often considered the standard against which everything is measured, since it combines the advantageous push-pull stage of the class D amplifier with a filter-free design like the class AB amplifier. The push-pull stage allows power to flow only from the power supply to the load or from the load to the earth, avoiding unwanted cross currents when the load is powered. In connection with a variable modulated power supply, the desired voltage and current with low ripple can be generated at the load without filters. In general, the class H amplifier only provides at the output the power required by the system consisting of amplifier and load at the corresponding switching moments. The amount of power and therefore the output signal follows the desired and amplified target signal.

[0011] Figure 1 An exemplary tracking amplifier circuit 100 suitable for driving a capacitive load 110 is shown. The operation of the entire circuit corresponds to the principle of a control loop. A time-continuous input signal 102 to be amplified is provided to a non-inverting input terminal A of a comparator 104. The comparator 104 also receives a feedback signal at an inverting input terminal B and compares the signal 102 with the feedback signal to provide a comparison result at an output terminal C of the comparator 104. The output signal of the comparator 104 drives a push-pull stage 108 of the amplifier 100. In the example shown, a simple inverter stage with two transistors 112 and 114 implements the push-pull stage 108 to provide an amplified output signal of the amplifier 100 at an output terminal D. The output signal is applied to a capacitive load 110. The time-continuous output signal at the output terminal D is fed back to the input terminal B of the comparator 104 via an adjustable voltage divider 116, exemplarily consisting of two resistors.

[0012] Depending on the two input signals at the terminals A and B of the comparator 104, a digital signal having a high level or a low level is generated at the output terminal C of the comparator 104. The resulting digital signal may first be buffered and / or amplified in the buffer or inverter stage 106 and in turn used to control the transistors 112, 114 of the push-pull inverter stage 108.

[0013] Therefore, a digital pulse width modulation (PWM) signal is generated at the output terminal D of the amplifier 100. However, due to the capacitive load 110, the PWM output signal is integrated. According to the driving strength of the push-pull inverter stage 108 and the capacitance of the load 110, the rate of change of the output signal at the terminal D of the push-pull inverter stage 108 (also the output terminal of the amplifier 100) is therefore limited, so that the feedback path 118 can be implemented using the voltage divider 116 without any additional feedback filter to form a stable and continuous control loop. As a result, in the absence of external modulation of the power supply source 120 and without an additional filter stage in the feedback path 118, the output signal is smooth. Therefore, the output signal at the output terminal D and the voltage-divided equivalent signal of the output signal at the input terminal B of the comparator 104 will follow the input signal at the terminal A.

[0014] Figure 1 The limitation of the tracking amplifier 100 in is the need for a load 110 with sufficient capacitance that integrates the output voltage at the output node D to achieve the desired control loop. In principle, Figure 1 The tracking amplifier 100 in FIG. 1 can also work with other loads, but if the load has no capacitive components or the capacitance of the load is too low, no time-continuous voltage will appear at the load. If a purely resistive load is used, only digital amplification can be achieved, since the PWM signal at the output terminal D of the push-pull inverter stage 108 will be fed back to the inverting terminal B of the comparator 104 without any delay or integration, so that the control loop will immediately adapt to the output signal. If the amplifier 100 is connected to an inductive load, the reactive element will still be present, but the amplifier 100 will still not achieve the desired result, i.e., the amplifier 100 will not output a time-continuous output current. This is because the physical behavior of the current and voltage of the capacitive load 110 is opposite to that of the inductive load. While the electric field of the capacitor is controlled by the applied voltage, the magnetic field of the coil is determined by the current flowing through it.

[0015] In this context, it is necessary to improve Figure 1 The design of the exemplary tracking amplifier 100 shown in , enables the amplifier circuit to drive an inductive load with a time-continuous current while ensuring low power consumption and efficient amplification. Summary of the invention

[0016] This brief summary is provided to introduce some concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter.

[0017] Aspects of the present invention bring together many requirements for the design of the amplifier circuit described above in this article in a new amplifier design that allows driving inductive loads and does not require complex output filters. One design aspect is to generate a time-continuous output current at the output terminal of the amplifier circuit, and convert the time-continuous output current into a time-continuous output voltage that can be fed back to the comparator as a feedback signal to realize a control loop. Typically, the amplifier circuit can, for example, generate a PWM voltage signal at the output terminal, which causes the time-continuous output current to flow toward the load. The conversion of the time-continuous current to the time-continuous voltage can be realized using a feedback network between the output node of the amplifier circuit and the input node of the comparator. The feedback network can be arranged in parallel with the load branch or in series with the load branch, which will become more apparent from the following examples. In addition, amplifier designs according to different embodiments of the present invention can use different voltage domains of comparators, buffer stages (if present) and amplifier stages.

[0018] Embodiments of the present invention provide different exemplary implementations of an amplifier circuit for connecting to an inductive load. In those different exemplary implementations, the amplifier circuit includes an amplifier stage. The amplifier stage may include a comparator. The comparator has a non-inverting input terminal and an inverting input terminal to receive a signal to be amplified and a feedback signal. The comparator is used to generate and output a comparator output signal at its output terminal, and the comparator output signal is obtained by comparing the signal to be amplified and the feedback signal and represents the result of the comparison. The amplifier stage may also include an inverter stage, which generates a pulse width modulated signal in response to the comparator output signal, and outputs the pulse width modulated signal as a time-continuous current signal at the output terminal of the inverter stage. The output terminal of the inverter stage may also be the output terminal of the amplifier circuit.

[0019] The amplifier circuit also includes a feedback stage. In some embodiments, the feedback stage may include a feedback filter, which is connected in parallel to the inductive load and directly connected to the output terminal of the inverter stage to receive the time-continuous current signal and convert the time-continuous current signal into a time-continuous voltage signal. "Directly connected" here means that the output terminal of the feedback filter at the inverter stage is connected to the same output potential as the inductive load. The feedback stage may also include a voltage divider, which receives the time-continuous voltage signal at its input and is connected to a reference potential at its output. The voltage divider can be configured to provide a time-continuous voltage signal of a reduced voltage level as the feedback signal to the comparator.

[0020] In another exemplary embodiment, a signal amplified by the amplifier circuit is received at a non-inverting input terminal of a comparator, and a feedback signal is received at an inverting input terminal of the comparator.

[0021] According to another embodiment, the feedback filter is a low pass filter. In an exemplary implementation, the impedance of the feedback filter is higher than the impedance of the inductive load to minimize the power flowing into the feedback filter.

[0022] In another embodiment, the voltage divider may be formed by a first resistor and a second resistor connected in series. The first resistor has one terminal coupled to the output of the feedback filter to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal. The second resistor has one terminal coupled to the other terminal of the first resistor and another terminal coupled to the reference potential.

[0023] In an alternative embodiment, the voltage divider comprises a first capacitor and a second capacitor connected in series. In this embodiment, the first capacitor has one terminal connected to the output of the feedback filter to receive the time-continuous voltage signal and another terminal connected to one of the input terminals of the comparator to provide the feedback signal; and the second capacitor has one terminal connected to the other terminal of the first capacitor and another terminal connected to the reference potential.

[0024] As previously described, the amplifier circuit also includes a feedback stage. In some embodiments, the feedback stage may include an inductor and a resistor connected in parallel. The inductor and the resistor may form a feedback network. The inductor is magnetically coupled to the inductive load to receive a time-continuous current signal through the inductive load. The magnetism coupled to the inductive load may induce a current signal received from the inductance of the load in the feedback network. The induced current signal may be a mirrored current, the waveform of the mirrored current mirroring the time-continuous current signal flowing through the inductive load. The resistor converts the received time-continuous current signal into a time-continuous voltage signal. The feedback stage may also include a voltage divider that receives a time-continuous voltage signal at its input and is connected to a reference potential at its output. The voltage divider may be configured to provide a time-continuous voltage signal of a reduced voltage level to the comparator as the feedback signal.

[0025] In another embodiment, the inductor and resistor of the feedback stage are connected in parallel to the inductive load.

[0026] In another embodiment, one terminal of each of the resistor and the inductor of the feedback stage is connected to the same reference potential and one terminal of the inductive load.

[0027] In another exemplary embodiment, the signal amplified by the amplifier circuit is received at a non-inverting input terminal of a comparator, and the feedback signal is received at the inverting input terminal of the comparator.

[0028] In another embodiment, the voltage divider may be formed by a first resistor and a second resistor connected in series. The first resistor has one terminal coupled to the resistor of the feedback stage to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide a feedback signal. The second resistor has one terminal coupled to the other terminal of the first resistor and another terminal coupled to the reference potential.

[0029] In an alternative embodiment, the voltage divider comprises a first capacitor and a second capacitor connected in series. In this embodiment, the first capacitor has one terminal coupled to the output of the feedback stage to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and the second capacitor has one terminal coupled to the other terminal of the first capacitor and another terminal coupled to the reference potential.

[0030] As previously described, the amplifier circuit also includes a feedback stage. In some embodiments, the feedback stage includes a resistor connected in series with the inductive load, wherein the resistor is used to convert a time-continuous current signal flowing through the inductive load into a time-continuous voltage signal. The resistor converts the received time-continuous current signal into a time-continuous voltage signal. The feedback stage may also include a voltage divider that receives the time-continuous voltage signal at its input and is connected to a reference potential at its output. The voltage divider may be configured to provide a time-continuous voltage signal of a reduced voltage level as the feedback signal to the comparator.

[0031] In another embodiment, the resistor of the feedback stage has a first terminal connected to the inductive load and another second terminal connected to the reference potential, and the input of the voltage divider is connected to the first terminal. In an exemplary implementation, the inductive load and the resistor of the feedback stage form a second voltage divider.

[0032] In another exemplary implementation of this embodiment, the second inductive load is connected in series with the inductive load and connected in parallel with the resistor of the feedback stage. In other words, in this embodiment, the two inductive loads may also be referred to as separate inductive load components of a common inductive load, wherein the resistor is connected in parallel to one of these load components, namely the second inductive load component. The two load components may have the same inductance and / or the same impedance. The first inductive load and the second inductive load are connected in series like a voltage divider, and the resistor is connected to the "center tap" between the two inductive load components.

[0033] In another exemplary embodiment, a signal amplified by the amplifier circuit is received at a non-inverting input terminal of a comparator, and a feedback signal is received at an inverting input terminal of the comparator.

[0034] In an exemplary embodiment, the signal to be amplified has a voltage level relative to a reference potential.

[0035] In another embodiment, the voltage divider can be formed by a first resistor and a second resistor connected in series. The first resistor has one terminal connected to the first terminal of the resistor of the feedback stage to receive the time continuous voltage signal and another terminal connected to one of the input terminals of the comparator to provide the feedback signal. The second resistor has one terminal connected to the other terminal of the first resistor and another terminal connected to the reference potential.

[0036] In an optional implementation, the voltage divider includes a first capacitor and a second capacitor connected in series. In this embodiment, the first capacitor has one terminal connected to the first terminal of the resistor of the feedback stage to receive the time-continuous voltage signal and another terminal connected to one of the input terminals of the comparator to provide the feedback signal; and the second capacitor has one terminal connected to the other terminal of the first capacitor and another terminal connected to the reference potential.

[0037] As previously described, the amplifier circuit also includes a feedback stage. In some embodiments, the feedback stage may include a current mirror having a first path and a second path, and the time-continuous current signal flows through the first path. The current mirror is configured to cause the mirrored time-continuous current signal to flow through the second path of the current mirror. The mirrored time-continuous current signal corresponds to the time-continuous current signal flowing through the first path. The feedback stage may also include a resistor having a terminal connected to the second path of the current mirror and another terminal connected to the output terminal or reference potential of the amplifier circuit. The resistor is configured to convert the mirrored time-continuous current signal of the second path of the current mirror into a time-continuous voltage signal. The feedback stage may also include a voltage divider that receives the time-continuous voltage signal at its input and is connected to the reference potential at its output. The voltage divider may be configured to provide the time-continuous voltage signal of the reduced voltage level to the comparator as the feedback signal.

[0038] In one embodiment, a first terminal of a resistor of the feedback stage is connected to an output terminal of the inverter stage, and a second terminal of the resistor is connected to an input terminal of a voltage divider and a second path of a current mirror. The second path of the current mirror is connected between the second terminal of the resistor and a reference potential, and the first path of the current mirror is connected between an inductive load and the reference potential. In this embodiment, an n-type transistor may be used to implement the current mirror.

[0039] In an alternative embodiment, a first terminal of a resistor of the feedback stage is connected to a reference potential, and a second terminal of the resistor is connected to an input terminal of a voltage divider and a second path of a current mirror. The second path of the current mirror is connected between an output terminal of the inverter stage and the second terminal of the resistor, and the first path of the current mirror is connected between the output terminal of the inverter stage and an inductive load. In this embodiment, a p-type transistor may be used to implement the current mirror.

[0040] In another embodiment, the time-continuous current signal of the mirror of the second path flowing through the current mirror can be proportional to the time-continuous current signal of the first path flowing through the current mirror and less than the time-continuous current signal of the first path flowing through the current mirror. For example, the time-continuous current signal of the mirror of the second path flowing through the current mirror can be 1 / N of the time-continuous current signal of the first path flowing through the current mirror. In addition, or alternatively, the resistance of the resistor of the feedback path can be N times the resistance of the inductive load.

[0041] According to another embodiment, the first path of the current mirror includes a first number of first transistors connected in parallel to each other. The first transistors connected in parallel receive a time-continuous current signal flowing through the inductive load at their gate terminals. The first path of the current mirror may also include a first number of second transistors, the first number of second transistors connected in parallel to each other and connected in series with the first transistor, wherein the gate terminal of the second transistor receives the current flowing through the first transistor. For example purposes only, the number of first transistors and second transistors is selected to be the same; different numbers of first transistors and second transistors can be used. Similarly, the second path of the current mirror includes a second number of third transistors and a second number of fourth transistors, the second number of third transistors connected in parallel to each other and their gate terminals are connected to the gate terminal of the first transistor, and the second number of fourth transistors connected in parallel to each other and connected in series with the third transistor, wherein the gate terminal of the fourth transistor is connected to the gate terminal of the second transistor. In this example, for example purposes only, the number of third transistors and fourth transistors is selected to be the same; different numbers of third transistors and fourth transistors can be used. In an example implementation, the first number is an integer multiple (e.g., N times) of the second number.

[0042] In another exemplary embodiment, the signal amplified by the amplifier circuit is received at a non-inverting input terminal of the comparator, and the feedback signal is received at an inverting input terminal of the comparator.

[0043] In another embodiment, the voltage divider may be formed by a first resistor and a second resistor connected in series. The first resistor has one terminal coupled to the output of the feedback filter to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal. The second resistor has one terminal coupled to the other terminal of the first resistor and another terminal coupled to the reference potential.

[0044] In an optional implementation, the voltage divider includes a first capacitor and a second capacitor connected in series. In this embodiment, the first capacitor has one terminal connected to the output of the feedback filter to receive the time-continuous voltage signal and another terminal connected to one of the input terminals of the comparator to provide the feedback signal; and the second capacitor has one terminal connected to the other terminal of the first capacitor and another terminal connected to the reference potential.

[0045] The following embodiments apply to all exemplary implementations of the feedback stage of the amplifier circuit discussed herein. In another embodiment of the invention, the signal to be amplified has a voltage level relative to a reference potential.

[0046] According to another embodiment, the amplifier stage further comprises one or more buffer circuits connected in series between the output terminal of the comparator and the input terminal of the inverter stage. In the embodiment shown herein, the input terminal of the inverter stage may be connected to the gate terminal of the active element (transistor) in the inverter stage.

[0047] In an exemplary implementation of this embodiment, the one or more buffer circuits are configured to perform a level shift of the comparator output signal and provide the level shifted comparator output signal to the input terminal of the inverter stage. In addition, the one or more buffer circuits may be configured to amplify the drive strength of the signal applied to the input terminal of the inverter stage.

[0048] In another embodiment, the inverter stage includes at least one pair of push-pull transistors connected in series and forming a push-pull configuration. In one example, the drain terminals of the push-pull transistors can be connected to each other and provide an output terminal of the inverter stage. A first push-pull transistor of the pair of push-pull transistors can be a p-type transistor, and the other second push-pull transistor of the pair of push-pull transistors can be an n-type transistor.

[0049] In an exemplary implementation of this embodiment, a first push-pull transistor of the pair of push-pull transistors may be connected to a first reference potential, and another second push-pull transistor of the pair of push-pull transistors may be connected to a second reference potential different from the first reference potential. The amplifier circuit may further include: a first bias control circuit configured to integrate the comparator output signal and provide the integrated comparator output signal as a first reference signal to a source terminal of the first push-pull transistor; and a second bias control circuit configured to integrate the comparator output signal and provide the integrated comparator output signal as a second reference signal to a source terminal of the second push-pull transistor.

[0050] In another exemplary implementation of this embodiment, a first push-pull transistor of the pair of push-pull transistors is connected to a first reference potential via one or more first bias transistors, the one or more first bias transistors being configured to control a current flowing through the first push-pull transistor to the output terminal of the inverter stage, and another second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential via another one or more second bias transistors, the one or more second bias transistors being configured to control a current flowing through the second push-pull transistor to the output terminal of the inverter stage. In this implementation, the one or more first bias transistors and the one or more second bias transistors may form a variable resistor. For example, the amplifier circuit may further include: a first bias control circuit configured to apply a bias signal to one or more gate terminals of the one or more first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage; and a second bias control circuit configured to apply a bias signal to one or more gate terminals of the one or more second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the second push-pull transistor to the output terminal of the inverter stage.

[0051] In one example, the first bias control circuit and the second bias control circuit are configured to integrate the comparator output signal and provide the integrated comparator output signal as the bias signal to the gate terminals of the one or more first bias transistors and the one or more second bias transistors, respectively.

[0052] In another example, the first bias control circuit is configured to selectively activate and deactivate a selected number of the first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage; and the second bias control circuit is configured to selectively activate and deactivate a selected number of the second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage. In this other example, the first bias control circuit and the second bias control circuit can be implemented, for example, with a counter or a switch matrix to selectively activate or deactivate a selected number of bias transistors.

[0053] In the above different implementations, each of the first bias control circuit and the second bias control circuit may include, for example, an inverter circuit connected between two DC voltage references and a buffer capacitor connected between an output terminal of the inverter circuit and one of the DC voltage references.

[0054] In another embodiment of the invention, the inverter stage comprises a plurality of cascaded inverters. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] The present specification will be better understood from the following detailed description read with reference to the accompanying drawings, wherein like reference numerals are used to refer to like parts throughout the appended description.

[0056] Figure 1 An exemplary tracking amplifier circuit suitable for driving a capacitive load is shown;

[0057] Figure 2 shows a schematic circuit implementation of a tracking amplifier 200 according to an embodiment of the present invention;

[0058] Figure 3 shows a schematic circuit diagram of a tracking amplifier 300 according to another exemplary embodiment;

[0059] Figure 4 Schematic circuit implementation of a tracking amplifier 400 according to another embodiment of the present invention is shown;

[0060] Figure 5 shows a schematic circuit diagram of a tracking amplifier 500 according to another exemplary embodiment;

[0061] Figure 6 Schematic circuit implementation of a tracking amplifier 600 according to another embodiment of the present invention is shown;

[0062] Fig. 7A and Figure 7Bshows a schematic circuit diagram of two tracking amplifiers 700 and 750 according to another example embodiment;

[0063] Fig. 8A shows a schematic circuit implementation of a tracking amplifier 800 according to an embodiment of the present invention;

[0064] Figure 8B shows a schematic circuit diagram of a tracking amplifier 800' according to another exemplary embodiment;

[0065] Fig. 9A shows a schematic circuit implementation of a tracking amplifier 900 according to an embodiment of the present invention;

[0066] Fig. 9B shows a schematic circuit diagram of a tracking amplifier 900' according to another exemplary embodiment;

[0067] Fig.10 and Fig.11 Shown as Figure 3 , Figure 5 , Fig. 7A , Figure 7B , Figure 8B and Fig. 9B illustrative waveforms in any of the amplifier circuits 300, 500, 700, 750, 800', 900' shown in; and

[0068] Fig.12 , Fig.13 and Fig.14 shows different embodiments of the present invention. Figures 2 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and a further exemplary modification of the output stage of the amplifier in FIG. 9C . DETAILED DESCRIPTION

[0069] Different embodiments of the present invention will be outlined in more detail below. As described above, the present disclosure generally relates to an amplifier circuit and design that is convenient for driving inductive loads and that does not require a complex feedback network for implementing a control loop. When the amplifier is implemented in an integrated circuit, these advantages can be further translated into an overall simpler design of the amplifier and a smaller area on the die / chip. Although the amplifier circuits can be simply designed, they can achieve good linearity, which directly translates into the amplified output signal being free from distortion. Therefore, according to the amplifier design of an embodiment of the present invention, the output signal generated by the amplifier circuit can show only a very limited deviation from the input signal, or, depending on the gain factor, a multiple of the input signal.

[0070] The amplifier designs discussed in this article may be particularly suitable for driving MEMS-based, SoC-based or SiP-based actuator systems, such as, for example and without limitation, sound pressure generating (electrodynamic) devices representing a load with an inductive component. For example, these sound pressure generating devices may be based on the principle of nano-electrostatic drive (NED) as described, for example, in patent application WO2012 / 095185A1. However, the field of application of the amplifier designs discussed in this article is not limited to this field of use.

[0071] One design aspect of the present invention is to generate a time-continuous output current at the output terminal of the amplifier circuit, and convert the time-continuous output current into a time-continuous output voltage, which can be fed back to the comparator as a feedback signal to implement a control loop. As will become more apparent from the embodiments discussed herein, the amplifier circuit can generate a PWM voltage signal at the output terminal, and generate a time-continuous output current to flow to the inductive load. The control loop is based on the conversion of the time-continuous current into a time-continuous voltage, which is implemented using a feedback network arranged between the output node of the amplifier circuit and one of the input nodes of the comparator. The feedback network can be arranged in parallel with the load branch or in series with the load branch. In addition, amplifier designs according to different embodiments of the present invention can use different voltage domains for the comparator, buffer stage (if present) and amplifier stage.

[0072] Figure 2 A schematic circuit implementation of a tracking amplifier 200 according to an embodiment of the present invention is shown. The amplifier circuit 200 includes an amplifier stage 240 and a feedback stage 250. The amplifier stage 240 includes a comparator 204 having a non-inverting terminal A and an inverting terminal B as input terminals. An input signal 202 is provided to the input terminal A. The input signal 202 can be a time-continuous voltage signal. When the amplifier circuit 200 is used to drive a sound pressure generating device (e.g., in a headphone, an in-ear device, etc.), the input signal 202 can be an audio signal or a sound signal that is used to drive (multiple) actuators of the sound pressure generating device to generate a desired sound pressure in an audible and / or non-audible frequency range of a spectrum.

[0073] The comparator 204 compares the signals (i.e., voltages / potentials) applied to its input terminals A and B, and provides a high or low signal at its output terminal C indicating the result of the comparison. The output signal of the comparator 204 is provided to the buffer circuit 206. The buffer circuit 206 is optional and may not be present. The buffer circuit 206 may, for example, include one or more buffer circuits, which may, for example, be used to perform a level shift of the output signal at the output terminal C to adjust the signal level (e.g., voltage / potential) and / or signal current to a desired range for driving the push-pull stage 208. The push-pull stage 208 is used to amplify the output signal of the comparator 204 (as processed by the optional buffer circuit 206) and provide the output signal of the amplifier 200 at the output terminal D.

[0074] The push-pull stage 208 generates a PWM signal relative to reference potentials 220A and 220B and in response to the output signal of the comparator 204, which is used as a control signal for the push-pull stage 208. The reference potential 220B is exemplarily shown as ground (GND). The reference potentials 220A and 220B may also be referred to as VDD and VSS, respectively. The reference potentials 220A and 220B may be adjustable, programmable, or controllable.

[0075] The output signal provided by the amplifier circuit 200 at the output terminal D may be a PWM voltage signal that causes a time-continuous current signal to flow into or from the node D to the amplifier circuit 200. The output signal of the amplifier circuit 200 at the terminal D is applied to an inductive load 210, which for example purposes is represented by an inductor 210A (L load ) and resistor 210B (R load ) modeling.

[0076] The output signal of amplifier circuit 200 at terminal D is applied to feedback stage 250. Figure 2 In the exemplary embodiment of , the feedback stage 250 includes a feedback network 222 and a voltage divider 216. The feedback network 222 is a circuit configured to convert a time-continuous current signal to flow into the node D or to flow from the node D into the amplifier circuit 200 into a time-continuous voltage signal. The time-continuous voltage signal is provided at the node E and is applied to the voltage divider 216. The voltage divider 216 adjusts the time-continuous voltage signal provided at the node E to an appropriate voltage level for application to the inverting terminal B of the comparator 204.

[0077] Figure 3 FIG. 2 shows a schematic circuit diagram of a tracking amplifier 300 according to another exemplary embodiment. The amplifier circuit 300 can be considered as Figure 2A more detailed implementation of the amplifier circuit 200 is shown in FIG. Figure 2 The buffer circuit 206 in FIG. 2 (which is optional) is shown as including two inverter stages that perform level shifting of the output signal of the comparator 204 at the terminal C. The push-pull stage 208 is implemented by a simple inverter stage. In other embodiments, the push-pull stage 208 may be implemented using a plurality of cascaded inverters.

[0078] The inverter stage is formed by a pair of transistors 212, 214, which in this example are n-type transistors (e.g., NPN) and p-type transistors (e.g., PNP). Transistors 212, 214 are connected in series between reference potentials 220A and 220B. The drain terminals of transistors 212, 214 are connected to each other and to output terminal D. The emitter terminals of transistors 212, 214 are connected to reference potentials 220A and 220B, respectively. The gate terminals of transistors 212, 214 are connected to terminal C providing the output signal of comparator 204 via buffer circuit 206 as described above. In some embodiments, transistors 212, 214 can be small signal transistors or small switching transistors, which can be implemented as bipolar junction transistors (BJT) (e.g., NPN transistors and PNP transistors), for example. However, field effect transistors (FETs), such as junction FETs (JFETs) or metal oxide semiconductor FETs (MOSFETs), can also be used. In principle, the transistors 212 and 214 may also be implemented using other switching elements (for example, using power transistors).

[0079] In addition, transistors 212, 214 are shown as different types (p-type and n-type, respectively), and are therefore driven by the same control signal corresponding to the output signal at node C of comparator 204. However, if the control signal corresponding to the output signal at node C of comparator 204 applied to the gate terminal of one of transistors 212, 214 is inverted (e.g., in an inverter), then both transistors 212, 214 can be implemented using the same transistor type. The control signal to the other gate terminal can be used "as is", or if the phase difference between the inverted control signal and the non-inverted control signal is critical to the correct operation of the amplifier stage 240, a delay element can be added to compensate for the phase difference between the inverted control signal and the non-inverted control signal. In other embodiments and application scenarios, the push-pull stage 208 can be replaced by a single transistor, the source terminal of which is connected to the reference potential 220A or 220B, and the gate terminal receives the control signal from node C. In this case, the drain terminal can be connected to the output node D.

[0080] and Figure 12, the input signal at the input terminal A of the comparator 204 is compared with the feedback signal at the terminal B of the comparator 204 which is based on the time-continuous output signal of the amplifier circuit 300 at the node D. Depending on the two input signals of the comparator 204, a "digital" signal with a high level or a low level is generated at the output terminal C of the comparator 204. The generated digital signal can be amplified in the buffer circuit 206 (if present) and used in turn to control the push-pull inverter stage 208 by driving the gate terminals of the transistors 212, 214. A PWM sequence is generated at the output terminal D of the amplifier 300. In order to connect the inductive load 210 (impedance L load and line resistance R load ) is converted into a time-continuous voltage, and the feedback network 222 is implemented by a simple low-pass filter. The low-pass filter is implemented by means of an RC element, that is, a resistor 226 (R filter ) and capacitor 224 (C filter ). Since the time-continuous feedback current from D continuously charges or discharges the capacitor 224, the voltage potential at the node E will also change with time. Low-pass filtering of a portion of the current on the output side node D again produces a usable, time-continuous voltage that is fed back via the voltage divider 216 in the feedback loop. The exemplary voltage divider 216 is formed by two resistors 228 (Rdiv1) and 230 (Rdiv2), and the center tap of the voltage divider between the two resistors 228 and 230 is connected to the inverting terminal B of the comparator 204, thereby completing the control loop. The voltage divider 216 can also be implemented using two capacitors. The ratio of the resistances of the resistors 228 and 230 can be set, controlled or designed to achieve the desired amplification gain of the amplifier circuit.

[0081] For example, the low pass filters 224, 226 of the feedback network 222 may also be implemented as LC elements. Depending on the field of use, the additional inductance of the LC elements may be undesirable. Another optional implementation of the feedback network 222 may be a switched capacitor filter.

[0082] In order to make the control loop work optimally, that is, the amplified target current on the output side at node D follows the corresponding input signal 202 on the input side, according to some embodiments, L load Divide by R load The load branch time constant is preferably equal to R filter Multiply by C filter The time constant of the parallel low-pass filter, i.e., L load / R load =R filter ·C filterThe impedance of the feedback branch 250 can be very high, minimizing the power flowing into the feedback stage 250. This enables a very high energy efficiency of the amplifier 200, 300, while at the same time the load 210 on the output side does not change due to the parallel connection of the feedback network 222 and the load 210.

[0083] Figure 4 Another schematic circuit implementation of a tracking amplifier 400 according to an embodiment of the present invention is shown. The amplifier circuit 400 includes an amplifier stage 240 and a feedback stage 450. The amplifier stage 240 includes a comparator 204 having a non-inverting terminal A and an inverting terminal B as input terminals. An input signal 202 is provided to the input terminal A. The input signal 202 can be a time-continuous voltage signal. When the amplifier circuit 400 is used to drive a sound pressure generating device (e.g., in a headphone, an in-ear device, etc.), the input signal 202 can be an audio signal or a sound signal that is used to drive (multiple) actuators of the sound pressure generating device to generate a desired sound pressure in an audible and / or non-audible frequency range of a spectrum.

[0084] The comparator 204 compares the signals (i.e., voltages / potentials) applied to its input terminals A and B, and provides a high signal or a low signal at its output terminal C indicating the result of the comparison. The output signal of the comparator 204 is provided to the buffer circuit 206. The buffer circuit 206 is optional and may not be present. The buffer circuit 206 may, for example, include one or more buffer circuits, which may, for example, be used to perform a level shift of the output signal at the output terminal C to adjust the signal level (e.g., voltage / potential) and / or signal current to a desired range for driving the push-pull stage 208. The push-pull stage 208 is used to amplify the output signal of the comparator 204 (as processed by the optional buffer circuit 206) and provide the output signal of the amplifier 400 at the output terminal D.

[0085] The push-pull stage 208 generates a PWM signal relative to reference potentials 220A and 220B and in response to the output signal of the comparator 204, which is used as a control signal for the push-pull stage 208. The reference potential 220B is exemplarily shown as ground (GND). The reference potentials 220A and 220B may also be referred to as VDD and VSS, respectively. The reference potentials 220A and 220B may be adjustable, programmable, or controllable.

[0086] The output signal provided by the amplifier circuit 400 at the output terminal D may be a PWM voltage signal that causes a time-continuous current signal to flow into the node D or from the node D into the amplifier circuit 400. The output signal of the amplifier circuit 400 at the terminal D is applied to the inductive load 210, which for example purposes is represented by the inductor 210A (Lload ) and resistor 210B (R load ) modeling.

[0087] The output signal of amplifier circuit 400 at terminal D is applied to feedback stage 450. Figure 4 In the exemplary embodiment of the present invention, the feedback stage 450 includes a feedback network 422 and a voltage divider 216. The feedback network 422 is a circuit configured to convert a time-continuous current signal to flow into the node D or to flow from the node D into the amplifier circuit 400 into a time-continuous voltage signal. The feedback network 422 is connected in parallel to the inductive load 210. The time-continuous voltage signal is provided at the node E and is applied to the voltage divider 216. The voltage divider 216 adjusts the time-continuous voltage signal provided at the node E to an appropriate voltage level for application to the inverting terminal B of the comparator 204.

[0088] Figure 5 FIG. 5 shows a schematic circuit diagram of a tracking amplifier 500 according to another exemplary embodiment. The amplifier circuit 500 can be considered as Figure 4 A more detailed implementation of the amplifier circuit 400 is shown in FIG. Figure 4 The buffer circuit 206 in FIG. 2 (which is optional) is shown as including two inverter stages that perform level shifting of the output signal of the comparator 204 at the terminal C. The push-pull stage 208 is implemented by a simple inverter stage. In other embodiments, the push-pull stage 208 may be implemented using multiple cascaded inverters.

[0089] The inverter stage is formed by a pair of transistors 212, 214, which are n-type transistors (e.g., NPN) and p-type transistors (e.g., PNP) in this example. Transistors 212, 214 are connected in series between reference potentials 220A and 220B. The drain terminals of transistors 212, 214 are connected to each other and to output terminal D. The emitter terminals of transistors 212, 214 are connected to reference potentials 220A and 220B, respectively. The gate terminals of transistors 212, 214 are connected to terminal C providing the output signal of comparator 204 via buffer circuit 206 as described above. In some embodiments, transistors 212, 214 can be small signal transistors or small switching transistors, which can be implemented as bipolar junction transistors (BJT) (e.g., NPN transistors and PNP transistors), for example. However, field effect transistors (FETs) can also be used, such as junction FETs (JFETs) or metal oxide semiconductor FETs (MOSFETs). In principle, transistors 212, 214 can also be implemented using other switching elements (e.g., using power transistors).

[0090] In addition, transistors 212, 214 are shown as different types (p-type and n-type, respectively), and are therefore driven by the same control signal corresponding to the output signal at node C of comparator 204. However, if the control signal corresponding to the output signal at node C of comparator 204 applied to the gate terminal of one of transistors 212, 214 is inverted (e.g., in an inverter), then both transistors 212, 214 can be implemented using the same transistor type. The control signal to the other gate terminal can be used "as is", or if the phase difference between the inverted control signal and the non-inverted control signal is critical to the correct operation of the amplifier stage 240, a delay element can be added to compensate for the phase difference between the inverted control signal and the non-inverted control signal. In other embodiments and application scenarios, the push-pull stage 208 can be replaced by a single transistor, the source terminal of which is connected to the reference potential 220A or 220B, and the gate terminal receives the control signal from node C. In this case, the drain terminal can be connected to the output node D.

[0091] and Figure 1 5 , the input signal at the input terminal A of the comparator 204 is compared with the feedback signal at the terminal B of the comparator 204 which is based on the time-continuous output signal of the amplifier circuit 500 at the node D. Depending on the two input signals of the comparator 204, a "digital" signal with a high level or a low level is generated at the output terminal C of the comparator 204. The generated digital signal can be amplified in the buffer circuit 206 (if present) and used in turn to control the push-pull inverter stage 208 by driving the gate terminals of the transistors 212 and 214. A PWM sequence is generated at the output terminal D of the amplifier 500. In order to connect the inductive load 210 (impedance L load and line resistance R load ) is converted into a time-continuous voltage, including another inductor 460 (impedance L 2 ) and another resistor 462 (resistance R convert ) is connected in parallel with the load 210. The inductors 210A and 460 are arranged in a manner that allows magnetic fields to be coupled through the inductors 210A and 460. The inductive load 210 and the inductors 210A and 460 of the feedback network 422 effectively create a transformer having a primary winding formed by the inductor 210A and a secondary winding formed by the inductor 460, respectively. The time-continuous charging or discharging current flowing into or out of the node D is mirrored to the node E through the transformer. The turns ratio between the primary winding (inductor 210A) and the secondary winding (inductor 460) and their magnetic coupling determine the ratio of the current at the node D and the current mirrored into the feedback network 422. The resistor 462 (R convert) converts the current mirrored into the feedback network 422 into a time-continuous voltage signal. Resistor 462 is connected in parallel to the voltage divider 216. The exemplary voltage divider 216 is formed by two resistors 216 (Rdiv1) and 230 (Rdiv2), and the center tap of the voltage divider between the two resistors 216, 230 is connected to the inverting terminal B of the comparator 204, thereby completing the control loop. The voltage divider 216 can also be implemented using two capacitors. The ratio of the resistances of the resistors 462, 216 and 230 and / or the turns ratio of the inductor 210A and the inductor 460 can be set, controlled or designed individually or together to achieve the desired amplification gain of the amplifier circuit.

[0092] For high energy efficiency, the current in the feedback path through the feedback network 422 should be much smaller than the desired output current through the inductive load 210. To make this different, the number of windings N of the inductor 460 is L2 It should be the inductive load 210, the inductance 210A, the winding number N Lload For example, in the case of M=100, the current passing through the inductive load 210 is M times the current passing through the inductor 460. In an exemplary embodiment, M≥50, preferably, M≥100, more preferably, M≥200, and even more preferably, M≥500.

[0093] In order for the control loop to work optimally, i.e. the amplified target current on the output side at node D follows the input signal 202 on the input side, according to some embodiments, the voltage across the resistor 462 should be (substantially) equal to the voltage of the input signal 202 on the input side of the amplifier circuit 500. To this end, the resistance R of the resistor 462 can be convert Select, set, control or configure to have (substantially) equal line resistance R load The product of the coefficient M (R convert =M·R load ). Therefore, the impedance of the feedback branch (216 and 422) can be very high, minimizing the power flowing into the feedback stage. This makes it possible for the amplifier 400, 500 to have a very high energy efficiency, and at the same time, due to the parallel connection of the feedback network 422 and the load 210, the load 210 on the output side does not change.

[0094] exist Figure 5 In the exemplary embodiment shown in , the discharge of the output current at terminal D can be through the inductive load 210. Therefore, in an alternative implementation, the inverter stage 208 can be replaced with a transistor (e.g., only transistor 212, and "eliminating" transistor 214, or vice versa) whose drain terminal is connected to the output terminal D.

[0095] Figure 6Another schematic circuit implementation of a tracking amplifier 600 according to an embodiment of the present invention is shown. The amplifier circuit 600 includes an amplifier stage 240 and a feedback stage 650. The amplifier stage 240 includes a comparator 204 having a non-inverting terminal A and an inverting terminal B as input terminals. An input signal 202 is provided to the input terminal A. The input signal 202 can be a time-continuous voltage signal. When the amplifier circuit 600 is used to drive a sound pressure generating device (e.g., in a headphone, an in-ear device, etc.), the input signal 202 can be an audio signal or a sound signal, which is used to drive (multiple) actuators of the sound pressure generating device to generate a desired sound pressure in an audible and / or non-audible frequency range of a spectrum.

[0096] The comparator 204 compares the signals (i.e., voltages / potentials) applied to its input terminals A and B, and provides a high or low signal at its output terminal C indicating the result of the comparison. The output signal of the comparator 204 is provided to the buffer circuit 206. The buffer circuit 206 is optional and may not be present. The buffer circuit 206 may, for example, include one or more buffer circuits, which may, for example, be used to perform a level shift of the output signal at the output terminal C to adjust the signal level (e.g., voltage / potential) and / or signal current to a desired range for driving the push-pull stage 208. The push-pull stage 208 is used to amplify the output signal of the comparator 204 (as processed by the optional buffer circuit 206) and provide the output signal of the amplifier 600 at the output terminal D.

[0097] The push-pull stage 208 generates a PWM signal relative to reference potentials 220A and 220B and in response to the output signal of the comparator 204, which is used as a control signal for the push-pull stage 208. The reference potential 220B is exemplarily shown as ground (GND). The reference potentials 220A and 220B may also be referred to as VDD and VSS, respectively. The reference potentials 220A and 220B may be adjustable, programmable, or controllable.

[0098] The output signal provided by the amplifier circuit 600 at the output terminal D may be a PWM voltage signal that causes a time-continuous current signal to flow into or from the node D to the amplifier circuit 600. The output signal of the amplifier circuit 600 at the terminal D is applied to the inductive load 210, which for example purposes is represented by an inductor 210A (L load ) and resistor 210B (R load ) modeling.

[0099] The output signal of amplifier circuit 600 at terminal D is applied to feedback stage 650. Figure 6In the exemplary embodiment of the present invention, the feedback stage 650 includes a feedback network 622 and a voltage divider 216. The feedback network 622 is a circuit configured to convert a time-continuous current signal to flow into the node D or to flow from the node D into the amplifier circuit 600 into a time-continuous voltage signal. The feedback network 622 is connected in series to the inductive load 210. The time-continuous voltage signal is provided at the node E and is applied to the voltage divider 216. The voltage divider 216 adjusts the time-continuous voltage signal provided at the node E to an appropriate voltage level for application to the inverting terminal B of the comparator 204.

[0100] Fig. 7A FIG. 8 is a schematic circuit diagram of a tracking amplifier 700 according to another exemplary embodiment. The amplifier circuit 700 can be considered as Figure 6 A more detailed implementation of amplifier circuit 600 is shown in FIG. Figure 6 The buffer circuit 206 in FIG. 2 (which is optional) is shown as including two inverter stages that perform level shifting of the output signal of the comparator 204 at the terminal C. The push-pull stage 208 is implemented by a simple inverter stage. In other embodiments, the push-pull stage 208 may be implemented using multiple cascaded inverters.

[0101] The inverter stage is formed by a pair of transistors 212, 214, which in this example are n-type transistors (e.g., NPN) and p-type transistors (e.g., PNP). Transistors 212, 214 are connected in series between reference potentials 220A and 220B. The drain terminals of transistors 212, 214 are connected to each other and to output terminal D. The emitter terminals of transistors 212, 214 are connected to reference potentials 220A and 220B, respectively. The gate terminals of transistors 212, 214 are connected to terminal C providing the output signal of comparator 204 via buffer circuit 206 as described above. In some embodiments, transistors 212, 214 can be small signal transistors or small switching transistors, which can be implemented as bipolar junction transistors (BJT) (e.g., NPN transistors and PNP transistors), for example. However, field effect transistors (FETs), such as junction FETs (JFETs) or metal oxide semiconductor FETs (MOSFETs), can also be used. In principle, the transistors 212 and 214 may also be implemented using other switching elements (for example, using power transistors).

[0102] In addition, transistors 212, 214 are shown as different types (p-type and n-type, respectively), and are therefore driven by the same control signal corresponding to the output signal at node C of comparator 204. However, if the control signal corresponding to the output signal at node C of comparator 204 applied to the gate terminal of one of transistors 212, 214 is inverted (e.g., in an inverter), then both transistors 212, 214 can be implemented using the same transistor type. The control signal to the other gate terminal can be used "as is", or if the phase difference between the inverted control signal and the non-inverted control signal is critical to the correct operation of the amplifier stage 240, a delay element can be added to compensate for the phase difference between the inverted control signal and the non-inverted control signal. In other embodiments and application scenarios, the push-pull stage 208 can be replaced by a single transistor, the source terminal of which is connected to the reference potential 220A or 220B, and the gate terminal receives the control signal from node C. In this case, the drain terminal can be connected to the output node D.

[0103] and Figure 1 2, the input signal at the input terminal A of the comparator 204 is compared with the feedback signal at the terminal B of the comparator 204 which is based on the time-continuous output signal of the amplifier circuit 700 at the node D. Depending on the two input signals of the comparator 204, a "digital" signal with a high level or a low level is generated at the output terminal C of the comparator 204. The generated digital signal can be amplified in the buffer circuit 206 (if present) and used in turn to control the push-pull inverter stage 208 by driving the gate terminals of the transistors 212, 214. A PWM sequence is generated at the output terminal D of the amplifier 700. In order to connect the inductive load 210 (impedance L load and line resistance R load ) current into a time-continuous voltage, including resistor 626 (resistance R convert ) is connected in series with the load 210. The resistor 626 converts the current through the inductive load 210 into a time-continuous voltage signal at the terminal E relative to the reference potential. The resistor 626 is connected between the output terminal of the inductive load 210 and the reference potential. The voltage at the terminal E is provided to the voltage divider 216. The exemplary voltage divider 216 is formed by two resistors 216 (Rdiv1) and 230 (Rdiv2), and the center tap of the voltage divider between the two resistors 216, 230 is connected to the inverting terminal B of the comparator 204, thereby completing the control loop. The voltage divider 216 can also be implemented using two capacitors. The ratio of the resistances of the resistors 626, 216 and 230 can be set, controlled or designed to achieve the desired amplification gain of the amplifier circuit.

[0104] Fig. 7AThe main advantage of the exemplary amplifier 700 in FIG. 7 is that it is easy to implement. However, the line resistance R of the load 210 load and the conversion resistance R of resistor 626 convert This additional voltage divider limits the maximum current through the load branch and also requires a higher output voltage at node D compared to the exemplary implementation where the inductive load 210 is directly connected to the reference potential in order to compensate for the resistor 626 (R convert ) additional voltage drop across the load inductor. It should also be noted that the load inductor 210A (L load ) The time-varying charge and discharge constants are controlled by the resistance R of resistor 626. convert The larger resistance R of resistor 626 convert To reduce the time constant, the smaller the resistance R of resistor 626 convert The time constant is increased. The impedance of the voltage divider 216 in the feedback path can again be chosen to be very high, minimizing the power flowing into the feedback stage. This enables very high energy efficiency of the amplifier 600, 700.

[0105] Figure 7B FIG. 7 is a schematic circuit diagram of a tracking amplifier 750 according to another exemplary embodiment. The amplifier circuit 750 can be considered as Figure 6 A more detailed implementation of the amplifier circuit 600 is shown in FIG. The tracking amplifier 750 is substantially similar to Fig. 7A Tracking amplifier 700. Fig. 7A and Figure 7B The main difference between the two embodiments in is the connection of the feedback stage 650 to the inductive load at the output of the amplifier. Figure 7B In the embodiment of FIG. 1 , the inductive load is formed by two load components 210 and 710 connected in series between the output terminal D and the reference potential. The two components 210 and 710 may have an impedance L shown as two inductors 210A and 210A. load , and the line resistance R formed by the resistive elements 210B and 210B load For example, the two inductors 210A and 210A may be implemented as coils with symmetrical center taps. Advantageously, the impedance of the load component 210A is L load / 2, and the impedance of the load component 210A is also L load / 2. The line resistance of the resistor component 210B is R load / 2, the line resistance of the resistor component 210B is also R load / 2. Of course, any other asymmetrical taps or combinations of two separate inductors 210A, 210A and / or resistors 210B and 210B may be implemented. Fig. 7A In the implementation, resistor 626 (resistance Rconvert ) is used in parallel with a lower inductance. Resistor R convert A usable time-continuous voltage is generated from the current on the output side and provided to the voltage divider 216 . Figure 7B The main advantage of the exemplary amplifier 750 in is again the ease of implementation. Fig. 7A Compared to the embodiment of FIG. 1 , the additional voltage divider at the output of amplifier 750 is now composed of resistor 210B (with R load / 2, compared to R in amplifier 700 load ) and resistor 626, which changes the voltage division at the center tap connected to terminal E. This reduces the maximum current through the load branch and also requires a higher output voltage at node D compared to the exemplary implementation where the inductive load 210 is directly connected to the reference potential in order to compensate for the voltage division at the center tap connected to terminal E via resistor 626 (R convert ) additional current path. Although the resistance R of resistor 626 convert 210A, ... convert impact.

[0106] exist Fig. 7A and Figure 7B In the two exemplary embodiments shown in , the discharge of the output current at terminal D can be through an inductive load. Therefore, in an alternative implementation, the inverter stage 208 can be replaced with a transistor (e.g., only transistor 212, and "eliminating" transistor 214, or vice versa), the drain terminal of which is connected to the output terminal D.

[0107] Fig. 8AA schematic circuit implementation of a tracking amplifier 800 according to an embodiment of the present invention is shown. The amplifier circuit 800 includes an amplifier stage 240 and a feedback stage 850. The amplifier stage 240 includes a comparator 204 having a non-inverting terminal A and an inverting terminal B as input terminals. An input signal 202 is provided to the input terminal A. The input signal 202 can be a time-continuous voltage signal. When the amplifier circuit 800 is used to drive a sound pressure generating device (e.g., in a headphone, an in-ear device, etc.), the input signal 202 can be an audio signal or a sound signal that is used to drive (multiple) actuators of the sound pressure generating device to generate a desired sound pressure in an audible and / or non-audible frequency range of a spectrum.

[0108] The comparator 204 compares the signals (i.e., voltages / potentials) applied to its input terminals A and B, and provides a signal at its output terminal C that is either high or low indicating the result of the comparison. The output signal of the comparator 204 is provided to the buffer circuit 206. The buffer circuit 206 is optional and may not be present. The buffer circuit 206 may, for example, include one or more buffer circuits, which may, for example, be used to perform a level shift of the output signal at the output terminal C to adjust the signal level (e.g., voltage / potential) and / or signal current to a desired range for driving the push-pull stage 208. The push-pull stage 208 is used to amplify the output signal of the comparator 204 (as processed by the optional buffer circuit 206) and provide the output signal of the amplifier 800 at the output terminal D.

[0109] The push-pull stage 208 generates a PWM signal relative to reference potentials 220A and 220B and in response to the output signal of the comparator 204, which is used as a control signal for the push-pull stage 208. The reference potential 220B is exemplarily shown as ground (GND). The reference potentials 220A and 220B may also be referred to as VDD and VSS, respectively. The reference potentials 220A and 220B may be adjustable, programmable, or controllable.

[0110] The output signal provided by the amplifier circuit 800 at the output terminal D may be a PWM voltage signal that causes a time-continuous current signal to flow into or from the node D to the amplifier circuit 800. The output signal of the amplifier circuit 800 at the terminal D is applied to the inductive load 210, which for example purposes is represented by the inductor 210A (L load ) and resistor 210B (R load ) modeling.

[0111] The output signal of amplifier circuit 800 at terminal D is applied to feedback stage 850. Fig. 8AIn the exemplary embodiment of the present invention, the feedback stage 850 includes a current mirror 860, a resistor 880, and a voltage divider 216. The current mirror 860 is connected to the resistor 880 and the inductive load 210. The current mirror 860 mirrors the load current flowing from the node D to the reference potential through the inductive load 210 and the first path 862 of the current mirror 860 to the second path 864 of the current mirror 860. Therefore, the mirrored time-continuous current signal flowing in the second path 864 is proportional to the load current flowing from the node D through the inductive load 210 and the first path 862 of the current mirror 860. Since the impedance of the voltage divider 216 is much higher than the impedance of the second path 864 of the current mirror 860, the current flowing through the resistor 880 will be substantially the same as the mirrored current signal in the second path 864 of the current mirror 860. The output terminal of resistor 880 connected to node E (i.e., the terminal of resistor 880 not connected to node D) provides a time-continuous voltage equivalent to the time-continuous current signal of the mirror image through resistor 880 to voltage divider 216. The other terminal of resistor 880 is connected to output node D. Therefore, resistor 880 converts the time-continuous current signal of the mirror image to flow into node D or to flow from node D into amplifier circuit 800 into a time-continuous voltage signal. The mirror image time-continuous voltage signal from resistor 880 is provided at node E and applied to voltage divider 216. Voltage divider 216 adjusts the mirror image time-continuous voltage signal provided at node E to an appropriate voltage level to be applied to inverting terminal B of comparator 204.

[0112] Figure 8B FIG. 8 is a schematic circuit diagram of a tracking amplifier 800 ′ according to another exemplary embodiment. The amplifier circuit 800 ′ can be considered as Fig. 8A A more detailed implementation of amplifier circuit 800 is shown. Figure 8B The buffer circuit 206 in FIG. 2 (which is optional) is shown as including two inverter stages that perform level shifting of the output signal of the comparator 204 at the terminal C. The push-pull stage 208 is implemented by a simple inverter stage. In other embodiments, the push-pull stage 208 may be implemented using multiple cascaded inverters.

[0113] The inverter stage is formed by a pair of transistors 212, 214, which are n-type transistors (e.g., NPN) and p-type transistors (e.g., PNP) in this example. Transistors 212, 214 are connected in series between reference potentials 220A and 220B. The drain terminals of transistors 212, 214 are connected to each other and to output terminal D. The emitter terminals of transistors 212, 214 are connected to reference potentials 220A and 220B, respectively. The gate terminals of transistors 212, 214 are connected to terminal C providing the output signal of comparator 204 via buffer circuit 206 as described above. In some embodiments, transistors 212, 214 can be small signal transistors or small switching transistors, which can be implemented as bipolar junction transistors (BJT) (e.g., NPN transistors and PNP transistors), for example. However, field effect transistors (FETs) can also be used, such as junction FETs (JFETs) or metal oxide semiconductor FETs (MOSFETs). In principle, transistors 212, 214 can also be implemented using other switching elements (e.g., using power transistors).

[0114] In addition, transistors 212, 214 are shown as different types (p-type and n-type, respectively), and are therefore driven by the same control signal corresponding to the output signal at node C of comparator 204. However, if the control signal corresponding to the output signal at node C of comparator 204 applied to the gate terminal of one of transistors 212, 214 is inverted (e.g., in an inverter), then both transistors 212, 214 can be implemented using the same transistor type. The control signal to the other gate terminal can be used "as is", or if the phase difference between the inverted control signal and the non-inverted control signal is critical to the correct operation of the amplifier stage 240, a delay element can be added to compensate for the phase difference between the inverted control signal and the non-inverted control signal. In other embodiments and application scenarios, the push-pull stage 208 can be replaced by a single transistor, the source terminal of which is connected to the reference potential 220A or 220B, and the gate terminal receives the control signal from node C. In this case, the drain terminal can be connected to the output node D.

[0115] and Figure 1800 ', the input signal at the input terminal A of the comparator 204 is compared with the feedback signal at the terminal B of the comparator 204 based on the time-continuous output signal of the amplifier circuit 900 at the node D. Depending on the two input signals of the comparator 204, a "digital" signal with a high level or a low level is generated at the output terminal C of the comparator 204. The generated digital signal can be amplified in the buffer circuit 206 (if present) and used in turn to control the push-pull inverter stage 208 by driving the gate terminals of the transistors 212 and 214. A PWM sequence is generated at the output terminal D of the amplifier 800 '. In order to pass the inductive load 210 (impedance L load and line resistance R load ) is converted into a time-continuous voltage, providing a resistor 880, while controlling the current through the resistor 880 using a current mirror 860. The resistor 880 is connected to the output node D at one end and to the terminal E at the other end, which is also connected to the second path 864 of the current mirror 860. The inductive load 210 is connected to the first path 862 of the current mirror 860, the first path 862 is connected in series with the load branch, and controls the current flowing in the second path 864 of the current mirror 860. The first path 862 is formed by a pair of transistors 870, 872. The drain terminal and the gate terminal of the transistor 870 are both connected to the inductive load 210. The drain terminal and the gate terminal of the transistor 872 are both connected to the source terminal of the transistor 870. The source terminal of the transistor 872 is connected to the reference potential. The second path 864 is formed by a pair of transistors 874, 876. The drain terminal of the transistor 874 is connected to the resistor 880 at the node E. The gate terminal of transistor 874 is connected to the inductive load 210, and is therefore connected to the gate of transistor 870. The drain terminal of transistor 876 is connected to the source terminal of transistor 874. The gate terminal of transistor 876 is connected to the source terminal of transistor 870, and is therefore connected to the gate of transistor 872. The source terminal of transistor 876 is connected to a reference potential. In one exemplary implementation, transistors 870, 872, 874, and 876 are n-type transistors. In addition, or alternatively, transistors 870, 872, 874, and 876 can all have the same parameters (e.g., the same channel length and / or the same channel thickness) so that they behave the same.

[0116] Although shown as a single transistor, each of transistors 870, 872, 874, and 876 may be implemented by multiple transistors connected in parallel, similar to the embodiments explained below. Fig.13860 (see transistors 702 and 704). Therefore, by appropriately configuring the amount of current that can be conducted in the first path 862 and the second path 864 of the current mirror 860 (e.g., by selecting an appropriate number of parallel transistors in each path and / or the parameters of the transistors in each path), the current mirrored from the first path 862 to the second path 864 can be much lower than the current in the first path 862. For higher energy efficiency of the amplifier design, the mirrored current signal in the second path 864 of the current mirror 860 (through transistors 874, 876) should be 1 / many times (e.g., 1 / N) the output current of the first path 862 flowing through the load 210 and the current mirror 860. In order to compensate for the mirror ratio 1 / N of the control loop, the resistance R of the resistor 880 is convert The resistance R may be equal to the line resistance 210B of the inductive load 210 load The product of N (i.e. the inverse of the mirror ratio 1 / N).

[0117] The exemplary voltage divider 216 is formed by two resistors 216 (Rdiv1) and 230 (Rdiv2), and the center tap of the voltage divider between the two resistors 216, 230 is connected to the inverting terminal B of the comparator 204, thereby completing the control loop. The voltage divider 216 can also be implemented using two capacitors. The ratio of the resistances of the resistors 216 and 230 can be set, controlled or designed to achieve the desired amplification gain of the amplifier circuit 800, 800'.

[0118] As previously mentioned, the impedance of the feedback branch 850 can be very high, so that the power flowing into the feedback stage 850 is minimized. This allows for very high energy efficiency of the amplifier 800, 800'. It is worth noting that the line resistance R of the load 210 load Another voltage divider is formed with the transistors 870, 872 of the first path 862 of the current mirror 860. This additional voltage divider limits the maximum current through the load branch and also requires a higher output voltage at node D compared to the exemplary implementation where the inductive load 210 is directly connected to the reference potential in order to compensate for the additional voltage drop at the transistors 870, 872 of the first path 862. It should also be noted that the load inductance 210A (L load )The time-varying charge and discharge constants are also affected by the current mirror 860.

[0119] Fig. 9A FIG. 2 shows a schematic circuit implementation of a tracking amplifier 900 according to another embodiment of the present invention. Fig. 8A In the example of FIG. 8 , the amplifier circuit 900 includes the amplifier stage 240 and the feedback stage 850. Fig. 9A In the exemplary embodiment of FIG. 8 , the feedback stage 850 includes a current mirror 960, a resistor 980, and a voltage divider 216. Fig. 8AUnlike the embodiment in FIG. 2 , the current mirror 960 is connected between the output node D on one side and the resistor 980 and the inductive load 210 on the other side. The current mirror 960 mirrors the load current flowing from the node D through the inductive load 210 and the first path 962 of the current mirror 960 / the load current flowing to the node D through the inductive load 210 and the first path 962 of the current mirror 960 to the second path 964 of the current mirror 960 / the load current flowing to the node D through the inductive load 210 and the first path 962 of the current mirror 960 to the second path 964 of the current mirror 960. Therefore, the mirrored time-continuous current signal in the second path 964 is proportional to the load current flowing from the node D through the first path 962 of the current mirror 960. Since the impedance of the voltage divider 216 is much higher than the impedance of the second path 964 of the current mirror 960, the current flowing through the resistor 980 will be substantially the same as the mirrored current signal in the second path 964 of the current mirror 960. The input terminal of resistor 980 connected to node E provides a time-continuous voltage to the voltage divider 216 that is (substantially) equivalent to the time-continuous current signal of the mirror image through resistor 980. The other terminal of transistor 980 is connected to the reference potential. Therefore, resistor 980 converts the time-continuous current signal of the mirror image to flow into node D or to flow from node D into amplifier circuit 800 into a time-continuous voltage signal. The mirror image time-continuous voltage signal from resistor 980 is provided at node E and applied to voltage divider 216. Voltage divider 216 adjusts the mirror image time-continuous voltage signal provided at node E to an appropriate voltage level to be applied to the inverting terminal B of comparator 204.

[0120] Fig. 9B FIG. 2 shows a schematic circuit diagram of a tracking amplifier 900 ′ according to another exemplary embodiment. The amplifier circuit 900 ′ can be considered as Fig. 9A In an exemplary implementation, the amplifier stage 240 of the amplifier circuit 900' can be combined with the above Figure 8B The amplifier stage 240 of the amplifier circuit 800' discussed above is the same. Fig. 9A Note that the current mirror 960 of the feedback stage 850 is connected between the output node D and the resistor 980 and the inductive load 210. The resistor 980 is used to separate the current flowing through the inductive load 210 (impedance L load and line resistance R load) is converted into a time-continuous mirror current signal proportional to the time-continuous current signal of the current mirror 960. The current signal through the resistor 980 is thus controlled by the current mirror 960. The resistor 980 is connected to the node E at one end and to the reference voltage at the other end thereof. The terminal of the resistor 980 connected to the node E is also connected to the second path 964 of the current mirror 960. The inductive load 210 is connected to the first path 962 of the current mirror 960, which is connected in series with the load branch and controls the current flowing into the second path 964 of the current mirror 960. The first path 962 of the current mirror 960 is formed by a pair of transistors 970, 972. The source terminal of the transistor 970 is connected to the node D. The drain terminal of the transistor 970 is connected to the gate terminal of the transistor 970 and the source terminal of the transistor 972. The drain terminal of the transistor 972 is connected to the gate terminal of the transistor 972 and the inductive load 210. The second path 964 is formed by a pair of transistors 974, 976. The source terminal of transistor 974 is connected to the output node D of amplifier 900'. The gate terminal of transistor 974 is connected to the gate of transistor 970 (and therefore also to its drain terminal). The source terminal of transistor 976 is connected to the drain terminal of transistor 974. The gate terminal of transistor 976 is connected to the gate terminal of transistor 972 (and therefore also to its drain terminal). The drain terminal of transistor 976 is connected to resistor 980 at node E. In one exemplary implementation, transistors 970, 972, 974 and 976 are p-type transistors. In addition, or alternatively, transistors 970, 972, 974 and 976 can all have the same parameters (e.g., the same channel length and / or the same channel thickness) so that they behave the same.

[0121] Although shown as a single transistor, each of transistors 970, 972, 974, and 976 may be implemented by multiple transistors connected in parallel, similar to the embodiments explained below. Fig.13 960 (see transistors 702 and 704). Therefore, by appropriately configuring the amount of current that can be conducted in the first path 962 and the second path 964 of the current mirror 960 (e.g., by selecting an appropriate number of parallel transistors in each path and / or the parameters of the transistors in each path), the current mirrored from the first path 962 to the second path 964 can be much lower than the current in the first path 962. For higher energy efficiency of the amplifier design, the mirrored current signal in the second path 964 of the current mirror 960 (through transistors 974, 976) should be 1 / many times (e.g., 1 / N) the output current flowing through the load 210 and the first path 962 of the current mirror 960. In order to compensate for the mirror ratio 1 / N of the control loop, the resistance R of the resistor 980 is convert The resistance R may be equal to the line resistance 210B of the inductive load 210load The product of N (i.e. the inverse of the mirror ratio 1 / N).

[0122] The exemplary voltage divider 216 is formed by two resistors 216 (Rdiv1) and 230 (Rdiv2), and the center tap of the voltage divider between the two resistors 216, 230 is connected to the inverting terminal B of the comparator 204, thereby completing the control loop. The voltage divider 216 can also be implemented using two capacitors. The ratio of the resistances of the resistors 216 and 230 can be set, controlled or designed to achieve the desired amplification gain of the amplifier circuit 900, 900'.

[0123] As previously mentioned, the impedance of the feedback branch 850 can be very high, minimizing the power flowing into the feedback stage 850. This allows for very high energy efficiency of the amplifiers 900, 900'. It is worth noting that the line resistance R of the load 210 load Another voltage divider is formed with the transistors 970, 972 of the first path 962 of the current mirror 960. This additional voltage divider limits the maximum current through the load branch and also requires a higher output voltage at the node D compared to the exemplary implementation where the inductive load 210 is directly connected to the reference potential in order to compensate for the additional voltage drop at the transistors 970, 972 of the first path 962. It should also be noted that the load inductance 210A (L load )The time-varying charge and discharge constants are also affected by the current mirror 960.

[0124] exist Figure 8B and Fig. 9B In the two exemplary embodiments shown in , the discharge of the output current at terminal D can be through an inductive load. Therefore, in an alternative implementation, the inverter stage 208 can be replaced by a transistor (e.g., only transistor 212, and "eliminating" transistor 214, or vice versa), the drain terminal of which is connected to the output terminal D.

[0125] Fig.10 and Fig.11 Shown as Figure 3 , Figure 5 , Fig. 7A , Figure 7B , Figure 8B and Fig. 9B 1002, 1004, 1006, 1008, and 1010 in any of the amplifier circuits 300, 500, 700, 750, 800', 900' shown in FIG. Fig.11 enlarge Fig.10 The left side of the mark V1 around Fig.10In the example shown, the input signal 202, 1002 is a 20kHz sine wave at input terminal A with a DC offset of 100mV and an amplitude of 100mV. The amplification factor is set to 2 by the voltage divider 216, so the maximum voltage at E must be twice as high as at the input terminal B of the comparator 204, i.e. 400mV. The signal waveform at node E is Fig.10 In the figure, it is indicated by reference numeral 2021002 and in Fig.11 The pulse train at the output node D is represented by 1104. Fig.10 is shown by reference numeral 1010, and in Fig.11 In the figure, it is shown by the reference numeral 1110.

[0126] exist Figure 2 and Figure 3 In the embodiment of the present invention, the pulse train at the node D is integrated in the load inductance 210A of the load 210, thereby generating a time-continuous target current (see Fig.10 Reference numerals 1006 and Fig.11 1106 in the figure) and is integrated in the low pass filters 224, 226 to generate a feedback voltage at the node E.

[0127] exist Figure 4 and Figure 5 In the embodiment of the present invention, the pulse train at the node D is integrated in the load inductance 210A of the load 210 to generate a time-continuous target current (see Fig.10 Reference numerals 1006 and Fig.11 1106 in the figure) and is integrated in the feedback network 422 to generate a feedback voltage at the node E.

[0128] exist Figure 6 , Fig. 7A and Figure 7B In the embodiment of the present invention, the pulse train at the node D is integrated in the load inductance 210A of the load 210 to generate a time-continuous target current (see Fig.10 Reference numerals 1006 and Fig.11 , and resistor 626 generates a corresponding feedback voltage at node E.

[0129] exist Figures 2 to 6 , Fig. 7A and Figure 7B In the embodiment, the line resistance R of the load inductor 210B of 16Ω paired with the voltage of 400mV at the node E loadAt the same time when the input side voltage signal 202 at node A reaches its maximum value, a desired maximum output current of 25 mA is given at node D (the output current at node D is Fig.10 In the figure, it is indicated by reference numeral 1006 and in Fig.11 Reference numerals 1008 and 1108 denote PWM voltage signals generated by the comparator 204 at its output node C, which alternate between 0.0V and 1.8V in the example shown.

[0130] exist Fig. 8A , Figure 8B , Fig. 9A and Fig. 9B In the embodiment of the present invention, the pulse train at the node D is integrated in the load inductance 210A of the load 210 to generate a time-continuous target current (see Fig.10 Reference numerals 1006 and Fig.11 1106 in the figure). This time-continuous current is mirrored by current mirror 860 at a given ratio, thereby generating a corresponding mirror current flowing through resistor 880. This mirror current signal is converted by resistor 880 into a time-continuous voltage signal provided at the feedback voltage of node E. In this example, resistor 880 generates a voltage of 400mV at node E, giving a desired maximum output current of 25mA at node D at the same time as the input side voltage signal 202 at node A reaches its maximum value (the output current at node D is Fig.10 In the figure, 1006 is used to represent Fig.11 Reference numerals 1008 and 1108 denote PWM voltage signals generated by the comparator 204 at its output node C, which alternate between 0.0V and 1.8V in the example shown.

[0131] and Figure 1 In contrast to the capacitive load shown in , the discharge current may flow through the load inductance. Therefore, the (n-type) transistor 214 is optional, ie, the inverter stage 208 may instead be implemented using only the (p-type) transistor 212, as described above.

[0132] To further improve the tracking capability of the amplifier circuit, it would be advantageous to provide improved control of the current sourced toward or sunk from the load 210. Figures 2 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A9C, the "on-off" nature of the push-pull stage 208 of the switching amplifier, therefore, by reducing the current driven by the push-pull output transistors 212, 214, the inductive ripple at the output node D can be reduced at small signal amplitudes. This process can be adjusted according to the desired output signal amplitude.

[0133] Fig.12 , Fig.13 and Fig.14 shows different embodiments of the present invention. Figures 2 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and further exemplary modifications to the output stage of the amplifier in FIG. 9C , which allow for increased dynamic drive strength of the overall amplifier design.

[0134] Fig.12 Shown for Figures 2 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A 9C . The push-pull transistor 212 is connected to the reference potential 220A via the bias transistor 1202 that controls the current flowing to the output terminal D of the inverter stage 208 through the push-pull transistor 212. The source of the transistor 212 is connected to the drain of the transistor 1202. The source of the transistor 1202 is connected to the reference potential 220A. The transistors 212 and 1202 can be, for example, p-type transistors. Similarly, the push-pull transistor 214 is connected to the second reference potential 220B via another bias transistor 1204 that controls the current flowing to the output terminal D of the inverter stage 208 through the push-pull transistor 214. The source of the transistor 214 is connected to the drain of the transistor 1204. The source of the transistor 1204 is connected to the second reference potential 220B (which can be, for example, ground (GND)). The transistors 214 and 1204 can be, for example, n-type transistors. Transistors 212 and 214 act as switches and are driven by the output signal of comparator 204 at node C, which passes through buffer 206, which is implemented as an inverter.

[0135] The control signal from node C is also forwarded to two integrator circuits. Each of the integrator circuits is formed by an inverter 1206, 1210 and a buffer capacitor 1208, 1212 to generate bias signals P2_bias and N2_bias that are applied to the gate terminals of bias transistors 1202 and 1204. The bias signals are analog (and not digital signals) so that transistors 1202 and 1204 act as voltage-dependent resistors that limit the current that can flow to or sink from the output node D. The key idea for this simple implementation of dynamic drive strength is to utilize the comparator output signal provided at node C for switching on and off, and further for increasing or decreasing the corresponding bias signal, and therefore the output current.

[0136] If the potential at node C is logically high, the potential at output terminal D should be increased. At the same time, bias signal P2_bias will decrease according to the corresponding time constant and thus reduce the effective resistance of p-type transistor 1202, which increases the current that can be sourced. If the potential at node C is logically low, the potential at output node D should be reduced. At the same time, bias signal N2_bias will increase according to the corresponding time constant and thus reduce the effective resistance of n-type transistor 1204, which increases the current that can be sunk.

[0137] Because the signal at node C is pulse width modulated, the bias signal will vary depending on the pulse width generated. Therefore, the drive strength of the output stage is also controlled by the comparator 204 linked to the feedback loop at the output node D.

[0138] Fig.13 Shown in order to Figures 2 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and a second modification of the output stage used in one of the amplifiers of FIG. 9C, the second modification being combined with Fig.12The first modification described is somewhat similar. The push-pull transistor 212 is connected to the reference potential 220A via a plurality of bias transistors 1302 connected in parallel, which control the current flowing through the push-pull transistor 212 to the output terminal D of the inverter stage 208. The source of the transistor 212 is connected to the drain terminal of the transistor 1302. The source terminal of the transistor 1302 is connected to the reference potential 220A. The transistors 212 and 1302 can be, for example, p-type transistors. Similarly, the push-pull transistor 214 is connected to the second reference potential 220B via another plurality of bias transistors 1304 connected in parallel, which control the current flowing through the push-pull transistor 214 to the output terminal D of the inverter stage 208. The source of the transistor 214 is connected to the drain terminal of the transistor 1304. The source terminal of the transistor 1304 is connected to the second reference potential 220B (which can be, for example, ground (GND)). The transistors 214 and 1304 can be, for example, n-type transistors. Transistors 212 and 214 act as switches and are driven by the output signal of comparator 204 at node C, which passes through buffer 206, which is implemented as an inverter.

[0139] exist Fig.13 , the PWM signal at node C is further processed in bias control circuit 1306 and bias control circuit 1308. These circuit blocks 1306 and 1308 can be implemented, for example, in digital logic, such as a counter or switch matrix that uses control signals C1 and C2 to selectively enable or disable the functions of a certain number of parallel bias transistors 1302 and 1304, respectively. Depending on the number of enabled / disabled transistors 1302, 1304, the resistance of the bias transistors 1302, 1304 connected in parallel can be changed so that the bias transistors 1302, 1304 behave like Fig.12 The bias transistors 1202 and 1204 in FIG. Fig.12 Instead, each of the bias transistors 1302, 1304 behaves like a switch that is activated or deactivated (turned on and off) according to a control signal applied to the respective gate terminal of the bias transistor 1302, 1304. The transistors 1302, 1304 may not all have the same gate width and / or gate length, and the control logic 1306, 1308 does not have to sequentially switch the bias transistors 1302 or 1304 one by one. The number of activated "switches" 1302 or 1304 can also be selected in a binary / exponential manner according to the processing of the output signal of the comparator 204 at the node C.

[0140] Fig.14 Shown for Figures 2 to 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Fig. 9A and a third modification of the output stage in one of the amplifiers of FIG. 9C. Fig.12 and Fig.13 different, Fig.14 The modification in does not use additional bias transistors in addition to the push-pull transistors 212, 214. Instead, similar to Fig.12 The two integrator circuits shown in FIG. 1 are used to provide an upper variable supply rail (at node var_vdd) and a lower variable supply rail (var_vss) for output transistors 212 and 214. Fig.12 Similarly, the integrator circuit providing the upper variable supply rail (at the node var_vdd) is formed by an inverter circuit 1402 connected to two reference potentials 1406 and 1408 between which the upper variable supply rail at the node var_vdd can vary. The output current of the inverter 1402 charges the buffer capacitor 1404 to provide the variable upper supply rail voltage at the node var_vdd to the source terminal of the push-pull transistor 212. Similarly, the integrator circuit providing the lower variable supply rail at the node var_vss is formed by an inverter circuit 1410 connected to two reference potentials 1414 and 1416 between which the lower variable supply rail at the node var_vss can vary. The reference potential 1414 can be higher than the reference potential 1416. Reference potential 1416 may be the lowest potential of reference potentials 1406, 1408, 1414, and 1416, while reference potential 1406 may be the highest potential. The output current of inverter 1410 charges buffer capacitor 1412 to provide a variable low supply rail voltage to the source terminal of push-pull transistor 214 at node var_vss.

[0141] If the potential at node C is logically high, the potential on output node D should be reduced. If the potential at node C is high, p-type push-pull transistor 212 is disabled and n-type push-pull transistor 214 is enabled, so that only the potential difference between output terminal D and the lower supply rail at node var_vss is relevant. With a high potential at node C, the energy stored in capacitor 1412 can be discharged to the lowest reference potential 1416 that reduces the potential at node var_vss. This causes the potential difference between output node D and node var_vss to change, which is equivalent to a change in the output resistance that sinks current from node D as described above. This current will flow from output node D through capacitor 1412 at node var_vss and through the NFET of inverter 1410 to reference potential 1416. Depending on the on-resistance of the NFET of inverter 1410, the on-resistance of push-pull transistor 214 and the charge stored on capacitor 1412, the current generated from output node D will flow and change over time.

[0142] If the potential at node C is logically low, the potential at output node D should be increased. If the potential at node C is low, n-type push-pull transistor 214 is disabled and p-type push-pull transistor 212 is enabled, so that output node D is related to the potential difference between the upper supply rails at node var_vdd. At the low potential at node C, the energy stored in capacitor 1404 at node var_vdd can charge to the highest reference potential 1406, which increases the potential at node var_vdd. This causes the potential difference between output node D and node var_vdd to change, which is equivalent to a change in the output resistance that provides current toward output node D as described above. This current will flow from the PFET of inverter 1402 through capacitor 1404 at node var_vdd and flow to output node D through push-pull transistor 212. Depending on the on-resistance of this PFET of the inverter 1402, the on-resistance of the push-pull transistor 212 and the charge already stored at the capacitor 1404, the resulting current will flow to the output node D and will vary with time.

[0143] It is worth noting that Fig.12 and Fig.13 compared to, Fig.14 The potential at node C has the exact opposite effect on the current. Because the digital signal is provided at node C as a PWM pulse train, the logic behind it can be inverted at any point in the signal chain. In addition, the inputs to terminals A and B of comparator 204 can be swapped to invert the PWM signal at node C. When using a comparator with outputs B and The fully differential comparator is used and at the output Output A can be used if the signal at Output B is an inverted / 180° shifted version of the signal at Output B. The signal at node C is provided by the signal at node C.

Claims

1. An amplifier circuit for connecting to an inductive load, the amplifier circuit comprising: Amplification stage, including: A comparator, wherein the comparator has a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal and the inverting input terminal are configured to receive a signal to be amplified and a feedback signal, and generate a comparator output signal by comparing the signal to be amplified and the feedback signal, and output the comparator output signal at an output terminal of the comparator; and an inverter stage configured to generate a pulse width modulated signal in response to the comparator output signal and to output the pulse width modulated signal as a time continuous current signal at an output terminal of the inverter stage, the output terminal of the inverter stage also being an output terminal of the amplifier circuit; A feedback stage, wherein the feedback stage comprises: a feedback filter coupled in parallel to the inductive load and directly to the output terminal of the inverter stage to receive the time-continuous current signal and convert the time-continuous current signal into a time-continuous voltage signal; and A voltage divider receives the time-continuous voltage signal at its input and is coupled to a reference potential at its output, wherein the voltage divider is configured to provide the time-continuous voltage signal of a reduced voltage level as the feedback signal to the comparator.

2. The amplifier circuit according to claim 1, wherein: The signal to be amplified is received at a non-inverting input terminal of the comparator, and the feedback signal is received at the inverting input terminal of the comparator.

3. The amplifier circuit according to claim 1 or 2, wherein: The feedback filter is a low pass filter.

4. The amplifier circuit according to claim 2, wherein: The impedance of the feedback filter is higher than the impedance of the inductive load to minimize the power flowing into the feedback filter.

5. The amplifier circuit according to one of claims 1 to 4, wherein: The voltage divider includes a first resistor and a second resistor connected in series, wherein the first resistor has one terminal coupled to the output of the feedback filter to receive a time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second resistor has one terminal coupled to the other terminal of the first resistor and another terminal coupled to the reference potential.

6. Amplifier circuit according to one of claims 1 to 4, wherein The voltage divider includes a first capacitor and a second capacitor connected in series, wherein the first capacitor has one terminal coupled to the output of the feedback filter to receive a time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second capacitor has one terminal coupled to the other terminal of the first capacitor and another terminal coupled to the reference potential.

7. Amplifier circuit according to one of claims 1 to 6, wherein: The signal to be amplified has a voltage level relative to the reference potential.

8. Amplifier circuit according to one of claims 1 to 7, wherein: The amplifier stage further includes one or more buffer circuits connected in series between the output terminal of the comparator and an input terminal of the inverter stage.

9. The amplifier circuit according to claim 8, wherein: The one or more buffer circuits are configured to perform a level shift of the comparator output signal and provide the level shifted comparator output signal to the input terminal of the inverter stage.

10. The amplifier circuit according to claim 9, wherein: The one or more buffer circuits are configured to amplify a drive strength of a signal applied to the input terminal of the inverter stage.

11. The amplifier circuit according to one of claims 1 to 10, wherein: The inverter stage comprises at least one pair of push-pull transistors connected in series and forming a push-pull configuration.

12. The amplifier circuit according to claim 11, wherein: A first push-pull transistor of the pair of push-pull transistors is a p-type transistor, and another second push-pull transistor of the pair of push-pull transistors is an n-type transistor.

13. The amplifier circuit according to claim 11 or 12, wherein: A first push-pull transistor of the pair of push-pull transistors is connected to a first reference potential, and another second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential different from the first reference potential.

14. The amplifier circuit of claim 13, further comprising: a first bias control circuit configured to integrate the comparator output signal and provide the integrated comparator output signal as a first reference signal to a source terminal of the first push-pull transistor; as well as The second bias control circuit is configured to integrate the comparator output signal and provide the integrated comparator output signal as a second reference signal to a source terminal of the second push-pull transistor.

15. The amplifier circuit according to claim 11 or 12, wherein: a first push-pull transistor of the pair of push-pull transistors being connected to a first reference potential via one or more first biasing transistors, the one or more first biasing transistors being configured to control a current flowing through the first push-pull transistor to the output terminal of the inverter stage, and wherein the other second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential via one or more further second biasing transistors, the one or more second biasing transistors being configured to control a current flowing through the second push-pull transistor to the output terminal of the inverter stage.

16. The amplifier circuit according to claim 15, wherein: The one or more first bias transistors and the one or more second bias transistors form a variable resistance.

17. The amplifier circuit according to one of claims 15 or 16, further comprising: a first bias control circuit configured to apply a bias signal to one or more gate terminals of the one or more first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage; as well as A second bias control circuit is configured to apply a bias signal to one or more gate terminals of the one or more second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the second push-pull transistor to the output terminal of the inverter stage.

18. The amplifier circuit according to claim 17, wherein: The first bias control circuit and the second bias control circuit are configured to integrate the comparator output signal and provide the integrated comparator output signal as the bias signal to the gate terminals of the one or more first bias transistors and the one or more second bias transistors, respectively.

19. The amplifier circuit according to claim 17, wherein: the first bias control circuit being configured to selectively activate and deactivate a selected number of the first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistors to the output terminal of the inverter stage; as well as A second bias control circuit is configured to selectively activate and deactivate a selected number of the second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage.

20. The amplifier circuit of claim 19, wherein: The first bias control circuit and the second bias control circuit are implemented as counters or switch matrices to selectively activate or deactivate the selected number of bias transistors.

21. The amplifier circuit according to claim 14 or 18, wherein: Each of the first bias control circuit and the second bias control circuit includes an inverter circuit connected between two DC voltage references and a buffer capacitor connected between an output terminal of the inverter circuit and one of the DC voltage references.

22. Amplifier circuit according to one of claims 1 to 21, wherein The inverter stage includes a plurality of cascaded inverters.

23. An amplifier circuit for connection to an inductive load, the amplifier circuit comprising: Amplification stage, including: A comparator, wherein the comparator has a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal and the inverting input terminal are configured to receive a signal to be amplified and a feedback signal, and generate a comparator output signal by comparing the signal to be amplified and the feedback signal, and output the comparator output signal at an output terminal of the comparator; and an inverter stage configured to generate a pulse width modulated signal in response to the comparator output signal and to output the pulse width modulated signal as a time continuous current signal at an output terminal of the inverter stage, the output terminal of the inverter stage also being an output terminal of the amplifier circuit; A feedback stage, wherein the feedback stage comprises: a resistor connected in series with the inductive load, wherein the resistor converts the time-continuous current signal flowing through the inductive load into a time-continuous voltage signal; A voltage divider receives the time-continuous voltage signal at its input and is coupled to a reference potential at its output, wherein the voltage divider is configured to provide the time-continuous voltage signal of a reduced voltage level as the feedback signal to the comparator.

24. The amplifier circuit of claim 23, wherein: The resistor of the feedback stage has a first terminal connected to the inductive load and another second terminal connected to a reference potential, and the input of the voltage divider is connected to the first terminal.

25. The amplifier circuit of claim 24, wherein: A second inductive load is connected in series with the inductive load and in parallel with the resistor of the feedback stage.

26. An amplifier circuit according to claim 24 or 25, wherein: The voltage divider includes a first resistor and a second resistor connected in series, wherein the first resistor has one terminal coupled to the first terminal of the resistor of the feedback stage to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second resistor has one terminal coupled to the other terminal of the first resistor and another terminal coupled to the reference potential.

27. An amplifier circuit according to claim 24 or 25, wherein: The voltage divider includes a first capacitor and a second capacitor connected in series, wherein the first capacitor has one terminal coupled to the first terminal of the resistor of the feedback stage to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second capacitor has one terminal coupled to the other terminal of the first capacitor and another terminal coupled to the reference potential.

28. Amplifier circuit according to one of claims 23 to 27, wherein The inductive load and the resistor of the feedback stage form a second voltage divider.

29. The amplifier circuit according to one of claims 23 to 28, wherein The signal to be amplified is received at a non-inverting input terminal of the comparator, and the feedback signal is received at the inverting input terminal of the comparator.

30. The amplifier circuit according to one of claims 23 to 29, wherein The signal to be amplified has a voltage level relative to the reference potential.

31. An amplifier circuit according to one of claims 23 to 30, wherein The amplifier stage further includes one or more buffer circuits connected in series between the output terminal of the comparator and an input terminal of the inverter stage.

32. The amplifier circuit of claim 31 , wherein: The one or more buffer circuits are configured to perform a level shift of the comparator output signal and provide the level shifted comparator output signal to the input terminal of the inverter stage.

33. The amplifier circuit of claim 32, wherein: The one or more buffer circuits are configured to amplify a drive strength of a signal applied to the input terminal of the inverter stage.

34. Amplifier circuit according to one of claims 23 to 33, wherein: The inverter stage comprises at least one pair of push-pull transistors connected in series and forming a push-pull configuration.

35. The amplifier circuit of claim 34, wherein: A first push-pull transistor of the pair of push-pull transistors is a p-type transistor, and another second push-pull transistor of the pair of push-pull transistors is an n-type transistor.

36. An amplifier circuit according to claim 34 or 35, wherein: A first push-pull transistor of the pair of push-pull transistors is connected to a first reference potential, and another second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential different from the first reference potential.

37. The amplifier circuit of claim 36, further comprising: a first bias control circuit configured to integrate the comparator output signal and provide the integrated comparator output signal as a first reference signal to a source terminal of the first push-pull transistor; as well as The second bias control circuit is configured to integrate the comparator output signal and provide the integrated comparator output signal as a second reference signal to a source terminal of the second push-pull transistor.

38. An amplifier circuit according to claim 34 or 35, wherein: a first push-pull transistor of the pair of push-pull transistors being connected to a first reference potential via one or more first biasing transistors, the one or more first biasing transistors being configured to control a current flowing through the first push-pull transistor to the output terminal of the inverter stage, and wherein the other second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential via one or more further second biasing transistors, the one or more second biasing transistors being configured to control a current flowing through the second push-pull transistor to the output terminal of the inverter stage.

39. The amplifier circuit of claim 38, wherein: The one or more first bias transistors and the one or more second bias transistors form a variable resistance.

40. The amplifier circuit of claim 38 or 39, further comprising: a first bias control circuit configured to apply a bias signal to one or more gate terminals of the one or more first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage; as well as A second bias control circuit is configured to apply a bias signal to one or more gate terminals of the one or more second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the second push-pull transistor to the output terminal of the inverter stage.

41. The amplifier circuit of claim 40, wherein: The first bias control circuit and the second bias control circuit are configured to integrate the comparator output signal and provide the integrated comparator output signal as the bias signal to the gate terminals of the one or more first bias transistors and the one or more second bias transistors, respectively.

42. The amplifier circuit of claim 40, wherein: the first bias control circuit being configured to selectively activate and deactivate a selected number of the first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistors to the output terminal of the inverter stage; as well as A second bias control circuit is configured to selectively activate and deactivate a selected number of the second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage.

43. An amplifier circuit according to claim 42, wherein: The first bias control circuit and the second bias control circuit are implemented as counters or switch matrices to selectively activate or deactivate the selected number of bias transistors.

44. An amplifier circuit according to claim 37 or claim 41, wherein: Each of the first bias control circuit and the second bias control circuit includes an inverter circuit connected between two DC voltage references and a buffer capacitor connected between an output terminal of the inverter circuit and one of the DC voltage references.

45. An amplifier circuit according to one of claims 23 to 44, wherein The inverter stage includes a plurality of cascaded inverters.

46. ​​An amplifier circuit for connection to an inductive load, the amplifier circuit comprising: Amplification stage, including: A comparator, wherein the comparator has a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal and the inverting input terminal are configured to receive a signal to be amplified and a feedback signal, and generate a comparator output signal by comparing the signal to be amplified and the feedback signal, and output the comparator output signal at an output terminal of the comparator; and an inverter stage configured to generate a pulse width modulated signal in response to the comparator output signal and to output the pulse width modulated signal as a time continuous current signal to flow through the inductive load at an output terminal of the inverter stage, the output terminal of the inverter stage also being an output terminal of the amplifier circuit; A feedback stage, wherein the feedback stage comprises: a current mirror having a first path and a second path, the time-continuous current signal flowing through the first path, wherein the current mirror is configured to cause a mirrored time-continuous current signal to flow through the second path of the current mirror, the mirrored time-continuous current signal corresponding to the time-continuous current signal flowing through the first path; a resistor having one terminal connected to the second path of the current mirror and another terminal connected to the output terminal of the amplifier circuit or a reference potential, wherein the resistor is configured to convert the mirrored time-continuous current signal flowing through the second path of the current mirror into a time-continuous voltage signal; and A voltage divider receives the time-continuous voltage signal at its input and is coupled to the reference potential at its output, wherein the voltage divider is configured to provide the time-continuous voltage signal of a reduced voltage level as the feedback signal to the comparator.

47. An amplifier circuit according to claim 46, wherein the first terminal of the resistor of the feedback stage being connected to the output terminal of the inverter stage, and the second terminal of the resistor being connected to the input terminal of the voltage divider and the second path of the current mirror; as well as The second path of the current mirror is connected between the second terminal of the resistor and a reference potential, and the first path of the current mirror is connected between the inductive load and the reference potential.

48. An amplifier circuit according to claim 47, wherein The current mirror is implemented using n-type transistors.

49. The amplifier circuit of claim 46, wherein: a first terminal of the resistor of the feedback stage connected to a reference potential and a second terminal of the resistor connected to the input terminal of the voltage divider and the second path of the current mirror; as well as The second path of the current mirror is connected between the output terminal of the inverter stage and the second terminal of the resistor, and the first path of the current mirror is connected between the output terminal of the inverter stage and the inductive load.

50. The amplifier circuit of claim 49, wherein: The current mirror is implemented using p-type transistors.

51. An amplifier circuit according to one of claims 46 to 50, wherein The mirrored time-continuous current signal flowing through the second path of the current mirror is proportional to the time-continuous current signal flowing through the first path of the current mirror and is smaller than the time-continuous current signal flowing through the first path of the current mirror.

52. The amplifier circuit of claim 51 , wherein: The mirrored time-continuous current signal flowing through the second path of the current mirror is 1 / N of the time-continuous current signal flowing through the first path of the current mirror.

53. The amplifier circuit of claim 52, wherein: The resistance of the resistor of the feedback stage is N times the resistance of the inductive load.

54. An amplifier circuit according to one of claims 46 to 53, wherein the first path of the current mirror comprises a first number of first transistors connected in parallel to each other and receiving the time-continuous current signal flowing through the inductive load at gate terminals thereof, and the first number of second transistors connected in parallel to each other and connected in series with the first transistor, wherein gate terminals of the second transistors receive the current flowing through the first transistor; and The second path of the current mirror comprises a second number of third transistors connected in parallel with each other and having their gate terminals coupled to the gate terminal of the first transistor, and a second number of fourth transistors connected in parallel with each other and in series with the third transistors, wherein the gate terminal of the fourth transistor is coupled to the gate terminal of the second transistor.

55. The amplifier circuit of claim 54, wherein: The first number is N times the second number.

56. An amplifier circuit according to one of claims 46 to 55, wherein The signal to be amplified is received at a non-inverting input terminal of the comparator, and the feedback signal is received at the inverting input terminal of the comparator.

57. An amplifier circuit according to one of claims 46 to 56, wherein The voltage divider includes a first resistor and a second resistor connected in series, wherein the first resistor has one terminal coupled to the output of the feedback filter to receive a time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second resistor has one terminal coupled to the other terminal of the first resistor and another terminal coupled to the reference potential.

58. An amplifier circuit according to one of claims 46 to 56, wherein The voltage divider includes a first capacitor and a second capacitor connected in series, wherein the first capacitor has one terminal coupled to the output of the feedback filter to receive a time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second capacitor has one terminal coupled to the other terminal of the first capacitor and another terminal coupled to the reference potential.

59. An amplifier circuit according to one of claims 46 to 58, wherein The signal to be amplified has a voltage level relative to the reference potential.

60. An amplifier circuit according to one of claims 46 to 59, wherein The amplifier stage further includes one or more buffer circuits connected in series between the output terminal of the comparator and an input terminal of the inverter stage.

61. The amplifier circuit of claim 60, wherein: The one or more buffer circuits are configured to perform a level shift of the comparator output signal and provide the level shifted comparator output signal to the input terminal of the inverter stage.

62. An amplifier circuit according to claim 61, wherein The one or more buffer circuits are configured to amplify a drive strength of a signal applied to the input terminal of the inverter stage.

63. An amplifier circuit according to one of claims 46 to 62, wherein: The inverter stage comprises at least one pair of push-pull transistors connected in series and forming a push-pull configuration.

64. An amplifier circuit according to claim 63, wherein A first push-pull transistor of the pair of push-pull transistors is a p-type transistor, and another second push-pull transistor of the pair of push-pull transistors is an n-type transistor.

65. An amplifier circuit according to claim 63 or 64, wherein A first push-pull transistor of the pair of push-pull transistors is connected to a first reference potential, and another second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential different from the first reference potential.

66. The amplifier circuit of claim 65, further comprising: a first bias control circuit configured to integrate the comparator output signal and provide the integrated comparator output signal as a first reference signal to a source terminal of the first push-pull transistor; as well as The second bias control circuit is configured to integrate the comparator output signal and provide the integrated comparator output signal as a second reference signal to a source terminal of the second push-pull transistor.

67. An amplifier circuit according to claim 63 or 64, wherein a first push-pull transistor of the pair of push-pull transistors being connected to a first reference potential via one or more first biasing transistors, the one or more first biasing transistors being configured to control a current flowing through the first push-pull transistor to the output terminal of the inverter stage, and wherein the other second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential via one or more further second biasing transistors, the one or more second biasing transistors being configured to control a current flowing through the second push-pull transistor to the output terminal of the inverter stage.

68. An amplifier circuit according to claim 67, wherein The one or more first bias transistors and the one or more second bias transistors form a variable resistance.

69. An amplifier circuit according to claim 67 or 68, further comprising: a first bias control circuit configured to apply a bias signal to one or more gate terminals of the one or more first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage; as well as A second bias control circuit is configured to apply a bias signal to one or more gate terminals of the one or more second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the second push-pull transistor to the output terminal of the inverter stage.

70. The amplifier circuit of claim 69, wherein: The first bias control circuit and the second bias control circuit are configured to integrate the comparator output signal and provide the integrated comparator output signal as the bias signal to the gate terminals of the one or more first bias transistors and the one or more second bias transistors, respectively.

71. The amplifier circuit of claim 69, wherein: the first bias control circuit being configured to selectively activate and deactivate a selected number of the first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistors to the output terminal of the inverter stage; as well as A second bias control circuit is configured to selectively activate and deactivate a selected number of the second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage.

72. The amplifier circuit of claim 71 , wherein: The first bias control circuit and the second bias control circuit are implemented as counters or switch matrices to selectively activate or deactivate the selected number of bias transistors.

73. An amplifier circuit according to claim 66 or claim 69, wherein: Each of the first bias control circuit and the second bias control circuit includes an inverter circuit connected between two DC voltage references and a buffer capacitor connected between an output terminal of the inverter circuit and one of the DC voltage references.

74. An amplifier circuit according to one of claims 46 to 73, wherein The inverter stage includes a plurality of cascaded inverters.

75. An amplifier circuit for connection to an inductive load, the amplifier circuit comprising: Amplification stage, including: A comparator, wherein the comparator has a non-inverting input terminal and an inverting input terminal, the non-inverting input terminal and the inverting input terminal are configured to receive a signal to be amplified and a feedback signal, and generate a comparator output signal by comparing the signal to be amplified and the feedback signal, and output the comparator output signal at an output terminal of the comparator; and an inverter stage configured to generate a pulse width modulated signal in response to the comparator output signal and to output the pulse width modulated signal as a time continuous current signal at an output terminal of the inverter stage, the output terminal of the inverter stage also being an output terminal of the amplifier circuit; A feedback stage, wherein the feedback stage comprises: an inductor and a resistor connected in parallel, the inductor being magnetically coupled to the inductive load to receive the time-continuous current signal through the inductive load, and The resistor is configured to convert the received time-continuous current signal into a time-continuous voltage signal; A voltage divider receives the time-continuous voltage signal at its input and is coupled to a reference potential at its output, wherein the voltage divider is configured to provide the time-continuous voltage signal of a reduced voltage level as the feedback signal to the comparator.

76. The amplifier circuit of claim 75, wherein: The inductor of the feedback stage and the resistor are connected in parallel to the inductive load.

77. An amplifier circuit according to claim 75 or 76, wherein One terminal of each of the resistor and the inductor of the feedback stage is connected to the same reference potential and one terminal of the inductive load.

78. An amplifier circuit according to one of claims 75 to 77, wherein The signal to be amplified is received at a non-inverting input terminal of the comparator, and the feedback signal is received at the inverting input terminal of the comparator.

79. An amplifier circuit according to one of claims 75 to 78, wherein The voltage divider includes a first resistor and a second resistor connected in series, wherein the first resistor has one terminal coupled to the resistor of the feedback stage to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second resistor has one terminal coupled to the other terminal of the first resistor and another terminal coupled to the reference potential.

80. An amplifier circuit according to one of claims 75 to 78, wherein The voltage divider includes a first capacitor and a second capacitor connected in series, wherein the first capacitor has one terminal coupled to the resistor of the feedback stage to receive the time-continuous voltage signal and another terminal coupled to one of the input terminals of the comparator to provide the feedback signal; and The second capacitor has one terminal coupled to the other terminal of the first capacitor and another terminal coupled to the reference potential.

81. An amplifier circuit according to one of claims 75 to 80, wherein: The signal to be amplified has a voltage level relative to the reference potential.

82. An amplifier circuit according to one of claims 75 to 81, wherein The amplifier stage further includes one or more buffer circuits connected in series between the output terminal of the comparator and an input terminal of the inverter stage.

83. The amplifier circuit of claim 82, wherein: The one or more buffer circuits are configured to perform a level shift of the comparator output signal and provide the level shifted comparator output signal to the input terminal of the inverter stage.

84. The amplifier circuit of claim 83, wherein: The one or more buffer circuits are configured to amplify a drive strength of a signal applied to the input terminal of the inverter stage.

85. An amplifier circuit according to one of claims 75 to 84, wherein The inverter stage comprises at least one pair of push-pull transistors connected in series and forming a push-pull configuration.

86. The amplifier circuit of claim 85, wherein: A first push-pull transistor of the pair of push-pull transistors is a p-type transistor, and another second push-pull transistor of the pair of push-pull transistors is an n-type transistor.

87. An amplifier circuit according to claim 85 or 86, wherein A first push-pull transistor of the pair of push-pull transistors is connected to a first reference potential, and another second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential different from the first reference potential.

88. The amplifier circuit of claim 87, further comprising: a first bias control circuit configured to integrate the comparator output signal and provide the integrated comparator output signal as a first reference signal to a source terminal of the first push-pull transistor; as well as The second bias control circuit is configured to integrate the comparator output signal and provide the integrated comparator output signal as a second reference signal to a source terminal of the second push-pull transistor.

89. An amplifier circuit according to claim 85 or 86, in, a first push-pull transistor of the pair of push-pull transistors being connected to a first reference potential via one or more first biasing transistors, the one or more first biasing transistors being configured to control a current flowing through the first push-pull transistor to the output terminal of the inverter stage, and wherein the other second push-pull transistor of the pair of push-pull transistors is connected to a second reference potential via one or more further second biasing transistors, the one or more second biasing transistors being configured to control a current flowing through the second push-pull transistor to the output terminal of the inverter stage.

90. The amplifier circuit of claim 89, wherein: The one or more first bias transistors and the one or more second bias transistors form a variable resistance.

91. An amplifier circuit according to claim 89 or 90, further comprising: a first bias control circuit configured to apply a bias signal to one or more gate terminals of the one or more first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage; as well as A second bias control circuit is configured to apply a bias signal to one or more gate terminals of the one or more second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the second push-pull transistor to the output terminal of the inverter stage.

92. The amplifier circuit of claim 91, wherein: The first bias control circuit and the second bias control circuit are configured to integrate the comparator output signal and provide the integrated comparator output signal as the bias signal to the gate terminals of the one or more first bias transistors and the one or more second bias transistors, respectively.

93. The amplifier circuit of claim 91, wherein: the first bias control circuit being configured to selectively activate and deactivate a selected number of the first bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistors to the output terminal of the inverter stage; as well as A second bias control circuit is configured to selectively activate and deactivate a selected number of the second bias transistors in response to the comparator output signal, thereby controlling the current flowing through the first push-pull transistor to the output terminal of the inverter stage.

94. An amplifier circuit according to claim 93, wherein: The first bias control circuit and the second bias control circuit are implemented as counters or switch matrices to selectively activate or deactivate the selected number of bias transistors.

95. An amplifier circuit according to claim 88 or 91, wherein: Each of the first bias control circuit and the second bias control circuit includes an inverter circuit connected between two DC voltage references and a buffer capacitor connected between an output terminal of the inverter circuit and one of the DC voltage references.

96. An amplifier circuit according to one of claims 75 to 95, wherein: The inverter stage includes a plurality of cascaded inverters.

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