Buffer circuit and imaging device

Abstract

Provided is a snubber circuit capable of achieving a wide dynamic range while maintaining a low output impedance and capable of achieving a reduction in area and a reduction in power consumption. The snubber circuit includes a first transistor, a current source, a second transistor, an output terminal, and first and second capacitors. The first transistor has a gate that receives an input signal input. The current source is connected to one terminal of the first transistor. The second transistor is connected to the other terminal of the first transistor. The output terminal is connected to the one terminal or the other terminal of the first transistor. The first capacitor and the second capacitor are disposed between the current source and a gate of the second transistor. The first transistor, the second transistor, and the first capacitor form a first feedback circuit. The first transistor, the current source, and the second capacitor form a second feedback circuit.

Description

Technical Field

[0001] A technology according to the present disclosure (the present technology) relates to a buffer circuit and an image pickup device including the buffer circuit. Background Art

[0002] In an image pickup device, a pixel signal read from a pixel is generally converted from an analog signal to a digital signal by a column analog-to-digital converter, and signal processing is performed by a digital signal processor (DSP). For the column analog-to-digital converter, a ramp signal source follower circuit is used. For the ramp signal source follower circuit, a buffer circuit that is beneficial to various characteristic improvements is desired. Therefore, as a buffer circuit that can achieve low output impedance, a flip voltage follower circuit (hereinafter, referred to as an FVF circuit) is known.

[0003] However, since the FVF circuit can only operate within a limited voltage range, there is a problem that the circuits that can be applied are also limited. For example, applying the FVF circuit to a ramp signal source follower circuit is expected to bring about various characteristic improvements. However, due to the specifications of the camera device, the ramp signal source follower circuit is required to have a wide dynamic range, so the FVF circuit cannot be applied.

[0004] The buffer circuit described in Patent Document 1 is a buffer circuit of a multi-stage structure using a common source amplifier circuit. Therefore, the structure is complicated, resulting in an increase in circuit area and an increase in power consumption.

[0005] Citation list

[0006] Patent Literature

[0007] Patent Document 1: WO2006 / 132315 Summary of the invention

[0008] Technical Problems to be Solved by the Invention

[0009] For some time, there has been a strong demand for a buffer circuit that can achieve a wide dynamic range and also achieve reduced area and reduced power consumption.

[0010] The present disclosure has been made in view of such circumstances, and an object of the present disclosure is to provide a buffer circuit and an image pickup device capable of achieving a wide dynamic range while maintaining low output impedance and capable of achieving area reduction and power consumption reduction.

[0011] Solutions to technical problems

[0012] One aspect of the present disclosure is a buffer circuit, including: a first transistor having a gate to which an input signal is input; a current source connected to one terminal of the first transistor; a second transistor connected to the other terminal of the first transistor; an output terminal connected to the one terminal or the other terminal of the first transistor; and a first capacitor and a second capacitor, which are arranged between the current source and the gate of the second transistor, the first transistor, the second transistor and the first capacitor forming a first feedback circuit, and the first transistor, the current source and the second capacitor forming a second feedback circuit.

[0013] Another aspect of the present disclosure is an imaging device, comprising: a pixel array unit including a plurality of pixels capable of generating pixel signals according to light incident from the outside; a buffer circuit; a signal processing unit, which compares an output signal of the buffer circuit with a pixel signal output from each of the plurality of pixels and generates image data based on the comparison result; and a power supply circuit, which supplies power required for the operation of each of the pixel array unit, the buffer circuit and the signal processing unit, the buffer circuit comprising: a first transistor having a gate to which an input signal is input; a current source connected to one terminal of the first transistor; a second transistor connected to another terminal of the first transistor; an output terminal connected to the one terminal or the other terminal of the first transistor; and a first capacitor and a second capacitor, which are arranged between the current source and the gate of the second transistor, the first transistor, the second transistor and the first capacitor forming a first feedback circuit, and the first transistor, the current source and the second capacitor forming a second feedback circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a block diagram showing an example of a schematic configuration of an image pickup device according to a first embodiment of the present disclosure.

[0015] Figure 2 is a block diagram for explaining an example of an image signal reading mechanism in the image pickup device according to the first embodiment of the present disclosure.

[0016] Figure 3 is a circuit diagram (Part 1) showing the configuration of a ramp signal buffer circuit according to a first embodiment of the present disclosure.

[0017] Figure 4 is a circuit diagram (Part 2) showing the configuration of the ramp signal buffer circuit according to the first embodiment of the present disclosure.

[0018] Figure 5: is a graph for showing a change in the voltage Vfb between the first capacitor and the second capacitor in a case where the second feedback circuit is not formed.

[0019] Figure 6 : is a graph for showing a change in the voltage Vfb between the first capacitor and the second capacitor in the case where the second feedback circuit is formed.

[0020] Figure 7 is a circuit diagram showing a configuration of a ramp signal buffer circuit according to a second embodiment of the present disclosure.

[0021] Figure 8 is a circuit diagram showing the configuration of a power supply circuit and a ramp signal buffer circuit according to a third embodiment of the present disclosure.

[0022] Fig. 9 is a circuit diagram showing a configuration of a ramp signal buffer circuit according to a fourth embodiment of the present disclosure.

[0023] Fig.10 is a circuit diagram showing a configuration of a ramp signal buffer circuit according to a fifth embodiment of the present disclosure.

[0024] Fig.11 is a circuit diagram showing a configuration of a ramp signal buffer circuit according to a sixth embodiment of the present disclosure.

[0025] Fig.12 is a circuit diagram showing a configuration of a ramp signal buffer circuit according to a seventh embodiment of the present disclosure.

[0026] Fig.13 is a circuit diagram showing a configuration of a ramp signal buffer circuit according to an eighth embodiment of the present disclosure.

[0027] Fig.14 : is a block diagram showing a configuration example of an imaging system as an electronic device to which the present technology is applied. DETAILED DESCRIPTION

[0028] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the description of the drawings referred to in the following description, the same or similar parts are represented by the same or similar reference numerals to avoid redundant description.

[0029] Note that the effects described in this specification are merely examples and are not limiting, and other effects may be provided.

[0030] <First embodiment>

[0031] (Overall Structure of Camera Device)

[0032] Figure 11 is a block diagram showing an example of a schematic configuration of an image pickup device according to a first embodiment of the present disclosure. The image pickup device 1 is a semiconductor device that converts the amount of charge corresponding to the intensity of light formed as an image on each pixel into an electric signal using a photoelectric conversion element such as a photodiode constituting each pixel and outputs the electric signal as image data, and the image pickup device 1 is configured as, for example, a CMOS image sensor. The image pickup device 1 can be integrally configured as, for example, a system on a chip (SoC) such as a CMOS LSI, but, for example, some components described below can be configured as separate LSIs.

[0033] As shown in the figure, the imaging device 1 includes components such as a pixel array unit 11 , a vertical driving unit 12 , a column processing unit 13 , a horizontal driving unit 14 , a system control unit 15 , a signal processing unit 16 , and a data storage unit 17 , for example.

[0034] The pixel array unit 11 includes a photoelectric conversion element group such as a photodiode that forms pixels 110 arranged in the horizontal direction (row direction) and the vertical direction (column direction). The pixel array unit 11 converts the amount of charge corresponding to the intensity of incident light formed as an image on each pixel 110 into an electric signal, and outputs the electric signal as a pixel signal.

[0035] The vertical driving unit 12 includes a shift register, an address decoder, etc. The vertical driving unit 12 supplies a driving signal and the like to each pixel 110 via a plurality of pixel driving lines 18 , thereby driving each pixel 110 of the pixel array unit 11 , for example, simultaneously or row by row.

[0036] The column processing unit 13 reads pixel signals from each pixel via the vertical signal line (VSL) 19 for each pixel column of the pixel array unit 11, and performs noise removal processing, correlated double sampling (CDS) processing, analog-to-digital (A / D) conversion processing, etc. The pixel signals processed by the column processing unit 13 are output to the signal processing unit 16.

[0037] The horizontal driving unit 14 includes a shift register, an address decoder, etc. The horizontal driving unit 14 sequentially selects the pixels 110 corresponding to the pixel columns of the column processing unit 13. When the selective scanning is performed by the horizontal driving unit 14 in this way, the pixel signals of the pixels 110 in the column processing unit 13 that have undergone signal processing are sequentially output to the signal processing unit 16.

[0038] The system control unit 15 includes a timing generator that generates various timing signals, etc. The system control unit 15 performs drive control of the vertical drive unit 12, the column processing unit 13, and the horizontal drive unit 14 based on the timing signals generated by the timing generator not shown in the figure, for example.

[0039] The signal processing unit 16 performs signal processing such as arithmetic processing on the pixel signals supplied from the column processing unit 13 while temporarily storing the data in the data storage unit 17 as necessary, and outputs an image signal based on each pixel signal.

[0040] Note that the image pickup device 1 to which the present technology is applied is not limited to the above-described configuration. For example, the image pickup device 1 may be configured such that the data storage unit 17 is arranged at the next stage of the column processing unit 13, and the pixel signal output from the column processing unit 13 is supplied to the signal processing unit 16 via the data storage unit 17. Alternatively, the image pickup device 1 may be configured such that the column processing unit 13, the data storage unit 17, and the signal processing unit 16 connected in cascade process the respective pixel signals in parallel.

[0041] Figure 2 1 is a block diagram for explaining an example of an image signal reading mechanism in the image pickup device according to the first embodiment of the present disclosure. In this figure, a pixel signal reading mechanism 20 from one pixel 110 in one pixel column is exemplarily shown.

[0042] The diagram shows a ramp signal buffer circuit 131 , a ramp signal generating circuit 132 , and an analog-to-digital converter (hereinafter, referred to as an AD converter) 133 as a configuration of the column processing unit 13 .

[0043] The ramp signal generating circuit 132 generates and outputs a ramp signal required for AD conversion processing by the AD converter 133. The ramp signal is, for example, a signal whose voltage level changes with time. The ramp signal buffer circuit 131 performs impedance conversion processing on the ramp signal output from the ramp signal generating circuit 132.

[0044] The AD converter 133 converts the pixel signal in an analog format output from the pixel 110 into a pixel signal (pixel data) in a digital format. The AD converter 133 is provided in parallel for each vertical signal line 19 corresponding to the pixel column. In addition, the AD converter 133 includes a comparator 134 and a counter 135. That is, the AD converter 133 counts through the counter 135 while comparing the ramp signal output from the ramp signal buffer circuit 131 with the pixel signal read from the pixel 110 over time through the comparator 134, and outputs the count value as a pixel signal in a digital format to the signal processing unit 16.

[0045] <Structure of Ramp Signal Buffer Circuit>

[0046] Figure 3 and Figure 4 is a circuit diagram showing the configuration of the ramp signal buffer circuit 131 according to the first embodiment of the present disclosure. Figure 3is a circuit diagram showing the configuration of the ramp signal buffer circuit 131 in the reset mode, and Figure 4 is a circuit diagram showing the configuration of the ramp signal buffer circuit 131 in the normal drive mode (AD mode).

[0047] like Figure 3 As shown, the ramp signal buffer circuit 131 includes an input control unit 141, an output control unit 142, a current source 143, an input terminal 144, an output terminal 145, a first capacitor (C1) 146, a second capacitor (C2) 147, a first switch unit 151, a second switch unit 152, a third switch unit 153, a fourth switch unit 154, a first voltage applying unit 161 and a second voltage applying unit 162.

[0048] The input control unit 141, the output control unit 142, and the current source 143 include, for example, P-type metal oxide semiconductor (MOS) transistors. The input terminal 144 is connected to the gate of the MOS transistor constituting the input control unit 141. The input terminal 144 allows the ramp signal output from the ramp signal generating circuit 132 to be input to the gate of the input control unit 141. In the case where the voltage of the ramp signal is higher than or equal to the threshold voltage Vth1 between the gate and the drain of the MOS transistor constituting the input control unit 141, the input control unit 141 enters a conductive state (on state). In contrast, in the case where the voltage of the ramp signal is lower than the threshold voltage Vth1 between the gate and the drain of the MOS transistor constituting the input control unit 141, the input control unit 141 enters a non-conductive state (off state).

[0049] The drain of the MOS transistor constituting the output control unit 142 and the output terminal 145 are connected to the source of the input control unit 141. In addition, the drain of the MOS transistor constituting the current source 143 is connected to the drain of the input control unit 141. The input control unit 141 inputs the ramp signal output from the ramp signal generating circuit 132 to the AD converter 133 by electrically connecting the input terminal 144 and the output terminal 145.

[0050] The first capacitor 146 and the second capacitor 147 are connected in series between the gate of the output control unit 142 and the gate of the current source 143. The input control unit 141, the output control unit 142 and the first capacitor 146 form a first feedback circuit FB1. The input control unit 141, the current source 143 and the second capacitor 147 form a second feedback circuit FB2.

[0051] The source of the output control unit 142 is connected to the power supply. The ramp signal input to the input terminal 144 is input to the gate of the output control unit 142 via the drain of the input control unit 141 and the first capacitor 146 as an alternating current (AC) voltage of the ramp signal. The output control unit 142 amplifies the output current flowing through the output terminal 145.

[0052] The first switch unit 151 connects or disconnects the connection between the gate of the output control unit 142 and the output terminal 145. The second switch unit 152 connects or disconnects the connection between the drain of the input control unit 141 and the first capacitor 146 and the second capacitor 147. The third switch unit 153 connects or disconnects the connection between the first voltage applying unit 161 and the first feedback circuit FB1. The fourth switch unit 154 connects or disconnects the connection between the second voltage applying unit 162 and the second feedback circuit FB2.

[0053] exist Figure 3 In the reset mode shown, the first switch unit 151, the third switch unit 153, and the fourth switch unit 154 are turned on, and the second switch unit 152 is turned off. That is, by turning on the first switch unit 151, the output control unit 142 becomes diode-connected, and the gate of the output control unit 142 is charged with the voltage Vy. By turning on the third switch unit 153, the voltage Vfb between the first capacitor 146 and the second capacitor 147 is charged to the externally applied voltage Vext from the first voltage applying unit 161. By turning on the fourth switch unit 154, the voltage Vz applied to the gate of the current source 143 is charged to the externally applied voltage Vbias from the second voltage applying unit 162.

[0054] exist Figure 4 In the driving mode shown, the first switch unit 151, the third switch unit 153 and the fourth switch unit 154 are turned off, and the second switch unit 152 is turned on. That is, by turning on the second switch unit 152, the signal is fed back from the drain of the input control unit 141 to the gate of the output control unit 142, and the difference between the voltages Vx and Vext is fed back from the drain of the input control unit 141 to the gate of the current source 143.

[0055] As a result, the input dynamic range Vin is expressed as follows:

[0056] Vx-|Vth1| <Vin<Vy+|Vth2|-Vsg1

[0057] Therefore, the larger the difference between Vx and Vy is, the wider the range is. Note that Vsg1 is a voltage between the gate and the source of the MOS transistor constituting the input control unit 141 .

[0058] (Reason 1 for requiring current source FB)

[0059] Here, the reason why feedback to the current source 143 is required will be described.

[0060] Assume that Q1 and Q2 represent the charges accumulated in the first capacitor 146 and the second capacitor 147 in the reset mode Φ1, and assume that Q'1 and Q'2 represent the charges accumulated in the first capacitor 146 and the second capacitor 147 in the drive mode Φ2. Assuming that the charge conservation law applies to Q1 and Q2 as well as Q'1 and Q'2 (in reality, since a small amount of charge escapes from Vx, an error will occur), the following equation holds:

[0061] Q1+Q2=Q'1+Q'2

[0062] C1(Vext-Vy)+C2(Vext-Vbias)=C1(Vx-Vy)+C2(Vx-Vz)

[0063] Vz=Vbias+K(Vx-Vext)

[0064] K=(C1+C2) / C2

[0065] Here, if (Vx-Vext) is an error voltage, negative feedback (feedback) acts to set the error voltage to 0, so that (Vx-Vext) converges to 0. As a result, Vx converges to Vext, and Vz converges to Vbias.

[0066] To sum up, the following two points can be drawn.

[0067] By applying negative feedback, the drain voltage Vx of the input control unit 141 can be determined by the externally applied voltage Vext. In addition, the final error of the gate voltage Vz of the current source 143 is small.

[0068] (Reason 2 for requiring current source FB)

[0069] Figure 5 FIG. 1 shows a change in the voltage Vfb between the first capacitor 146 and the second capacitor 147 when the second feedback circuit FB2 is not formed.

[0070] In the reset mode Φ1, the second switch unit 152 is turned off, and the third switch unit 153 is turned on, so that the voltage Vfb between the first capacitor 146 and the second capacitor 147 is charged to the external applied voltage Vext. In the drive mode Φ2, the second switch unit 152 is turned on, and the third switch unit 153 is turned off. As a result, when the voltage Vfb charged to the applied voltage Vext is short-circuited with the drain voltage Vx of the input control unit 141, the voltage Vfb becomes a voltage close to the drain voltage Vx of the input control unit 141. This is because the potential is pulled to the side with lower impedance.

[0071] Figure 6 FIG. 1 shows a change in the voltage Vfb between the first capacitor 146 and the second capacitor 147 in the case where the second feedback circuit FB2 is formed.

[0072] In the reset mode Φ1, the second switch unit 152 is turned off, and the third switch unit 153 is turned on, so that the voltage Vfb between the first capacitor 146 and the second capacitor 147 is charged to the external applied voltage Vext. In the driving mode Φ2, the second switch unit 152 is turned on, and the third switch unit 153 is turned off. As a result, in the case where the voltage Vfb charged to the applied voltage Vext is short-circuited with the drain voltage Vx of the input control unit 141, the voltage Vfb is momentarily pulled by the drain voltage Vx of the input control unit 141. However, since negative feedback works, the voltage Vfb eventually converges to the applied voltage Vext.

[0073] <Functions and Effects of the First Embodiment>

[0074] As described above, according to the first embodiment, the first capacitor 146 is inserted in the first feedback circuit FB1, and the second capacitor 147 is inserted in the second feedback circuit FB2, so that only the AC voltage is fed back to the gate of the output control unit 142. This makes it possible to prevent the drain of the input control unit 141 and the gate of the output control unit 142 from being at the same potential in a DC manner, and to ensure a wide dynamic range while maintaining a low output impedance.

[0075] In addition, according to the first embodiment, by using the externally applied voltage Vext from the first voltage applying unit 161 and the externally applied voltage Vbias from the second voltage applying unit 162 , a sufficiently wide dynamic range can be ensured for the application.

[0076] <Second Implementation Method>

[0077] Figure 7 is a circuit diagram showing the configuration of a ramp signal buffer circuit 131A according to a second embodiment of the present disclosure. Figure 7 In the above Figure 3and Figure 4 The same components are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0078] In the second embodiment of the present disclosure, the input control unit 311 includes, for example, an N-type MOS transistor having a polarity opposite to that of a P-type. Figure 3 and Figure 4 Compared with the case where the ramp signal is turned on, the roles of the MOS transistors constituting the output control unit 142 and the current source 143 are reversed. The input terminal 312 is connected to the gate of the MOS transistor constituting the input control unit 311. In the case where the voltage of the ramp signal is higher than or equal to the threshold voltage between the gate and the source of the MOS transistor constituting the input control unit 311, the input control unit 311 enters a conductive state (on state). In contrast, in the case where the voltage of the ramp signal is lower than the threshold voltage between the gate and the source of the MOS transistor constituting the input control unit 311, the input control unit 311 enters a non-conductive state (off state).

[0079] The drain of the MOS transistor constituting the current source 143 is connected to the drain of the input control unit 311. In addition, the drain of the MOS transistor constituting the output control unit 142 and the output terminal 313 are connected to the source of the input control unit 311. The input control unit 311, the current source 143, and the second capacitor 147 form a second feedback circuit FB2A. The input control unit 311, the output control unit 142, and the first capacitor 146 form a first feedback circuit FB1A.

[0080] The first switch unit 314 turns on or off the connection between the gate of the output control unit 142 and the output terminal 313. The second switch unit 315 turns on or off the connection between the drain of the input control unit 311 and the first capacitor 146 and the second capacitor 147.

[0081] In the reset mode, the first switch unit 314, the third switch unit 153, and the fourth switch unit 154 are turned on, and the second switch unit 315 is turned off. That is, by turning on the first switch unit 314, the output control unit 142 becomes a diode connection, and the gate of the output control unit 142 is charged with the voltage Vy. By turning on the third switch unit 153, the voltage Vfb between the first capacitor 146 and the second capacitor 147 is charged to the externally applied voltage Vext from the first voltage applying unit 161. By turning on the fourth switch unit 154, the voltage Vz applied to the gate of the current source 143 is charged to the externally applied voltage Vbias from the second voltage applying unit 162.

[0082] In the driving mode, the first switch unit 314, the third switch unit 153, and the fourth switch unit 154 are turned off, and the second switch unit 315 is turned on. That is, by turning on the second switch unit 315, a signal is fed back from the drain of the input control unit 311 to the gate of the current source 143, and the difference between the voltages Vy and Vext is fed back from the drain of the input control unit 311 to the gate of the output control unit 142.

[0083] <Functions and Effects of the Second Embodiment>

[0084] As described above, according to the second embodiment, similar actions and effects to those of the first embodiment can be achieved.

[0085] <Third Implementation Method>

[0086] Figure 8 is a circuit diagram showing the configuration of a power supply circuit 410 and a ramp signal buffer circuit 131B according to a third embodiment of the present disclosure. Figure 8 In the above Figure 3 and Figure 4 The same components are denoted by the same reference numerals, and their detailed description is omitted.

[0087] The power supply circuit 410 supplies the power required for the operation of each of the pixel array unit 11, the column processing unit 13 including the ramp signal buffer circuit 131B, and the signal processing unit 16. The power supply circuit 410 according to the fourth embodiment of the present disclosure includes a low drop out (LDO) 411. As an example, the LDO 411 is a direct current (DC) to direct current (DC) converter. The LDO 411 is a component that compensates for the power supply rejection ratio (PSRR) of the power supply circuit 410. The power supply rejection ratio of the power supply circuit 410 is the ability of the power supply circuit 410 to eliminate voltage fluctuations of the power supply VDD when there are fluctuations (ripples) in the power supply voltage.

[0088] That is, the LDO 411 may attenuate the amount of fluctuation of the power supply voltage input from the power supply circuit 410 , and output a reference signal of a constant voltage level to the input control unit 141 , the output control unit 142 , and the current source 143 .

[0089] <Functions and Effects of the Third Embodiment>

[0090] As described above, according to the third embodiment, by providing the LDO 411 for the power supply circuit 410 itself, the power supply rejection ratio can be improved.

[0091] <Fourth Implementation Plan>

[0092] Fig. 9 is a circuit diagram showing the configuration of a ramp signal buffer circuit 131C according to a fourth embodiment of the present disclosure. Fig. 9 In the above Figure 3 and Figure 4 The same components are denoted by the same reference numerals, and their detailed description is omitted.

[0093] The ramp signal buffer circuit 131C according to the fourth embodiment of the present disclosure includes a source follower circuit 510 connected to a power line that supplies power required for operation to an input control unit 141, an output control unit 142, and a current source 143. The source follower circuit 510 includes, for example, an N-type MOS transistor. The source of the output control unit 142 is connected to the source of the source follower circuit 510. The power line is connected to the drain of the source follower circuit 510.

[0094] The source follower circuit 510 can attenuate power supply noise of a power supply voltage input via a drain, and output a reference signal of a constant voltage level to the input control unit 141 , the output control unit 142 , and the current source 143 .

[0095] <Functions and Effects of the Fourth Embodiment>

[0096] As described above, according to the fourth embodiment, power supply noise can be attenuated by providing the source follower circuit 510 .

[0097] <Fifth Implementation Plan>

[0098] Fig.10 is a circuit diagram showing the configuration of a ramp signal buffer circuit 131D according to a fifth embodiment of the present disclosure. Fig.10 In the above Figure 3 and Figure 4 The same components are denoted by the same reference numerals, and their detailed description is omitted.

[0099] In the ramp signal buffer circuit 131D according to the fifth embodiment of the present disclosure, a cascode transistor 610 is inserted in the first feedback circuit FB1D formed by the input control unit 141, the output control unit 142 and the first capacitor 146. The cascode transistor 610 includes, for example, a P-type MOS transistor. The source of the input control unit 141 is connected to the drain of the cascode transistor 610. The drain of the output control unit 142 and the output terminal 145 are connected to the source of the cascode transistor 610.

[0100] <Functions and Effects of the Fifth Embodiment>

[0101] As described above, according to the fifth embodiment, by inserting the cascode transistor 610 in the first feedback circuit FB1D, the loop gain of the first feedback circuit FB1D can be improved.

[0102] <Sixth Implementation Plan>

[0103] Fig.11 is a circuit diagram showing a configuration of a ramp signal buffer circuit 131E according to a sixth embodiment of the present disclosure. Fig.11 In the above Figure 7 The same components are denoted by the same reference numerals, and their detailed description is omitted.

[0104] In the ramp signal buffer circuit 131E according to the sixth embodiment of the present disclosure, a cascode transistor 710 is inserted in the first feedback circuit FB1E formed by the input control unit 311 , the output control unit 142 , and the first capacitor 146 .

[0105] The cascode transistor 710 includes, for example, an N-type MOS transistor. The source of the input control unit 141 is connected to the drain of the cascode transistor 710. The drain of the output control unit 142 and the output terminal 313 are connected to the source of the cascode transistor 710.

[0106] <Functions and Effects of the Sixth Embodiment>

[0107] As described above, according to the sixth embodiment, by inserting the cascode transistor 710 in the first feedback circuit FB1E, the loop gain of the first feedback circuit FB1E can be improved.

[0108] <Seventh Implementation Plan>

[0109] Fig.12 is a circuit diagram showing the configuration of a ramp signal buffer circuit 131F according to a seventh embodiment of the present disclosure. Fig.12 In the above Figure 3 and Figure 4 The same components are denoted by the same reference numerals, and their detailed description is omitted.

[0110] In the ramp signal buffer circuit 131F according to the seventh embodiment of the present disclosure, a cascode transistor 810 is inserted in the second feedback circuit FB2F formed by the input control unit 141, the current source 143, and the second capacitor 147. The cascode transistor 810 includes, for example, an N-type MOS transistor, and is a component for compensating for the linearity of the current source 143.

[0111] The drain of the input control unit 141 is connected to the drain of the cascode transistor 810. The drain of the current source 143 is connected to the source of the cascode transistor 810.

[0112] <Functions and Effects of the Seventh Implementation Method>

[0113] As described above, according to the seventh embodiment, by connecting the cascode transistor 810 between the input control unit 141 and the current source 143 , the linearity of the current source 143 can be improved.

[0114] <Eighth Implementation Plan>

[0115] Fig.13 is a circuit diagram showing a configuration of a ramp signal buffer circuit 131G according to an eighth embodiment of the present disclosure. Fig.13 In the above Figure 7 The same components are denoted by the same reference numerals, and their detailed descriptions are omitted.

[0116] In the ramp signal buffer circuit 131G according to the eighth embodiment of the present disclosure, a cascode transistor 910 is inserted in the second feedback circuit FB2G formed by the input control unit 311, the current source 143, and the second capacitor 147. The cascode transistor 910 includes, for example, a P-type MOS transistor, and is a component for compensating for the linearity of the current source 143.

[0117] The drain of the input control unit 311 is connected to the drain of the cascode transistor 910. The drain of the current source 143 is connected to the source of the cascode transistor 910.

[0118] <Functions and Effects of the Eighth Implementation Method>

[0119] As described above, according to the eighth embodiment, by connecting the cascode transistor 910 between the input control unit 311 and the current source 143 , the linearity of the current source 143 can be improved.

[0120] <Other Implementation Options>

[0121] The present technology has been described above according to the first to eighth embodiments, but it should not be understood that the description and drawings constituting a part of the present disclosure limit the present technology. It is obvious to those skilled in the art that when the spirit of the technical content disclosed in the first to eighth embodiments described above is understood, the present technology may include various alternative embodiments, examples and operating techniques. In addition, the configurations disclosed in the first to eighth embodiments can be appropriately combined within the scope of no contradiction. For example, the configurations disclosed in multiple different embodiments can be combined, or the configurations disclosed in multiple variations of the same embodiment can be combined.

[0122] <Application examples of electronic equipment>

[0123] The above-mentioned photoelectric detection device can be applied to various electronic devices, for example, imaging devices such as digital cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

[0124] Fig.14 : is a block diagram showing a configuration example of an imaging system as an electronic device to which the present technology is applied.

[0125] Fig.14 The illustrated imaging system 2201 includes an optical system 2202, a shutter device 2203, a solid-state imaging element 2204 as an imaging device, a control circuit 2205, a signal processing circuit 2206, a monitor 2207, and two memories 2208, and can capture still images and moving images.

[0126] The optical system 2202 includes one or more lenses, and guides light (incident light) from a subject to the solid-state imaging element 2204 to form an image on a light receiving surface of the solid-state imaging element 2204 .

[0127] The shutter device 2203 is arranged between the optical system 2202 and the solid-state imaging element 2204 , and controls a light irradiation period and a light shielding period of the solid-state imaging element 2204 under the control of the control circuit 2205 .

[0128] The solid-state imaging element 2204 includes a package having the above-mentioned solid-state imaging element. The solid-state imaging element 2204 accumulates signal charges for a certain period of time according to the light formed as an image on the light receiving surface via the optical system 2202 and the shutter device 2203. The signal charges accumulated on the solid-state imaging element 2204 are transmitted according to the drive signal (timing signal) supplied from the control circuit 2205.

[0129] The control circuit 2205 outputs a drive signal for controlling the transfer operation of the solid-state imaging element 2204 and the shutter operation of the shutter device 2203 to drive the solid-state imaging element 2204 and the shutter device 2203 .

[0130] The signal processing circuit 2206 performs various types of signal processing on the signal charge output from the solid-state imaging element 2204. The image (image data) obtained by the signal processing performed by the signal processing circuit 2206 is supplied to the monitor 2207 for display or supplied to the memory 2208 for storage (recording).

[0131] Also in the imaging system 2201 configured as described above, the imaging device 1 may be applied instead of the above-described solid-state imaging element 2204 .

[0132] Note that the present disclosure may also have the following configurations. (1)

[0134] A buffer circuit, comprising:

[0135] A first transistor having a gate to which an input signal is input;

[0136] a current source connected to one terminal of the first transistor;

[0137] a second transistor connected to the other terminal of the first transistor;

[0138] an output terminal connected to the one terminal or the other terminal of the first transistor; and

[0139] a first capacitor and a second capacitor disposed between the current source and the gate of the second transistor,

[0140] The first transistor, the second transistor and the first capacitor form a first feedback circuit,

[0141] The first transistor, the current source, and the second capacitor form a second feedback circuit. (2)

[0143] The buffer circuit according to (1), further comprising:

[0144] A first voltage applying unit applies a predetermined first voltage to the first feedback circuit. (3)

[0146] The buffer circuit according to (2) further includes:

[0147] A second voltage applying unit applies a second voltage different from the first voltage to the second feedback circuit. (4)

[0149] The buffer circuit according to (3) further includes:

[0150] a first switch unit that switches on or off the connection between the gate of the second transistor and the output terminal;

[0151] a second switch unit that switches on or off a connection between a terminal of the first transistor that is not connected to the output terminal and the first capacitor and the second capacitor;

[0152] a third switching unit that switches on or off the connection between the first voltage applying unit and the first capacitor and the second capacitor; and

[0153] a fourth switching unit that switches on or off the connection between the second voltage applying unit and the second capacitor and the current source,

[0154] In the reset mode, the first switch unit, the third switch unit and the fourth switch unit are turned on, and the second switch unit is turned off, and

[0155] In a driving mode, the first switching unit, the third switching unit, and the fourth switching unit are turned off, and the second switching unit is turned on. (5)

[0157] The buffer circuit according to (1), wherein the first transistor is of a first conductivity type, and

[0158] The output terminal is connected between the first transistor and the second transistor. (6)

[0160] The buffer circuit according to (5), further comprising:

[0161] A first voltage applying unit, which applies a predetermined first voltage to the first feedback circuit;

[0162] a second voltage applying unit, which applies a second voltage different from the first voltage to the second feedback circuit;

[0163] a first switch unit that switches on or off the connection between the gate of the second transistor and the output terminal;

[0164] a second switch unit that switches on or off a connection between a terminal of the first transistor that is not connected to the output terminal and the first capacitor and the second capacitor;

[0165] a third switching unit that switches on or off the connection between the first voltage applying unit and the first capacitor and the second capacitor; and

[0166] a fourth switching unit that switches on or off the connection between the second voltage applying unit and the second capacitor and the current source,

[0167] In the reset mode, the first switch unit, the third switch unit and the fourth switch unit are turned on, and the second switch unit is turned off, and

[0168] In a driving mode, the first switching unit, the third switching unit, and the fourth switching unit are turned off, and the second switching unit is turned on. (7)

[0170] The buffer circuit according to (5), wherein a cascode transistor is connected between the first transistor and the output terminal. (8)

[0172] The buffer circuit according to (5), wherein a cascode transistor is connected between the first transistor and the current source. (9)

[0174] The buffer circuit according to (5), wherein the first transistor is of a second conductivity type having a polarity opposite to that of the first conductivity type, and

[0175] The output terminal is connected between the first transistor and the second transistor. (10)

[0177] The buffer circuit according to (9), further comprising:

[0178] A first voltage applying unit, which applies a predetermined first voltage to the first feedback circuit;

[0179] a second voltage applying unit, which applies a second voltage different from the first voltage to the second feedback circuit;

[0180] a first switch unit that switches on or off the connection between the second transistor and the output terminal;

[0181] a second switch unit that switches on or off a connection between a terminal of the first transistor that is not connected to the output terminal and the first capacitor and the second capacitor;

[0182] a third switching unit that switches on or off the connection between the first voltage applying unit and the first capacitor and the second capacitor; and

[0183] a fourth switching unit that switches on and off the connection between the second voltage applying unit and the second capacitor and the current source,

[0184] In the reset mode, the first switch unit, the third switch unit and the fourth switch unit are turned on, and the second switch unit is turned off, and

[0185] In a driving mode, the first switching unit, the third switching unit, and the fourth switching unit are turned off, and the second switching unit is turned on. (11)

[0187] The buffer circuit according to (9), wherein a cascode transistor is connected between the first transistor and the output terminal. (12)

[0189] The buffer circuit according to (9), wherein a cascode transistor is connected between the first transistor and the current source. (13)

[0191] The buffer circuit according to (1), further comprising:

[0192] A source follower circuit is connected to a power supply line that supplies power required for operation to the first transistor, the second transistor, and the current source, and outputs a reference signal of a constant voltage level to the first transistor, the second transistor, and the current source. (14)

[0194] A camera device, comprising:

[0195] a pixel array unit including a plurality of pixels capable of generating pixel signals according to light incident from the outside;

[0196] Buffer circuit;

[0197] a signal processing unit that compares an output signal of the buffer circuit with a pixel signal output from each of the plurality of pixels and generates image data based on a comparison result; and

[0198] a power supply circuit that supplies power required for operation of each of the pixel array unit, the buffer circuit, and the signal processing unit,

[0199] The buffer circuit comprises:

[0200] A first transistor having a gate to which an input signal is input;

[0201] a current source connected to one terminal of the first transistor;

[0202] a second transistor connected to the other terminal of the first transistor;

[0203] an output terminal connected to the one terminal or the other terminal of the first transistor; and

[0204] a first capacitor and a second capacitor disposed between the current source and the gate of the second transistor,

[0205] The first transistor, the second transistor and the first capacitor form a first feedback circuit,

[0206] The first transistor, the current source, and the second capacitor form a second feedback circuit. (15)

[0208] The imaging device according to (14), wherein the power supply circuit has a function of outputting a reference signal of a constant voltage level to the first transistor, the second transistor, and the current source.

[0209] Reference numerals list

[0210] 1 Camera device

[0211] 11 Pixel Array Unit

[0212] 12 vertical drive units

[0213] 13 columns of processing units

[0214] 14 Horizontal drive unit

[0215] 15 System control unit

[0216] 16 Signal Processing Unit

[0217] 17 Data storage unit

[0218] 18 pixel drive lines

[0219] 19 vertical signal line

[0220] 20 Pixel signal reading mechanism

[0221] 110 pixels

[0222] 131, 131A, 131B, 131C, 131D, 131E, 131G ramp signal buffer circuit

[0223] 132 Ramp signal generation circuit

[0224] 133 AD Converter

[0225] 134 Comparator

[0226] 135 Counter

[0227] 141, 311 Input control unit

[0228] 142 Output control unit

[0229] 143 Current Source

[0230] 144, 312 Input terminals

[0231] 145, 313 output terminals

[0232] 146 first capacitor (C1)

[0233] 147 second capacitor (C2)

[0234] 151, 314 first switch unit

[0235] 152, 315 Second switch unit

[0236] 153 Third switch unit

[0237] 154 Fourth switch unit

[0238] 161 first voltage applying unit

[0239] 162 second voltage applying unit

[0240] 201 Module 1

[0241] 202 Module 2

[0242] 211, 212 Source Follower Circuit

[0243] 410 Power Circuit

[0244] 411LDO

[0245] 510 source follower circuit

[0246] 610, 710, 810, 910 Cascode transistors

[0247] 2201 Camera System

[0248] 2202 Optical System

[0249] 2203 shutter device

[0250] 2204 solid-state imaging element

[0251] 2205 control circuit

[0252] 2206 signal processing circuit

[0253] 2207 Monitor

[0254] 2208 Memory

Claims

1. A buffer circuit, comprising: A first transistor having a gate to which an input signal is input; a current source connected to one terminal of the first transistor; a second transistor connected to the other terminal of the first transistor; an output terminal connected to the one terminal or the other terminal of the first transistor; as well as a first capacitor and a second capacitor disposed between the current source and the gate of the second transistor, The first transistor, the second transistor and the first capacitor form a first feedback circuit, The first transistor, the current source, and the second capacitor form a second feedback circuit.

2. The buffer circuit according to claim 1, further comprising: A first voltage applying unit applies a predetermined first voltage to the first feedback circuit.

3. The buffer circuit according to claim 2, further comprising: A second voltage applying unit applies a second voltage different from the first voltage to the second feedback circuit.

4. The buffer circuit according to claim 3, further comprising: a first switch unit that switches on or off the connection between the gate of the second transistor and the output terminal; a second switch unit that switches on or off a connection between a terminal of the first transistor that is not connected to the output terminal and the first capacitor and the second capacitor; a third switch unit that switches on or off the connection between the first voltage applying unit and the first capacitor and the second capacitor; as well as a fourth switching unit that switches on or off the connection between the second voltage applying unit and the second capacitor and the current source, In the reset mode, the first switch unit, the third switch unit and the fourth switch unit are turned on, and the second switch unit is turned off, and In a driving mode, the first switching unit, the third switching unit, and the fourth switching unit are turned off, and the second switching unit is turned on.

5. The buffer circuit according to claim 1 , wherein the first transistor is of a first conductivity type, and The output terminal is connected between the first transistor and the second transistor.

6. The buffer circuit according to claim 5, further comprising: A first voltage applying unit, which applies a predetermined first voltage to the first feedback circuit; a second voltage applying unit, which applies a second voltage different from the first voltage to the second feedback circuit; a first switch unit that switches on or off the connection between the gate of the second transistor and the output terminal; a second switch unit that switches on or off a connection between a terminal of the first transistor that is not connected to the output terminal and the first capacitor and the second capacitor; a third switch unit that switches on or off the connection between the first voltage applying unit and the first capacitor and the second capacitor; as well as a fourth switching unit that switches on or off the connection between the second voltage applying unit and the second capacitor and the current source, In the reset mode, the first switch unit, the third switch unit and the fourth switch unit are turned on, and the second switch unit is turned off, and In a driving mode, the first switching unit, the third switching unit, and the fourth switching unit are turned off, and the second switching unit is turned on.

7. The buffer circuit according to claim 5, wherein a cascode transistor is connected between the first transistor and the output terminal.

8. The buffer circuit according to claim 5, wherein a cascode transistor is connected between the first transistor and the current source.

9. The buffer circuit according to claim 5, wherein the first transistor is of a second conductivity type having a polarity opposite to that of the first conductivity type, and The output terminal is connected between the first transistor and the second transistor.

10. The buffer circuit according to claim 9, further comprising: A first voltage applying unit, which applies a predetermined first voltage to the first feedback circuit; a second voltage applying unit, which applies a second voltage different from the first voltage to the second feedback circuit; a first switch unit that switches on or off the connection between the second transistor and the output terminal; a second switch unit that switches on or off a connection between a terminal of the first transistor that is not connected to the output terminal and the first capacitor and the second capacitor; a third switch unit that switches on or off the connection between the first voltage applying unit and the first capacitor and the second capacitor; as well as a fourth switching unit that switches on and off the connection between the second voltage applying unit and the second capacitor and the current source, In the reset mode, the first switch unit, the third switch unit and the fourth switch unit are turned on, and the second switch unit is turned off, and In a driving mode, the first switching unit, the third switching unit, and the fourth switching unit are turned off, and the second switching unit is turned on.

11. The buffer circuit according to claim 9, wherein a cascode transistor is connected between the first transistor and the output terminal.

12. The buffer circuit of claim 9, wherein a cascode transistor is connected between the first transistor and the current source.

13. The buffer circuit according to claim 1, further comprising: A source follower circuit is connected to a power supply line that supplies power required for operation to the first transistor, the second transistor, and the current source, and outputs a reference signal of a constant voltage level to the first transistor, the second transistor, and the current source.

14. A camera device, comprising: a pixel array unit including a plurality of pixels capable of generating pixel signals according to light incident from the outside; Buffer circuit; a signal processing unit that compares an output signal of the buffer circuit with a pixel signal output from each of the plurality of pixels and generates image data based on a comparison result; as well as a power supply circuit that supplies power required for operation of each of the pixel array unit, the buffer circuit, and the signal processing unit, The buffer circuit comprises: A first transistor having a gate to which an input signal is input; a current source connected to one terminal of the first transistor; a second transistor connected to the other terminal of the first transistor; an output terminal connected to the one terminal or the other terminal of the first transistor; and a first capacitor and a second capacitor disposed between the current source and the gate of the second transistor, The first transistor, the second transistor and the first capacitor form a first feedback circuit, The first transistor, the current source, and the second capacitor form a second feedback circuit. 15 . The image pickup device according to claim 14 , wherein the power supply circuit has a function of outputting a reference signal of a constant voltage level to the first transistor, the second transistor, and the current source.

Images