Deposition mask

Abstract

A deposition mask includes a mask body including a silicon substrate, where a plurality of apertures are defined through the mask body, and the mask body further includes a plurality of mask grids extending to define the plurality of apertures. A cross-section of each of the plurality of mask grids has an inverted tapering shape having a width increasing from a back surface to an upper surface of the deposition mask, and each side surface of each of the plurality of mask grids defining the plurality of holes includes a first concave curved surface.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits arising from Korean Patent Application No. 10-2023-0108366, filed on August 18, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure relate to deposition masks. Background Art

[0004] Wearable devices in the form of glasses or helmets are being developed that form a focal point at a short distance from the user's eyes. For example, the wearable device may be a head mounted display (HMD) device or augmented reality (AR) glasses. Such wearable devices provide AR images or virtual reality (VR) images to the user.

[0005] Wearable devices such as HMD devices or AR glasses may be expected to have a display specification of at least 2000 pixels per inch (PPI) to allow users to use it for a long time without dizziness. In order to realize wearable devices, organic light emitting diode on silicon (OLEDoS) technology is being proposed, which is used for small high-resolution organic light emitting display devices. OLEDoS technology is a technology for placing an organic light emitting diode (OLED) on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is provided. Summary of the invention

[0006] Embodiments of the present disclosure provide a deposition mask for providing a high-resolution organic light-emitting display device, wherein the deposition mask has improved reliability by improving pixel position accuracy (PPA).

[0007] Embodiments of the present disclosure also provide a deposition mask capable of reducing shadow defects and accumulation of deposition materials on the mask.

[0008] Embodiments of the present disclosure also provide methods of manufacturing a deposition mask having improved mask rigidity.

[0009] According to an embodiment of the present invention, a deposition mask comprises a mask body, the mask body comprising a silicon substrate, wherein a plurality of holes are defined through the mask body, and the mask body further comprises a mask grid extending to define the holes. In such an embodiment, a cross-section of each mask grid has a reverse tapered shape, the reverse tapered shape having a width that increases (substantially increases) from a rear surface to an upper surface of the deposition mask, and each side surface of each mask grid defining the hole comprises a first concave curved surface.

[0010] In an embodiment, the distance between adjacent holes may be less than or equal to about 5 micrometers (μm).

[0011] In an embodiment, the taper angle of each mask grid may be in a range of about 60 degrees to about 88 degrees.

[0012] In an embodiment, the maximum width of each mask grid may be less than or equal to about 10 μm.

[0013] In an embodiment, the maximum thickness of each mask grid may be less than or equal to about 15 μm.

[0014] In an embodiment, the rear surface of each mask grid may include a second concavely curved surface.

[0015] In an embodiment, a depth of the first concave curved surface included in each side surface of each mask grid may be less than or equal to about 20% of a thickness of the mask grid.

[0016] In an embodiment, the mask grid may include a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one material.

[0017] In an embodiment, the mask grid may include at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar alloy.

[0018] In an embodiment, each side surface of each mask grid may include a plurality of first concave curved surfaces.

[0019] According to an embodiment of the present disclosure, a deposition mask may include a mask body including a silicon substrate, wherein a plurality of holes are defined through the mask body, and the mask body further includes a mask grid extending to define the holes. In such an embodiment, a cross-section of each mask grid has an inverse tapered shape having a width that increases from a rear surface to an upper surface of the deposition mask, and each side surface of each mask grid defining the hole includes a plurality of first concave curved surfaces.

[0020] In an embodiment, the distance between adjacent holes may be less than or equal to about 5 μm.

[0021] In an embodiment, the taper angle of each mask grid may be in a range of about 60 degrees to about 88 degrees.

[0022] In an embodiment, the maximum width of each mask grid may be less than or equal to about 10 μm.

[0023] In an embodiment, the maximum thickness of each mask grid may be less than or equal to about 15 μm.

[0024] In an embodiment, the rear surface of each mask grid may include a second concavely curved surface.

[0025] In an embodiment, a depth of each first concave curved surface included in each side surface of each mask grid may be less than or equal to about 20% of a thickness of the mask grid.

[0026] In an embodiment, the mask grid may include an inorganic layer including a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one material.

[0027] In an embodiment, the mask grid may include a metal layer including at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar alloy.

[0028] In an embodiment, each mask grid may have a multi-layer structure in which inorganic layers and metal layers are alternately stacked.

[0029] However, the embodiments of the present disclosure are not limited to the embodiments described herein. The above and other features of the embodiments of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other features of the embodiments will become apparent and more readily understood from the following description of detailed embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a perspective view of a head mounted display device according to an embodiment;

[0032] Figure 2 yes Figure 1 An exploded perspective view of an example of a head mounted display device;

[0033] Figure 3 is a perspective view of a head mounted display device according to an embodiment;

[0034] Figure 4 is an exploded perspective view of a display device according to an embodiment;

[0035] Figure 5 is a cross-sectional view of an example of a portion of a display panel according to an embodiment;

[0036] Figure 6 is a perspective view of a mask according to an embodiment;

[0037] Figure 7 is a schematic cross-sectional view of a mask according to an embodiment;

[0038] Figure 8 is a schematic cross-sectional view of a mask according to an embodiment;

[0039] Fig. 9 is a perspective view of a portion of a mask according to an embodiment;

[0040] Fig.10 is a cross-sectional view for explaining a deposition process performed using a mask according to an embodiment;

[0041] Fig.11 is a cross-sectional view showing mask grids each including a lower curved surface in a mask according to an embodiment used in a deposition process;

[0042] Fig.12 is a cross-sectional view showing mask grids each having a plurality of curved surfaces included in each side surface in a mask according to an embodiment used in a deposition process; and

[0043] Fig.13 is a cross-sectional view showing mask grids each formed in multiple layers including a metal layer in a mask according to an embodiment used in a deposition process. DETAILED DESCRIPTION

[0044] The present invention will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the present invention are shown. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the present invention to those skilled in the art.

[0045] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Throughout the specification, like reference numerals refer to like components throughout.

[0046] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the present invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0047] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be restrictive. Unless the context clearly indicates otherwise, as used herein, "one", "one (kind / person)", "described (the)" and "at least one (kind / person)" do not represent the limitation to quantity, and are intended to include both the singular and the plural. Therefore, the reference to "described" element after citing an element in the claims includes one element and a plurality of described elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one (kind / person)" will not be interpreted as limiting "one" or "one (kind / person)". "Or" means "and / or". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that the terms “comprises and / or comprising” or “includes and / or including”, when used in this specification, indicate the presence of stated features, regions, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components and / or groups thereof.

[0048] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship of one element to another element as shown in the drawings. It will be understood that, in addition to the orientation depicted in the drawings, relative terms are intended to cover different orientations of the device. For example, if the device is turned over in one of the multiple drawings, the element described as being on the "lower" side of another element will then be oriented to be on the "upper" side of the other element. Therefore, depending on the specific orientation of the drawings, the term "lower" can cover both "lower" and "upper" orientations. Similarly, if the device is turned over in one of the multiple drawings, the element described as being "below" or "below" another element will then be oriented to be "above" the other element. Therefore, the term "below..." or "below..." can cover both upper and lower orientations.

[0049] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0050] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formalized sense.

[0051] Embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are anticipated. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the accompanying drawings are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, nor are they intended to limit the scope of the claims.

[0052] The features of each of the various embodiments of the present disclosure may be partially or completely combined with each other, and may be technically coordinated with each other differently, and the various embodiments may be implemented independently of each other, or may be implemented together in association with each other.

[0053] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0054] Figure 1 is a perspective view of the head mounted display device 1 according to the embodiment. Figure 2 yes Figure 1 1 is an exploded perspective view of an example of the head mounted display device 1.

[0055] Reference Figure 1 and Figure 2According to the embodiment, the head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device housing 110, a housing cover 120, a first eyepiece 131, a second eyepiece 132, a head-mounted band 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0056] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 4 and Figure 5 The display devices 10 described are substantially the same. Therefore, the description of the first display device 10_1 and the second display device 10_2 will be referred to with reference to Figure 4 and Figure 5 The description given is used instead.

[0057] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0058] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 supports and fixes the first display device 10_1, the second display device 10_2, and the control circuit board 170.

[0059] The control circuit board 170 may be disposed between the middle frame 160 and the display device housing 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source received from the outside into digital video data and transmit the digital video data to the first display device 10_1 and the second display device 10_2 through the connector.

[0060] In an embodiment, the control circuit board 170 may transmit digital video data corresponding to a left-eye image optimized for the left eye of the user to the first display device 10_1, and transmit digital video data corresponding to a right-eye image optimized for the right eye of the user to the second display device 10_2. Alternatively, the control circuit board 170 may transmit the same digital video data to the first display device 10_1 and the second display device 10_2.

[0061] The display device housing 110 houses or accommodates the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The housing cover 120 is placed to cover the opening surface of the display device housing 110. The housing cover 120 may include a first eyepiece 131 and a second eyepiece 132, the left eye of the user is placed at the first eyepiece 131, and the right eye of the user is placed at the second eyepiece 132. In an embodiment, as shown in FIG. Figure 1 and Figure 2 As shown in FIG. 1 , the first eyepiece 131 and the second eyepiece 132 are separately provided, but the embodiments of the present disclosure are not limited thereto. Optionally, the first eyepiece 131 and the second eyepiece 132 may also be combined into one body.

[0062] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151, and the second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may view the image of the first display device 10_1 magnified as a virtual image by the first optical member 151 through the first eyepiece 131, and may view the image of the second display device 10_2 magnified as a virtual image by the second optical member 152 through the second eyepiece 132.

[0063] The head-mounted strap 140 fixes the display device housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 remain placed at the user's left eye and right eye, respectively. In an embodiment where it is desired to implement the display device housing 110 as being lightweight and small, the head-mounted display device 1 may include a Figure 3 , rather than the headband 140 .

[0064] In an embodiment, the head mounted display device 1 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0065] Figure 3 is a perspective view of a head mounted display device 1_1 according to an embodiment.

[0066] Reference Figure 3The head mounted display device 1_1 according to the embodiment may be a display device in which the display device housing 120_1 is implemented in a light-weight and small glasses form. The head mounted display device 1_1 according to the embodiment may include a display device 10_3, a left-eye lens 311, a right-eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 120_1.

[0067] Figure 3 The display device 10_3 shown in FIG. Figure 4 and Figure 5 The display device 10 described is substantially the same. Therefore, reference will be made to Figure 4 and Figure 5 A description is given instead of the description of the display device 10_3.

[0068] The display device housing 120_1 may accommodate the display device 10_3, the optical member 320, and the optical path conversion member 330. The image displayed in the display device 10_3 may be magnified by the optical member 320, may have its optical path converted by the optical path conversion member 330, and may then be provided to the right eye of the user through the right eye lens 312. Therefore, the user may view an augmented reality image through the right eye, into which the virtual image displayed in the display device 10_3 and the real image viewed through the right eye lens 312 are combined.

[0069] In an embodiment, Figure 3 As shown in , the display device housing 120_1 can be set at the right end of the supporting frame 350, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the display device housing 120_1 can also be set at the left end of the supporting frame 350. In such an embodiment, the image of the display device 10_3 can be provided to the left eye of the user. Optionally, the display device housing 120_1 can be set at both the left and right ends of the supporting frame 350. In such an embodiment, the user can view the image displayed on the display device 10_3 through both the left eye and the right eye.

[0070] Figure 4 is an exploded perspective view of the display device 10 according to the embodiment.

[0071] Reference Figure 4, the display device 10 according to the embodiment is a device for displaying dynamic images or still images. The display device 10 according to the embodiment can be applied to portable electronic devices (such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, laptop computers, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs)). In an embodiment, for example, the display device 10 can be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. Optionally, the display device 10 can be applied to smart watches, watch phones, and head-mounted displays for realizing virtual reality and augmented reality.

[0072] The display device 10 according to the embodiment includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0073] The display panel 410 may have a planar shape similar to a quadrilateral. In an embodiment, for example, the display panel 410 may have a planar shape similar to a quadrilateral having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the display panel 410, each corner where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be rounded with a predetermined curvature, or may be a right angle. The planar shape of the display panel 410 is not limited to a quadrilateral shape, but may also be similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may correspond to the planar shape of the display panel 410, but the embodiments of the present disclosure are not limited thereto.

[0074] The display panel 410 includes a display area where an image is displayed and a non-display area where no image is displayed.

[0075] The display area includes a plurality of pixels, and each of the plurality of pixels includes a plurality of sub-pixels SP1 to SP3 (see Figure 5 ). The sub-pixels SP1 to SP3 include a plurality of pixel transistors PTR (see Figure 5 ). The pixel transistor PTR may be formed by a semiconductor process and may be disposed on a semiconductor substrate SSUB (see Figure 5 In an embodiment, for example, the pixel transistor PTR may be formed as a complementary metal oxide semiconductor (CMOS).

[0076] The heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3 which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be provided on a surface (e.g., a back surface) of the display panel 410. The heat dissipation layer 420 dissipates heat generated in the display panel 410. The heat dissipation layer 420 may include graphite or a metal having high thermal conductivity such as silver (Ag), copper (Cu), or aluminum (Al).

[0077] The circuit board 430 may be electrically connected to a plurality of pads in the pad area of ​​the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board including or made of a flexible material, or the circuit board 430 may be a flexible film. Figure 4 4 shows the circuit board 430 in an unfolded state, but the circuit board 430 may also be bent. In the bent state, one end of the circuit board 430 may be placed on the back of the display panel 410. The end of the circuit board 430 may be an end opposite to the other end of the circuit board 430, which is connected to the pad in the pad area of ​​the display panel 410 by using a conductive adhesive member.

[0078] The driving circuit 440 may receive digital video data and a timing signal from the outside, and may generate a scanning timing control signal, an emission timing control signal, and a data timing control signal for controlling the display panel 410 according to the timing signal.

[0079] The power supply circuit 450 may generate a plurality of panel driving voltages according to a power supply voltage received from the outside. In an embodiment, for example, the power supply circuit 450 may generate a first driving voltage (e.g., a low driving voltage), a second driving voltage (e.g., a high driving voltage), and a third driving voltage (e.g., an initialization voltage), and supply the first driving voltage to the third driving voltage to the display panel 410.

[0080] Each of the driving circuit 440 and the power supply circuit 450 may be formed as an integrated circuit and attached to a surface of the circuit board 430 .

[0081] Figure 5 is a cross-sectional view of an example of a portion of a display panel 410 according to an embodiment. In particular, Figure 5 A partial cross-sectional structure of a display area including a plurality of sub-pixels SP1 to SP3 is shown.

[0082] Reference Figure 5 , an embodiment of the display panel 410 includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizer (not shown).

[0083] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the pixel transistors PTR.

[0084] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type impurity. A plurality of well areas WA may be defined or provided on the upper surface of the semiconductor substrate SSUB. The well area WA may be an area doped with a second type impurity. The second type impurity may be different from the first type impurity. In an embodiment, for example, in the case where the first type impurity is a p-type impurity, the second type impurity may be an n-type impurity. Alternatively, in the case where the first type impurity is an n-type impurity, the second type impurity may be a p-type impurity.

[0085] Each of the well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode, and a channel region CH disposed between the source region SA and the drain region DA.

[0086] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of each pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be disposed on one side of the gate electrode GE, and the drain region DA may be disposed on the opposite side of the gate electrode GE.

[0087] Each of the well regions WA further includes a first lightly doped impurity region disposed between the channel region CH and the source region SA and a second lightly doped impurity region disposed between the channel region CH and the drain region DA. The first lightly doped impurity region may be a region having a lower impurity concentration than the source region SA. The second lightly doped impurity region may be a region having a lower impurity concentration than the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first lightly doped impurity region and the second lightly doped impurity region. Therefore, the length of the channel region CH of each pixel transistor PTR may be increased, thereby effectively preventing a breakdown phenomenon and a hot carrier phenomenon caused by a short channel.

[0088] The first semiconductor insulating layer SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be an inorganic layer of silicon nitride carbon (SiCN) or silicon oxide (SiO x ) type inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0089] The second semiconductor insulating layer SINS2 may be disposed on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be silicon oxide (SiO x ) type inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0090] The contact terminal CTE may be disposed on the second semiconductor insulating layer SINS2. Each of the contact terminals CTE may be connected to at least one selected from the gate electrode GE, the source area SA, and the drain area DA of the pixel transistor PTR through a hole formed or defined through the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The contact terminal CTE may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0091] The third semiconductor insulating layer SINS3 may be disposed on a side surface of each of the contact terminals CTE. The upper surface of each of the contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be silicon oxide (SiO x ) type inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0092] In an embodiment, the semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate (such as a polyimide resin substrate). In such an embodiment, the thin film transistor may be disposed on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that cannot be bent, and the polymer resin substrate may be a flexible substrate that can be bent or curved.

[0093] The light emitting element back plate EBP includes first to eighth metal layers ML1 to ML8, reflective electrodes RL1 to RL4, a plurality of vias VA1 to VA10, and a step layer STPL. In addition, the light emitting element back plate EBP includes a plurality of interlayer insulating layers INS1 to INS10 disposed between the first to eighth metal layers ML1 to ML8.

[0094] The first metal layer ML1 to the eighth metal layer ML8 are used to realize the circuit of the first sub-pixel SP1, the second sub-pixel SP2 or the third sub-pixel SP3 by connecting the contact terminal CTE exposed in the semiconductor backplane SBP. That is, only the first transistor to the sixth transistor are formed in the semiconductor backplane SBP, and the connection of the first transistor to the sixth transistor and the first capacitor and the second capacitor is realized through the first metal layer ML1 to the eighth metal layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor and the source region corresponding to the source electrode of the fifth transistor and the first electrode of the light-emitting element is also realized through the first metal layer ML1 to the eighth metal layer ML8.

[0095] The first interlayer insulating layer INS1 may be disposed on the semiconductor backplane SBP. The first vias VA1 may pass through or be disposed to pass through the first interlayer insulating layer INS1 and may be respectively connected to the contact terminals CTE exposed in the semiconductor backplane SBP. The first metal layer ML1 may be disposed on the first interlayer insulating layer INS1 and may be respectively connected to the first vias VA1.

[0096] The second interlayer insulating layer INS2 may be disposed on the first interlayer insulating layer INS1 and the first metal layer ML1. The second via holes VA2 may pass through or be disposed to pass through the second interlayer insulating layer INS2 and may be respectively connected to the exposed first metal layers ML1. The second metal layer ML2 may be disposed on the second interlayer insulating layer INS2 and may be respectively connected to the second via holes VA2.

[0097] The third interlayer insulating layer INS3 may be disposed on the second interlayer insulating layer INS2 and the second metal layer MI2. The third vias VA3 may pass through or be disposed to pass through the third interlayer insulating layer INS3 and may be respectively connected to the exposed second metal layers ML2. The third metal layers ML3 may be disposed on the third interlayer insulating layer INS3 and may be respectively connected to the third vias VA3.

[0098] The fourth interlayer insulating layer INS4 may be disposed on the third interlayer insulating layer INS3 and the third metal layer ML3. The fourth vias VA4 may pass through or be disposed to pass through the fourth interlayer insulating layer INS4 and may be respectively connected to the exposed third metal layers ML3. The fourth metal layers ML4 may be disposed on the fourth interlayer insulating layer INS4 and may be respectively connected to the fourth vias VA4.

[0099] The fifth interlayer insulating layer INS5 may be disposed on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. The fifth vias VA5 may pass through or be disposed to pass through the fifth interlayer insulating layer INS5 and may be respectively connected to the exposed fourth metal layers ML4. The fifth metal layer ML5 may be disposed on the fifth interlayer insulating layer INS5 and may be respectively connected to the fifth vias VA5.

[0100] The sixth interlayer insulating layer INS6 may be disposed on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. The sixth vias VA6 may pass through or be disposed to pass through the sixth interlayer insulating layer INS6 and may be respectively connected to the exposed fifth metal layers ML5. The sixth metal layer ML6 may be disposed on the sixth interlayer insulating layer INS6 and may be respectively connected to the sixth vias VA6.

[0101] The seventh interlayer insulating layer INS7 may be disposed on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. The seventh vias VA7 may pass through or be disposed to pass through the seventh interlayer insulating layer INS7 and may be respectively connected to the exposed sixth metal layer ML6. The seventh metal layer ML7 may be disposed on the seventh interlayer insulating layer INS7 and may be respectively connected to the seventh vias VA7.

[0102] The eighth interlayer insulating layer INS8 may be disposed on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. The eighth vias VA8 may pass through or be disposed to pass through the eighth interlayer insulating layer INS8 and may be respectively connected to the exposed seventh metal layer ML7. The eighth metal layer ML8 may be disposed on the eighth interlayer insulating layer INS8 and may be respectively connected to the eighth vias VA8.

[0103] The first metal layer ML1 to the eighth metal layer ML8 and the first via VA1 to the eighth via VA8 may include substantially the same material as each other or be made of substantially the same material as each other. In this article, "via" may refer to the via itself and the connecting element accommodated in the via. The first metal layer ML1 to the eighth metal layer ML8 and the first via VA1 to the eighth via VA8 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or their alloys, or be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or their alloys. The first via VA1 to the eighth via VA8 may include substantially the same material as each other or be made of substantially the same material as each other. In an embodiment, each of the first interlayer insulating layer INS1 to the eighth interlayer insulating layer INS8 may be silicon oxide (SiO x) type inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0104] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same as each other. In an embodiment, for example, the thickness of the first metal layer ML1 may be about The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may each be about 100 Å. And the thickness of the first via hole VA1, the thickness of the second via hole VA2, the thickness of the third via hole VA3, the thickness of the fourth via hole VA4, the thickness of the fifth via hole VA5, and the thickness of the sixth via hole VA6 may each be about 1000 Å.

[0105] The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be greater than the thickness of the seventh via VA7 and the thickness of the eighth via VA8. The thickness of the seventh via VA7 and the thickness of the eighth via VA8 may each be greater than the thickness of the first via VA1, the thickness of the second via VA2, the thickness of the third via VA3, the thickness of the fourth via VA4, the thickness of the fifth via VA5, and the thickness of the sixth via VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same as each other. In an embodiment, for example, the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may each be approximately The thickness of the seventh via hole VA7 and the thickness of the eighth via hole VA8 may each be about

[0106] The ninth interlayer insulating layer INS9 may be disposed on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. In an embodiment, the ninth interlayer insulating layer INS9 may be silicon oxide (SiO x ) type inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0107] The ninth via hole VA9 may pass through the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth metal layer ML8, respectively. The ninth via hole VA9 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or their alloys, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or their alloys. In an embodiment, for example, the thickness of the ninth via hole VA9 may be about

[0108] The first reflective electrode RL1 may be disposed on the ninth interlayer insulating layer INS9 and may be connected to the ninth via holes VA9, respectively. The first reflective electrode RL1 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0109] The second reflective electrode RL2 may be disposed on the first reflective electrode RL1, respectively. The second reflective electrode RL2 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or an alloy thereof, or may include metal nitride. In an embodiment, for example, the second reflective electrode RL2 may be titanium nitride (TiN).

[0110] In the first sub-pixel SP1, the step layer STPL may be disposed on the second reflective electrode RL2. The step layer STPL may not be disposed in the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be set in consideration of the wavelength of the light of the first color and the distance from the light-emitting element layer EML to the fourth reflective electrode RL4 to facilitate reflection of the light of the first color emitted from the light-emitting element layer EML of the first sub-pixel SP1. In an embodiment, the step layer STPL may be silicon nitride carbon (SiCN) or silicon oxide (SiO x ) type inorganic layer, but the embodiments of the present disclosure are not limited thereto. The thickness of the step layer STPL may be about

[0111] In the first sub-pixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In each of the second sub-pixel SP2 and the third sub-pixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode R13 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0112] In an embodiment, at least one selected from the first to third reflective electrodes RL1 to RL3 may be omitted.

[0113] The fourth reflective electrode RL4 may be disposed on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may be a layer that reflects light from the light emitting element layer EML. The fourth reflective electrode RL4 may include a metal having a high reflectivity to facilitate reflection of light. The fourth reflective electrode RL4 may include aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy as an alloy of silver (Ag), palladium (Pd) and copper (Cu), or an APC alloy and an indium tin oxide stacked structure (ITO / APC / ITO), or made of aluminum (Al), a stacked structure of aluminum and titanium (Ti / Al / Ti), an aluminum and indium tin oxide stacked structure (ITO / Al / ITO), an APC alloy as an alloy of silver (Ag), palladium (Pd) and copper (Cu), or an APC alloy and an indium tin oxide stacked structure (ITO / APC / ITO), but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the thickness of each of the fourth reflective electrodes RL4 may be about 500 Å.

[0114] The tenth interlayer insulating layer INS10 may be disposed on the ninth interlayer insulating layer INS9 and the fourth reflective electrode RL4. In an embodiment, the tenth interlayer insulating layer INS10 may be silicon oxide (SiO x ) type inorganic layer, but the embodiments of the present disclosure are not limited thereto.

[0115] The tenth via hole VA10 may pass through or be arranged to pass through the tenth interlayer insulating layer INS10, and may be respectively connected to the exposed fourth reflective electrode RL4. The tenth via hole VA10 may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or their alloys, or be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or their alloys. Due to the step layer STPL, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the thickness of the tenth via hole VA10 in the first sub-pixel SP1 may be about And the thickness of the tenth via hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 may be about 1000 Å.

[0116] The light emitting element layer EML may be disposed on the light emitting element backplane EBP. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer PDL, each of the plurality of light emitting elements including a first electrode AND, an intermediate layer IL, and a second electrode CAT. Figure 5 The first electrode AND shown in FIG. 1 is shown as being included in the light emitting element back plate EBP, even though the first electrode AND is Figures 10 to 13 It is shown as being disposed on the light emitting element backplane EBP.

[0117] The first electrode AND of each of the plurality of light emitting elements may be disposed on the tenth interlayer insulating layer INS10 and may be connected to the tenth via VA10. The first electrode AND of each of the plurality of light emitting elements may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth via VA10, the first reflective electrode RL1 to the fourth reflective electrode RL4, the first via VA1 to the ninth via VA9, the first metal layer ML1 to the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the plurality of light emitting elements may include at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or their alloys, or may be made of at least one selected from copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd) or their alloys, or may include metal nitride. In an embodiment, for example, the first electrode AND of each of the plurality of light emitting elements may be titanium nitride (TiN).

[0118] The pixel defining layer PDL may be disposed on a portion of the first electrode AND of each of the plurality of light emitting elements. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the plurality of light emitting elements. The pixel defining layer PDL defines first to third emission areas EA1 to EA3.

[0119] The first emission area EA1 may be defined as an area in the first sub-pixel SP1 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The second emission area EA2 may be defined as an area in the second sub-pixel SP2 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light. The third emission area EA3 may be defined as an area in the third sub-pixel SP3 where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked to emit light.

[0120] The pixel defining layer PDL may include first to third pixel defining layers PDL1 to PDL3. The first pixel defining layer PDL1 may be disposed on or cover the edge of the first electrode AND of each of the plurality of light emitting elements, the second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1, and the third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. In an embodiment, each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be silicon oxide (SiO x ) type inorganic layer, but the embodiments of the present disclosure are not limited thereto. Figure 5In the embodiment, the thickness of the second pixel defining layer PDL2 and the thickness of the third pixel defining layer PDL3 are each less than the thickness of the first pixel defining layer PDL1, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the thickness of the first pixel defining layer PDL1, the thickness of the second pixel defining layer PDL2, and the thickness of the third pixel defining layer PDL3 may each be approximately

[0121] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0122] The intermediate layer IL may have a tandem structure including a plurality of intermediate layers IL1 to IL3, and the plurality of intermediate layers IL1 to IL3 respectively emit different lights or emit lights in different wavelength ranges. In an embodiment, for example, the intermediate layer IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked sequentially.

[0123] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0124] The intermediate layer IL may cover the first electrode AND in each opening of the pixel defining layer PDL and cover the pixel defining layer PDL between adjacent sub-pixels SP1 to SP3 , but may also be partially disconnected.

[0125] In an embodiment, in the case where the intermediate layer IL is disconnected between adjacent sub-pixels SP1 to SP3, leakage current between adjacent sub-pixels SP1 to SP3 can be effectively prevented, and a color interference phenomenon can be effectively prevented. The color interference phenomenon refers to a phenomenon in which, for example, a red sub-pixel adjacent to a blue sub-pixel is unintentionally turned on when the blue sub-pixel emits light. The color interference phenomenon occurs due to leakage current, and the color interference phenomenon may occur when a blue sub-pixel and a red sub-pixel having a large difference in pixel driving voltage are adjacent to each other. For example, leakage current refers to a phenomenon in which a portion of the driving current is transmitted to the red sub-pixel through at least some conductive layers of the intermediate layer IL when a driving current is supplied to a light-emitting element of a blue sub-pixel to turn on the blue sub-pixel. If a leakage current occurs, the red sub-pixel may be turned on unintentionally while the blue sub-pixel is turned on.

[0126] The number of intermediate layers emitting different light is not limited to Figure 5 In the embodiment, for example, the intermediate layer IL may include two intermediate layers. In such an embodiment, at least one intermediate layer selected from the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other intermediate layer may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In such an embodiment, a charge generation layer may be provided between the two intermediate layers to supply electrons to one intermediate layer selected from the two intermediate layers and holes to the other intermediate layer.

[0127] In an embodiment, Figure 5 As shown in , the first intermediate layer IL1 to the third intermediate layer IL3 may all be disposed in the first emission area EA1, the second emission area EA2 and the third emission area EA3, but the embodiments of the present disclosure are not limited thereto. In an embodiment, for example, the first intermediate layer IL1 may be disposed in the first emission area EA1, and may not be disposed in the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be disposed in the second emission area EA2, and may not be disposed in the first emission area EA1 and the third emission area EA3. In such an embodiment, the third intermediate layer IL3 may be disposed in the third emission area EA3, and may not be disposed in the first emission area EA1 and the second emission area EA2. In such an embodiment, the first color filter CF1 to the third color filter CF3 of the optical layer OPL may be omitted.

[0128] The second electrode CAT may be disposed on the third intermediate layer IL3. The second electrode CAT may be disposed on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may include a transparent conductive material (TCO) capable of transmitting light, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag, or may be made of a transparent conductive material (TCO) capable of transmitting light, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a semi-transmissive conductive material, such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. In an embodiment in which the second electrode CAT is made of a semi-transmissive conductive material, the light output efficiency of each of the first to third sub-pixels SP1 to SP3 may be increased by a microcavity effect.

[0129] The encapsulation layer TFE may be disposed on the light emitting element layer EML. The encapsulation layer TFE may include one or more inorganic layers to prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign matter such as dust. In an embodiment, for example, the encapsulation layer TFE may include a first encapsulation inorganic layer TFE1, an encapsulation organic layer TFE2, and a second encapsulation inorganic layer TFE3.

[0130] The first encapsulation inorganic layer TFE1 may be disposed on the second electrode CAT, the encapsulation organic layer TFE2 may be disposed on the first encapsulation inorganic layer TFE1, and the second encapsulation inorganic layer TFE3 may be disposed on the encapsulation organic layer TFE2. Each of the first encapsulation inorganic layer TFE1 and the second encapsulation inorganic layer TFE3 may be a multilayer in which silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layer. The encapsulation organic layer TFE2 may be a single layer. Alternatively, the encapsulation organic layer TFE2 may be an organic layer made of or including an organic material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin).

[0131] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL together. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member (such as a transparent adhesive layer or a transparent adhesive resin layer).

[0132] The optical layer OPL includes a plurality of color filters CF1 to CF3, a plurality of lenses LNS, and a filling layer FIL. The color filters CF1 to CF3 may include first to third color filters CF1 to CF3. The first to third color filters CF1 to CF3 may be disposed on the adhesive layer ADL.

[0133] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of the first color, that is, light in a blue wavelength band. The blue wavelength band may be about 370 nanometers (nm) to about 460 nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0134] The second color filter CF2 may overlap with the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of the second color, i.e., light in the green wavelength band. The green wavelength band may be about 480 nm to about 560 nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0135] The third color filter CF3 may overlap with the third emission area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color, i.e., light in a red wavelength band. The red wavelength band may be about 600 nm to about 750 nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0136] The lenses LNS may be disposed on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the lenses LNS may be used to increase the orientation of the display device 10 (see FIG. Figure 4 ) in front of the lens. Each of the lenses LNS may have a cross-sectional shape that is convex upward.

[0137] The filling layer FIL may be disposed on the lens LNS. The filling layer FIL may have a predetermined refractive index so that light may propagate in the third direction DR3 at the interface between the lens LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic layer made of or including an organic material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin).

[0138] The cover layer CVL may be disposed on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin substrate (such as a polyimide resin substrate). In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In such an embodiment, the filling layer FIL may be used to bond the cover layer CVL. In an embodiment where the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. In an embodiment where the cover layer CVL is a polymer resin substrate (such as a resin), the cover layer CVL may be directly applied to the filling layer FIL.

[0139] A polarizer (not shown) may be disposed on the surface of the cover layer CVL. The polarizer may be a structure for preventing visibility reduction due to reflection of external light. The polarizer may include a linear polarizer and a phase delay film. In an embodiment, for example, the phase delay film may be a quarter wave plate (λ / 4 plate), but the embodiments of the present disclosure are not limited thereto. If the visibility reduction caused by reflection of external light is sufficiently improved by the first color filter CF1 to the third color filter CF3, the polarizer may be omitted.

[0140] Figure 6 is a perspective view of a mask MK according to the embodiment. Figure 6 1 is a perspective view showing a state in which one unit mask UM is separated from a plurality of unit masks UM. Figure 6 The mask MK of the embodiment shown in FIG. 1 can be used to deposit reference Figure 5 In the process of at least a portion of the intermediate layer IL of the display panel 410 described above. For example, the intermediate layer IL may be configured to be Figure 5 ) emits light of a different color in each of them.

[0141] Reference Figure 6 The mask MK may include a mask frame MF and a plurality of unit masks UM. A plurality of unit openings COP formed through the mask frame MF along a thickness direction (e.g., a third direction DR3) of the mask MK may be defined in the mask frame MF. The unit masks UM may be disposed to correspond to the unit openings COP, respectively. Each of the unit openings COP may correspond to one display panel 410 (see FIG. 4 ). Figure 4 ). That is, one unit mask UM may be used in a process of depositing one display panel 410. In the present disclosure, the term "unit mask UM" may be replaced with a term such as "mask unit UM".

[0142] Each of the unit masks UM may include a mask body MP and a plurality of holes OP. The holes OP may be formed in the mask body MP and arranged in a matrix form. The holes OP may be defined by passing through the unit mask UM along the thickness direction (e.g., the third direction DR3) of the mask MK. The mask body MP of each of the unit masks UM may include a plurality of first mask grids extending along a first direction DR1 and spaced apart from each other in a second direction DR2 perpendicular to the first direction DR1. In addition, each of the unit masks UM may include a plurality of second mask grids extending along a second direction DR2 perpendicular to the first direction DR1 and spaced apart from each other in the first direction DR1. The first mask grid and the second mask grid may intersect with each other to define the holes OP. In the present disclosure, the term "mask body MP" may be replaced with a term such as "mask support". In the present disclosure, the term "mask grid" may be replaced with a term such as "mask rib". In the present disclosure, a combination of mask grids may be referred to as a term such as "mask film member" or "film member". For example, the film member may be a term referring to a portion used as a blocking portion in one unit mask.

[0143] The unit mask UM may be disposed on the mask frame MF. The unit mask UM and the cell openings COP may be disposed to correspond to each other one by one.

[0144] In embodiments, the area of ​​the mask main body MP of each unit mask UM may be substantially the same as the area of ​​each cell opening COP on a plane (eg, a plane defined by the first direction DR1 and the second direction DR2 ).

[0145] Figure 7 is a schematic cross-sectional view of a mask MK according to the embodiment. Figure 7 The unit mask UM (see Figure 6 )one of the.

[0146] Reference Figure 7, the mask MK according to the embodiment may be a silicon mask, wherein the mask film 730 (ie, the mask grid 731) is formed on a silicon substrate 710 (eg, a silicon wafer substrate). A fine metal mask (FMM) using an invar sheet has been widely used as a conventional deposition mask. However, the problem with FMM is that its pixel position accuracy performance is not enough to manufacture high-resolution pixels. In the mask MK according to the embodiment, the mask film 730 is formed on the silicon substrate 710 using an electroplating method, so that the mask MK can be manufactured with the accuracy of a semiconductor process. The mask MK according to the embodiment can increase the alignment accuracy and can be used to manufacture an organic light emitting diode on silicon (OLEDoS) panel having a high-resolution pixel of about 2000 pixels per inch (PPI) or more. The mask MK according to the embodiment may be an electroformed silicon mask (ESM) in which a mask film 730 is formed on a silicon substrate 710 using an electroplating method.

[0147] The mask MK according to the embodiment may include a silicon substrate 710 (e.g., a semiconductor wafer substrate) included in the mask body MP, a seed metal layer 720 disposed on the silicon substrate 710, and a mask film member 730 disposed on the seed metal layer 720, the mask film member 730 having a plurality of holes OP (i.e., mask openings) defined therethrough. The mask grid 731 of the mask film member 730 may surround or define the holes OP. The holes OP may overlap with the cell openings COP.

[0148] The mask grid 731 of the mask film member 730 may include a plating layer formed using an electroplating method. The mask grid 731 may be disposed on the seed metal layer 720 .

[0149] The seed metal layer 720 may be a single layer or a multilayer, each of which includes or is made of at least one selected from titanium (Ti), titanium nitride (TiN) and copper (Cu). However, the metal material forming the seed metal layer 720 is not limited, and any metal may be used as long as it is used for electroplating or electroforming methods.

[0150] Each of the mask grids 731 may include a plated layer formed by a damascene process (eg, using an electroplating or electroforming method).

[0151] Each of the mask grids 731 may have an inverse tapered shape in which the width increases from the rear surface 7311 to the upper surface 7312. Here, the rear surface 7311 of each of the mask grids 731 may be a surface facing the deposition source DS, and the upper surface 7312 of each of the mask grids 731 may be a surface facing the deposition target substrate (e.g., the display panel 410 (see FIG. 4 ). Figure 4 ) (i.e., the backplane substrate)) or the surface opposite to the rear surface 7311. The mask grids 731 according to the embodiment can reduce shadow defects due to their inverse tapered shape. For example, the tapered angle A1 (see Fig.10 ) can be less than or equal to the deposition incident angle A2 (see Fig.10 ), the incident angle A2 is the angle from the deposition source DS to the hole OP. In an embodiment, for example, the tapered angle A1 of each mask grid 731 can be designed to be in the range of about 60 degrees to about 88 degrees, and the maximum width L2 (see Fig. 9 ) may be less than or equal to about 10 μm, and the maximum thickness L3 (see Fig. 9 ) may be less than or equal to about 15 μm. The mask MK according to the embodiment may reduce shadow defects by reducing the thickness of each mask grid 731 and having a reverse tapered shape.

[0152] The mask grids 731 according to the embodiment may have a sagging problem because their maximum thickness L3 is reduced to less than or equal to about 15 μm. The mask grids 731 according to the embodiment are made of a magnetic metal as a plating layer. Therefore, the use of a magnetic member (not shown) in a depositor (not shown) can effectively prevent the sagging of the mask grid 731, and can improve the alignment accuracy.

[0153] According to an embodiment, the interval between the holes OP may be less than or equal to about 5 μm. In an embodiment, for example, the distance L1 between adjacent holes OP (see Fig. 9 ) (or the distance between centers of adjacent holes OP) may be less than or equal to about 5 μm.

[0154] According to an embodiment, each side surface of each mask grid 731 may include a first concave curved surface 901 (see Fig. 9 In the mask MK according to the embodiment, since each of the mask grids 731 constituting the mask film member 730 has an inverse tapered shape and a concave side surface, it is possible to reduce shadow defects caused by accumulation of deposition material on the surface of the mask MK during a deposition process.

[0155] For reference, part of the deposited material may accumulate on the surface of each mask grid 731 during the deposition process, and such material accumulation may increase the shadow area. In the mask MK according to the embodiment, each side surface of each mask grid 731 has a concave surface, so that each side surface of each mask grid 731 can provide a space in which the deposited material can be accumulated. That is, in the mask MK according to the embodiment, since each side surface of each mask grid 731 has a concave surface, even if material accumulation occurs, the tapered angle A1 of each mask grid 731 can be maintained at the initial angle, and the shadow defect can be reduced.

[0156] The deposition mask MK according to the embodiment may be effectively used to manufacture a high-resolution organic light-emitting display device, and may have improved reliability by improving pixel position accuracy.

[0157] Furthermore, the deposition mask MK according to the embodiment may reduce shadow defects and accumulation of deposition materials on the mask MK.

[0158] In addition, the deposition mask MK according to the embodiment can effectively prevent itself from sagging by applying the mask grid 731 (or mask rib) using a magnetic metal. Therefore, the alignment accuracy of the mask MK can be improved, and the unevenness (mura) defect caused by the sagging of the mask MK can be effectively prevented.

[0159] In addition, the deposition mask MK according to the embodiment has improved rigidity, thereby increasing the number of times the deposition mask MK is used and reducing costs.

[0160] Figure 8 is a schematic cross-sectional view of a mask MK according to the embodiment.

[0161] In addition to the mask grid 731 being made of an inorganic layer and the oxide layer 810 being replaced by Figure 7 In addition to the seed metal layer 720, Figure 8 Examples and Figure 7 For ease of description, the description of Figure 8 of Figure 7 Any repeated detailed description of the same or similar features of the embodiments of the present invention will be described below only. Figure 8 Examples and Figure 7 The embodiments are different.

[0162] Reference Figure 8 According to the embodiment, the mask MK may include a silicon substrate 710 (e.g., a semiconductor wafer substrate) used as a mask body, an oxide layer 810 disposed on the silicon substrate 710, and a mask film member 730 disposed on the oxide layer 810, the mask film member 730 having a plurality of holes OP (i.e., mask openings) defined therethrough.

[0163] The mask film 730 may include a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ), or at least one material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) is made of at least one material.

[0164] The mask MK according to the embodiment may be a fine silicon mask (FSM) in which a mask film member 730 formed by applying a photolithography process and a dry etching method to an inorganic layer is disposed on a silicon substrate 710 .

[0165] Fig. 9 is a perspective view of a portion of the mask MK according to the embodiment. Fig.10 is a cross-sectional view for explaining a deposition process performed using the mask MK according to the embodiment.

[0166] Fig. 9 The mask MK shown in FIG. 1 may be Figure 7 The portion of the mask MK shown in FIG. Figure 8 Part of the mask MK is shown in . Fig.10 It is shown that when the mask MK is in contact with the display panel (eg, the semiconductor substrate SSUB (see Figure 5 The display panel may be in a state where the deposition material evaporates from the deposition source DS when the semiconductor backplane SBP (see Figure 5 ) and the light emitting element backplane EBP, and then the light emitting element layer EML (see Figure 5 ), and the mask MK according to the embodiment can be used to form the light emitting element layer EML on the display panel in the above state.

[0167] Reference Fig. 9 and Fig.10 The mask film member 730 of the mask MK according to the embodiment may be provided with a plurality of holes OP, and the holes OP may be surrounded or defined by the mask grid 731. The deposition material evaporated from the deposition source DS may be deposited on the surface of the display panel as a target deposition substrate through the holes OP provided in the mask MK.

[0168] In an embodiment, the mask grid 731 may be provided by Figure 7 In such an embodiment, for example, the mask grid 731 may include a material selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiO x ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ) at least one material.

[0169] In an embodiment, the mask grid 731 may be provided by Figure 8 In the embodiment shown in FIG. 8 , an oxide layer 810 is formed on a silicon substrate 710. In such an embodiment, for example, the mask grid 731 may include at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar alloy.

[0170] According to an embodiment, each side surface of each mask grid 731 may include a first concave curved surface 901. In the mask MK according to an embodiment, since each of the mask grids 731 constituting the mask film member 730 has an inverse tapered shape and a concave side surface, it is possible to reduce shadow defects caused by accumulation of deposition material on the side surface of the mask MK during a deposition process.

[0171] In the mask MK according to the embodiment, since each side surface of each mask grid 731 has a concave surface, each side surface of each mask grid 731 can provide a space in which the deposition material can be accumulated. That is, in the mask MK according to the embodiment, since each side surface of each mask grid 731 has a concave surface, even if material accumulation occurs, the tapered angle A1 of each mask grid 731 can be maintained at the initial angle, and the shadow defect can be reduced. Fig.10 Reference numeral 1001 in FIG. 7 represents a portion of the deposition material accumulated on the concave side surface of each mask grid 731. Fig.10 As indicated by reference numeral 1001 in FIG. 1 , during the deposition process, a portion of the deposition material may accumulate on the concave side surface (i.e., the first concave curved surface 901) of the mask grid 731. Even if the deposition material accumulates, it can be seen that the tapered angle A1 of each mask grid 731 and the deposition incident angle A2 from the deposition source DS to the aperture OP are maintained at about 60 degrees or more.

[0172] Typically, after being used in a process of depositing a certain number of light-emitting element layers EML of a display panel, the mask MK is replaced. In an embodiment of the present disclosure, since the side surface of each mask grid 731 has a concave shape, the number of times the mask MK is used can be increased, and the manufacturing cost can be reduced. In an embodiment, the side surface of each mask grid 731 can be formed by additional laser processing (e.g., laser ablation).

[0173] According to an embodiment, the mask MK may be designed to manufacture a high-resolution organic light emitting display device.

[0174] According to an embodiment, the distance L1 between adjacent holes OP (see Fig. 9 ) can be less than or equal to about 5 μm.

[0175] According to an embodiment, the tapered angle A1 of each mask grid 731 may be in the range of about 60 degrees to about 88 degrees so that the deposition incident angle A2 within the depositor is greater than or equal to about 60 degrees, thereby minimizing the shadow area.

[0176] According to an embodiment, the maximum width L2 of each mask grid 731 may be less than or equal to about 10 μm.

[0177] According to an embodiment, the maximum thickness L3 of each mask grid 731 may be less than or equal to about 15 μm.

[0178] According to an embodiment, the depth L4 (see FIG. 14 ) of the first concave curved surface 901 disposed on each side surface of each mask grid 731 is Fig. 9 ) may be less than or equal to about 20% of the thickness of the mask grid 731. Here, the depth L4 of the first concave curved surface 901 may be defined as a distance of the first concave curved surface 901 from an imaginary plane that contacts an end portion of the upper surface 7312 corresponding thereto and an end portion of the rear surface 7311 corresponding thereto.

[0179] Fig.11 is a cross-sectional view showing mask grids 731 each including a lower curved surface 902 in a mask MK according to an embodiment used in a deposition process.

[0180] In addition to the rear surface 7311 of each mask grid 731 including a second concave curved surface (lower concave curved surface) 902, Fig.11 Examples and Figure 7 , Figure 8 and Fig.10 For ease of description, the embodiments of Fig.11 of Figure 7 , Figure 8 and Fig.10Any repeated detailed description of the same or similar features of the embodiments of the present invention will only be described below. Fig.11 Examples and Figure 7 , Figure 8 and Fig.10 The embodiments are different.

[0181] Reference Fig.11 , each mask grid 731 of the mask MK according to the embodiment has an inverse tapered shape, and each of the side surfaces includes a first concave curved surface 901. In the embodiment, as Fig.11 As shown in FIG. 1 , each mask grid 731 may further include a rear surface 7311 (see Fig.10 ) on the second concave curved surface 902. The back surface 7311 of each mask grid 731 may be a surface facing the deposition source DS. The mask MK according to an embodiment may reduce shadow defects caused by material accumulation by allowing deposition material to accumulate on the first concave curved surface 901 and the second concave curved surface 902 during a deposition process. Fig.11 In FIG. 1 , reference numeral 1101 denotes a portion of the deposition material accumulated on the first concave curved surface 901 of each mask grid 731. Fig.11 , reference numeral 1102 denotes a portion of the deposition material accumulated on the second concavely curved surface 902 of each mask grid 731 .

[0182] Fig.12 is a cross-sectional view showing mask grids 731 each having a plurality of curved surfaces included in each side surface in a mask MK according to an embodiment used in a deposition process.

[0183] In addition to each side surface of each mask grid 731 including a plurality of first concave curved surfaces 1210, Fig.12 Examples and Figure 7 , Figure 8 and Fig.10 For ease of description, the embodiments of Fig.12 of Figure 7 , Figure 8 and Fig.10 Any repeated detailed description of the same or similar features of the embodiments of the present invention will only be described below. Fig.12 Examples and Figure 7 , Figure 8 and Fig.10 The embodiments are different.

[0184] Reference Fig.12, each mask grid 731 of the mask MK according to the embodiment may have an inverted tapered shape, and each of the side surfaces may include a plurality of first concave curved surfaces 1210. A plurality of first concave curved surfaces (i.e., a plurality of first curved surfaces) 1210 may be provided on each side surface of each mask grid 731, and may extend from the bottom to the top of each side surface of each mask grid 731. In an embodiment, for example, assuming that each side surface of each mask grid 731 includes n first curved surfaces 1210, a first sub-curved surface 1211 may be provided at the bottom of each side surface, and a second sub-curved surface 1212 may be provided at the upper end of the first sub-curved surface 1211 to extend from the end of the first sub-curved surface 1211. Here, n is a natural number greater than 1. A third sub-curved surface 1213 may be provided at the upper end of the second sub-curved surface 1212 to extend from the end of the second sub-curved surface 1212. In this way, a plurality of first curved surfaces 1210 may be included in each side surface of each mask grid 731.

[0185] According to an embodiment, the first curved surfaces 1210 may all have substantially the same curvature as each other, but the present disclosure is not necessarily limited thereto.

[0186] According to an embodiment, the first curved surfaces 1210 may all have substantially the same depth as one another, but the present disclosure is not necessarily limited thereto.

[0187] Fig.13 is a cross-sectional view showing mask grids 731 each formed in multiple layers including a metal layer in a mask MK according to an embodiment used in a deposition process.

[0188] In addition to each mask grid 731 including a plurality of layers in which inorganic layers 1320 and metal layers 1310 are alternately stacked, Fig.13 Examples and Fig.12 For ease of description, the description of Fig.13 of Fig.12 Any repeated detailed description of the same or similar features of the embodiments of the present invention will be described below only. Fig.13 Examples and Fig.12 The embodiments are different.

[0189] Reference Fig.13 Each mask grid 731 of the mask MK according to the embodiment may include a multilayer (multilayer structure) in which an inorganic layer 1320 and a metal layer 1310 are alternately stacked. Here, the inorganic layer 1320 may include a metal selected from silicon (Si), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxide (SiOx ), titanium oxide (TiO x ), amorphous silicon (a-Si) and aluminum oxide (AlO x ). Here, the metal layer 1310 may include at least one material selected from copper (Cu), nickel (Ni), aluminum (Al), tungsten (W), molybdenum (Mo), titanium (Ti), and Invar alloy. In such an embodiment, each of the inorganic layer 1320 and the metal layer 1310 may include a corresponding sub-curved surface of the first curved surface 1210.

[0190] In an embodiment, Fig.13 As shown in , each mask grid 731 includes two metal layers 1310 and three inorganic layers 1320, but the present disclosure is not limited thereto. In an embodiment, for example, each mask grid 731 may have any stacking order as long as each mask grid 731 includes at least one metal layer 1310 and at least one inorganic layer 1320.

[0191] According to an embodiment, each mask grid 731 may include a metal layer 1310 to increase the rigidity of the mask MK. In such an embodiment, since the metal layer 1310 includes a magnetic metal, it is possible to prevent sagging of the mask MK by using a magnetic member within the depositor, thereby improving the alignment accuracy of the mask MK and preventing uneven defects caused by sagging of the mask MK.

[0192] The present invention should not be construed as being limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the present invention to those skilled in the art.

[0193] While the invention has been particularly shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A deposition mask, wherein: The deposition mask comprises: a mask body comprising a silicon substrate, wherein a plurality of holes are defined through the mask body; and wherein the mask body further comprises a plurality of mask grids extending to define the plurality of holes, wherein a cross-section of each of the plurality of mask grids has an inverted tapered shape having a width that increases from a rear surface to an upper surface of the deposition mask, and each side surface of each of the plurality of mask grids defining the plurality of holes includes a first concave curved surface.

2. The deposition mask according to claim 1, wherein: A distance between adjacent holes in the plurality of holes is less than or equal to 5 μm.

3. The deposition mask according to claim 1, wherein: The taper angle of each of the plurality of mask grids is in a range of 60 degrees to 88 degrees.

4. The deposition mask according to claim 1, wherein: A maximum width of each of the plurality of mask grids is less than or equal to 10 μm.

5. The deposition mask according to claim 1, wherein: A maximum thickness of each of the plurality of mask grids is less than or equal to 15 μm.

6. The deposition mask according to claim 1, wherein: The rear surface of each of the plurality of mask grids includes a second concavely curved surface.

7. The deposition mask according to claim 1, wherein: A depth of the first concave curved surface included in each of the side surfaces of each of the plurality of mask grids is less than or equal to 20% of a thickness of each of the plurality of mask grids.

8. The deposition mask according to claim 1, wherein: Each of the plurality of mask grids includes at least one material selected from the group consisting of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon, and aluminum oxide.

9. The deposition mask according to claim 8, wherein: Each of the plurality of mask grids further comprises at least one material selected from the group consisting of copper, nickel, aluminum, tungsten, molybdenum, titanium, and Invar alloy.

10. The deposition mask according to claim 1, wherein: Each of the side surfaces of the each of the plurality of mask grids includes a plurality of first curved surfaces instead of the first concave curved surface.

11. A deposition mask, wherein: The deposition mask comprises: a mask body comprising a silicon substrate, wherein a plurality of holes are defined through the mask body; and wherein the mask body further comprises a plurality of mask grids extending to define the plurality of holes, wherein a cross-section of each of the plurality of mask grids has an inverted tapered shape having a width that increases from a rear surface to an upper surface of the deposition mask, and each side surface of each of the plurality of mask grids defining the plurality of holes includes a plurality of first concave curved surfaces.

12. The deposition mask according to claim 11, wherein: A distance between adjacent holes in the plurality of holes is less than or equal to 5 μm.

13. The deposition mask according to claim 11, wherein: The taper angle of each of the plurality of mask grids is in a range of 60 degrees to 88 degrees.

14. The deposition mask according to claim 11, wherein: A maximum width of each of the plurality of mask grids is less than or equal to 10 μm.

15. The deposition mask according to claim 11, wherein: A maximum thickness of each of the plurality of mask grids is less than or equal to 15 μm.

16. The deposition mask according to claim 11, wherein: The rear surface of each of the plurality of mask grids includes a second concavely curved surface.

17. The deposition mask according to claim 11, wherein: A depth of each of the plurality of first concave curved surfaces included in each of the side surfaces of the each of the plurality of mask grids is less than or equal to 20% of a thickness of the each of the plurality of mask grids.

18. The deposition mask according to claim 11, wherein: Each of the plurality of mask grids includes an inorganic layer including at least one material selected from the group consisting of silicon, silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, amorphous silicon, and aluminum oxide.

19. The deposition mask according to claim 18, wherein: The plurality of mask grids also each include a metal layer including at least one material selected from the group consisting of copper, nickel, aluminum, tungsten, molybdenum, titanium, and Invar alloy.

20. The deposition mask according to claim 19, wherein: Each of the plurality of mask grids has a multi-layer structure in which the inorganic layers and the metal layers are alternately stacked.

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