Method for assessing bending stiffness of high aspect ratio nanostructures
By generating test patterns on semiconductor substrates and measuring slump using electron beam microscopes, the problem of evaluating mechanical properties of high aspect ratio nanostructures is solved, and rapid evaluation and improvement of process uniformity is achieved.
Patent Information
- Application Number
- CN202411077687.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-12
- Filing Date
- 2024-08-07
- Publication Date
- 2025-02-21
AI Technical Summary
The prior art is difficult to quickly and efficiently evaluate the mechanical properties of high aspect ratio nano-size structures on semiconductor substrates, especially in large-scale production and process steps, resulting in pattern collapse and inhomogeneity of mechanical properties.
By generating multiple test patterns in different regions of the semiconductor substrate, each of which includes a regular array of high aspect ratio structures, the collapse rate of the array is scanned and measured by electron beam microscope, thereby evaluating the bending stiffness of the structure.
A rapid evaluation of the bending stiffness of high aspect ratio nanostructures is achieved, which can identify and eliminate inhomogeneities in lithography and etching processes, and improve process uniformity and production efficiency.
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Figure CN119492766A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to semiconductor processing, in particular to the production of high aspect ratio nanoscale structures, and the characterization of the mechanical properties of these structures. Background Art
[0002] With the continued miniaturization of structures in semiconductor processing, tall and narrow upright structures like fins or pillars are being fabricated on wafers. These structures are called high aspect ratio nanoscale structures, hereinafter referred to as nanoscale structures or nanostructures. For example, pillars are known to be produced with diameters on the order of a few nanometers to tens of nanometers and heights on the order of 100 nanometers to 10 micrometers, i.e., aspect ratios higher than 10:1. Similar aspect ratios can be obtained for fin-shaped structures with widths on the order of a few nanometers or tens of nanometers. For such structures, bending stiffness is an important mechanical property because it determines the integrity of the structure during the various process steps.
[0003] For example, during wet cleaning processes, surface tension exerted by the rinse liquid often causes the collapse of high-aspect-ratio nanostructures arranged in a regular array. This phenomenon is often referred to as pattern collapse. It has been determined that there is a correlation between the mechanical stiffness of the structures and the pattern collapse rate, which is a value that represents the number of structures in a given array that have collapsed.
[0004] It is possible to determine the bending stiffness of each individual structure by applying destructive methods, such as selectively removing a structure from an array by focused ion beam (FIB) and then measuring the force and deflection relationship in a transmission electron microscope (TEM). However, these methods have low throughput and are not suitable for rapid evaluation of the mechanical properties of nanostructures produced on a substrate, such as a 300 mm diameter process wafer comprising hundreds of semiconductor dies, each of which comprises a large number of high aspect ratio nanostructures arranged in various patterns. There are also non-destructive methods, for example, mechanical models can be built using 3D geometries obtained by scattering measurements to calculate the average bending stiffness of high aspect ratio structures. However, scattering measurements require large areas of about 40 μm in size with uniform patterning, and in some cases, mechanical models may not be easily available for structures with complex stacking and geometry.
[0005] It is known that the mechanical properties of structures having the same design dimensions may vary significantly across a wafer as a result of the degree of non-uniformity of the lithography and etching techniques used to produce each structure. It is therefore highly desirable to obtain knowledge of this variation in mechanical properties without reverting to destructive measurement techniques and without requiring precise 3D profilometry of the structure in question. Summary of the invention
[0006] The present invention relates to a method disclosed in the accompanying claims. The present invention enables the evaluation of the bending stiffness of high aspect ratio nanoscale structures, which are arranged in a plurality of test patterns produced by lithography and etching in a corresponding plurality of different areas of a semiconductor substrate. Each test pattern comprises at least one regular array of high aspect ratio structures, i.e. an array formed of mutually identical structures with a constant gap between any pair of adjacent structures in the array, such as a rectangular or hexagonal array. The array is characterized by a plurality of parameters, including the in-plane dimensions of the structures, their height, the material of the structures, and the gaps between adjacent structures in the array. "In-plane dimensions" refers to dimensions measured in a plane parallel to the plane in which the structures lie, such as the diameter of a pillar structure or the width of a fin structure measured at the mid-height of each structure.
[0007] The method includes:
[0008] scanning the array in a plurality of test patterns by an electron beam generated according to a set of beam conditions that are the same for each pattern,
[0009] Export images of each array by electron beam microscopy, and
[0010] The collapse rate caused by the electron beam is determined from each image, and the collapse rate is a value between 0 and 1, indicating the percentage of structures in each array that have collapsed under the influence of the electron beam scan. The collapse rate caused by the electron beam indicates the bending stiffness of the structure. The term "indication" covers various embodiments, for example, embodiments with a collapse rate of 0 or 1, indicating that the stiffness is sufficient to withstand processes that exhibit similar effects to the electron beam on the test pattern. According to other embodiments, the electron beam is configured to cause various collapse rates (0 < collapse rate < 1) of the same structure distributed on the substrate or wafer by wafer. The latter embodiment can be applied to determine the non-uniformity or variation of the patterning process in terms of the lithography and etching processes used to generate the test pattern. This information can then be used to eliminate the non-uniformity from the pattern collapse measurement, which is applied to evaluate the uniformity of another process (such as a wet cleaning process). In other embodiments, the electron beam is configured to cause and compare the collapse rates of structures with different geometries (such as different CDs, gaps and heights) or different materials. This enables the relative strength of any high aspect ratio structure to be compared. Throughout the specification and the appended claims, the term "high aspect ratio nanoscale structure" refers to a structure characterized by an in-plane critical dimension, such as a diameter or width, which is on the order of a few nanometers to tens of nanometers and a height significantly higher than the in-plane critical dimension. According to a preferred embodiment, the height is at least 3 times the in-plane critical dimension. According to further embodiments, the height is at least 5 times or at least 10 times the in-plane critical dimension.
[0011] The present invention relates in particular to a method for evaluating the bending stiffness of high aspect ratio nanoscale structures arranged in a plurality of test patterns produced by photolithography and etching in a respective plurality of different areas of a semiconductor substrate, each test pattern comprising a regular array of said structures, said method comprising the following steps:
[0012] scanning the regular array of the plurality of test patterns with an electron beam generated according to a set of beam conditions that are the same for each array,
[0013] from scanning of the array, deriving an image of the array in each test pattern by electron beam microscopy,
[0014] An electron beam induced collapse rate is determined from each of the images, the collapse rate being a value between 0 and 1 representing the percentage of structures in each array that have collapsed under the influence of the electron beam scan, and wherein the electron beam induced collapse rate is indicative of the bending stiffness of the structures.
[0015] According to an embodiment, one or more parameters defining the array exhibit variations between different test patterns generated in respective different regions of the substrate, and wherein beam conditions are configured such that the variations result in corresponding variations in collapse rate.
[0016] According to an embodiment, the one or more parameters that exhibit variation are one or more of: the in-plane dimensions of the structures, the height of the structures, the material of the structures, the gaps between adjacent structures in the array.
[0017] According to an embodiment, the beam conditions are configured to match the effects of a semiconductor process applicable on the substrate on the collapse rate of structures in the array.
[0018] According to an embodiment, the array in the test pattern is generated based on the same design pattern formed by an array of structures characterized by one or more in-plane design dimensions, and the test pattern is generated by applying the same etching recipe.
[0019] According to one embodiment, each of the test patterns generated in the plurality of regions of the substrate, respectively, comprises a plurality of regular arrays generated based on a plurality of design patterns, the plurality of design patterns being characterized by a respective plurality of values of a design dimension in at least one plane and / or a gap between adjacent structures, wherein the plurality of values are distributed within a given range.
[0020] According to an embodiment, the collapse rate is recorded in the form of a curve representing the collapse rate as a function of the plurality of values in the central region, the middle region and the edge region of the substrate.
[0021] According to an embodiment, the test pattern is generated using a mask configured to print a device pattern on a plurality of die regions on the substrate, the mask comprising a metrology target included in a field of view of a lithography tool for printing the device pattern, and the target is configured to generate the test pattern in the respective die regions.
[0022] According to an embodiment, the value of the bending stiffness is derived from the electron beam induced collapse rate based on a previously determined relationship between collapse rate and stiffness.
[0023] The present invention also relates to a method for evaluating process uniformity of a process applicable to a semiconductor substrate, the method comprising the following steps:
[0024] a plurality of test patterns are generated in respective plurality of different regions of the substrate by a photolithography and etching sequence, each pattern comprising a regular array of high aspect ratio nano-sized structures, wherein the array is generated based on the same design pattern, and wherein the test patterns are generated by applying the same etching recipe, and wherein the photolithography and etching sequence exhibits a degree of non-uniformity such that one or more parameters defining the array exhibit variation between different test patterns generated in respective different regions of the substrate,
[0025] applying the method according to the invention to said plurality of arrays, thereby obtaining a plurality of collapse rate measurements for said respective plurality of arrays,
[0026] The process was performed on:
[0027] the substrate, wherein the test pattern further comprises at least one copy of the array in the respective plurality of different regions, or
[0028] another substrate having the same size as the substrate and including a copy of the array in the same plurality of different regions,
[0029] determining a collapse rate caused by the process to the image of the corresponding copy of the array,
[0030] The electron beam induced collapse rate is used in order to eliminate the effect of the non-uniformity of the lithography and etching sequence from the process induced collapse rate.
[0031] According to an embodiment of a method for evaluating process uniformity:
[0032] Each test pattern comprises said array generated based on a plurality of design patterns of a plurality of regular arrays, said design patterns being characterized by a corresponding plurality of values of a design dimension in a plane, wherein said values are distributed within a given range,
[0033] The electron beam induced collapse rate is recorded in the form of a curve, which represents the collapse rate as a function of the design dimensions in the center region, the middle region and the edge region of the substrate,
[0034] The process-induced collapse rate is also recorded in the form of a curve, which represents the collapse rate as a function of the design dimensions in the center region, the middle region and the edge region of the substrate,
[0035] The process uniformity is evaluated based on whether the horizontal shifts between the curves corresponding to the center region, the middle region, and the edge region are the same for the process-induced collapse rate and the electron beam-induced collapse rate.
[0036] According to an embodiment of the method for evaluating process uniformity, the process is a wet cleaning process or a deposition process. BRIEF DESCRIPTION OF THE DRAWINGS
[0037] Figure 1a and 1b The ability to scan an electron beam across a regular pattern of nanopillars to induce pattern collapse is demonstrated.
[0038] Figure 2a and 2b The same capability is demonstrated with an array of nano-sized fins.
[0039] Figure 3 The measurement results of the electron beam-induced collapse rate of nano-sized pillars as a function of the bending stiffness of the pillars are illustrated.
[0040] Figures 4a to 4c A process wafer is illustrated which is provided with printing and etching metrology targets suitable for use in the method according to the invention.
[0041] Figure 5a and 5b A suitable calibration procedure according to an embodiment of the present invention is explained. DETAILED DESCRIPTION
[0042] It is known that, by scanning the array with an electron beam in a scanning electron microscope, the pattern collapse in the regular array of high aspect ratio nanostructures can be intentionally induced. For example, reference "Mechanism of nanostructure movement under an electron beam and its application in patterning (mechanism of nanostructure movement under electron beam and its application in patterning)", Semira et al., Physical Review B 83235438 (2011). Beam conditions can be selected so that at least a portion of the structure in the array is bent or deflected due to interaction with the beam. The image obtained from the microscope reveals the collapsed structure, and enables it to be counted to obtain a value called collapse rate, which can be expressed as a number between 0 and 1, which is defined as the ratio of the number of collapsed structures in a given array to the total number of structures in the array.
[0043] Figure 1a and 1b Examples of SEM images before and after pattern collapse in an array of nanometer-sized pillars are illustrated. The first image was obtained by applying an electron beam with insufficient power to cause pattern collapse. Pattern collapse as shown in the second image can be caused, for example, by increasing the beam current and / or exposure time. Figure 2a and 2b As shown, the same effect can be achieved in an array of fin-shaped nanoscale structures.
[0044] This intentionally induced pattern collapse phenomenon is applied in the method of the present invention to quantify the difference in bending stiffness of high aspect ratio nanostructures on a substrate and / or between substrates. Figure 3 A graph including a plurality of data points is illustrated, each data point representing an inventor's Figure 1a Results of measurements on an array of nanosized pillars similar to the array shown, where the average bending stiffness of each pillar in the array varies within a given range. The Y-axis of the graph represents the collapse rate as a result of scanning the array with an electron beam that is identical in terms of beam conditions. The X-axis represents the average bending stiffness of each pillar in the array. The pillars are modeled using a mechanical model based on a conical profile obtained by scattering measurements on the array. The graph shows that there is a correlation between the collapse rate induced by the electron beam and the average stiffness of the pillars. Under identical beam conditions, higher collapse rates are observed for structures with lower average bending stiffness.
[0045] According to the present invention, test patterns formed by high aspect ratio nano-size structures are generated in different regions of the substrate. Each test pattern includes at least one regular array of the structures. The arrays of test patterns generated in the regions are scanned by an electron beam generated according to a set of beam conditions that are the same for each scan. These beam conditions include the following: beam current, exposure time (which can also be expressed as a number of frames), field of view, landing energy, scanning rate, interlaced scanning. The array is configured so that the collapse rate caused by the electron beam between 0 and 1 can be determined with a sufficiently high resolution, so that the change in the collapse rate within the range of 0 to 1 can be measured. This mainly requires that the number of structures in each array is high enough. The optimal number may vary depending on the shape and size of the structure. As shown in Figures 1 and 2, the appropriate number ranges from about 100 to several hundred. Each array can be a rectangular array as shown in Figures 1 and 2, or any other type of regular array, such as an array of structures arranged according to a hexagonal packing arrangement. By scanning the arrays in different regions of the substrate, an image of the array is obtained by an electron beam microscope, and the collapse rate is determined from each image by counting the number of collapsed structures. The array is produced by photolithography and etching according to a given set of design dimensions, including the in-plane dimensions of the structures in the array, the height of the structures, and the gaps between adjacent structures.
[0046] According to an embodiment of the present invention, each test pattern is obtained by printing and etching the same pattern multiple times in different areas of the substrate surface, applying the same photolithography and etching conditions in each area, wherein at least one array in each test pattern (i.e., in each area of the substrate) is defined by the same set of design dimensions, including the in-plane dimensions and height of the structure.
[0047] The repeating test pattern may be, for example, a large array of identical structures with a constant gap between adjacent structures. The size of the array may be in the order of tens of micrometers. Thus, the large array comprises multiple copies of the same smaller array comprising, for example, hundreds of structures, such that collapse rate measurements may be performed on multiple of the multiple copies. According to another embodiment, the repeating test pattern may comprise multiple arrays defined by different in-plane design dimensions, such as different design widths of an array of fin-shaped structures, or different gaps between adjacent structures.
[0048] According to other embodiments, the test patterns generated in different areas may differ in the type of structures, their geometry and / or the material of the structures. This may be achieved by applying different lithography and / or etching conditions in one or more of the different areas, and / or by applying different lithography masks for generating the different test patterns, and / or by generating one or more of the different test patterns in areas consisting of different materials. The determination of the collapse rate over one or more arrays within the test pattern enables an assessment of the bending stiffness of the structures included in the test pattern. The term "assessment" comprises many embodiments and is not limited to the actual numerical determination of the bending stiffness. If the relationship between collapse rate and stiffness has been predetermined, for example Figure 3 The latter is possible if the curve is in the form shown. In this case, the curve can be used to derive the stiffness from measurements of the electron beam-induced collapse rate.
[0049] However, the method is also applicable when, for example, the actual stiffness value is unknown if a mechanical model of the structure is not available. One way to apply the method in this way is to verify whether the structures in the test pattern can withstand a specific semiconductor process, such as a wet cleaning step, without actually performing the process. As mentioned in the introduction, a wet cleaning process can cause pattern collapse in a regular array of high aspect ratio nanoscale structures. This may also be the case for other processes. For example, certain deposition processes, such as flowable CVD (chemical vapor deposition), may also cause pattern collapse.
[0050] According to one embodiment, electron beam conditions are selected to match the effect of a given process on a test pattern comprising an array characterized by a given set of design dimensions. By applying these electron beam conditions to various test patterns distributed on a wafer, it can be verified whether these test patterns can withstand the corresponding process by evaluating the collapse rate caused by the electron beam. If the collapse rate is zero across the entire wafer, the process can be applied. If the collapse rate in at least some areas of the wafer is higher than zero, another process should be selected.
[0051] Another application of the method is to assess and compare the relative strength of structures with different geometries. For example, applying the same electron beam conditions to different structures with unknown mechanical properties allows for a rapid assessment of their relative strength compared to a reference structure.
[0052] According to other embodiments, the electron beam conditions are selected to reveal variations in the stiffness of the structure across the substrate. It is known that when a regular array of structures characterized by the same in-plane design dimensions is reproduced multiple times on a wafer, deviations in one or more of the in-plane design dimensions are inevitable, and such deviations are different in different areas of the substrate. Uneven etching may also result in variations in the height of the structure. Such dimensional differences can result in differences in the bending stiffness of the structure, and it is therefore important for the designer to be able to quantify such differences.
[0053] Therefore, according to embodiments of the present invention, the beam conditions are configured such that the collapse rate of at least one array of test patterns reproduced according to the same design dimensions in different regions of the substrate falls within a suitable range, preferably between 0 and 1, more preferably between 0.2 and 0.8. In other words, suitable electron beam conditions according to these embodiments are determined by the requirement that the electron beam conditions enable sufficient sensitivity to compare the measured collapse rate variations across the wafer or from wafer to wafer.
[0054] Electron beam conditions that affect the collapse rate include: beam current, exposure time, field of view, landing energy, scanning rate. Therefore, it is preferred to select beam conditions for a given purpose (e.g., revealing the effect of stiffness variation or matching a given process) by setting or changing one or more of these conditions.
[0055] According to an embodiment of the present invention, the same test pattern is part of a metrology target included in a field of view of a lithography tool used to produce a plurality of semiconductor dies on a semiconductor wafer. Figure 4a A process wafer 1 is illustrated, which may be a silicon wafer known in the art, such as a standard 300 mm process wafer. Semiconductor dies 2 are produced on a plurality of dedicated areas of the wafer. One die area is enlarged and shown in FIG. Figure 4b In the central portion 3 of the die area 2, a given layout of active devices such as transistors and diodes is manufactured by a series of process steps including lithography and etching steps, which are configured to produce a regular array of high aspect ratio nanostructures as described above. It is known to include metrology targets in the lithography masks designed to produce such regular arrays. The targets are included in the field of view of the die, but outside the active device area 3, for example in the upper left corner of the die area 2, as shown in Figure 4.
[0056] Metrology targets applicable in the methods of the present invention may include test patterns in the form of one or more regular arrays of high aspect ratio nanostructures. Examples of such targets 4 are Figure 4c3. The target is designed to produce an array of fins 5 having specific design dimensions in terms of the width and length of the fins and the gaps between adjacent parallel fins. These dimensions represent the dimensions of the array included in the active area 3 of the die. The critical dimension (CD) of the fin is defined as the width of the fin. In the example shown, the target includes a single array characterized by a single design CD, but the target may include multiple arrays characterized by the same or different design CDs and possibly different fin lengths and gaps. As described above, the lithography and etching processes may exhibit a certain degree of non-uniformity across the wafer, resulting in deviations in the actual CD of the printed and etched structures from the design CD. This, in turn, results in variations in the bending stiffness of the fins.
[0057] According to an embodiment of the invention, this variation is quantified by scanning the target array 4 in each die area 2 with an electron beam after the array is created on the wafer by lithography and etching. The beam conditions are selected so that the beam causes measurable differences in collapse rate as a function of differences in the actual CD on the wafer. The collapse rate is measured on an image obtained by scanning the target pattern in a SEM tool.
[0058] From individual images of the target array, the collapse rate is determined by counting the number of collapsed fins in each image. The collapse rate can be mapped onto the various dies of the wafer, producing a map that reveals differences in the bending stiffness of structures in active regions having the same or similar design CDs and arranged in an array similar to that included in target 4.
[0059] One useful application of the invention relates to the determination of process uniformity on a wafer of semiconductor processing steps performed on the wafer. For example, the effect of a wet cleaning step should be as uniform as possible, i.e. the cleaning action should be the same in every area of the wafer. As mentioned in the introduction, it is known that a wet cleaning step causes pattern collapse, so measuring the collapse rate of a test pattern formed by high aspect ratio nano-sized structures after performing this process on a wafer is one way to determine process uniformity. However, due to the variation in the size of the individual structures on the wafer, it is difficult to correctly interpret the collapse rate measurement. The method of the invention provides the possibility to determine this variation before performing the cleaning process and thereby determine the baseline correction to be applied to the collapse rate caused by the cleaning process. Thus, the method of the invention allows calibrating the wafer with respect to the variation in intrinsic bending stiffness, so that the effect of said variation can be eliminated from the collapse rate caused by the processing steps. For example, a metrology target can be provided comprising a large micron-sized regular array of fins of the same nano-size. Within this large array, two smaller arrays with the same size and the same number of structures can be selected. The first of the two smaller arrays can be used to determine the collapse rate caused by the electron beam in accordance with the present invention to determine a baseline correction for the bending stiffness of the structure, while the second of the two smaller arrays can be used to determine the collapse rate caused by a process (e.g., a wet cleaning process).
[0060] The calibration described in the previous paragraph is based on only one design CD and therefore may not provide sufficient information about process uniformity for other design CD values. An example of a more advanced baseline calibration is given in Figure 5a and 5b In each die area of the wafer, multiple fin arrays are included in the test pattern, characterized by different design CDs regularly distributed within a given range, for example from 34nm to 38nm in steps of 0.5nm. Figures 4a to 4c As shown, the fin arrays may be included in metrology targets 4 distributed across the wafer, or the test wafer may be designed to include test patterns only in the corresponding die areas 2. In the latter case, a range of design CDs may be applied to different fin lengths and / or different pitches of the array to provide even more variables for which process uniformity may be evaluated.
[0061] After reproducing the fin array in each die area by photolithography and etching, the various arrays were imaged by SEM and the collapse rate was measured as a function of the designed CD. This was done using electron beam conditions that enabled the measurement of a wide range of collapse rates as a function of the designed CD in at least one area of the wafer.
[0062] The result of this calibration is Figure 5a As shown, for the above-mentioned design CD range of 34-38nm and the given fin length and pitch values. Figure 5b As shown in the abbreviations C, M and E, the collapse rate is determined in three radially adjacent regions of the wafer (designated as center, middle and edge). Figure 5a The graphs in show the relationship between the measured electron beam induced collapse rate in these three regions and the designed CD contained in the test array. It can be seen that for a collapse rate of about 0.45, there is a significant shift S1 and S2 in the curves in the center and edge regions of the wafer relative to the curves in the middle region of the wafer.
[0063] The same curves can be obtained after the wet cleaning step. If the same offsets S1 and S2 are observed after cleaning, it is concluded that the cleaning process is uniform in the center, middle and edge areas. Another way to determine uniformity is to apply the inverse offsets -S1 and -S2 to the edge and center curves obtained after cleaning and verify whether the offset curves are consistent with the middle curve. If this is the case, the process is uniform. Any remaining offsets between the curves indicate a lack of process uniformity.
[0064] As described above, the above calibration procedure is performed on a substrate and the results can be used to evaluate the process non-uniformity of the substrate itself. However, the results can also be used on another substrate to evaluate the uniformity of the same process on the other substrate. The other substrate has the same dimensions as the initial substrate and is provided with a copy of one or more regular arrays used in the calibration procedure and produced in the same area as the initial substrate.
[0065] Although the invention has been illustrated and described in detail in the drawings and the foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive. By studying the drawings, the present disclosure and the appended claims, a person skilled in the art may understand and implement other variations of the disclosed embodiments in practicing the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The mere fact that certain measures are stated in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.
Claims
1. A method for evaluating the bending stiffness of high aspect ratio nanoscale structures (5) arranged in a plurality of test patterns produced by photolithography and etching in respective plurality of different regions of a semiconductor substrate (1), each test pattern comprising a regular array of said structures (5), said method comprising the following steps: - scanning said regular array of said plurality of test patterns by an electron beam generated according to a set of beam conditions which is the same for each array, - from the scanning of the array, deriving by electron beam microscopy an image of said array in a corresponding test pattern, - determining from each of the images an electron beam induced collapse rate, the collapse rate being a value between 0 and 1 representing the percentage of structures in each array that have collapsed under the influence of the electron beam scan, and wherein the electron beam induced collapse rate is indicative of the bending stiffness of the structures.
2. The method according to claim 1, characterized in that One or more parameters defining the array exhibit variations between different test patterns produced in respective different regions of the substrate (1), and wherein the beam conditions are configured such that the variations result in corresponding variations in the collapse rate.
3. The method according to claim 2, characterized in that The one or more parameters that exhibit variation are one or more of: the in-plane dimensions of the structures (5), the height of the structures (5), the material of the structures, the gaps between adjacent structures in the array.
4. The method according to claim 1, characterized in that: The beam conditions are configured to match the effects on the collapse rate of structures in the array of a semiconductor process applicable on the substrate (1).
5. The method according to any one of the preceding claims, characterized in that The array in the test pattern is generated based on the same design pattern formed by an array of structures characterized by one or more in-plane design dimensions, and wherein the test pattern is generated by applying the same etching recipe.
6. The method according to claim 5, characterized in that Each test pattern generated in the plurality of regions of the substrate (1) comprises a plurality of regular arrays generated based on a plurality of design patterns, wherein the plurality of design patterns are characterized by a plurality of corresponding values of a design dimension in at least one plane and / or a gap between adjacent structures, wherein the plurality of values are distributed within a given range.
7. The method according to claim 6, characterized in that The collapse rate is recorded in the form of a curve which represents the collapse rate as a function of the plurality of values in the central region, the middle region and the edge region of the substrate (1).
8. The method according to any one of the preceding claims, characterized in that The test pattern is produced using a mask configured to print device patterns on a plurality of die areas (2) on the substrate (1), the mask comprising a metrology target (4) included in a field of view of a lithography tool used to print the device pattern, and wherein the target is configured to produce the test pattern in the respective die areas (2).
9. The method according to any one of the preceding claims, characterized in that The value of the bending stiffness is derived from the electron beam induced collapse rate based on the previously determined relationship between collapse rate and stiffness.
10. A method for evaluating process uniformity of a process applicable to a semiconductor substrate (1), the method comprising the following steps: A plurality of test patterns are generated in respective plurality of different regions of the substrate (1) by a photolithography and etching sequence, each pattern comprising a regular array of high aspect ratio nano-sized structures (5), wherein the array is generated based on the same design pattern, and wherein the test patterns are generated by applying the same etching recipe, and wherein the photolithography and etching sequence exhibits a degree of non-uniformity such that one or more parameters defining the array exhibit variation between different test patterns generated in respective different regions of the substrate (1), applying the method according to claim 2 to the plurality of arrays, thereby obtaining a plurality of collapse rate measurements for the corresponding plurality of arrays, The process was performed on: The substrate (1), wherein the test pattern further comprises at least one copy of the array in the corresponding plurality of different regions, or another substrate having the same size as the substrate and including a copy of the array in the same plurality of different regions, determining a collapse rate caused by the process to the image of the corresponding copy of the array, The electron beam induced collapse rate is used in order to eliminate the effect of the non-uniformity of the lithography and etching sequence from the process induced collapse rate.
11. The method according to claim 10, characterized in that: Each test pattern comprises said array generated based on a plurality of design patterns of a plurality of regular arrays, said design patterns being characterized by a corresponding plurality of values of a design dimension in a plane, wherein said values are distributed within a given range, The electron beam induced collapse rate is recorded in the form of a curve, which represents the collapse rate as a function of the design dimensions in the center region, the middle region and the edge region of the substrate, The process-induced collapse rate is also recorded in the form of a curve, which represents the collapse rate as a function of the design dimensions in the center region, the middle region and the edge region of the substrate, The process uniformity is evaluated based on whether the horizontal shifts between the curves corresponding to the center region, the middle region, and the edge region are the same for the process-induced collapse rate and the electron beam-induced collapse rate.
12. The method according to claim 10 or 11, characterized in that: The process is a wet cleaning process or a deposition process.