Zero-crossing detection circuit and method

Abstract

The embodiments of the present disclosure provide a zero-crossing detection circuit and method, the circuit comprising: a logic driving module for sampling a voltage signal of a switch node to a comparison module when an upper power tube is turned off; a digital storage module for obtaining a specified output voltage and a specified inductance value, locally searching for a specified output voltage value corresponding to the specified output voltage, and searching for a specified resistance value corresponding to the specified inductance value; a digital-to-analog converter for converting the specified output voltage value and the specified resistance value into analog levels to obtain a specified output voltage signal and a specified resistance; a current generating module for generating a first current signal according to the specified output voltage signal and the specified resistance; a comparison module for obtaining a zero-crossing detection signal according to the voltage signal of the switch node, the first current signal and a power ground signal; a logic driving module for turning off the lower power tube based on a valid zero-crossing detection signal; and a power output stage module for obtaining an output voltage through the switching process of the upper power tube and the lower power tube.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technology, and in particular to a zero-crossing detection circuit and method. Background Art

[0002] When the synchronous rectifier works in DCM (Discontinuous Conduction Mode), if the synchronous rectifier tube cannot be turned off in time when the inductor current crosses zero, it will cause current backflow. Figure 1 The figure shows the current backflow path of the synchronous BUCK circuit. Figure 2 The figure is a schematic diagram of the inductor current backflow waveform. The output capacitor will discharge to the ground through the rectifier tube, resulting in unstable output voltage, reduced chip efficiency and increased risk of damage to the rectifier tube. Summary of the invention

[0003] The purpose of the embodiments of the present disclosure is to provide a zero-crossing detection circuit and method, which obtains a first current signal through output voltage signals and resistances corresponding to different output voltages and inductors, and obtains a zero-crossing detection signal for controlling the power tube to be turned off based on the first current signal, the voltage signal of the switch node, and the power ground signal, thereby realizing a high-precision zero-crossing detection function in different output voltage and inductance application scenarios, while improving the conversion efficiency of the chip when working in DCM and weakening the ringing of the switch node.

[0004] In order to achieve the above-mentioned purpose, a first aspect of an embodiment of the present disclosure provides a zero-crossing detection circuit, including: a logic drive module, a digital storage module, a digital-to-analog converter, a current generation module, a comparison module and a power output stage module. Wherein, the logic driving module is configured to sample the voltage signal of the switch node in the power output stage module to the comparison module when the upper power tube in the power output stage module is turned off; the digital storage module is configured to obtain the specified output voltage and the specified inductance value, and locally search for the specified output voltage value corresponding to the specified output voltage, and search for the specified resistance value corresponding to the specified inductance value; the digital-to-analog converter is configured to convert the specified output voltage value and the specified resistance value into analog levels to obtain a specified output voltage signal and a specified resistance; the current generating module is configured to generate a first current signal according to the specified output voltage signal and the specified resistance; the comparison module is configured to obtain a zero-crossing detection signal according to the voltage signal of the switch node, the first current signal and the power ground signal in the power output stage module; the logic driving module is also configured to turn off the lower power tube in the power output stage module based on the effective zero-crossing detection signal; the power output stage module is configured to obtain the output voltage through the switching process of the upper power tube and the lower power tube.

[0005] In some embodiments of the present disclosure, the logic driving module includes: a driving circuit and a sampling circuit, wherein the driving circuit is configured to control the switching of the upper power tube and the lower power tube; and the sampling circuit is configured to provide the voltage signal of the switching node to the comparison module when the upper power tube is turned off.

[0006] In some embodiments of the present disclosure, the sampling circuit includes: a first inverter, a first buffer and a first switch, wherein the input end of the first inverter is coupled to the output end of the shutdown signal of the upper power tube, and the output end of the first inverter is coupled to the input end of the first buffer; the output end of the first buffer is coupled to the control end of the first switch; the input end of the first switch is coupled to the output end of the voltage signal of the switch node, and the output end of the first switch is coupled to the first input end of the comparison module.

[0007] In some embodiments of the present disclosure, the digital storage module includes: a communication module, an output voltage register and an inductance register, wherein the communication module is configured to receive a specified output voltage and a specified inductance input by a user; the output voltage register is configured to locally search for a specified output voltage value corresponding to the specified output voltage; and the inductance register is configured to locally search for a specified resistance value corresponding to the specified inductance.

[0008] In some embodiments of the present disclosure, the output voltage register pre-stores a plurality of different output voltages, and the inductance register pre-stores a plurality of different inductance values ​​and a resistance value corresponding to each inductance value.

[0009] In some embodiments of the present disclosure, the current generating module includes: a first voltage comparator, a first transistor, a second transistor and an adjustable resistor, wherein the non-inverting input terminal of the first voltage comparator is coupled to the output terminal of the specified output voltage signal, and the inverting input terminal of the first voltage comparator is coupled to the first terminal of the adjustable resistor and the output terminal of the first voltage comparator; the control electrode of the first transistor is coupled to the control electrode of the second transistor, the second electrode of the first transistor and the output terminal of the first voltage comparator, and the first electrode of the first transistor is coupled to the first voltage terminal; the first electrode of the second transistor is coupled to the first voltage terminal, and the second electrode of the second transistor is coupled to the output terminal of the first current signal; the control terminal of the adjustable resistor is coupled to the output terminal of the specified resistor, the second terminal of the adjustable resistor and the second voltage terminal.

[0010] In some embodiments of the present disclosure, the comparison module includes: a second resistor and a second voltage comparator, wherein the first end of the second resistor is coupled to the output end of the first current signal, the second input end of the comparison module and the non-inverting input end of the second voltage comparator, and the second end of the second resistor is coupled to the output end of the voltage signal of the switching node; the inverting input end of the second voltage comparator is coupled to the third input end of the comparison module and the output end of the power ground signal in the power output stage module, and the output end of the second voltage comparator is coupled to the output end of the zero-crossing detection signal.

[0011] In some embodiments of the present disclosure, the product of the first current signal and the second resistor is the early shutdown amount of the lower power tube. When the sum of the early shutdown amount and the voltage signal of the switch node is equal to the power ground signal in the power output stage module, the obtained zero-crossing detection signal is a valid signal.

[0012] A second aspect of an embodiment of the present disclosure provides a zero-crossing detection method. According to the zero-crossing detection circuit described in the first aspect, the method includes: obtaining a specified output voltage and a specified inductance, and locally searching for a specified output voltage value corresponding to the specified output voltage, and searching for a specified resistance value corresponding to the specified inductance; converting the specified output voltage value and the specified resistance value into analog levels to obtain a specified output voltage signal and a specified resistance; generating a first current signal based on the specified output voltage signal and the specified resistance; obtaining a zero-crossing detection signal based on a voltage signal of a switch node sampled when the upper power tube is turned off, the first current signal, and a power ground signal; and turning off the lower power tube based on the effective zero-crossing detection signal.

[0013] In some embodiments of the present disclosure, the zero-crossing detection signal obtained based on the voltage signal of the switch node sampled when the upper power tube is turned off, the first current signal and the power ground signal includes: the product of the first current signal and the second resistor is the early shutdown amount of the lower power tube; when the sum of the early shutdown amount and the voltage signal of the switch node is equal to the power ground signal in the power output stage module, the obtained zero-crossing detection signal is a valid signal.

[0014] Other features and advantages of the embodiments of the present disclosure will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings are used to provide a further understanding of the embodiments of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present disclosure, but do not constitute a limitation on the embodiments of the present disclosure. In the accompanying drawings:

[0016] Figure 1 This is a schematic diagram of the current backflow path of the synchronous BUCK circuit;

[0017] Figure 2 It is a schematic diagram of the inductor current backflow waveform;

[0018] Figure 3 It is a schematic diagram of a zero-crossing detection circuit;

[0019] Figure 4 This is a waveform diagram of the advanced shutdown of the lower power tube;

[0020] Figure 5 It is a waveform diagram of the power tube under delayed shutdown;

[0021] Figure 6 is a schematic block diagram of a zero-crossing detection circuit according to an embodiment of the present disclosure;

[0022] Figure 7 is a schematic block diagram of a logic driver module according to an embodiment of the present disclosure;

[0023] Figure 8 is an exemplary circuit diagram of a sampling circuit according to an embodiment of the present disclosure;

[0024] Fig. 9 is an exemplary circuit diagram of a current generating module according to an embodiment of the present disclosure;

[0025] Fig.10 is an exemplary circuit diagram of a comparison module according to an embodiment of the present disclosure;

[0026] Fig.11 is a waveform diagram of a zero-crossing detection circuit according to an embodiment of the present disclosure.

[0027] The elements in the drawings are schematic and not drawn to scale. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work also fall within the scope of protection of the present disclosure.

[0029] In all embodiments of the present disclosure, since the source and drain of a metal oxide semiconductor (MOS) transistor are symmetrical, and the conduction current directions between the source and drain of an N-type transistor and a P-type transistor are opposite, in the embodiments of the present disclosure, the controlled middle terminal of the MOS transistor is referred to as a control terminal, and the remaining two terminals of the MOS transistor are referred to as a first terminal and a second terminal, respectively. In addition, terms such as "first" and "second" are only used to distinguish one component (or a portion of a component) from another component (or another portion of a component).

[0030] To avoid Figure 1 In order to prevent the current backflow situation shown in the figure from happening, it is necessary to design a zero-crossing detection circuit. The zero-crossing detection circuit can detect the state of the inductor current. When it is detected that the inductor current is zero, it will output a control signal to quickly turn off the rectifier tube. Due to the existence of the on-resistance of the power tube, when the lower power tube LS is freewheeling, the potential of the switch node SW will decrease linearly with the decrease of the inductor current. Therefore, when the inductor current drops to 0, the potential of the switch node SW also decreases to 0. The existing commonly used zero-crossing detection circuits all detect the potential of the switch node SW to detect the inductor current, such as Figure 3 As shown, it is mainly composed of a comparator and a logic drive part. When the upper power tube HS is turned off, the shutdown signal of the upper power tube is delayed by the inverter INV1 and the buffer BUFFER1 to close the switch S1. The switch node SW voltage and the power ground signal PGND are sampled to the comparator COMP's in-phase input and the reverse input for comparison to monitor the inductor current state. In order to offset the non-ideal delay of the comparator COMP and the logic drive part, an artificial resistor R1 and a current source I are set. B The actual potential of the switch node SW is V when the comparator COMP starts to flip. PGND +I B R1, the inductor current IL is greater than 0. When the comparator offset is set appropriately, even if the zero-crossing detection signal requires a long delay to enable, the lower power tube can be turned off before the inductor current crosses zero. In addition, in order to increase the robustness of the circuit design, Figure 3 A correction module is added to adjust the comparator offset parameters. When the inductor test engineer performs zero-crossing detection module performance test on the actual chip, he will first enter the chip test mode, at which time the upper power tube of the control chip is turned off and the lower power tube is turned on. Then the inductor test engineer will use external excitation on the test board to slowly reduce the current flowing through the lower power tube LS to the power ground signal PGND to obtain the actual inductor current value when zero-crossing detection is enabled, and use this to adjust the current source I B Correction is made and finally the lower power tube is turned off just when the inductor current IL is 0.

[0031] However, the above zero-crossing detection circuit can only achieve high zero-crossing detection accuracy under a fixed inductor current slope di / dt. When the chip is corrected, the corresponding comparator offset is also fixed. From the current slope calculation formula di / dt=-V_OUT / L during inductor freewheeling, it can be seen that when the chip is in different applications requiring different inductors L and output voltages VOUT, the inductor current slope di / dt will change, causing the lower power tube LS to close ahead or behind, resulting in non-ideal conditions. Figure 4 The waveform diagram of the lower power tube is turned off in advance, so that the body diode D2 of the lower power tube LS is turned on, which increases the number of unbalanced minority carriers stored in the body diode D2, resulting in an increase in the reverse recovery current, and Figure 5 It is a waveform diagram of the delayed shutdown of the lower power tube, which makes the body diode D1 of the upper power tube HS turned on, increasing the number of unbalanced minority carriers stored in the body diode D1 and causing the reverse recovery current to increase. Figure 4 and Figure 5 Both will cause more residual current in the inductor to generate greater ringing at the switch node SW, thereby greatly reducing the chip efficiency.

[0032] In order to solve the above problems, Figure 6 FIG. 4 shows a schematic block diagram of a zero-crossing detection circuit 600 according to an embodiment of the present disclosure. Figure 6 As shown, the zero-crossing detection circuit 600 includes: a logic driving module 610 , a digital storage module 620 , a digital-to-analog converter 630 , a current generating module 640 , a comparing module 650 and a power output stage module 660 .

[0033] The logic drive module 610 is configured to sample the voltage signal of the switch node SW in the power output stage module 660 to the comparison module 650 when the upper power tube in the power output stage module 660 is turned off. The digital storage module 620 is configured to obtain the specified output voltage and the specified inductance value, and to search the specified output voltage value corresponding to the specified output voltage locally, and to search the specified resistance value corresponding to the specified inductance value. The digital-to-analog converter 630 is configured to convert the specified output voltage value and the specified resistance value into analog levels to obtain the specified output voltage signal A. V OUT With the specified resistance R L The current generating module 640 is configured to output the specified output voltage signal A according to the V OUT With the specified resistance R L , generating a first current signal I B The comparison module 650 is configured to compare the voltage signal VSW of the switch node SW, the first current signal I BThe logic driving module 610 is further configured to turn off the lower power tube in the power output stage module 660 based on the effective zero-crossing detection signal ZCD. The power output stage module 660 is configured to obtain an output voltage through the switching process of the upper power tube and the lower power tube.

[0034] Among them, Figure 7 As shown, the logic driving module 610 includes: a driving circuit 611 and a sampling circuit 612. The driving circuit 611 is configured to control the switching of the upper power tube and the lower power tube. The specific circuit structure is not limited in the embodiment of the present disclosure, and can be specifically adaptively adjusted according to the power output stage module 660. The sampling circuit 612 is configured to provide the voltage signal of the switch node SW to the comparison module 650 when the upper power tube is turned off.

[0035] like Figure 8 As shown, the sampling circuit 612 may include: a first inverter INV1, a first buffer BUFFER1, and a first switch k1. The input end of the first inverter INV1 is coupled to the output end of the shutdown signal HS OFF of the upper power tube, and the output end of the first inverter INV1 is coupled to the input end of the first buffer BUFFER1. The output end of the first buffer BUFFER1 is coupled to the control end of the first switch k1. The input end of the first switch k1 is coupled to the voltage signal end of the switch node SW, and the output end of the first switch k1 is coupled to the first input end of the comparison module 650.

[0036] like Figure 6As shown, the digital storage module 620 may include: a communication module 621, an output voltage register 622 and an inductance register 623. The communication module 621 is configured to receive a specified output voltage VOUT and a specified inductance L input by a user. The output voltage register 622 is configured to locally search for a specified output voltage value corresponding to the specified output voltage VOUT. The inductance register 623 is configured to locally search for a specified resistance value corresponding to the specified inductance L. The output voltage register 622 pre-stores a plurality of different output voltages, and the inductance register 623 pre-stores a plurality of different inductance values, and a resistance value corresponding to each inductance value. The user can call through the communication module 621 according to the use requirements, so as to realize the zero-crossing detection function of different output voltages and inductances. In addition, the communication module 621 can realize the communication function through the I2C (Inter-Integrated Circuit) protocol or the SPI (Serial Peripheral Interface) protocol, including communication with external and internal registers.

[0037] The digital-to-analog converter 630 can convert the specified output voltage value and the specified resistance value of the digital code into a specified output voltage signal and a specified resistance of the corresponding analog level. The digital-to-analog converter in the embodiment of the present disclosure is not specifically limited, and any digital-to-analog converter that can realize the conversion of digital codes to analog levels can be selected according to user needs.

[0038] like Fig. 9 As shown, the current generating module 640 may include: a first voltage comparator COMP1, a first transistor M1, a second transistor M2 and an adjustable resistor R1. The non-inverting input terminal of the first voltage comparator COMP1 is coupled to the specified output voltage signal A V OUT The output terminal of the first voltage comparator COMP1 is coupled to the first terminal of the adjustable resistor R1 and the output terminal of the first voltage comparator COMP1. The control terminal of the first transistor M1 is coupled to the control terminal of the second transistor M2, the second terminal of the first transistor M1 and the output terminal of the first voltage comparator COMP1. The first terminal of the first transistor M1 is coupled to the first voltage terminal V1. The first terminal of the second transistor M2 is coupled to the first voltage terminal V1, and the second terminal of the second transistor M2 is coupled to the first current signal I B The control end of the adjustable resistor R1 is coupled to the specified resistor R LThe output terminal of the adjustable resistor R1, the second terminal of the adjustable resistor R1 and the second voltage terminal V2. The first transistor M1 and the second transistor M2 form a mirror circuit, and the width-to-length ratio of the second transistor M2 is C times the width-to-length ratio of the first transistor M1.

[0039] like Fig.10 As shown, the comparison module 650 may include: a second resistor R2 and a second voltage comparator COMP2. The first end of the second resistor R2 is coupled to the first current signal I B The output terminal of the comparison module 650, the second input terminal of the comparison module 650 and the non-inverting input terminal of the second voltage comparator COMP2, the second end of the second resistor R2 is coupled to the output terminal of the voltage signal VSW of the switch node SW. The inverting input terminal of the second voltage comparator COMP2 is coupled to the third input terminal of the comparison module 650 and the output terminal PGND of the power ground signal VPGND in the power output stage module 660, and the output terminal of the second voltage comparator COMP2 is coupled to the output terminal of the zero-crossing detection signal ZCD.

[0040] In the embodiment of the present disclosure, the circuit structure of the power output stage module 660 is not specifically limited, and only needs to include an upper power tube and a lower power tube whose switches are controlled by the logic drive module 610. The power output stage module 660 can obtain an output voltage containing duty cycle information through the switching process and filtering of external passive devices.

[0041] exist Figure 6-10 In the example, a high voltage signal is input from the first voltage terminal V1, and the second voltage terminal V2 is grounded. The first transistor M1 and the second transistor M2 are both PMOS transistors. Those skilled in the art should understand that based on the above inventive concept, Figure 6-10 Variations of the circuit shown in the figure should also fall within the scope of protection of the present disclosure. In this variation, the transistor and the voltage terminal may also have the same Figure 6-10 Examples of different setups are shown.

[0042] In addition, in the above embodiment, although the zero-crossing detection circuit 600 is described as a Buck type converter, it can be understood that the embodiments of the present disclosure include but are not limited to Buck type, and can also be Boost type, Buck-boost type, motor type, driver type and other power supply circuits involving accurate zero-crossing detection implementation, and are also applicable.

[0043] Furthermore, the present disclosure provides a method corresponding to Figure 6 The zero-crossing detection method of the zero-crossing detection circuit 600 is combined with Figure 6-10The detection method is described with reference to the structural diagram of the present invention, and the method includes: obtaining a specified output voltage and a specified inductor, and locally searching for a specified output voltage value corresponding to the specified output voltage, and searching for a specified resistance value corresponding to the specified inductor; converting the specified output voltage value and the specified resistance value into analog levels to obtain a specified output voltage signal and a specified resistance; generating a first current signal according to the specified output voltage signal and the specified resistance; obtaining a zero-crossing detection signal according to a voltage signal of a switch node sampled when the upper power tube is turned off, the first current signal, and a power ground signal; and turning off the lower power tube based on the effective zero-crossing detection signal.

[0044] Specifically, when the inductor is in the freewheeling state, the shutdown signal provided by the logic drive module 610 to the lower power tube in the power output stage module 660 will be inverted by the first inverter INV1 and delayed by the first buffer BUFFER1, so that the first switch k1 is closed to sample the voltage signal of the switch node SW to the comparison module 650, and at the same time prevent the voltage signal of the switch node SW from being interfered by the noise when the switch in the power output stage module 660 is switched. Then, according to the specified output voltage and the specified inductor called by the user's needs, the specified output voltage value corresponding to the specified output voltage is searched locally, and the specified resistance value corresponding to the specified inductor is searched. Among them, the specified output voltage is positively correlated with the specified output voltage value searched locally, and the specified inductor is positively correlated with the specified resistance value. For example, VOUT=A V OUT , L=B R L .

[0045] Since the width-to-length ratio of the second transistor M2 in the current generating module 640 is C times the width-to-length ratio of the first transistor M1, the first current signal I generated by the current generating module 640 is B It can be expressed by the following formula (1):

[0046] Formula (1)

[0047] Therefore, the early shutdown amount VOS of the lower power tube can be obtained by the following formula (2):

[0048] Formula (2)

[0049] in, It is the inductor current slope when the lower power tube is freewheeling.

[0050] Therefore, when the sum of the voltage signal VSW of the switch node SW and the early shutdown amount VOS of the lower power tube is equal to the power ground signal VPGND, the obtained zero-crossing detection signal ZCD is a valid signal. By using the valid zero-crossing detection signal ZCD, the lower power tube is turned off just when the inductor current crosses zero. Fig.11 As shown, accurate zero-crossing detection control is achieved. For example, when the zero-crossing detection signal ZCD is at a high level, it is a valid signal.

[0051] In addition, after the lower power tube is turned on, the following equations (3) and (4) exist:

[0052] Equation (3)

[0053] Equation (4)

[0054] in, is the on-resistance of the lower power tube, is a fixed delay time.

[0055] Therefore, the coefficients A, B, C, D and the resistance value of the second resistor R2 can be determined by equation (4) to obtain the fixed delay time The required early shutdown amount VOS of the lower power tube.

[0056] The disclosed embodiment can realize high-precision zero-crossing detection in different output voltage and inductance application scenarios, improve product flexibility, and improve the conversion efficiency of the chip when working in DCM and weaken the ringing of the switch node. At the same time, high-precision zero-crossing detection in different output voltage and inductance application scenarios can be realized only by configuring the digital register, and the circuit structure is simple.

[0057] Unless the context clearly indicates otherwise, the singular form of the words used herein and in the appended claims includes the plural and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used herein, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0058] Further aspects and scopes of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0059] Several embodiments of the present disclosure are described in detail above, but it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the attached claims.

Claims

1. A zero-crossing detection circuit, characterized in that: include: Logic drive module, digital storage module, digital-to-analog converter, current generation module, comparison module and power output stage module, Wherein, the logic driving module is configured to sample the voltage signal of the switch node in the power output stage module to the comparison module when the upper power tube in the power output stage module is turned off; The digital storage module is configured to obtain a specified output voltage and a specified inductance value, and locally search for a specified output voltage value corresponding to the specified output voltage, and search for a specified resistance value corresponding to the specified inductance value; The digital-to-analog converter is configured to convert the specified output voltage value and the specified resistance value into analog levels to obtain a specified output voltage signal and a specified resistance; The current generating module is configured to generate a first current signal according to the specified output voltage signal and the specified resistance; The comparison module is configured to obtain a zero-crossing detection signal according to the voltage signal of the switch node, the first current signal and the power ground signal in the power output stage module; The logic driving module is further configured to turn off the lower power tube in the power output stage module based on the effective zero-crossing detection signal; The power output stage module is configured to obtain an output voltage through a switching process of an upper power tube and a lower power tube.

2. The zero-crossing detection circuit according to claim 1, characterized in that: The logic driving module includes: a driving circuit and a sampling circuit. Wherein, the driving circuit is configured to control the switching of the upper power tube and the lower power tube; The sampling circuit is configured to provide the voltage signal of the switch node to the comparison module when the upper power tube is turned off.

3. The zero-crossing detection circuit according to claim 2, characterized in that: The sampling circuit includes: a first inverter, a first buffer and a first switch. Wherein, the input end of the first inverter is coupled to the output end of the shutdown signal of the upper power tube, and the output end of the first inverter is coupled to the input end of the first buffer; The output terminal of the first buffer is coupled to the control terminal of the first switch; An input terminal of the first switch is coupled to an output terminal of a voltage signal of the switch node, and an output terminal of the first switch is coupled to a first input terminal of the comparison module.

4. The zero-crossing detection circuit according to claim 1, characterized in that: The digital storage module includes: a communication module, an output voltage register and an inductance register. Wherein, the communication module is configured to receive a specified output voltage and a specified inductance input by a user; The output voltage register is configured to locally look up a designated output voltage value corresponding to the designated output voltage; The inductance register is configured to locally look up a specified resistance value corresponding to the specified inductance.

5. The zero-crossing detection circuit according to claim 4, characterized in that: The output voltage register pre-stores a plurality of different output voltages, and the inductance register pre-stores a plurality of different inductance values ​​and a resistance value corresponding to each inductance value.

6. The zero-crossing detection circuit according to claim 1, characterized in that: The current generating module comprises: a first voltage comparator, a first transistor, a second transistor and an adjustable resistor. Wherein, the non-inverting input terminal of the first voltage comparator is coupled to the output terminal of the specified output voltage signal, and the inverting input terminal of the first voltage comparator is coupled to the first terminal of the adjustable resistor and the output terminal of the first voltage comparator; The control electrode of the first transistor is coupled to the control electrode of the second transistor, the second electrode of the first transistor and the output terminal of the first voltage comparator, and the first electrode of the first transistor is coupled to the first voltage terminal; A first electrode of the second transistor is coupled to the first voltage terminal, and a second electrode of the second transistor is coupled to the output terminal of the first current signal; The control end of the adjustable resistor is coupled to the output end of the specified resistor, the second end of the adjustable resistor and the second voltage end.

7. The zero-crossing detection circuit according to claim 1, characterized in that: The comparison module includes: a second resistor and a second voltage comparator, Wherein, a first end of the second resistor is coupled to an output end of the first current signal, a second input end of the comparison module and a non-inverting input end of the second voltage comparator, and a second end of the second resistor is coupled to an output end of the voltage signal of the switch node; The inverting input terminal of the second voltage comparator is coupled to the third input terminal of the comparison module and the output terminal of the power ground signal in the power output stage module, and the output terminal of the second voltage comparator is coupled to the output terminal of the zero-crossing detection signal.

8. The zero-crossing detection circuit according to claim 7, characterized in that: The product of the first current signal and the second resistor is the early shutdown amount of the lower power tube. When the sum of the early shutdown amount and the voltage signal of the switch node is equal to the power ground signal in the power output stage module, the obtained zero-crossing detection signal is a valid signal.

9. A zero-crossing detection method, characterized in that: According to the zero-crossing detection circuit according to any one of claims 1 to 8, the method comprises: Obtaining a specified output voltage and a specified inductance, and locally searching for a specified output voltage value corresponding to the specified output voltage, and searching for a specified resistance value corresponding to the specified inductance; Converting the specified output voltage value and the specified resistance value into analog levels to obtain a specified output voltage signal and a specified resistance; generating a first current signal according to the specified output voltage signal and the specified resistance; Obtaining a zero-crossing detection signal according to a voltage signal of a switch node sampled when the upper power tube is turned off, the first current signal, and a power ground signal; The lower power tube is turned off based on the valid zero-crossing detection signal.

10. The zero-crossing detection method according to claim 9, characterized in that: The step of obtaining a zero-crossing detection signal according to the voltage signal of the switch node, the first current signal and the power ground signal obtained by sampling when the upper power tube is turned off includes: The product of the first current signal and the second resistor is the early closing amount of the lower power tube; When the sum of the early closing amount and the voltage signal of the switch node is equal to the power ground signal in the power output stage module, the obtained zero-crossing detection signal is a valid signal.

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