Microprocessing system and program execution method

Abstract

The invention provides a microprocessing system and a program execution method, the microprocessing system comprises a microprocessor, an external random access memory and a read-only memory, and the address range of the external random access memory is overlapped with the address range of the read-only memory; wherein the microprocessor, the external random access memory and the read-only memory are connected to three groups of buses, and the three groups of buses are a control bus, an address bus and a data bus; the data bus and the address bus are respectively provided with a path switching circuit, and the path switching circuits are used for switching a program in the read-only memory to the external random access memory for execution by switching a program access path of the microprocessor. According to the technical scheme, the program reading and executing speed of the microprocessor can be improved.

Description

Technical Field

[0001] The present application relates to the field of computers, and in particular to a microprocessor system and a program execution method. Background Art

[0002] Harvard architecture and von Neumann architecture are two different computer architectures, which differ in memory structure, instruction access speed, and application fields. In Harvard architecture, instructions and data are stored in different memories, and the processor reads information from both memories at the same time to achieve parallel access to instructions and data. The processor can read and execute instructions faster, and is mainly used in embedded systems and real-time systems, and is suitable for application scenarios that require high performance and real-time response. In von Neumann architecture, instructions and data share the same memory, and the processor reads instructions from the memory in sequence. The instruction access speed is relatively slow, and is mainly used in the field of general-purpose computers.

[0003] In a microprocessor system based on Harvard architecture, the memory includes read-only memory (ROM) and external random access memory (RAM). ROM can only be read and is mainly used to store programs, while external RAM can be read and written at any time and is mainly used to store data during program execution. When the processor executes a program, it needs to read the program from ROM and run it. Due to the response rate of ROM, it takes a long time to read and run the program. The program execution rate is limited by the response rate of ROM.

[0004] Invention

[0005] The present application provides a microprocessor system and a program execution method, aiming to improve the program execution rate.

[0006] In a first aspect, a microprocessor system is provided, comprising a microprocessor, an external random access memory and a read-only memory, wherein an address range of the external random access memory overlaps with an address range of the read-only memory; wherein:

[0007] The microprocessor, the external random access memory and the read-only memory are connected to three groups of buses, which are a control bus, an address bus and a data bus;

[0008] The data bus and the address bus are both provided with a path switching circuit, and the path switching circuit is used to switch the program in the read-only memory to the external random access memory for execution by switching the program access path of the microprocessor.

[0009] In this technical solution, the microprocessor system includes a microprocessor, an external RAM and a ROM, the address ranges of the external RAM and the ROM overlap, the microprocessor and the RAM and the ROM are connected to a control bus, an address bus and a data bus, and a path switching circuit is provided on the data bus and the address bus. The path switching circuit is used to switch the program in the ROM to the external RAM for execution by switching the program access path of the microprocessor; since the speed at which the microprocessor accesses the external RAM is significantly faster than the speed at which the microprocessor accesses the ROM, by providing a path switching circuit on the data bus and the address bus in the microprocessor system, the path switching circuit switches the program in the ROM to the external RAM for execution by switching the program access path of the microprocessor, which can improve the speed at which the microprocessor reads and executes the program, thereby improving the program execution rate.

[0010] In combination with the first aspect, in a possible implementation, the path switching circuit on the data bus is arranged between a first data bus branch and a first branch intersection, the first data bus branch is a bus branch on the data bus connected to the read-only memory, the first branch intersection is the intersection of a second data bus branch and a third data bus branch, the second data bus branch is a bus branch on the data bus connected to the external random access memory, and the third data bus branch is a bus branch on the data bus connected to the microprocessor; the path switching circuit on the address bus is arranged between a first address bus branch and a second branch intersection, the first address bus branch is a bus branch on the address bus connected to the read-only memory, the second branch intersection is the intersection of a second address bus branch and a third address bus branch, the second address bus branch is a bus branch on the address bus connected to the external random access memory, and the third address bus branch is a bus branch on the address bus connected to the microprocessor.

[0011] The path switching circuit on the data bus and the path switching circuit on the address bus are set between the intersection of the bus branch connecting the ROM and the bus branch connecting the microprocessor and the bus branch connecting the RAM. The path switching circuit will only affect the path of the microprocessor accessing the ROM, but will not affect the path of the microprocessor accessing the external RAM. While realizing the switching of the program access path of the microprocessor, it can ensure the normal access of the microprocessor to the external RAM.

[0012] In combination with the first aspect, in a possible implementation, the microprocessor includes a first interface and a second interface, the first interface is a data address common interface, and the second interface is an address interface; wherein: the data bus is connected between the first interface and the external random access memory and the read-only memory; the address bus includes a first address bus and a second address bus, the first address bus is connected between the first interface and the external random access memory and the read-only memory, and the second address bus is connected between the second interface and the external random access memory and the read-only memory, the microprocessor system also includes an address latch, and the address latch is arranged on the first address bus; the path switching circuit on the address bus includes a first path switching circuit and a second path switching circuit, the first path switching circuit is arranged between the intersection of the first address bus branch and the second branch on the first address bus, and the second path switching circuit is arranged between the intersection of the first address bus branch and the second branch on the second address bus.

[0013] When there are multiple groups of address buses, multiple groups of program access paths of the microprocessor can be controlled by setting multiple path switching circuits.

[0014] In combination with the first aspect, in a possible implementation, the microprocessor is used to back up the target program to the external random access memory when the target program to be executed in the read-only memory is a preset program, and when executing the target program, control the path switching circuit to switch the program access path of the microprocessor from accessing the read-only memory to accessing the external random access memory, obtain the target program access path, and execute the target program based on the target program access path.

[0015] When the target program to be executed in the ROM is a preset program, the target program is backed up to the external RAM, and when the target program is executed, the path switching circuit is controlled to switch the program access path of the microprocessor from the ROM to the external RAM to obtain the target program access path. The target program is executed based on the target program access path, and the target program can be copied to the external RAM for execution, thereby improving the execution rate of the target program.

[0016] In combination with the first aspect, in a possible implementation, the microprocessor is also used to control the path switching circuit to switch the program access path of the microprocessor from accessing the random access memory back to accessing the read-only memory after the execution of the target program is completed, so as to obtain the original program access path.

[0017] After the target program is executed, the control path switching circuit switches the program access path of the microprocessor from the external RAM back to the ROM to obtain the original program access path, which can ensure that other programs in the ROM are executed normally.

[0018] In a second aspect, a program execution method is provided, which is applied to the microprocessing system of the first aspect, and the method comprises:

[0019] Obtaining a target program to be executed in the read-only memory;

[0020] When the target program is the preset program, backing up the target program to the external random access memory, and when executing the target program, controlling the path switching circuit to switch the program access path of the microprocessor from accessing the read-only memory to accessing the external random access memory, so as to obtain the target program access path;

[0021] The target program is executed based on the target program access path.

[0022] In this technical solution, when the target program to be executed in the ROM is a preset program, the target program is backed up to the external RAM, and when the target program is executed, the path switching circuit is controlled to switch the program access path of the microprocessor from the ROM to the external RAM to obtain the target program access path, and the target program is executed based on the target program access path. The target program can be copied to the external RAM for execution. Since the speed at which the microprocessor accesses the external RAM is significantly faster than the speed at which the microprocessor accesses the ROM, copying the target program to the external RAM for execution can improve the execution rate of the target program.

[0023] In combination with the second aspect, in a possible implementation, after the execution of the target program is completed, the path switching circuit is controlled to switch the program access path of the microprocessor from accessing the random access memory back to accessing the read-only memory to obtain the original program access path.

[0024] After the target program is executed, the control path switching circuit switches the program access path of the microprocessor from the external RAM back to the ROM to obtain the original program access path, which can ensure that other programs in the ROM are executed normally.

[0025] In combination with the second aspect, in a possible implementation method, after obtaining the target program to be executed in the read-only memory, it also includes: determining whether there is a preset mark for the target program; if there is a preset mark for the target program, determining that the target program is the preset program; if the preset mark does not exist for the target program, determining that the target program is not the preset program.

[0026] By detecting whether a program has a preset mark, it is determined whether the program is a program that needs to be executed faster, and the implementation method is simple and convenient.

[0027] In combination with the second aspect, in a possible implementation method, executing the target program based on the target program access path includes: sending a backup address of the target program in the external random access memory to the external random access memory through the target program access path, and receiving the target program obtained by the external random access memory from the backup address; executing the target program.

[0028] In combination with the second aspect, in a possible implementation method, after obtaining the target program to be executed in the read-only memory, it also includes: when the target program is not the preset program, skipping the execution of backing up the target program to the external random access memory, and when executing the target program, controlling the path switching circuit to switch the program access path of the microprocessor from accessing the read-only memory to accessing the external random access memory, thereby obtaining the step of obtaining the target program access path.

[0029] When the target program is not a preset program, the step of backing up the target program to the external RAM is skipped, and when executing the target program, the path switching circuit is controlled to switch the program access path of the microprocessor to the external RAM to obtain the target program access path, so that the target program can be loaded and run normally in the ROM.

[0030] The present application can achieve the following technical effects: since the speed at which the microprocessor accesses the external RAM is significantly faster than the speed at which the microprocessor accesses the ROM, by setting a path switching circuit on the data bus and the address bus in the microprocessor system, the path switching circuit switches the program access path of the microprocessor and switches the program in the ROM to the external RAM for execution, which can increase the speed at which the microprocessor reads and executes the program, thereby increasing the program execution rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments of the present application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative labor.

[0032] Figure 1 A bus connection diagram of a microprocessor system with a three-bus structure provided in an embodiment of the present application;

[0033] Figure 2The address distribution of ROM and RAM when ROM and RAM are uniformly addressed;

[0034] Figure 3 Schematic diagram of the address distribution of ROM and RAM when ROM and RAM are addressed independently;

[0035] Figure 4 A schematic diagram of the structure of a microprocessor system provided in an embodiment of the present application;

[0036] Figure 5 A schematic diagram of a relay subcircuit included in a path switching circuit provided in an embodiment of the present application;

[0037] Fig. 6A and Figure 6B A schematic diagram of bus connection before and after a relay subcircuit is set on the bus;

[0038] Figure 7 This is a schematic diagram of the I / O ports of the MCS-51 series;

[0039] Figure 8 A bus connection diagram of a microprocessor system provided in an embodiment of the present application;

[0040] Fig. 9 A schematic diagram of a backup of a target program provided in an embodiment of the present application;

[0041] Fig.10 A flowchart of a program execution method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0043] It should be noted that, if there is no conflict, the various features in the embodiments of the present application can be combined with each other, all within the scope of protection of the present application. In addition, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different order from the module division in the device or the flow chart. Furthermore, the words "first", "second", "third", etc. used in this application do not limit the data and execution order, but only distinguish the same items or similar items with basically the same functions and effects.

[0044] The technical solution of the present application is applicable to a microprocessor system, and in particular to a microprocessor system based on a Harvard architecture.

[0045] In a microprocessor system based on the Harvard architecture, a three-bus structure is usually used to connect the microprocessor and the memory. Figure 1 , Figure 1 A bus connection diagram of a microprocessor system with a three-bus structure provided in an embodiment of the present application is shown in FIG. Figure 1 As shown in the figure, the microprocessor, ROM and RAM are connected to three groups of buses, namely the control bus (CB), address bus (AB) and data bus (DB). Among them, the data bus is used to transmit data information. The microprocessor can read data from ROM or RAM through the data bus, and can also write data to RAM through the data bus. The address bus is used to transmit the address information sent by the microprocessor, and the address bus is a unidirectional bus. The control bus is used to transmit control signals, timing signals and status information, etc., and the control bus is a bidirectional bus.

[0046] In a microprocessor system based on the Harvard architecture, programs are usually stored in ROM. The microprocessor reads the program from the ROM and runs it. Due to the response rate of the ROM, it takes a long time to read the program and run it. The program execution rate is limited by the response rate of the ROM.

[0047] In a feasible technical solution, it is proposed that the portable code segment is copied from the ROM and written into the group buffer released by the RAM, and the function pointer table entry called by each associated portable code module is updated to point the call to the portable code module from the flash memory address to the RAM address of the associated callable function. The portable code module will be executed faster than when executed from the flash ROM, that is, the program in the ROM is copied to the RAM, and the address pointed to by the function pointer is modified from the address of the program in the flash memory to the address of the program in the RAM, so that the program is executed in the RAM, improving the execution rate of the program. This technical solution is applicable to the case where the ROM and RAM are uniformly addressed, and can be referred to Figure 2 , Figure 2 This is a diagram of the address distribution of ROM and RAM when ROM and RAM are uniformly addressed. Since ROM and RAM are uniformly addressed, the address range of ROM does not overlap with the address range of RAM. Changing the address pointed to by the pointer can determine the unique storage location. By updating the pointer entry, the loading and execution location of the program can be changed, and the loading and execution location of the program can be changed from ROM to RAM. This solution is not suitable for the case where ROM and RAM are independently addressed. For reference, Figure 3 , Figure 3Schematic diagram of the address distribution of ROM and RAM when ROM and RAM are addressed independently. Since ROM and RAM are addressed independently, the address range of ROM overlaps with the address range of RAM. The unique location cannot be determined based on the address pointed to by the pointer, and updating the pointer entry may not necessarily change the loading and execution location of the program from ROM to RAM.

[0048] In response to the situation where the address range of ROM overlaps with the address range of RAM, the present application sets a path switching circuit on the data bus and the address bus. The path switching circuit switches the program access path of the microprocessor and switches the program in the ROM to the external RAM for execution, which can increase the speed at which the microprocessor reads and executes the program, thereby increasing the program execution rate.

[0049] The technical solution of this application is described in detail below. Figure 4 , Figure 4 A schematic diagram of the structure of a microprocessor system provided in an embodiment of the present application is shown in FIG. Figure 4 As shown, the microprocessor system 10 includes a microprocessor 101, an external random access memory 102 and a read-only memory 103, and the address range of the external random access memory 102 overlaps with the address range of the read-only memory 103; wherein:

[0050] The microprocessor 101, the external random access memory 102 and the read-only memory 103 are connected to three sets of buses, which are a control bus L1, an address bus L2 and a data bus L3;

[0051] A path switching circuit 104 is provided on both the data bus L3 and the address bus L2 . The path switching circuit 104 is used to switch the program in the read-only memory 103 to the external random access memory 102 for execution by switching the program access path of the microprocessor 101 .

[0052] The microprocessor 101 is a Harvard architecture microprocessor, for example, a microprocessor based on a 51 core. The microprocessor 101 accesses an external random access memory 102 and a read-only memory 103 through a control bus L1, an address bus L2, and a data bus L3.

[0053] The external random access memory 102 may also be called an extended RAM, which refers to a RAM connected to the outside of the microprocessor 101. The address range of the external random access memory 102 overlaps with the address range of the read-only memory 103, which means that some or all of the addresses of the external random access memory 102 are the same as the addresses in the read-only memory 103. Figure 3, the address range of ROM is 0000H~FFFFH, and the address range of external RAM is also 0000H~FFFFH. The address ranges of the two are the same, that is, there is an overlap in the address ranges.

[0054] The path switching circuit 104 is a hardware switching circuit provided on the data bus L3 and the address bus L2. The path switching circuit 104 may include a plurality of switch elements. The path switching circuit 104 is used to switch the program access path of the microprocessor 101 on the data bus L3 and the address bus L2. The program access path of the microprocessor 101 is the path for the microprocessor 101 to obtain the program. Under normal circumstances, the microprocessor 101 accesses the read-only memory 103 through the address bus L2 and the data bus L3 to obtain the program from the read-only memory 103. The path for the microprocessor to access the read-only memory 103 through the address bus L2 and the data bus L3 to obtain the program is the original program access path. The original program access path is as follows: Figure 4 As shown in the dotted path l11 and the dotted path l12 in the figure. The path switching circuit 104 can switch the program access path of the microprocessor 101 on the data bus L3 and the address bus L2 from accessing the read-only memory 103 to accessing the external random access memory 102, or switch the program access path of the microprocessor 101 on the data bus L3 and the address bus L2 from accessing the external random access memory 102 back to accessing the read-only memory 103. Among them, the path switching circuit 104 switches the program access path of the microprocessor 101 on the data bus L3 and the address bus L2 under the control of the microprocessor 101. The specific principle of the microprocessor 101 controlling the path switching circuit 104 to switch the program access path of the microprocessor 101 on the data bus L3 and the address bus L2 will be described in the subsequent specific introduction of the microprocessor 101, and no further description will be made here.

[0055] like Figure 4 As shown, the path switching circuit 104 includes a path switching circuit 1041 on the data bus L3 and a path switching circuit 1042 on the address bus L2.

[0056] The path switching circuit 1041 on the data bus L3 is arranged between the first data bus branch L3-1 and the first branch intersection p1. The first data bus branch L3-1 is a bus branch on the data bus L3 connected to the read-only memory 103. The first branch intersection p1 is the intersection of the second data bus branch L3-2 and the third data bus branch L3-3. The second data bus branch L3-2 is a bus branch on the data bus L3 connected to the external random access memory 102. The third data bus branch L3-3 is a bus branch on the data bus L3 connected to the microprocessor 101.

[0057] The path switching circuit 1042 on the address bus L2 is arranged between the first address bus branch L2-1 and the second branch intersection p2, the first address bus branch L2-1 is a bus branch on the address bus L2 connected to the read-only memory 103, the second branch intersection p2 is the intersection of the second address bus branch L2-2 and the third address bus branch L2-3, the second address bus branch L2-2 is a bus branch on the address bus L2 connected to the external random access memory 102, and the third address bus branch L2-3 is a bus branch on the address bus L2 connected to the microprocessor 101.

[0058] The path switching circuit on the data bus and the path switching circuit on the address bus are set between the intersection of the bus branch connecting the ROM and the bus branch connecting the microprocessor and the bus branch connecting the RAM. The path switching circuit will only affect the path of the microprocessor accessing the ROM, but will not affect the path of the microprocessor accessing the external RAM. While realizing the switching of the program access path of the microprocessor, it can ensure the normal access of the microprocessor to the external RAM.

[0059] In a specific design, the path switching circuit 104 may include a plurality of relay subcircuits. The number of relay subcircuits included in the path switching circuit 104 is the same as the number of buses corresponding to the path switching circuit 104. One relay subcircuit is used to control the program access path on one bus. For example, if a group of data buses includes 8 data buses, then the path switching circuit on a group of data buses includes 8 relay subcircuits, and one relay subcircuit is set on one data bus. The composition structure of the relay subcircuits on each bus is the same. For example, the relay subcircuits on one bus can be as follows: Figure 5As shown, it includes a first resistor R1, a second resistor R2, a transistor Q1, a relay K1 and a diode D1, wherein one end of the first resistor is connected to the enable end en of the microprocessor 101, the other end of the first resistor R1 is connected to one end of the second resistor R2 and the base of the transistor Q1, the other end of the second resistor R2 is connected to the emitter of the transistor Q1 and is grounded, the collector of the transistor Q1 is connected to one end of the coil of the relay K1 and the anode of the diode D1, the cathode of the diode D1 is connected to the other end of the coil of the relay K1 and is connected to a power supply, the normally closed end of the switch of the relay K1 is connected to the first bus branch, the first bus branch is a bus branch connected to a read-only memory on the bus, the normally open end of the switch of the relay K1 is connected to the second bus branch, the second bus branch is a bus branch connected to an external random access memory on the bus, the common end of the switch of the relay K1 is connected to the branch intersection p, the branch intersection p is the intersection of the second bus branch and the third bus branch, and the third bus branch is a bus branch connected to the microprocessor 101 on the bus. Taking one of the buses (data bus or address bus) between the microprocessor 101, the random access memory 102 and the read-only memory 103 as an example, the bus connection without the relay subcircuit is as follows: Fig. 6A As shown, in Fig. 6A The bus settings shown are Figure 5 After the relay subcircuit shown, the bus connections are as follows Figure 6B shown.

[0060] Figure 5 The working principle of the relay subcircuit shown is: when the enable terminal en of the microprocessor outputs a low level, the transistor Q1 is in the off state, the coil of the relay K1 is not energized, the common terminal of the switch of the relay K1 is connected to the normally closed terminal of the switch of the relay K1, the first bus branch is connected to the bus, and the read-only memory 103 is connected to the bus; when the enable terminal en of the microprocessor outputs a high level, the transistor Q1 is in the on state, the coil of the relay K1 is energized, the common terminal of the switch of the relay K1 is connected to the normally open terminal of the switch of the relay K1, the second bus branch is connected to the bus, and the external random access memory is connected to the bus.

[0061] By setting the same relay subcircuit on each data bus and each address bus between the microprocessor 101, the external random access memory 102 and the read-only memory 103, a path switching circuit on the data bus and a path switching circuit on the address bus can be obtained.

[0062] It should be understood that the path switching circuit 104 may also have other feasible circuit designs, and is not limited to the circuit designs of Figure 5 The relay sub-circuit composition shown in the figure does not limit the specific circuit form of the path switching circuit 104 in this application.

[0063] In the above Figure 4 In the corresponding technical solution, the microprocessor system includes a microprocessor, an external RAM and a ROM, the address ranges of the external RAM and the ROM overlap, the microprocessor and the RAM and the ROM are connected to a control bus, an address bus and a data bus, and a path switching circuit is provided on the data bus and the address bus. The path switching circuit is used to switch the program in the ROM to the external RAM for execution by switching the program access path of the microprocessor; since the speed at which the microprocessor accesses the external RAM is significantly faster than the speed at which the microprocessor accesses the ROM, by providing a path switching circuit on the data bus and the address bus in the microprocessor system, the path switching circuit switches the program in the ROM to the external RAM for execution by switching the program access path of the microprocessor, which can increase the speed at which the microprocessor reads and executes the program, thereby increasing the program execution rate.

[0064] The microprocessor 101 in the microprocessing system 10 is described in detail below.

[0065] Among them, the microprocessor 101 in the microprocessor system 10 is connected to three groups of buses through an input / output (I / O) port. The I / O port of the microprocessor 101 includes a control interface, which is connected to the control bus L1; the I / O port of the microprocessor 101 also includes an address interface, which is connected to the address bus L2; ​​the I / O port of the microprocessor 101 also includes a data interface, which is connected to the data bus L3. The I / O port of the microprocessor 101 may also include an I / O port for realizing other functions. The number and specific use of the I / O port of the microprocessor 101 in the microprocessor system 10 depends on the specific design of the microprocessor 101, and this application does not limit it.

[0066] In a specific design, the I / O port of the microprocessor 101 for connecting the three groups of buses may include a first interface and a second interface, the first interface is a data address common interface, the data address common interface is used to connect the data bus and the address bus; the second interface is an address interface, the address interface is used to connect the address bus. For example, the microprocessor 101 is a microprocessor of the MCS-51 series, which can be referred to Figure 7 The P0 port (P0.0 pin ~ P0.7 pin) in the MCS-51 series of microprocessors is a shared data address interface. The P0 port is used to connect both the data bus and the address bus. The P2 port (P2.0 pin ~ P2.7 pin) in the MCS-51 series of microprocessors is an address interface. The P2 port is used to connect the address bus.

[0067] In the case where the I / O port of the microprocessor 101 for connecting the three groups of buses includes a first interface and a second interface, the microprocessor system 10 can refer to Figure 8, the data bus L3 is connected between the first interface J1 and the external random access memory 102 and the read-only memory 103 .

[0068] The address bus L2 includes a first address bus L2a and a second address bus L2b. The first address bus L2a is connected between the first interface J1 and the external random access memory 102 and the read-only memory 103. The second address bus L2b is connected between the second interface J2 and the external random access memory 102 and the read-only memory 103. The microprocessor system 10 also includes an address latch 105, which is arranged on the first address bus L2a.

[0069] The path switching circuit 1042 on the address bus L2 includes a first path switching circuit 1042a and a second path switching circuit 1042b. The first path switching circuit 1042a is set between the intersection of the first address bus branch and the second branch on L2a on the first address bus, and the second path switching circuit is set between the intersection of the first address bus branch and the second branch on the first address bus L2b.

[0070] When there are multiple groups of address buses, multiple groups of program access paths of the microprocessor can be controlled by setting multiple path switching circuits.

[0071] It can be understood that the number of path switching circuits and their specific locations on the data bus and address bus depend on the specific design of the microprocessor 101. The number and specific locations of the path switching circuits will vary accordingly depending on the model of the microprocessor 101. The present application does not limit the number of path switching circuits and their specific locations on the data bus and address bus.

[0072] Among them, the microprocessor 101 is used to back up the target program to the external random access memory 102 when the target program to be executed in the read-only memory 103 is a preset program. When executing the target program, the control path switching circuit 104 switches the program access path of the microprocessor 101 from accessing the read-only memory 103 to accessing the external random access memory 102, obtains the target program access path, and executes the target program based on the target program access path.

[0073] The preset program is a program in the predefined read-only memory 103 that needs to be loaded into the external RAM for execution. The preset program can be some programs that run complex algorithms, or programs that need to be executed quickly. For example, the preset program can be a firmware upgrade program. Of course, the preset program can also be other programs that need to be executed quickly. This application does not limit what kind of program the preset program is.

[0074] Backing up the target program to the external random access memory 102 means copying the target program stored in the read-only memory 103 to the external random access memory 102, so that the target program exists in the external random access memory 102. The target program stored in the read-only memory 103 can be copied to a predefined array (hereinafter referred to as the predefined array) in the external random access memory 102, the predefined array is used to store the target program, the address of the predefined array in the external random access memory 102 is determined, the address of the predefined array in the external random access memory 102 is used as the backup address of the target program in the external random access memory, and an address mapping relationship between the backup address of the target program in the external random access memory and the storage address of the target program in the read-only memory 103 is established.

[0075] For example, see Fig. 9 , the address of the target program Function() in the ROM is 0x100H-0x01FFH, then the address 0x100H-0x01FFH in the external random access memory 102 can be used as the address of the predefined array, and the target program Function() can be stored in the predefined array, and a mapping relationship is established between the address 0x100H-0x01FFH of the predefined array in the external random access memory 102 and the address 0x100H-0x01FFH of the target program in the ROM.

[0076] It should be noted that the backup address of the target program in the external random access memory 102 and the storage address of the target program in the read-only memory 103 may be different.

[0077] The path for the microprocessor 101 to access the read-only memory 103 can be as follows: Figure 4 As shown in the dotted line path l11 and the dotted line path l12 in FIG. 1 , the dotted line path l11 and the dotted line path l12 are the original program access paths. The path for the microprocessor 101 to access the external random access memory 102 can be as follows: Figure 4 The dotted line path l21 and the dotted line path l22 in FIG. 1 are the target program access paths. Switching the program access path of the microprocessor 101 from accessing the read-only memory 103 to accessing the external random access memory 102 to obtain the target program access path means switching the program access path of the microprocessor 101 from accessing the read-only memory 103 to accessing the external random access memory 102 to obtain the target program access path. Figure 4 The dotted path l11 and the dotted path l12 in the Figure 4 The dotted path l21 and the dotted path l22 in .

[0078] The microprocessor 101 can switch the program access path of the microprocessor 101 from accessing the read-only memory 103 to accessing the external random access memory 102 by enabling the path switching circuit 104, thereby obtaining the target program access path. The path switching circuit 104 includes a plurality of relay subcircuits, and the relay subcircuits are as follows: Figure 5 As shown in the figure as an example, the microprocessor 101 can write a high level in the register, and the register outputs a high level signal to the enable end of the microprocessor 101. The high level signal serves as an enable signal, so that the coils in each relay sub-circuit in the path switching circuit 104 are energized, the connection between the bus and the first bus branch (the bus branch connected to the read-only memory on the bus) is disconnected, and the connection between the bus and the second bus branch (the bus branch connected to the external random access memory on the bus) is connected, thereby switching the program access path of the microprocessor 101 from accessing the read-only memory to accessing the external random access memory, thereby enabling the path switching circuit 104.

[0079] The microprocessor 101 is also used to control the path switching circuit 104 to switch the program access path of the microprocessor 101 from accessing the external random access memory 102 back to accessing the read-only memory 103 to obtain the original program access path after the target program is executed. Switching the program access path of the microprocessor 101 from accessing the external random access memory 102 back to accessing the read-only memory 103 to obtain the original program access path means that Figure 4 The dotted path l21 and the dotted path l22 in the Figure 4 The dotted path l11 and the dotted path l12 in .

[0080] The microprocessor 101 can switch the program access path of the microprocessor 101 from accessing the external random access memory 102 back to accessing the read-only memory 103 by disabling the enable of the path switching circuit 104, thereby obtaining the original program access path. The path switching circuit 104 includes a plurality of relay subcircuits, and the relay subcircuits are as follows: Figure 5 Taking the example shown, the microprocessor 101 can write a low level in the register, and the register outputs a low level signal to the enable end of the microprocessor 101. The low level signal serves as a non-enable signal, so that the coils in each relay sub-circuit in the path switching circuit 104 are powered off, the connection between the bus and the second bus branch is disconnected, and the connection between the bus and the first bus branch is restored, thereby switching the program access path of the microprocessor 101 from accessing the external random access memory back to accessing the read-only memory, thereby enabling and shutting down the path switching circuit 104.

[0081] Based on the above-mentioned microprocessor system 10, the program execution method of the present application can be implemented, and the program execution method of the present application aims to load the program in the ROM into the RAM for execution, so as to improve the execution rate of the program. The program execution method of the present application is introduced below.

[0082] See also Fig.10 , Fig.10 A flowchart of a program execution method provided in an embodiment of the present application is shown, and the method is applied to the aforementioned microprocessing system 10, such as Fig.10 As shown, the method comprises the following steps:

[0083] S201, obtaining a target program to be executed in a read-only memory in a microprocessor system.

[0084] S202, determining whether the target program is a preset program.

[0085] It can be determined whether the target program has a preset mark; if the target program has a preset mark, the target program is determined to be a preset program; if the target program does not have a preset mark, the target program is determined not to be a preset program. The preset mark is a mark used to indicate that the target program needs to be loaded into the external RAM for execution, and the preset mark is pre-written in the preset program.

[0086] When the target program is a preset program, it means that the target program is a program that needs to be accelerated and needs to be loaded into the external RAM for execution, and step S203 is executed; when the target program is not a preset program, it means that the target program is a program that does not need to be accelerated and is executed normally in the ROM, and step S208 is executed.

[0087] S203, backing up the target program to an external random access memory.

[0088] Here, regarding the implementation principle of step S203, reference may be made to the aforementioned detailed introduction to the microprocessor 101, which will not be repeated here.

[0089] S204, when executing the target program, controlling the path switching circuit in the microprocessor system to switch the program access path of the microprocessor from accessing the read-only memory in the microprocessor system to accessing the external random access memory in the microprocessor system, thereby obtaining the target program access path.

[0090] Here, regarding the meaning of the target program access path and the specific implementation principle of switching the program access path of the microprocessor, please refer to the above-mentioned specific introduction to the microprocessor 101, which will not be repeated here.

[0091] S205: Execute the target program based on the target program access path.

[0092] Wherein, in the process of executing the target program based on the target program access path, the backup address of the target program in the external random access memory can be sent to the external random access memory through the target program access path, and the target program obtained from the backup address by the external random access memory is received; and the target program is executed. Wherein, the backup address of the target program in the external random access memory can be determined according to the address mapping relationship between the backup address of the target program in the external random access memory and the storage address of the target program in the read-only memory, and the backup address of the target program in the external random access memory can be sent to the external random access memory through the target program access path on the address bus, and the target program obtained from the backup address by the external random access memory is received through the target program access path on the data bus. The target program access path on the address bus and the target program access path on the data bus can be respectively as follows: Figure 4 As shown in l21 and l22.

[0093] S206, determining whether the target program has been executed to completion.

[0094] If the target program is executed, step S207 is executed; if the target program is not executed, step S205 is continued.

[0095] Among them, after the execution of the target program is completed, the backup of the target program in the external random access memory in the microprocessor system can also be deleted. Deleting the backup of the target program in the external random access memory in the microprocessor system includes deleting the target program stored in the backup address in the external random access memory in the microprocessor system, and deleting the address mapping relationship between the backup address of the target program in the external random access memory and the storage address of the target program in the read-only memory.

[0096] After the target program is executed, by deleting the backup of the target program in the external RAM, the program's occupation of the external RAM can be avoided, thus saving storage space of the external RAM.

[0097] S207, controlling the path switching circuit in the microprocessor system to switch the program access path of the microprocessor in the microprocessor system from accessing the external random access memory in the microprocessor system to accessing the read-only memory in the microprocessor system, and obtaining the original program access path.

[0098] S208, executing the target program based on the original program access path.

[0099] In the process of executing the target program based on the original program access path, the storage address of the target program in the read-only memory can be sent to the read-only memory through the original program access path, and the target program obtained by the read-only memory from the storage address of the target program can be received; then the target program is executed. In the process of executing the target program based on the original program access path, the storage address of the target program in the read-only memory can be sent to the read-only memory through the original program access path on the address bus, and the target program obtained by the read-only memory from the storage address of the target program can be received through the original program access path on the data bus. The original program access path on the address bus and the original program access path on the address bus are respectively as follows: Figure 4 As shown in l11 and l12.

[0100] In the technical solution corresponding to the above-mentioned Figure 6, when the target program to be executed in the ROM is a preset program, the target program is backed up to the external RAM, and when the target program is executed, the path switching circuit is controlled to switch the program access path of the microprocessor from the ROM to the external RAM to obtain the target program access path, and the target program is executed based on the target program access path. The target program can be copied to the external RAM for execution. Since the speed at which the microprocessor accesses the external RAM is significantly faster than the speed at which the microprocessor accesses the ROM, copying the target program to the external RAM for execution can improve the execution rate of the target program.

[0101] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0102] The above disclosure is only the preferred embodiment of the present application, which certainly cannot be used to limit the scope of rights of the present application. Therefore, equivalent changes made according to the claims of the present application are still within the scope covered by the present application.

Claims

1. A microprocessing system, characterized in that: The invention comprises a microprocessor, an external random access memory and a read-only memory, wherein the address range of the external random access memory overlaps with the address range of the read-only memory; wherein: The microprocessor, the external random access memory and the read-only memory are connected to three groups of buses, which are a control bus, an address bus and a data bus; The data bus and the address bus are both provided with a path switching circuit, and the path switching circuit is used to switch the program in the read-only memory to the external random access memory for execution by switching the program access path of the microprocessor.

2. The microprocessing system according to claim 1, characterized in that: The path switching circuit on the data bus is arranged between a first data bus branch and a first branch intersection, the first data bus branch is a bus branch on the data bus connected to the read-only memory, the first branch intersection is an intersection of a second data bus branch and a third data bus branch, the second data bus branch is a bus branch on the data bus connected to the external random access memory, and the third data bus branch is a bus branch on the data bus connected to the microprocessor; The path switching circuit on the address bus is arranged between the intersection of a first address bus branch and a second branch, the first address bus branch is a bus branch on the address bus connected to the read-only memory, the second branch intersection is an intersection of a second address bus branch and a third address bus branch (L2-3), the second address bus branch is a bus branch on the address bus connected to the external random access memory, and the third address bus branch is a bus branch on the address bus connected to the microprocessor.

3. The microprocessing system according to claim 2, characterized in that: The microprocessor comprises a first interface and a second interface, wherein the first interface is a data address common interface and the second interface is an address interface; wherein: The data bus is connected between the first interface and the external random access memory and the read-only memory; The address bus includes a first address bus and a second address bus, wherein the first address bus is connected between the first interface and the external random access memory and the read-only memory, and the second address bus is connected between the second interface and the external random access memory and the read-only memory, and the microprocessor system further includes an address latch, which is arranged on the first address bus; The path switching circuit on the address bus includes a first path switching circuit and a second path switching circuit, the first path switching circuit is arranged between the intersection of the first address bus branch and the second branch on the first address bus, and the second path switching circuit is arranged between the intersection of the first address bus branch and the second branch on the second address bus.

4. The microprocessing system according to any one of claims 1 to 3, characterized in that: The microprocessor is used to back up the target program to be executed in the read-only memory to the external random access memory when the target program to be executed in the read-only memory is a preset program, and when executing the target program, control the path switching circuit to switch the program access path of the microprocessor from accessing the read-only memory to accessing the external random access memory, thereby obtaining the target program access path, and executing the target program based on the target program access path.

5. The microprocessing system according to claim 4, characterized in that: The microprocessor is also used to control the path switching circuit to switch the program access path of the microprocessor from accessing the random access memory to accessing the read-only memory after the execution of the target program is completed, so as to obtain the original program access path.

6. A program execution method, characterized in that: Applied to the microprocessing system according to any one of claims 1 to 5, the method comprises: Obtaining a target program to be executed in the read-only memory; When the target program is the preset program, backing up the target program to the external random access memory, and when executing the target program, controlling the path switching circuit to switch the program access path of the microprocessor from accessing the read-only memory to accessing the external random access memory, so as to obtain the target program access path; The target program is executed based on the target program access path.

7. The method according to claim 6, characterized in that The method further comprises: After the execution of the target program is completed, the path switching circuit is controlled to switch the program access path of the microprocessor from accessing the random access memory to accessing the read-only memory, so as to obtain the original program access path.

8. The method according to claim 6, characterized in that After obtaining the target program to be executed in the read-only memory, the method further includes: Determine whether the target program has a preset mark; If the target program has a preset mark, determining that the target program is the preset program; If the preset mark does not exist for the target program, it is determined that the target program is not the preset program.

9. The method according to claim 6, characterized in that The executing the target program based on the target program access path includes: Sending a backup address of the target program in the external random access memory to the external random access memory through the target program access path, and receiving the target program obtained by the external random access memory from the backup address; Execute the target program.

10. The method according to any one of claims 6 to 9, characterized in that: After obtaining the target program to be executed in the read-only memory, the method further includes: In the case that the target program is not the preset program, the step of backing up the target program to the external random access memory is skipped, and when executing the target program, the path switching circuit is controlled to switch the program access path of the microprocessor from accessing the read-only memory to accessing the external random access memory to obtain the target program access path.

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