A verification method, apparatus, electronic device, and readable storage medium

Abstract

The embodiment of the present invention provides a verification method, device, electronic device and readable storage medium, the method comprising: configuring a test item in a first file, and setting a link address of the first file in a link script of a test program; the test program is used to provide an underlying operating environment for the test case of the test item; compiling the test program based on a compilation tool chain and the link script to obtain a binary file corresponding to the test program; mirroring the binary file and the first file to obtain a first image file; loading the first image file in a simulation system, and driving the design to be tested to run the test program, so as to load the first file from the link address and execute the test case corresponding to the test item. The embodiment of the present invention can reduce the compilation power consumption of the test program, which is conducive to improving the overall verification efficiency of the processor chip system.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a verification method, device, electronic device and readable storage medium. Background Art

[0002] In the verification of the central processing unit (CPU) chip system, since there are many test items, it is usually necessary to compile many test items for testing. When the general code of the test program changes (optimization or bug fixes), all test items need to be recompiled and updated, and the modified test program is used for testing. Sometimes there are hundreds or thousands of test items, and such a recompilation process is time-consuming and labor-intensive. Summary of the invention

[0003] The embodiments of the present invention provide a verification method, device, electronic device and readable storage medium, which can solve the problem of time-consuming and labor-intensive recompiling process after the general code of the test program changes in the related art.

[0004] In one aspect, an embodiment of the present invention discloses a verification method, the method comprising:

[0005] Configuring the test items in a first file, and setting the link address of the first file in a link script of a test program; the test program is used to provide an underlying operating environment for the test cases of the test items;

[0006] Compile the test program based on the compilation tool chain and the link script to obtain a binary file corresponding to the test program;

[0007] Performing image packaging on the binary file and the first file to obtain a first image file;

[0008] The first image file is loaded in the simulation system, and the design to be tested is driven to run the test program, so as to load the first file from the link address and execute the test case corresponding to the test item.

[0009] Optionally, the method further comprises:

[0010] Modifying the test item into a target test item in the first file according to the link address;

[0011] In the simulation system, the design to be tested is driven to reload the first file from the link address, and the test case corresponding to the target test item is executed.

[0012] Optionally, the method further comprises:

[0013] After the source code of the test program changes, the test program is recompiled based on the compilation tool chain and the link script to obtain a target binary file corresponding to the test program;

[0014] The target binary file and the first file are packaged as an image to obtain a new first image file.

[0015] Optionally, the performing image packaging on the binary file and the first file to obtain the first image file includes:

[0016] Mirror-packing the binary file and the first file according to the link address to obtain a first mirror file;

[0017] The offset of the packaging position of the first file in the first image file relative to the starting address of the binary file in the first image file is equal to the offset of the link address in the link script.

[0018] Optionally, before configuring the test items in the first file, the method further includes:

[0019] Write test cases corresponding to each test item in the test program.

[0020] Optionally, the compilation tool chain includes a compiler and a linker; the compiling process of the test program based on the compilation tool chain and the link script to obtain a binary file corresponding to the test program includes:

[0021] Compiling the source files of the test program using the compiler to obtain binary files corresponding to each source file;

[0022] The linker is used to execute the link script to merge the binary files of the various source files into a binary file corresponding to the test program.

[0023] On the other hand, an embodiment of the present invention discloses a verification device, the device comprising:

[0024] A configuration module, configured to configure a test item in a first file, and to set a link address of the first file in a link script of a test program; the test program is configured to provide an underlying operating environment for a test case of the test item;

[0025] A compiling module, used for compiling the test program based on a compiling tool chain and the linking script to obtain a binary file corresponding to the test program;

[0026] A packaging module, used for performing image packaging on the binary file and the first file to obtain a first image file;

[0027] The first loading module is used to load the first image file in the simulation system and drive the design to be tested to run the test program, so as to load the first file from the link address and execute the test case corresponding to the test item.

[0028] Optionally, the device further comprises:

[0029] A modification module, used for modifying the test item into a target test item in the first file according to the link address;

[0030] The second loading module is used to drive the design to be tested to reload the first file from the link address in the simulation system and execute the test case corresponding to the target test item.

[0031] Optionally, the compiling module is further used for:

[0032] After the source code of the test program changes, the test program is recompiled based on the compilation tool chain and the link script to obtain a target binary file corresponding to the test program;

[0033] The packaging module is also used to:

[0034] The target binary file and the first file are packaged as an image to obtain a new first image file.

[0035] Optionally, the packaging module includes:

[0036] A packaging submodule, used for performing mirror packaging on the binary file and the first file according to the link address to obtain a first mirror file;

[0037] The offset of the packaging position of the first file in the first image file relative to the starting address of the binary file in the first image file is equal to the offset of the link address in the link script.

[0038] Optionally, the device further comprises:

[0039] The test case writing module is used to write the test cases corresponding to each test item in the test program.

[0040] Optionally, the compilation tool chain includes a compiler and a linker; the compilation module includes:

[0041] A compiling submodule, used to compile the source files of the test program using the compiler to obtain binary files corresponding to each source file;

[0042] The link submodule is used to execute the link script using the linker to merge the binary files of the various source files into a binary file corresponding to the test program.

[0043] On the other hand, an embodiment of the present invention further discloses an electronic device, which includes a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the aforementioned verification method.

[0044] The embodiment of the present invention further discloses a readable storage medium. When instructions in the readable storage medium are executed by a processor of an electronic device, the electronic device can execute the aforementioned verification method.

[0045] The embodiments of the present invention include the following advantages:

[0046] The embodiment of the present invention provides a verification method, which can ensure that the first file will not be overwritten or occupied by other files during the compilation process by configuring the test items in a special first file, distinguishing the test items from the system files of the test program, and specifying a special link address for the first file in the link script of the test program; the embodiment of the present invention packages the first file together with the binary file of the test program, and the simulation system can quickly deploy the test program by loading the packaged first mirror file, drive the content in the first file, and provide the design to be tested with the test cases corresponding to the test items therein. In the embodiment of the present invention, the configuration file of the test item is decoupled from the test program, and the first file configuring the test item is independent of the system file of the test program. When the general code of the test program changes, it is only necessary to recompile the general code of the test program, and re-package the recompiled binary file with the first file by mirroring, without recompiling the test items, simplifying the compilation process after modifying the test program, reducing the compilation power consumption of the test program, and helping to improve the overall verification efficiency of the processor chip system. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0048] Figure 1 is a flowchart of steps of an embodiment of a verification method of the present invention;

[0049] Figure 2is a structural block diagram of a verification device of the present invention;

[0050] Figure 3 It is a structural block diagram of an electronic device for verification provided by an example of the present invention. DETAILED DESCRIPTION

[0051] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0052] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0053] Method Embodiment

[0054] Reference Figure 1 , shows a flowchart of a verification method embodiment of the present invention, the method may specifically include the following steps:

[0055] Step 101, configuring a test item in a first file, and setting a link address of the first file in a link script of a test program; the test program is used to provide an underlying operating environment for a test case of the test item;

[0056] Step 102: compile the test program based on the compilation tool chain and the link script to obtain a binary file corresponding to the test program;

[0057] Step 103: Mirror-pack the binary file and the first file to obtain a first mirror file;

[0058] Step 104: load the first image file in the simulation system, and drive the design to be tested to run the test program to load the first file from the link address and execute the test case corresponding to the test item.

[0059] The verification method provided by the embodiment of the present invention can generate an image file corresponding to the test program, and the simulation system verifies the design to be tested by loading the image file.

[0060] It should be noted that the Design Under Test (DUT) in the present invention refers to the circuit design or implementation to be tested in prototype verification, for example, a Register Transfer Level (RTL) circuit, a processor chip, an on-chip network, etc., or it can be other hardware designs.

[0061] The simulation system is used to provide a verification platform for the design to be tested. The hardware behavior of the DUT is simulated in the simulation system, and the execution results of the test cases of each test item of the design to be tested are used to verify whether there is a problem with the design to be tested. Exemplarily, the simulation system can be a hardware simulation platform Palladium, a logic simulation tool VCS, a field programmable gate array (FPGA), and the like. Taking the simulation system as an FPGA chip as an example, the RTL circuit of the design to be tested can be converted into a bitstream file, and the design to be tested can be burned to the FPGA chip through the bitstream file. In the verification process of the design to be tested, the first image file is first loaded into the storage module of the FPGA chip, and the design to be tested reads the first image file from the storage module of the FPGA chip and parses it, and executes the test case corresponding to the test item. In the process of executing the test case of the design to be tested, the intermediate state of the design to be tested can be recorded through hardware snapshots, interrupts and other technologies, and the design to be tested can be judged whether it is running wrong according to the intermediate state of the design to be tested and the execution results of the test case.

[0062] The test program in the embodiment of the present invention is used to provide an underlying operating environment for the test case of the test item. As an example, the test program can be understood as a bare metal operating system, the test item refers to a test item for a certain function of the design to be tested, and the test case is a specific test code for the test item. The test program provides the test case with an underlying operating environment; the test case is the specific implementation of the test item in the test system.

[0063] In an embodiment of the present invention, a file specifically used for configuring test items is provided: a first file. The first file may be a general configuration file of a test program, configured to set the test items to be run in the test program. Exemplarily, the first file may be inserted into the test program using the AutoRun tool, so that when the test program is started, the first file is automatically opened and the test items configured in the first file are run to perform the test. For example, the first file may be autorun.cfg.

[0064] It is understandable that configuring the test item in the first file may include: writing the name or unique identifier of the test item to be tested in the test program, as well as other configuration parameters of the test item, such as execution conditions, execution times, and other parameters.

[0065] In a possible application scenario, each test item may correspond to a file or function, and the design to be tested may load a first file and call the file or function corresponding to the test item configured in the first file to execute the test case corresponding to the test item.

[0066] In an embodiment of the present invention, a link address of the first file is set in the link script of the test program, that is, a link address space is specified in the link script of the test program for accessing the first file. The link script is used to describe how to map various parts of the input file to the output file and control the memory layout of the output file. The link script guides the compiler to compile the programming language and tells the compiler which part of the code to put at which offset address during linking. In an embodiment of the present invention, a link address space can be reserved for the first file in the link script, thereby ensuring that the first file will not be overwritten or occupied by other files during the compilation process.

[0067] Furthermore, the link address of the first file may be an address before the system dynamic memory area, thereby separating the output segment where the first file is located from the system dynamic memory area, ensuring that the output segment of the first file will not be allocated and released by the system.

[0068] By compiling the test program based on the compilation tool chain and link script, you can get the binary file corresponding to the test program. It should be noted that the compilation tool chain is used to convert programs written in high-level programming languages ​​into machine languages ​​so that computer hardware can execute them directly. The compilation tool chain can include a compiler, a linker, a debugger, and other auxiliary tools, such as a preprocessor, which is used to process preprocessing instructions in the source code before compilation.

[0069] Among them, the compiler is the core part of the compilation tool chain. Its main function is to convert source code written in high-level programming languages ​​(such as C, C++, Java, etc.) into machine language (binary code) that the target machine can understand. For example, for a C language program, the GCC (GNU Compiler Collection) compiler will process the source file with the ".c" suffix through multiple complex stages such as lexical analysis, syntax analysis, semantic analysis, intermediate code generation, and code optimization, and finally generate an executable file. At the same time, during the compilation process, the compiler will also optimize the code to improve the performance of the program. For example, it can optimize the loop structure, reduce unnecessary calculations, and adjust the instruction order to better utilize the pipeline characteristics of the CPU.

[0070] The linker is used to combine multiple target files (generated by the compiler and assembler) and library files into an executable file or library file. In large software projects, the code is usually divided into multiple source files for development, and each source file will generate a target file after compilation and assembly. The linker will handle the reference relationship between these target files, such as function calls, variable references, etc. For example, if a program contains two source files, main.c and func.c, and main.c calls the function in func.c, the linker will correctly combine the code in these two target files so that the function call can work properly. At the same time, the linker will also handle the program's reference to the library file, such as the standard library in the C language (such as the library file corresponding to stdio.h), and link the relevant code in the library with the program's target file.

[0071] The debugger is used to help developers find and fix errors (bugs) in the program. It allows developers to pause the execution of the program during the program running, view the value of variables, the state of memory, the function call stack and other information. For example, in the GDB (GNU Debugger) debugger, you can use the break command to set a breakpoint at a specified line of code. When the program executes to the breakpoint, you can use the print command to view the value of the variable, such as print variable_name. Through these operations, you can analyze the logic errors or runtime errors of the program.

[0072] In the embodiment of the present invention, the source code of the test program can be first compiled into binary code using a compiler in the compilation tool chain, and then the linker can be used to build each part of the input file of the test program and the library file into a complete executable program, that is, a binary file corresponding to the test program, according to the link address set in the link script. Furthermore, the debugger can also be used to debug and repair errors that occur during the compilation process.

[0073] Next, the binary file of the test program and the first file configured with the test items are mirror-packaged to obtain a first mirror file. It can be understood that the first mirror file is a portable file that contains all the content required to run the test program. In addition to the binary file and the first file of the test program, the first mirror file may also contain the operating environment dependency files, system configuration information, etc. of the test program. Among them, the operating environment dependency files are used to configure the runtime environment of the test program, for example, may include an interpreter and related libraries. The system configuration information may include environment variable settings, user account information, network configuration, etc.

[0074] After the image packaging is completed, the first image file is loaded in the simulation system, and the test program and the test cases corresponding to the test items can be quickly deployed in the simulation system. During the test process, the design to be tested is driven to run the test program, specifically: the first file is loaded from the link address, and the test cases corresponding to the test items configured in the first file are executed.

[0075] Further, it is possible to determine whether the design to be tested is wrong based on the execution of the test case by the design to be tested. For example, if the execution result of the design to be tested does not match the reference result, it can be determined that the design to be tested is wrong. Alternatively, the design to be tested can be controlled to run the test program synchronously with the reference model of the design to be tested, and the execution result of the design to be tested can be compared with the execution result of the reference model. If the execution result of the design to be tested does not match the execution result of the reference model, it can be determined that the design to be tested is wrong. Among them, the reference model is used to implement the same function as the design to be tested. In the process of verifying the design to be tested, it can be considered that the data generated when the reference model is called is correct, and is used as reference data to compare with the data generated by the design to be tested. It can be understood that different reference models are generated for different designs to be tested. As an example, before the design to be tested is subjected to high-level synthesis processing, a source design model of the design to be tested can be generated according to the design code of the C / C++ language of the design to be tested. The source design model has the same algorithm function as the design to be tested and can be used as a reference model of the design to be tested.

[0076] The embodiment of the present invention configures the test items in a special first file, distinguishes the test items from the system files of the test program, and specifies a special link address for the first file in the link script of the test program, so as to ensure that the first file will not be overwritten or occupied by other files during the compilation process; the embodiment of the present invention packages the first file together with the binary file of the test program, and the simulation system can quickly deploy the test program by loading the packaged first mirror file, drive the content in the first file, and allow the design to be tested to execute the test cases corresponding to the test items therein. In the embodiment of the present invention, since the first file for configuring the test items is independent of the system file of the test program, when the general code of the test program changes, it is only necessary to recompile the general code of the test program, and re-package the recompiled binary file with the first file as a mirror, without recompiling the test items, which simplifies the compilation process after modifying the test program, reduces the compilation power consumption, and is conducive to improving the overall verification efficiency of the processor chip system.

[0077] In an optional embodiment of the present invention, the method further includes:

[0078] Step S11, modifying the test item into a target test item in the first file according to the link address;

[0079] Step S12: driving the design to be tested to reload the first file from the link address in the simulation system, and executing the test case corresponding to the target test item.

[0080] In the process of verifying the design under test, the test items configured in the first file can be modified, so as to perform different tests on the design under test. Specifically, the loading address of the first file can be directly accessed according to the link address, and the test items in the first file can be modified to target test items, and then the test program can be reset and re-run to drive the file under test to reload the first file from the link address and execute the test case corresponding to the target test item.

[0081] In an embodiment of the present invention, the simulation system can modify any memory. After loading the packaged first image file for testing into the memory, it can choose to directly access the loading address of the first file to modify the test item, and then reset and start running the test program to execute the test case corresponding to the modified target test item, thereby realizing dynamic loading of the test item.

[0082] It is understandable that the test items in the first file can be modified based on the interface, library function or other software tools provided by the simulation system. For example, for a simulation system implemented using a logic simulation tool VCS, the test items in the first file can be modified based on the interface or library function provided by VCS; or, for a simulation system implemented using FPGA, the test items in the first file can be modified through the jtag interface using the software tools provided by the FPGA manufacturer.

[0083] As an example, when compiling the test program for the first time, the name of the test item to be tested is written in the first file, such as the auto_run.cfg file. When dynamically modifying the test item, directly modify the corresponding content in the script of the simulation system (such as FPGA). For example, configure the memory_test test item in the auto_run.cfg file and then compile it. When the program image is running, the memory_test test will be executed; later, the FPGA script can dynamically modify the memory content of auto_run.cfg to timer_test, and the timer_test test will be executed when the program is running.

[0084] Optionally, the method further comprises:

[0085] Step S21, after the source code of the test program changes, recompile the test program based on the compilation tool chain and the link script to obtain a target binary file corresponding to the test program;

[0086] Step S22: Mirror-package the target binary file and the first file to obtain a new first mirror file.

[0087] In an embodiment of the present invention, if the source code of the test program is changed, for example, the test program is updated, or the test program is debugged and repaired, etc., the test program can be recompiled based on the compilation tool chain, and the target binary file obtained after the recompilation and the first file for configuring the test item are re-imaged and packaged to obtain a new image file. The simulation system loads the new first image file, and then resets and starts running the test program, and the latest test program can be used.

[0088] After the test program is updated, the embodiment of the present invention only needs to recompile the test program and re-image-package the target binary file of the test program and the first file. There is no need to recompile the test items, which simplifies the compilation process after modifying the test program, reduces compilation power consumption, and is beneficial to improving the overall verification efficiency of the processor chip system.

[0089] Optionally, the step 103 of performing image packaging on the binary file and the first file to obtain a first image file includes:

[0090] The binary file and the first file are packaged as images according to the link address to obtain a first image file.

[0091] The offset of the packaging position of the first file in the first image file relative to the starting address of the binary file in the first image file is equal to the offset of the link address in the link script.

[0092] When the binary file of the test program and the first file are image packaged, the binary file of the test program and the first file can be spliced ​​together according to the offset of the link address of the first file in the link script, so that the offset of the packaging position of the first file in the first image file relative to the starting address of the binary file in the first image file is equal to the offset of the link address in the link script.

[0093] Exemplarily, the offset of the link address of the first file in the link script is recorded as offset1, the starting address of the binary file of the test program in the first image file is recorded as address A, and the packaging position of the first file in the first image file is recorded as address B. Address B and address A satisfy the following relationship: address B=address A+offset1.

[0094] In an embodiment of the present invention, when the binary file and the first file of the test program are image packaged, the offset of the packaging position of the first file in the first image file relative to the starting address of the binary file in the first image file is equal to the offset of the link address in the link script, which can ensure that after the simulation system loads the first image file, the running address of the first file is consistent with the link address.

[0095] Optionally, before configuring the test items in the first file, the method further includes:

[0096] Write test cases corresponding to each test item in the test program.

[0097] The test program in the embodiment of the present application is used to provide an underlying operating environment for the test cases of the test items. Before verification, all the test cases that need to be tested can be written in the test program.

[0098] Optionally, the compilation tool chain includes a compiler and a linker; the step 102 of compiling the test program based on the compilation tool chain and the link script to obtain a binary file corresponding to the test program includes:

[0099] Step S31, using the compiler to compile the source files of the test program to obtain binary files corresponding to each source file;

[0100] Step S32: Utilize the linker to execute the link script to merge the binary files of the various source files into a binary file corresponding to the test program.

[0101] It is understood that the compilation tool chain is used to convert programs written in high-level programming languages ​​into machine languages ​​so that computer hardware can directly execute them. The compilation tool chain may include a compiler, a linker, a debugger, and other auxiliary tools, such as a preprocessor, which is used to process preprocessing instructions in the source code before compilation.

[0102] In the embodiment of the present invention, the test program is compiled based on the compilation tool chain and the link script to obtain a binary file corresponding to the test program.

[0103] For example, the source code of the test program can be first compiled into binary code using a compiler in the compilation tool chain, and then a linker can be used to build the binary files and library files corresponding to each source file of the test program into a complete executable program, that is, the binary file corresponding to the test program, according to the link address set in the link script.

[0104] Furthermore, the debugger can be used to debug and repair errors that occur during the compilation process.

[0105] In summary, the embodiment of the present invention provides a verification method, which can ensure that the first file will not be overwritten or occupied by other files during the compilation process by configuring the test items in a special first file, distinguishing the test items from the system files of the test program, and specifying a special link address for the first file in the link script of the test program; the embodiment of the present invention packages the first file together with the binary file of the test program, and the simulation system can quickly deploy the test program by loading the packaged first mirror file, drive the content in the first file, and provide the design to be tested with the test cases corresponding to the test items therein. In the embodiment of the present invention, since the first file for configuring the test items is independent of the system file of the test program, when the general code of the test program changes, it is only necessary to recompile the general code of the test program, and re-package the recompiled binary file with the first file, without recompiling the test items, which simplifies the compilation process after modifying the test program, reduces the compilation power consumption, and is conducive to improving the overall verification efficiency of the processor chip system.

[0106] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0107] Device Embodiment

[0108] Reference Figure 2 , shows a structural block diagram of a verification device of the present invention, and the device may specifically include:

[0109] Configuration module 201, used to configure test items in a first file, and set the link address of the first file in a link script of a test program; the test program is used to provide an underlying operating environment for the test cases of the test items;

[0110] A compiling module 202, configured to compile the test program based on a compiling tool chain and the linking script to obtain a binary file corresponding to the test program;

[0111] The packaging module 203 is used to perform image packaging on the binary file and the first file to obtain a first image file;

[0112] The first loading module 204 is used to load the first image file in the simulation system, and drive the design under test to run the test program, so as to load the first file from the link address and execute the test case corresponding to the test item.

[0113] Optionally, the device further comprises:

[0114] A modification module, used for modifying the test item into a target test item in the first file according to the link address;

[0115] The second loading module is used to drive the design to be tested to reload the first file from the link address in the simulation system and execute the test case corresponding to the target test item.

[0116] Optionally, the compiling module is further used for:

[0117] After the source code of the test program changes, the test program is recompiled based on the compilation tool chain and the link script to obtain a target binary file corresponding to the test program;

[0118] The packaging module is also used to:

[0119] The target binary file and the first file are packaged as an image to obtain a new first image file.

[0120] Optionally, the packaging module includes:

[0121] A packaging submodule, used for performing mirror packaging on the binary file and the first file according to the link address to obtain a first mirror file;

[0122] The offset of the packaging position of the first file in the first image file relative to the starting address of the binary file in the first image file is equal to the offset of the link address in the link script.

[0123] Optionally, the device further comprises:

[0124] The test case writing module is used to write the test cases corresponding to each test item in the test program.

[0125] Optionally, the compilation tool chain includes a compiler and a linker; the compilation module includes:

[0126] A compiling submodule, used to compile the source files of the test program using the compiler to obtain binary files corresponding to each source file;

[0127] The link submodule is used to execute the link script using the linker to merge the binary files of the various source files into a binary file corresponding to the test program.

[0128] In summary, the embodiment of the present invention provides a verification device, which can ensure that the first file will not be overwritten or occupied by other files during the compilation process by configuring the test items in a special first file, distinguishing the test items from the system files of the test program, and specifying a special link address for the first file in the link script of the test program; the embodiment of the present invention packages the first file together with the binary file of the test program, and the simulation system can quickly deploy the test program by loading the packaged first mirror file, drive the content in the first file, and allow the design to be tested to execute the test cases corresponding to the test items therein. In the embodiment of the present invention, since the first file for configuring the test items is independent of the system file of the test program, when the general code of the test program changes, it is only necessary to recompile the general code of the test program, and re-package the recompiled binary file with the first file, without recompiling the test items, which simplifies the compilation process after modifying the test program, reduces the compilation power consumption, and is conducive to improving the overall verification efficiency of the processor chip system.

[0129] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0130] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0131] Regarding the processor in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0132] Reference Figure 3 , is a structural block diagram of an electronic device for verification provided by an embodiment of the present invention. Figure 3 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method of the aforementioned embodiment.

[0133] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0134] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0135] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0136] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The verification method shown.

[0137] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0138] It should be understood by those skilled in the art that the embodiments of the present invention may be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0139] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0140] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0141] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0142] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0143] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0144] The above is a detailed introduction to a verification method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A verification method, characterized in that: The method comprises: Configuring the test items in a first file, and setting the link address of the first file in a link script of a test program; the test program is used to provide an underlying operating environment for the test cases of the test items; Compile the test program based on the compilation tool chain and the link script to obtain a binary file corresponding to the test program; Performing image packaging on the binary file and the first file to obtain a first image file; The first image file is loaded in the simulation system, and the design to be tested is driven to run the test program, so as to load the first file from the link address and execute the test case corresponding to the test item.

2. The method according to claim 1, characterized in that The method further comprises: Modifying the test item into a target test item in the first file according to the link address; In the simulation system, the design to be tested is driven to reload the first file from the link address, and the test case corresponding to the target test item is executed.

3. The method according to claim 1, characterized in that The method further comprises: After the source code of the test program changes, the test program is recompiled based on the compilation tool chain and the link script to obtain a target binary file corresponding to the test program; The target binary file and the first file are packaged as an image to obtain a new first image file.

4. The method according to claim 1, characterized in that: The step of performing image packaging on the binary file and the first file to obtain a first image file includes: Mirror-packing the binary file and the first file according to the link address to obtain a first mirror file; The offset of the packaging position of the first file in the first image file relative to the starting address of the binary file in the first image file is equal to the offset of the link address in the link script.

5. The method according to claim 1, characterized in that Before configuring the test items in the first file, the method further includes: Write test cases corresponding to each test item in the test program.

6. The method according to claim 1, characterized in that The compiling tool chain includes a compiler and a linker; the compiling process of the test program based on the compiling tool chain and the link script to obtain a binary file corresponding to the test program includes: Compiling the source files of the test program using the compiler to obtain binary files corresponding to each source file; The linker is used to execute the link script to merge the binary files of the various source files into a binary file corresponding to the test program.

7. A verification device, characterized in that: The device comprises: A configuration module, configured to configure a test item in a first file, and to set a link address of the first file in a link script of a test program; the test program is configured to provide an underlying operating environment for a test case of the test item; A compiling module, used for compiling the test program based on a compiling tool chain and the linking script to obtain a binary file corresponding to the test program; A packaging module, used for performing image packaging on the binary file and the first file to obtain a first image file; The first loading module is used to load the first image file in the simulation system and drive the design to be tested to run the test program, so as to load the first file from the link address and execute the test case corresponding to the test item.

8. The device according to claim 7, characterized in that The device also includes: A modification module, used for modifying the test item into a target test item in the first file according to the link address; The second loading module is used to drive the design to be tested to reload the first file from the link address in the simulation system and execute the test case corresponding to the target test item.

9. An electronic device, characterized in that: The electronic device includes a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store executable instructions, and the executable instructions enable the processor to execute the verification method as described in any one of claims 1 to 6.

10. A readable storage medium, characterized in that: When the instructions in the readable storage medium are executed by a processor of an electronic device, the processor is enabled to perform the verification method as claimed in any one of claims 1 to 6.

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