Active display pixel circuit and pulse width modulation driving method thereof

Abstract

The present application relates to a pulse width modulation (PWM) driving method for a pixel circuit, which achieves the effect of row-by-row writing and row-by-row luminescence. The present application also relates to an active display pixel circuit and an electronic device including the aforementioned display pixel circuit.

Description

Technical Field

[0001] The present application relates to the field of display, and in particular to an active display pixel circuit, a display device including an active display pixel array, and a pulse width modulation driving method for the display pixel circuit. Background Art

[0002] In recent years, research on micro-light-emitting diode (Micro-LED) display technology has attracted widespread attention. Compared with traditional displays such as liquid crystal displays (LCDs) or organic light-emitting diodes (OLEDs), Micro-LED displays offer advantages such as ultra-high brightness, high contrast, fast switching response speeds, and potentially better stability.

[0003] However, due to the unique optoelectronic characteristics of Micro-LEDs, the Pulse Amplitude Modulation (PAM) method used in traditional displays is not suitable for Micro-LED displays. The reasons include that the current-voltage characteristic curve of Micro-LEDs is steep, much steeper than that of traditional OLED displays, making it difficult to accurately control the display grayscale by controlling the amplitude of current or voltage. The external quantum efficiency (EQE) of Micro-LEDs varies with the driving current, especially at low driving currents, where the EQE decreases significantly. In addition, the emission wavelength of Micro-LEDs varies with the driving current, and a more obvious color shift occurs, especially at low driving currents.

[0004] Existing Micro-LED displays use a pulse width modulation (PWM) drive method, which can maintain high luminous efficiency and a constant wavelength for Micro-LEDs. This solves the problems of low luminous efficiency and wavelength shift associated with PAM (Pulse Width Modulation) drive. However, the existing PWM drive method is also unsuitable for display devices with high frame rates and high display resolutions.

[0005] Furthermore, active displays in applications such as mobile phones and televisions are large or medium in size, and thin-film transistors (TFTs) are often used to fabricate pixel circuits and driver circuits for these active displays. However, TFTs commonly used to fabricate pixel circuits suffer from low mobility and long write times, making them unable to meet the high frame rate and high display resolution requirements of display devices.

[0006] Active displays in applications like AR and VR are miniature in size, and single-crystal silicon CMOS processes are commonly used to fabricate pixel and driver circuits. However, CMOS processes suffer from issues such as device mismatch and high leakage current, and require higher-frequency drive schemes, which translates to higher mobility, compared to TFT processes. CMOS processes also suffer from issues such as insufficient mobility and long write times, making them unable to meet the high frame rate and resolution requirements of display devices.

[0007] Therefore, a new driving method is needed to address the shortcomings of the aforementioned LED pixel circuits in terms of display accuracy, resolution, frame rate, and other aspects, and to improve the performance of active-light-emitting displays. The PWM driving method is not limited to Micro-LEDs but can also be applied to LED, OLED, QLED, and other displays. Summary of the Invention

[0008] In response to the technical problems existing in the prior art, the present application proposes a pulse width modulation driving method for a display pixel circuit, comprising receiving initial display data, wherein for a display pixel circuit, the initial display data of each frame comprises an X-bit L-ary number, wherein X and L are both integers greater than or equal to 2; converting the initial display data into intermediate display data, wherein the intermediate display data comprises a K-ary number having Y bits, wherein Y is an integer greater than 0, X is greater than Y, and K is greater than L and an integer greater than or equal to 3; wherein the intermediate display data corresponds to one frame, each frame is divided into Y subframes, each subframe corresponds to one bit of the intermediate display data, each subframe comprises a write time and a maximum light-emitting time, the maximum light-emitting time in each subframe is at least a function of K and a sequence number y of the subframe, wherein y is an integer greater than 0 and less than or equal to Y; and during the write time of the first subframe of each row, the intermediate display data of the first subframe of each row is used to write the intermediate display data of the first subframe of each row. The display pixel circuit is written using a first data line, and the light-emitting elements in each row of display pixels emit light based on the intermediate display data of the first subframe immediately after the intermediate display data of the first subframe is written; after the maximum light-emitting time of the first subframe of each row ends, the intermediate display data of the second subframe of the corresponding row is written into the display pixel circuit using a second data line, and the light-emitting elements in each row of display pixels emit light based on the intermediate display data of the second subframe immediately after the intermediate display data of the second subframe is written; wherein the sum of the writing time and the longest light-emitting time of the first subframe of the first row and the writing time and the longest light-emitting time of the second subframe is greater than or equal to the sum of the writing time of the first subframe of each row; wherein the actual light-emitting time of the light-emitting element in each subframe is at least a function of the value of the corresponding bit of the intermediate display data, K, and the sequence number y of the subframe, and the actual light-emitting time is less than or equal to the longest light-emitting time of the subframe.

[0009] In particular, the driving method also includes a comparison operation between the intermediate display signal and the reference signal in each subframe, and when the relative relationship between the intermediate display signal and the reference signal changes, the luminous state of the light-emitting element changes, wherein the intermediate display signal includes a voltage corresponding to the value of each bit of the intermediate display data.

[0010] In particular, when the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

[0011] The present application also provides an active display pixel circuit, comprising a light-emitting element; a PWM signal generating module configured to receive a first scanning signal, a second scanning signal, and a reference signal; the PWM signal generating module comprising at least two data lines; the PWM signal generating module further configured to receive a first display signal using a first data line or a second display signal using a second data line under the control of the first scanning signal and the second scanning signal, and output a PWM signal; wherein the PWM signal generating module comprises a comparing unit, the comparing unit configured to compare the first display signal or the second display signal with the reference signal, and to cause the PWM signal to jump when the comparison result changes; a constant current module configured to provide a light-emitting current to the light-emitting element; a switching module coupled between the constant current module and the light-emitting element, configured to be turned on or off under the control of the PWM signal; wherein the intermediate display data comprises a K-ary number having Y bits, where Y is an integer greater than 0 and K is an integer greater than or equal to 3; wherein the intermediate display data corresponds to one frame, each frame is divided into Y subframes, each subframe corresponds to one bit of the intermediate display data, and each subframe corresponds to one bit of the intermediate display data. A frame includes a writing time and a maximum light-emitting time; during the writing time of the first subframe of each row, intermediate display data of the first subframe of each row is written into the display pixel circuit using a first data line, and the light-emitting elements in the display pixels of each row emit light based on the intermediate display data of the first subframe immediately after the intermediate display data of the first subframe is written; wherein the first display signal corresponds to the first subframe; after the maximum light-emitting time of the first subframe of each row ends, intermediate display data of the second subframe of the corresponding row is written into the display pixel circuit using a second data line, and the light-emitting elements in the display pixels of each row emit light based on the intermediate display data of the second subframe immediately after the intermediate display data of the second subframe is written; wherein the second display signal corresponds to the second subframe; wherein the sum of the writing time and the maximum light-emitting time of the first subframe of the first row and the writing time and the maximum light-emitting time of the second subframe is greater than or equal to the sum of the writing time of the first subframe of each row; wherein the actual light-emitting time of the light-emitting element in each subframe is at least a function of the value of the corresponding bit of the intermediate display data, K, and the sequence number y of the subframe, and the actual light-emitting time is less than or equal to the maximum light-emitting time of the subframe.

[0012] In particular, when the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

[0013] In particular, the switching module includes a switching transistor (304, 404, 504, 604 or 704), the control electrode of the switching transistor (304, 404, 504, 604 or 704) is coupled to the PWM signal generating module to receive the PWM signal, the first electrode is coupled to the constant current module, and the second electrode is coupled to the anode of the light-emitting element; and the constant current module includes a first transistor (T34, T44, T54, T64 or T74), the control electrode of the first transistor (T34, T44, T54, T64 or T74) receives an enable signal, the first electrode is configured to receive a high level, and the second electrode is coupled to the first electrode of the switching transistor (304, 404, 504, 604 or 704); wherein the switching transistor and the first transistor are of the same type.

[0014] In particular, the comparison unit in the PWM signal generating module includes a second transistor (T51, T61 or T71) and a first capacitor (C51, C61 or C71); the first end of the first capacitor (C51, C61 or C71) is configured to receive the reference signal; the control electrode of the second transistor (T51, T61 or T71) is coupled to the second end of the first capacitor (C51, C61 or C71), and the first electrode is coupled to the control electrode of the first transistor (T54, T64 or T74); the PWM signal generating module also includes a third transistor (T52, T62, T72), the first electrode of which is configured to receive a high level, the second electrode is coupled to the first electrode of the second transistor (T51, T61 or T71) and serves as the output end of the PWM signal generating module, and the control electrode of which is configured to receive a charging signal; wherein the second transistor and the third transistor are of the same type.

[0015] In particular, the PWM signal generating module further includes four transistors (T63a, T73a), wherein the control electrode of the fourth transistor (T63a, T73a) receives the first scanning signal, the first electrode receives the first display signal, and the second electrode is coupled to the second electrode of the second transistor (T61, T71); a fifth transistor (T63b, T73b), wherein the control electrode of the fifth transistor (T63b, 73b) receives the second scanning signal, the first electrode receives the second display signal, and the second electrode is coupled to the second electrode of the second transistor (T61, T71); and a sixth transistor (T63b, T73b). a transistor (T66, T76), a first electrode of which is coupled to the second electrode of the third transistor, a second electrode of which is coupled to the control electrode of the second transistor (T51, T61 or T71) and the second end of the first capacitor (C51, C61 or C71), and a control electrode of which is configured to receive a reset signal; a seventh transistor (T65, T75), a first electrode of which is coupled to the second electrode of the second transistor (T51, T61 or T71), a second electrode of which is grounded, and a control electrode of which receives an enable signal; wherein the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are of the same type.

[0016] In particular, the constant current module further includes an eighth transistor (T710), a ninth transistor (T77), a tenth transistor (T711), an eleventh transistor (T79), a twelfth transistor (T78) and a second capacitor (C72), wherein the control electrode of the eighth transistor (T710) receives the charging signal, and the first electrode receives a high level; the control electrode of the ninth transistor (T77) receives an enable signal, the first electrode receives a high level, the second electrode is coupled to the second electrode of the eighth transistor (T710), and the control electrode receives the enable signal; the control electrode of the tenth transistor (T711) receives a reset signal, the first electrode is coupled to the eighth transistor (T710) and the first electrode a second electrode of a ninth transistor (T77); a first electrode of the eleventh transistor (T79) coupled to the second electrodes of the eighth transistor (T710) and the ninth transistor (T77), and a second electrode coupled to the first electrode of the first transistor (T74); a first end of the second capacitor (C72) grounded, and a second end coupled to the control electrode of the eleventh transistor (T79); a control electrode of the twelfth transistor (T78) receiving a constant current scan signal, a second electrode coupled to the first electrode of the first transistor (T74), and a first electrode receiving a constant current display signal; wherein the eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor, and the twelfth transistor are of the same type.

[0017] Particularly, the constant current module further comprises a first current bias unit, a first end of which receives a high level, and a second end of which is coupled to the first electrode of the first transistor (T64).

[0018] In particular, the PWM signal generating module further includes a thirteenth transistor (T53a), a first electrode of which receives a first display signal, a second electrode of which is coupled to a control electrode of the second transistor (T51), and a control electrode of which receives a first scan signal; and a fourteenth transistor (T53b), a first electrode of which receives a second display signal, a second electrode of which is coupled to a control electrode of the second transistor (T51), and a control electrode of which receives a second scan signal; wherein the thirteenth transistor and the fourteenth transistor are of the same type.

[0019] In particular, the constant current module further includes a fifteenth transistor (T57), a sixteenth transistor (T59), a seventeenth transistor (T58), and a third capacitor (C52), wherein the first electrode of the fifteenth transistor (T57) receives a high level, and the control electrode receives an enable signal; the first electrode of the sixteenth transistor (T59) is coupled with the second electrode of the fifteenth transistor (T57), and the second electrode is coupled with the first electrode of the first transistor (T54); the first end of the third capacitor (C52) is grounded, and the second end is coupled with the control electrode of the sixteenth transistor (T59); the control electrode of the seventeenth transistor (T58) receives a constant current scan signal, the first electrode receives a constant current display signal, and the second electrode is coupled with the second end of the third capacitor (C52); wherein the fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are of the same type.

[0020] In particular, the comparison unit includes an eighteenth transistor (T31) and a nineteenth transistor (T32), the control electrode of the eighteenth transistor (T31) and the control electrode of the nineteenth transistor (T32) are coupled to each other as the input terminal of the comparison unit, the second electrode of the nineteenth transistor (T32) receives a high level, the second electrode of the eighteenth transistor (T31) is grounded, and the first electrode of the nineteenth transistor (T32) and the first electrode of the eighteenth transistor (T31) are coupled to serve as the output terminal of the comparison unit; and the PWM signal generating module includes a fourth capacitor (C31), a first terminal of which is configured to receive the reference signal, and a second terminal of which is coupled to the input terminal of the comparison unit; the PWM signal generating module includes a fourth capacitor (C31), a first terminal of which is configured to receive the reference signal, and a second terminal of which is coupled to the input terminal of the comparison unit; The signal generating module includes a twentieth transistor (T33a) and a twenty-first transistor (T33b), wherein a first electrode of the twentieth transistor (T33a) receives a first display signal, a first electrode of the twenty-first transistor (T33b) receives a second display signal, second electrodes of the twentieth transistor (T33a) and the twenty-first transistor (T33b) are coupled to an input terminal of the comparison unit, a control electrode of the twentieth transistor (T33a) receives a first scan signal, and a control electrode of the twenty-first transistor (T33b) receives a second scan signal; wherein the nineteenth transistor (T32) is complementary to the eighteenth transistor (T31), the twentieth transistor, and the twenty-first transistor.

[0021] Particularly, the constant current module further comprises a second current bias unit, a first end of the second current bias unit receives a high level, and a second end is coupled to the first electrode of the first transistor (T34).

[0022] In particular, the PWM signal generating module includes a twenty-second transistor (T43a) and a twenty-third transistor (T43b), the second electrode of the twenty-second transistor (T43a) is coupled to the first electrode of the twenty-third transistor (T43b), the control electrode of the twenty-second transistor (T43a) receives the first scanning signal, the control electrode of the twenty-third transistor (T43b) receives the second scanning signal, the first electrode of the twenty-second transistor (T43a) receives the first display signal, and the second electrode of the twenty-second transistor (T43b) receives the second display signal; the PWM signal generating module also includes a fifth capacitor (C41), a first end of which is grounded, and the second end of which is grounded. The two ends are coupled to the second electrode of the twenty-second transistor (T43a) and the first electrode of the twenty-third transistor (T43b); the PWM signal generating module further comprises a buffer, the input end of the buffer is coupled to the output end of the comparison unit, and the output end is coupled to the control electrode of the switching transistor (T404); the comparison unit comprises a twenty-fourth transistor (T41), a twenty-fifth transistor (T42), a twenty-sixth transistor (T46), a twenty-seventh transistor (T45), a twenty-eighth transistor (T47) and a twenty-ninth transistor (T48) and a third current biasing unit; wherein the control electrode and the first electrode of the twenty-fourth transistor (T41) are coupled to the second The control electrode of the fifteenth transistor (T42) is coupled, the second electrodes of the twenty-fourth transistor (T41) and the twenty-fifth transistor (T42) are coupled to each other and receive a high level; the first electrode of the twenty-fifth transistor (T42) is coupled to the input terminal of the buffer and serves as the output terminal of the comparison unit; the control electrode of the twenty-seventh transistor (T45) receives the reference signal, the first electrode thereof is coupled to the first electrode of the twenty-fourth transistor (T41), and the second electrode thereof is coupled to the first electrode of the twenty-eighth transistor (T47); the control electrode of the twenty-sixth transistor (T46) is coupled to the second end of the fifth capacitor (C41), and the first electrode thereof is coupled to the second terminal of the fifth transistor (T47). 42), and its second electrode is coupled to the first electrode of the twenty-eighth transistor (T47); the second electrode of the twenty-eighth transistor (T47) is grounded, the control electrode is coupled to the control electrode and the first electrode of the twenty-ninth transistor (T48), and the second electrode of the twenty-ninth transistor (T48) is coupled to the first end of the fifth capacitor (C41); the first end of the third current bias unit receives a high level, and the second end is coupled to the first electrode of the twenty-ninth transistor (T48); wherein the twenty-fourth transistor (T41) and the twenty-fifth transistor (T42) are of the same type, and are complementary to the types of other transistors in the comparison unit and the PWM signal generation module.

[0023] Particularly, the constant current module further comprises a fourth current bias unit, a first end of the fourth current bias unit receives a high level, and a second end is coupled to the first electrode of the first transistor (T44).

[0024] The present application also provides a display device, which includes a display pixel array, wherein the display pixel array includes any of the display pixel circuits described above, and also includes a timing control circuit, a gate drive circuit, and a data drive circuit; wherein the gate drive circuit is coupled to the timing control circuit and the pixel array, and is configured to provide an enable signal, a scan signal, and a reference signal to the pixel array under the control of the timing control circuit; the data drive circuit is coupled to the timing control circuit and the pixel array, and is configured to provide a display signal to the pixel array under the control of the timing control circuit.

[0025] The present application also provides an electronic device, comprising the display device as described above.

[0026] The driving method disclosed in this application combines the advantages of high precision, long effective luminescence time, and good stability. It can be applied to traditional displays such as OLED and new display circuits such as Micro-LED, and has a wide range of uses. In addition, by adopting the solution of this application, it is possible to effectively increase the proportion of pixel circuit luminescence time while improving the accuracy of grayscale control, thereby improving the display quality of the pixel circuit, improving the operating efficiency of the display device, reducing the display driver power consumption, and achieving better performance of the display device.

[0027] The solution provided in this application can be applied not only to Micro-LED, but also to active displays integrated with thin film transistors, active displays integrated with single-crystal silicon CMOS, and active displays integrated with TFT and single-crystal silicon CMOS. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0029] Figure 1 This is a schematic diagram of the luminous time of the existing digital PWM driving method using a driving mode of writing and emitting light row by row;

[0030] Figure 2A is a schematic structural diagram of an active display pixel circuit according to an embodiment of the present application;

[0031] Figure 2B This is a schematic diagram of the working timing of the pixel circuit during the light-emitting period according to one embodiment of the present application;

[0032] Figure 2CThis is a schematic diagram of the luminous time of a pixel circuit according to an embodiment of the present application using a row-by-row writing and luminous driving method.

[0033] Figure 3A is a structural diagram of an active display pixel circuit according to an embodiment of the present application;

[0034] Figure 3B yes Figure 3A The working timing diagram of the pixel circuit shown;

[0035] Figure 4A is a structural diagram of an active display pixel circuit according to another embodiment of the present application;

[0036] Figure 4B yes Figure 4A The working timing diagram of the pixel circuit shown;

[0037] Figure 5A is a structural diagram of an active display pixel circuit according to yet another embodiment of the present application;

[0038] Figure 5B yes Figure 5A The working timing diagram of the pixel circuit shown;

[0039] Figure 6A is a structural diagram of an active display pixel circuit according to another embodiment of the present application;

[0040] Figure 6B yes Figure 6A The working timing diagram of the pixel circuit shown;

[0041] Figure 7A is a structural diagram of an active display pixel circuit according to yet another embodiment of the present application;

[0042] Figure 7B is a schematic diagram of the working timing of the pixel circuit when the intermediate display data is an octal number; and

[0043] Figure 8 Schematic diagram of the structure of a display device according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0045] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0046] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0047] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be single crystal silicon, hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor. Its control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, the corresponding second electrode may be the source or drain of the field effect transistor, and the control electrode or the third electrode may be the gate; when the transistor is a bipolar transistor, its control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, the corresponding second electrode may be the emitter or collector of the bipolar transistor, and the control electrode or the third electrode may be the base. The transistor may be manufactured using single crystal silicon, amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process. The following description takes the high level as the effective level as an example for explanation.

[0048] The PWM display drive method maintains a constant light-emitting current and changes the average current level within a frame by controlling the duration of the light-emitting current. The average current level determines the brightness of the light-emitting element, reflecting different display grayscales.

[0049] A frame can be divided into multiple subframes (SF), with the number of subframes related to the display data. Each frame of display data can be divided into multiple parts or bits, with one part or bit written into each subframe. In addition to the time taken for a single write operation, a subframe also includes the maximum possible light-emitting time of the light-emitting element within that subframe. The light-emitting time in each subframe is related to the data written into each subframe, and the integral of the light-emitting time of each subframe corresponds to the displayed grayscale within that row and frame.

[0050] In common digital PWM drive methods, display data is a binary number. The value of each bit of this binary number determines whether the light-emitting element in the corresponding subframe emits light. This means that in each subframe, the light-emitting element can only be in one of two states: illuminated or not (0 or 1). Subframes corresponding to the same bit of the binary number in different rows have the same duration of illumination. Furthermore, the maximum possible illumination durations of adjacent subframes in the same row, from the lowest bit to the highest bit, are two times the maximum possible illumination duration. For example, the maximum possible illumination duration in the subframe corresponding to the least significant bit (LSB) of the display data is half the maximum possible illumination duration of the adjacent subframe.

[0051] However, existing digital PWM drive methods display a large number of data bits, resulting in long addressing and programming times and insufficient effective luminescence duration. Furthermore, existing digital PWM drive methods utilize a row-by-row write-to-light-up method. If there are too many subframes, most of the time within a frame is dedicated to writing operations, resulting in a short luminescence duration. Even at high frame rates, the writing time can exceed the entire frame, making digital PWM drive methods unsuitable for high frame rate requirements.

[0052] In addition, due to the special requirements of Micro-LEDs driven by PWM as mentioned above, most of them adopt a driving method of writing row by row and emitting light simultaneously. There is no driving method suitable for Micro-LEDs that write row by row and emit light row by row (hereinafter referred to as row by row emission).

[0053] Figure 1 This is a schematic diagram of the luminous time of the existing digital PWM driving method using a driving method of writing and emitting light row by row. Among them, the dark gray solid line represents the row-by-row writing time of all rows, and the light gray solid line represents the concentrated luminous time of all rows. Figure 1As shown, conventional digital PWM drive methods require waiting for all pixels in the display pixel array to have their respective first subframe data written before using the remaining time in each subframe to simultaneously illuminate all pixels. This means that in conventional PWM drive methods, not only do the multiple write operations across multiple subframes shorten the time available for illumination within a frame, but they also waste some time within each subframe. For example, before the data for the last row of pixels is written, the data for the first row of pixels may have already been written, but there's still a wait before all rows of pixels can simultaneously illuminate.

[0054] In order to solve the technical problems in the above-mentioned PWM driving method and its display circuit, the present application proposes a pulse width modulation (PWM) driving method and an active display pixel circuit, which can realize row-by-row writing and row-by-row lighting to increase the longest possible lighting time while improving the grayscale control accuracy, thereby enabling the active display device to achieve better performance.

[0055] Figure 2A 1 is a schematic diagram of the structure of an active display pixel circuit according to an embodiment of the present application.

[0056] According to one embodiment, Figure 2A As shown, the pixel circuit 200 may include a PWM signal generating module 201, which is coupled to the gate drive circuit and configured to receive an enable signal, a scan signal, and a reference signal. The display pixel circuits in the same row share the same scan and reference signals. The following description uses two signal lines as an example. Of course, more signal lines may be included without departing from the scope of this application.

[0057] According to one embodiment, the PWM signal generation module 201 may be further coupled to the data driving circuit via two display signal lines and configured to receive the first display signal or the second display signal. According to one embodiment, the PWM signal generation module 201 may include a comparison unit 211 configured to compare the first display signal / the second display signal with a reference signal and output a PWM signal based on the comparison result to control the light emission of the pixel circuit 200.

[0058] In this document, the initial display data and the corresponding intermediate display data correspond to the same frame. According to an embodiment of the present application, the intermediate display data can be Y-bit K-base display data converted from the initial display data expressed in X-bit L-base form, where X is an integer greater than or equal to 2, Y is an integer greater than 0, and X is greater than Y; L and K are integers greater than or equal to 2, and L is less than K. Accordingly, the intermediate display data is transmitted by the intermediate display signal. For example, the initial display data can be expressed in binary, and the corresponding intermediate display data can be expressed in a higher base.

[0059] According to an embodiment of the present application, the first display data corresponds to a subframe within a frame, and the first display data may be a bit within the intermediate display data. The second display data corresponds to another subframe within the frame, and the second display data may be another bit within the intermediate display data. The first and second herein are merely used to distinguish one from the other and do not necessarily represent first and second in a sequential order.

[0060] The display signal may be an electrical quantity such as voltage representing display data.

[0061] According to an embodiment of the present application, the PWM signal generating module 201 can be coupled to the data driving circuit through more display signal lines, such as three display signal lines, to receive, for example, the first display signal, the second display signal, or the third display signal, depending on actual needs.

[0062] According to one embodiment, the PWM signal generating module 201 can receive a first scan signal and a second scan signal from the gate driving circuit via two scan signal lines. The first scan signal and the second scan signal can jump to an active level at different times, and the control comparison unit 211 can receive the first display signal and the second display signal at different times.

[0063] According to one embodiment, the pixel circuit 200 may further include a light emitting element 203 and a switch module 204. According to an embodiment of the present application, the light emitting element 203 may include OLED, LED, Micro-LED, QLED, etc., depending on actual needs.

[0064] According to one embodiment, the pixel circuit 200 may further include a constant current module 202 coupled to the light-emitting element 203 via a switch module 204 under the control of a PWM signal output by the PWM signal generating module 201, and configured to provide a constant light-emitting current to the light-emitting element 203. The constant current module 202 may also be coupled to a gate drive circuit and configured to receive an enable signal. According to other embodiments of the present application, the constant current module 202 may have a certain degree of adjustability to meet the different relationships between the luminous efficiency and the light-emitting current of the R, G, and B sub-pixel circuits, thereby maintaining the highest operating efficiency of each sub-pixel circuit.

[0065] According to an embodiment of the present application, J columns of display pixel circuits may receive a first display signal and a second display signal from a data driver circuit via a display signal line. Accordingly, the data driver circuit may include at least 2J digital-to-analog converter (DAC) units, with each display pixel circuit coupled to two DAC units to receive its own first display signal or second display signal. Display pixel circuits in the same column share a DAC unit, where J is an integer greater than 0.

[0066] According to an embodiment of the present application, each DAC unit is configured to receive one bit of display data in the intermediate display data and convert it into, for example, a first display signal or a second display signal.

[0067] The display pixel circuit 200 is controlled to emit light by the intermediate display data, and the time of one frame is correspondingly divided into Y subframes. According to one embodiment of the present application, the write time of each subframe can be the same, which can be referred to as a unit write time. Therefore, compared with the traditional digital PWM driving method, because the number of bits of the intermediate display data (Y bits in K-ary system) is reduced relative to the number of bits of the initial display data (X bits in L-ary system), the write time of one frame is shortened from X unit write times to Y unit write times.

[0068] According to embodiments of the present application, the intermediate display signal can be a corresponding voltage generated based on the value of the intermediate display number, or can be other electrical signals, depending on actual needs. To ensure that the light-emitting element's light-emitting duration in each subframe can range from the maximum possible light-emitting duration to zero, the maximum value of the reference signal should be less than the maximum possible value of the intermediate display signal, and the minimum value of the reference signal should be greater than the minimum possible value of the intermediate display signal.

[0069] According to one embodiment of the present application, both the intermediate display signal and the reference signal described above can be transformed based on specific device structures and other factors, such as by amplifying or reducing the signal accordingly. Whether it is the intermediate display signal and its transformation or the reference signal and its transformation, the original signals before transformation must satisfy the aforementioned relative relationship. The specific signal input to the pixel circuit is determined based on actual needs.

[0070] Depending on the embodiment, the initial display data and the intermediate display data may correspond to the total time a light-emitting element is illuminated or the total time a light-emitting element is not illuminated within a frame, depending on the circuit structure. The total time of illumination or non-illumination within a frame determines the grayscale displayed within that frame.

[0071] According to one embodiment, within a subframe, I rows of pixel circuits may receive a reference signal from a gate driver circuit, where I is an integer greater than 0. Due to the different durations of each subframe, the reference signal lasts for different durations in different subframes. The duration of the reference signal in each subframe is the same as the longest possible luminous duration of the subframe (i.e., the duration of the subframe minus the write time of the subframe). According to one embodiment of the present application, the reference signal may be a ramp signal.

[0072] According to an embodiment of the present application, theoretically, the comparison unit 211 can generate a PWM signal that changes the conduction state of the light emitting element 203 when the magnitude relationship between the reference signal and the display signal changes.

[0073] Figure 2B : is a schematic diagram of the working timing of the pixel circuit according to an embodiment of the present application during the light-emitting time. According to a more preferred embodiment, the reference signal can be a monotonically changing signal that is discontinuous with time, for example, it can be a step signal, such as Figure 2B When the reference signal is a step signal, even when the magnitude relationship between the reference signal and the display signal changes, there will be a large voltage difference between the two. Therefore, the comparison unit 211 can accurately capture this change and quickly output a PWM signal that changes the conduction state of the light-emitting element 203, thereby reducing the error in the light-emitting time and grayscale.

[0074] According to an embodiment of the present application, the step signal serving as a reference signal may include different potentials generated by (K-1) equal-height steps in each subframe, each step having the same duration, and the longest luminous time in each subframe being evenly divided into (K-1) parts.

[0075] According to one embodiment of the present application, the grayscale of a frame is the sum of the grayscales of each subframe. Since each subframe corresponds to a different bit of the intermediate display data, the unit luminous time length corresponding to each subframe is also different. According to an embodiment of the present application, the unit luminous time of each subframe can be expressed as the luminous time T corresponding to the minimum data bit (LSB) of the initial display data. LSB The product of 0 to (Y-1) power of K. The actual luminous time of each subframe may be related to the intermediate display data and the unit luminous time corresponding to the subframe.

[0076] Figure 2C This is a schematic diagram of the light-emission time of a pixel circuit within multiple subframes according to one embodiment of the present application. According to this embodiment of the present application, each pixel circuit 200 in a row receives a scan signal via two shared scan signal lines, as well as a first display signal and a second display signal via two display signal lines, each coupled to a data driver circuit. Therefore, the second display signal corresponding to the second subframe of each pixel circuit in the first row can be written after the longest possible light-emission time of the first subframe of that pixel circuit has expired, without having to wait until the pixel circuits in the same column in the last row have completed writing their first display signals.

[0077] like Figure 2C As shown, the display pixel array in which the pixel circuit 200 is located realizes row-by-row lighting. The PWM driving method of the present application can significantly increase the actual lighting time of a single pixel circuit within a subframe. Since multi-bit display data is used, the number of write operations can be reduced, thereby shortening the total writing time within a frame, thereby increasing the total possible lighting time of the display pixel array within a frame.

[0078] According to an embodiment of the present application, when a single pixel circuit 200 receives display signals via M display signal lines, it requires M scan signal lines to receive M scan signals to control the pixel circuit 200 to emit light based on different display signals at different times. Accordingly, to avoid data conflicts on the display signal lines, the PWM drive method used in the display pixel array in which the pixel circuit 200 is located requires that the write operation of the Mth subframe of the last row of pixels be completed before the write operation of the (M+1)th subframe of each pixel circuit in the first row, where M is an integer greater than or equal to 1 and less than Y.

[0079] Specifically, according to one embodiment of the present application, when the display pixel circuit 200 receives display signals via M display signal lines, the sum of the longest possible light-emitting times of the subframes corresponding to the M received intermediate display data must be greater than or equal to (IM) write times, where I is the total number of rows in the pixel array in which the display pixel circuit 200 is located.

[0080] Taking two display signal lines as an example, for the first row of pixels, the first display signal line and the second display signal line can be used to receive the first display signal and the second display signal corresponding to the first subframe and the second subframe, respectively. Because two display signal lines are used, the writing of the second display signal does not need to wait for the completion of the writing of the first display signal to any row of pixels. However, when transmitting the display data corresponding to the third subframe to the first row of pixels, the first or second display signal line is still required for transmission. Therefore, the writing of the first display signal to the last row of pixels must be completed before the new display data is written.

[0081] According to an embodiment of the present application, the display pixel circuit 200 receives display data of two subframes at different times via two display signal lines. Therefore, the longest possible light-emitting time corresponding to the intermediate display data received by the display pixel circuit 200 needs to satisfy the following relationship:

[0082]

[0083] in, is the longest possible luminous time corresponding to the display data of the y1-th subframe, is the longest possible luminous time corresponding to the display data of the y2-th subframe, T scan is the write time, I is the total number of rows in the display array, y1 and y2 are both integers greater than or equal to 1 and less than or equal to Y, and y1 is not equal to y2. In other words, the sum of the longest light-emitting times of the y1th subframe and the y2th subframe corresponding to the data received by the pixel circuit 200 must be greater than or equal to (I-2) write times.

[0084] According to one embodiment of the present application, the longest possible lighting time of each subframe, for example, the y1-th subframe, is The following relationship is satisfied:

[0085]

[0086] Obviously, the longest possible luminous time of each subframe is related to the base number and the total number of rows in the pixel array. Therefore, in actual production, the total number of rows in the pixel array and the base number can be adjusted according to equations (1) and (2) to achieve better display effects.

[0087] According to one embodiment of the present application, T LSB The following relationship is satisfied:

[0088]

[0089] Wherein, f (frequency, Hz) is the frame rate of the display, and the following calculations are based on a display with a frame rate of 120 Hz; X is the color depth in the initial display data (X bits in base L), and the initial display data is calculated as 10 bits in base 2. According to an embodiment of the present application, under the conditions of a specific number of pixel array rows and a base number, the transmission order of the subframes can be swapped so that the longest possible luminous time corresponding to the subframe of the data currently obtained by the pixel circuit 200 through the two display signal lines satisfies (1).

[0090] Since when receiving the initial display data and converting the intermediate display data, the bit where the display data is located corresponds to the length of the subframe corresponding to the display data in theory, if you want to adjust the length of the theoretically longest possible luminous time of the two subframes by changing the transmission order of the subframes, you can correspondingly change the positions of the two bits of data in the intermediate display data and transmit the display data in the order after the change.

[0091] For example, when the pixel array has 1080 rows, the display frame rate is 120Hz, the display data bit depth is 10 bits, and the display pixel circuit write time is 0.2μs, after converting the 10-bit binary display data into 4-bit octal display data, the maximum possible light-emitting time corresponding to the four sub-frames is: Since the display data corresponding to the fourth subframe is converted from 1-bit binary data, it does not conform to the ratio of the longest possible luminous time of other subframes, which is obtained by calculating the remaining time. Among them, the longest possible luminous time of the third and fourth subframes exceeds the length of (1-2) writing times. Therefore, the order of the second and third subframes can be swapped to arrange the subframe times of the pixel circuit in a short and long arrangement, satisfying the relationship shown in formula (1) and achieving row-by-row writing and luminous.

[0092] According to other embodiments of the present application, the order of data and its corresponding subframes can be arbitrarily changed according to formula (1) in accordance with production requirements, and the present application does not impose any restrictions on this.

[0093] Figure 3A FIG. 1 is a schematic diagram of an active display pixel circuit structure according to an embodiment of the present application. Figure 3A As shown, the pixel circuit 300 may include a PWM signal generating module 301, a constant current module 302, a light emitting element 303, and a switch module such as a switch transistor T304 coupled to the PWM signal generating module 301. The PWM signal generating module 301 may include a comparison unit 311.

[0094] According to one embodiment of the present application, the PWM signal generating module 301 may include transistors T31, T32, T33a, and T33b. Figure 3A As shown, the comparison unit 311 may include transistors T31 and T32 of complementary types connected in series to form an inverter amplifier. For example, transistors T31, T33a, and T33b are N-type transistors, and T32 is a P-type transistor. The control electrode of transistor T31 is coupled to the control electrode of transistor T32. The second electrode of transistor T32 receives a high voltage level VGH, and the first electrode is coupled to the first electrode of transistor T31. The second electrode of transistor T31 is grounded.

[0095] According to one embodiment, for a pixel at row i and column j, the second electrode of transistor T33a is configured to first receive the first display signal DATA corresponding to the pixel. PWM1 [y1]. y1 is any integer from 1 to Y, and refers to the subframe number corresponding to the intermediate display data included in the first display signal DATAPWM1[y1]. DATAPWM1[y1] represents the inverse value of the display signal corresponding to the data of the y1-th subframe in the Y-bit K-ary intermediate display data received by transistor T33a. The first electrode of transistor T33a is coupled to the control electrodes of transistors T31 and T32, and its control electrode is configured to receive the first scan signal SCAN of the row in which the pixel is located. PWM1 [i].

[0096] According to one embodiment, the second electrode of the transistor T33b is configured to receive the second display signal DATA after the pixel finishes emitting light according to the first display signal received by the transistor T33a. PWM2[y2]. y2 is any integer from 1 to Y that is different from y1 and refers to the subframe number corresponding to the intermediate display data included in the second display signal DATAPWM2[y2]. DATAPWM2[y2] represents the inverse value of the display signal corresponding to the data of the y2-th subframe in the Y-bit K-ary intermediate display data received by transistor T33b. The first electrode of transistor T33b is coupled to the control electrodes of transistors T31 and T32, and its control electrode is configured to receive the second scan signal SCAN for the row in which the pixel is located. PWM2 [i].

[0097] According to the embodiments of the present application, Figure 3A In the illustrated pixel circuit 300, the comparison unit 311 does not directly determine the magnitude relationship between the reference signal and the intermediate display signal, or the difference between the two. Instead, it processes the intermediate display signal, generates first and second display signals based on the intermediate display signal, and then performs a comparison operation based on the sum of the reference signal and the first display signal, or the sum of the reference signal and the second display signal. Therefore, the amplitudes of the first and second display signals can be signals generated by adjusting the intermediate display signal according to actual needs, for example, by taking the opposite voltage value of the intermediate display signal. For example, in this embodiment, the intermediate display signal can be a signal with a potential range of -0.5 to 6.5 V, and the first and second display signals can be signals with a potential range of -6.5 to 0.5 V.

[0098] According to an embodiment of the present application, the PWM signal generating module 301 may further include a capacitor C31, a first end of which is configured to receive a reference signal such as a step signal V STEP [i], a second end thereof is coupled to the first electrodes of the transistors T33a and T33b at point A, ie, the input end of the comparison unit 311, and is coupled to the control electrodes of the transistors T31 and T32.

[0099] According to one embodiment of the present application, the reference signal may be a step signal with a potential range of 0-6V. Since the reference signal is a step signal, the step potential increases step by step. In order to achieve normal comparison between the reference signal and the first or second display signal, it is necessary to meet the following requirements: if the first and second display signals correspond to the non-luminous time of the light-emitting element, the maximum value of the reference signal should be less than the inverse of the minimum possible values ​​of the first and second display signals, and the minimum value of the reference signal should be greater than the inverse of the maximum possible values ​​of the first and second display signals. Specifically, the condition shown in formula (1) needs to be met:

[0100]

[0101] Among them, DATA PWM [y] includes the first display signal DATA PWM1[y1] and the second display signal DATA PWM2 [y2].

[0102] According to an embodiment of the present application, the constant current module 302 may include a transistor T34 and a current bias unit. The control electrode of the transistor T34 receives an enable signal EM[i]. The second electrode is coupled to the first electrode of the transistor 304 to control the conduction of the light-emitting element 303. The first electrode of the transistor T34 is coupled to the current bias unit to receive the constant current signal to provide a light-emitting current to the light-emitting element 303.

[0103] According to one embodiment of the present application, the pixel circuit 300 may further include a switching transistor T304, whose control electrode is coupled to the output end of the comparison unit 311 at point B, that is, coupled to the first electrode of the transistor T32 and the first electrode of the transistor T31, receives the PWM signal output by the PWM signal generation module 301, and the first electrode is coupled to the second electrode of the transistor T34, and the second electrode is coupled to the anode of the light-emitting element 303. According to an embodiment of the present application, the transistors T34 and T304 may be N-type transistors.

[0104] According to an embodiment of the present application, the transistors T31 , T32 , T33 a , T33 b , T34 , T35 and T304 may be made of thin film transistors (TFTs), for example, low temperature polycrystalline oxide thin film transistors (LTPO TFTs).

[0105] Figure 3B Shown Figure 3A The pixel circuit 300 is shown as a schematic diagram of two sub-frame operation timings. According to one embodiment of the present application, the pixel circuit 300 includes a writing phase and a light emitting phase in a sub-frame.

[0106] In the writing phase, as shown in FIG3B , the transistor T33a in the pixel circuit of the first row of the pixel array receives the first scan signal SCAN of the first row. PWM1 [1] and turns on, the first display signal DATA PWM1 [y1] is transmitted to the input terminal A of the comparison unit 311. At this time, the potential at point A is DATA PWM1 [y1].

[0107] According to one embodiment, Figure 3B As shown, the present application adopts a mechanism of writing and emitting light row by row, so the pixel circuit of row 1 receives the scan signal SCAN in the first subframe. PWM1 [1] After the writing operation of the display signal is completed, that is, after the pixel circuit of the row receives the first display signal of the first subframe, the pixel circuit is turned on during the light-emitting phase in the first subframe.

[0108] In the light emitting stage, the enable signal EM[1] of the pixel circuit of the first row jumps to a high level, turning on the transistor T34 in the pixel circuit. At this time, the reference signal V STEP [1], the potential V at the second terminal of capacitor C31 IN The corresponding value becomes V IN [1,j]=V STEP [1]+DATA PWM1 [1], as the input of the comparison unit 311.

[0109] According to one embodiment of the present application, when the potential V IN [1, j] is less than the threshold voltage of the transistor T31, which means that the first display signal DATA PWM1 [1] is less than the reference signal V STEP [1], T31 is turned off, T32 is turned on, and the high level VGH is transmitted to the switch transistor T304 through the turned-on transistor T32, turning on the switch transistor T304. At this time, the transistor T34 is also turned on, and the light-emitting element 303 can receive a constant light-emitting current I from the current bias unit. LED [1,j], starts to emit light.

[0110] According to an embodiment of the present application, while the display pixel circuits in the first row enter the light emitting stage, the display pixel circuits in the second row can receive the scan signal SCAN of the row. PWM1 [2], then the writing operation is completed and the light-emitting stage begins. The same process is repeated for other rows until row I.

[0111] According to one embodiment, when V IN [1, j] is greater than the threshold voltage of T31. At this time, T31 is turned on and T32 is turned off. The PWM signal generating module 301 outputs a low level to the switching transistor T304. The transistor T304 is turned off. The light-emitting element 303 no longer emits light, and the light-emitting phase of this subframe ends.

[0112] According to one embodiment, the enable signals EM[1] to EM[I] maintain a high level for a fixed period of time, corresponding to the longest possible luminous time in a subframe. When the longest possible luminous time in the subframe ends, the potential V at point A in the pixel circuit is IN [i, j] is still smaller than the threshold voltage of T31. At this time, the enable signal jumps to a low level, and the transistor T34 is turned off, so that the light-emitting element 303 no longer emits light, and the light-emitting phase of this subframe ends.

[0113] According to one embodiment of the present application, the transistor T33b in the display pixel circuit of the 1st row and the jth column starts to receive the second scan signal SCAN of the 1st row after the light emitting phase of the first subframe ends.PWM2 [1] The second subframe is turned on and the second display signal DATA is transmitted to display data in the middle of the second subframe. PWM2 [2] is transmitted to the input terminal A of the comparison unit 311. At this time, the potential at point A is DATA PWM2 [2] At this time, the pixel circuit 300 starts the writing phase of the second subframe. After the pixel circuits in the first row complete the writing operation, the scanning signal SCAN of the pixel circuits in the second row is PWM2 [2] Turn on and start the writing phase until row I.

[0114] According to an embodiment of the present application, in a pixel array having I rows and J columns of display pixel circuits, the writing phase of the y2-th subframe of the pixel circuit 300 in the i-th row and j-th column can start before the last row of pixel circuits in the display pixel array where it is located ends the writing phase of the y1-th subframe, and end before the 1-th row of pixel circuits starts the writing phase of the (y2+1)-th subframe, where i is an integer greater than 1 and less than I, and j is an integer greater than 1 and less than J.

[0115] Figure 4A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 4A As shown, the pixel circuit 400 may include a PWM signal generating module 401 , a constant current module 402 , a light emitting element 403 , and a switching module such as a switching transistor T404 .

[0116] The PWM signal generating module 401 may include transistors T41, T42, T43a, T43b, T45, T46, T47, and T48, as well as a buffer 412 and a bias current source I bias The comparison unit 411 may include a dual-input operational amplifier circuit formed by transistors T41, T42, T45, T46, T47, and T48, for comparing the display signal with the reference signal. According to an embodiment of the present application, transistors T41 and T42 may be P-type transistors, and T43a, T43b, T45, T46, T47, and T48 may be N-type transistors. The PWM signal generation module may further include a capacitor C41.

[0117] like Figure 4AAs shown, the control electrode of transistor T41 is coupled to the control electrode of transistor T42 and the first electrode of T41. The second electrode of transistor T41 and the second electrode of transistor T42 are coupled to each other and configured to receive the high level VGH. The first electrode of transistor T42 and the first electrode of transistor T46 are coupled at point B, which is the output terminal of the comparison unit. The second electrode of transistor T46 is coupled to the second electrode of transistor T45, and the control electrode is coupled to the second electrode of transistor T43a and the first electrode of T43b. The first electrode of transistor T45 is coupled to the first electrode of transistor T41, and the control electrode is configured to receive the reference signal V STEP [i].

[0118] According to an embodiment of the present application, the first electrode of the transistor T43a is configured to receive the first display signal DATA PWM1 [y1], the control electrode is configured to receive the first scan signal SCAN PWM1 [i], and the second electrode is coupled to the control electrode of transistor T46. Wherein, y1 is any integer between 1 and Y, and refers to the subframe number corresponding to the intermediate display data included in the first display signal DATAPWM1[y1]. DATAPWM1[y1] represents the display signal corresponding to the data of the y1th subframe in the Y-bit K-ary intermediate display data received by transistor T43a.

[0119] According to one embodiment, the second electrode of the transistor T43b may be configured to receive the second display signal DATA PWM2 [y2], whose control electrode can be configured to receive a scan signal SCAN PWM2 [i], whose first electrode is coupled to the control electrode of transistor T46 and one plate of capacitor C41. The other plate of C41 is coupled to the second electrode of T48 and grounded. Wherein, y2 is any integer between 1 and Y that is different from y1 and refers to the subframe number corresponding to the intermediate display data included in the second display signal DATAPWM2[y2]. DATAPWM2[y2] represents the display signal corresponding to the data of the y2-th subframe in the Y-bit K-ary intermediate display data received by transistor T43b.

[0120] According to one embodiment of the present application, the reference signal may be a stepped signal with a potential range of 0-6V. To ensure proper comparison between the reference signal and the intermediate display signal, the amplitudes of the first and second display signals may be adjusted according to actual needs, or may be equal to the voltage value corresponding to the intermediate display signal. For example, in this embodiment, the first and second display signals may be signals with a potential range of -0.5 to 6.5V.

[0121] According to an embodiment of the present application, the input end of the buffer 412 is coupled to the first electrode of the transistor T42 and the first electrode of the transistor T46 at point B, and the output end is coupled to the control electrode of the switching transistor T404 to output a PWM signal to the switching transistor 404 .

[0122] The control electrode of transistor T48 is coupled to its first electrode and the control electrode of transistor T47, and the second electrode is coupled to the second electrode of transistor T47 and grounded. The first electrode of transistor T47 is coupled to the second electrode of transistor T45 to form a current mirror. The first electrode of transistor T48 is also coupled to the bias current source I bias The coupling provides a bias current for the transistor T47 to maintain the normal operation of the comparison unit 411.

[0123] According to one embodiment of the present application, the bias current source I bias It can be located inside or outside the pixel circuit 400.

[0124] According to one embodiment of the present application, the constant current module 402 may include a transistor T44 and a current bias unit. The control electrode of the transistor T44 receives an enable signal EM[i], and the second electrode is coupled to the first electrode of the switching transistor T404 to control the conduction state of the light-emitting element 403. The first electrode of the transistor T44 is coupled to the current bias unit to receive a constant current signal to provide a light-emitting current to the light-emitting element 403.

[0125] According to one embodiment of the present application, Figure 4A In the illustrated pixel circuit 400, to ensure that the reference signal is less than the first or second display signal, causing the light-emitting element to emit light, the current flowing through transistor T46 must be greater than the current flowing through transistor T47 to ensure that the potential at point B is greater than the common-mode level of buffer 412. In other words, the bias voltage of transistor T46 must be greater than the bias voltage of transistor T45, and the difference between the two must be greater than the common-mode level of buffer 412. Therefore, in this embodiment, the difference between the maximum possible value of the first or second display signal and the maximum value of the reference signal must be greater than the common-mode level V of buffer 412. CM Similarly, in order to satisfy the requirement that the reference signal is greater than the first or second display signal to turn off the light emitting element, the difference between the minimum possible value of the first or second display signal and the minimum value of the reference signal should be less than the common mode level V CM Specifically, the conditions shown in formula (5) need to be met:

[0126]

[0127] Among them, DATA PWM [y] includes the first display signal DATA PWM1 [y1] and the second display signal DATA PWM2[y2].

[0128] According to one embodiment of the present application, the pixel circuit 400 may further include a switching transistor T404, whose control electrode is coupled to the output end of the buffer 412 in the PWM signal generating module 401 and receives the PWM signal output by the PWM signal generating module 401. The first electrode of the switching transistor T404 is coupled to the second electrode of the transistor T44, and the second electrode is coupled to the anode of the light-emitting element 403. According to an embodiment of the present application, the transistors T44 and T404 may be N-type transistors.

[0129] According to one embodiment of the present application, the transistors T41 - T49 may be made of CMOS devices.

[0130] Figure 4B yes Figure 4A The pixel circuit 400 is shown as a schematic diagram of two sub-frame operation timings. According to one embodiment of the present application, the pixel circuit 400 includes a writing phase and a light emitting phase in a sub-frame.

[0131] According to one embodiment, in the writing phase, as shown in FIG4B , the transistor T43a of the display pixel circuit in the first row receives the first scan signal SCAN of the first row. PWM1 [1] and turns on, the first display signal DATA PWM1 [y1] is transmitted to one of the input terminals of the comparison unit 411, ie, the control terminal of the transistor T46.

[0132] According to one embodiment, Figure 4B As shown, the present application adopts a mechanism of writing and emitting light row by row, so the pixel circuit of row 1 receives the scan signal SCAN in the first subframe. PWM1 [1] After the writing operation of the display signal is completed, that is, after the pixel circuit of the row receives the first display signal of the first subframe, the pixel circuit is immediately turned on during the light-emitting phase of the first subframe.

[0133] According to one embodiment, in the light emitting stage, the enable signal EM[1] of the pixel circuit in the first row jumps to a high level, the transistor T44 is turned on, and the control electrode of the transistor T45 receives the reference signal V STEP [1], the control electrode of transistor T46 receives the first display signal DATA PWM1 [1], for the first display signal DATA PWM1 [1] with the reference signal V STEP [1] compares and outputs the PWM signal to the control electrode of the switching transistor T404 through the buffer 412.

[0134] According to one embodiment of the present application, when the first display signal DATA PWM1[1] Greater than the reference signal V STEP [1], the current flowing through transistor T46 increases, the current flowing through transistor T45 decreases, and transistor T42 turns on, receiving the high level VGH. At this time, the potential at point B is greater than the common mode level V of buffer 412. CM Buffer 412 outputs a high level VGH as a PWM signal to the switching transistor T404 to turn on the transistor T404, and the light emitting element 403 receives a constant current I from the current bias unit. LED [1,j], starts to emit light.

[0135] According to an embodiment of the present application, while the display pixel circuits in the first row enter the light emitting stage, the display pixel circuits in the second row can receive the scan signal SCAN of the row. PWM1 [2], then the writing operation is completed and the light-emitting stage begins. The same process is repeated for other rows until row I.

[0136] According to one embodiment, when the first display signal DATA PWM1 [1] is less than the reference signal V STEP [1], the current flowing through transistor T46 decreases, the current flowing through transistor T45 increases, and the potential at point B is less than the common-mode level V of buffer 412. CM , the buffer 412 outputs the ground level to the switch transistor T404, the switch transistor T404 is turned off, the light-emitting element 403 no longer emits light, and the light-emitting phase of this subframe ends.

[0137] According to one embodiment, enable signals EM[1] to EM[I] remain high for a fixed period of time, corresponding to the longest possible luminous duration within a subframe. When the first display signal remains greater than the reference signal at the end of the longest possible luminous duration within the subframe, the enable signal transitions to a low level, turning off transistor T44 and causing light-emitting element 403 to cease luminescence, thus ending the luminous phase of the subframe.

[0138] According to one embodiment of the present application, the transistor T43b in the display pixel circuit of the 1st row and the jth column starts to receive the second scan signal SCAN of the 1st row after the light emitting phase of the first subframe ends. PWM2 [1] The second subframe is turned on and the second display signal DATA is transmitted to display data in the middle of the second subframe. PWM2 [2] is transmitted to the second electrode of transistor T43b. At this time, the pixel circuit 400 starts the writing phase of the y2 subframe. After the pixel circuit of the first row completes the writing operation, the scanning signal SCAN of the pixel circuit of the second row PWM2 [2] Turn on and start the writing phase until row I.

[0139] According to an embodiment of the present application, in a pixel array having I rows and J columns of display pixel circuits, the writing phase of the y2-th subframe of the pixel circuit 400 in the i-th row and j-th column can start before the last row of pixel circuits in the display pixel array where it is located ends the writing phase of the y1-th subframe, and end before the first row of pixel circuits starts the writing phase of the (y2+1)-th subframe, where i is an integer greater than 1 and less than I, and j is an integer greater than 1 and less than J.

[0140] Figure 5A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 5A As shown, the pixel circuit 500 located in the i-th row and the j-th column may include a PWM signal generating module 501 , a constant current module 502 , a light emitting element 503 and a switch module such as a switch transistor T504 .

[0141] According to one embodiment of the present application, the PWM signal generating module 501 may include a transistor T51 as a comparison transistor. The control electrode of the transistor T51 is coupled to the second electrodes of the transistors T53a and T53b at point A, and is coupled to the second end of the capacitor C51. The first end of the capacitor C51 receives the reference signal V STEP [i] According to one embodiment of the present application, the reference signal may be a step signal with a potential range of 0-6V.

[0142] According to one embodiment, the control electrode of the transistor T53a can be configured to receive the first scan signal SCAN PWM1 [i], the first electrode can be configured to receive the first display signal DATA PWM1 [y1]. y1 is any integer from 1 to Y, and refers to the subframe number corresponding to the intermediate display data included in the first display signal DATAPWM1[y1]. DATAPWM1[y1] represents the inverse value of the display signal corresponding to the data of the y1th subframe within the Y-bit K-ary intermediate display data received by transistor T53a.

[0143] According to one embodiment, the control electrode of the transistor T53b may be configured to receive the second scan signal SCAN PWM2 [i], the first electrode can be configured to receive the second display signal DATA PWM2[y2]. y2 is any integer between 1 and Y that is different from y1 and refers to the subframe number corresponding to the intermediate display data included in the second display signal DATAPWM2[y2]. DATAPWM2[y2] represents the inverse value of the display signal corresponding to the data of the y2-th subframe in the Y-bit K-ary intermediate display data, received by transistor T53b. The control electrode of transistor T52 receives the charging signal CHG[i]. The first electrode receives the high voltage level VGH. The second electrode is coupled to the first electrode of transistor T51 at point B and is coupled to the control electrode of transistor T504 as the output of the PWM signal generation module 501. Transistors T51, T52, T53a, and T53b can be N-type transistors.

[0144] Figure 5A In the illustrated pixel circuit 500, a comparison unit, such as comparison transistor T51, cannot directly compare the reference signal and the intermediate display signal or determine the difference between the two. Instead, it processes the intermediate display signal when generating the first and second display signals, performing a comparison based on the sum of the reference signal and the first or second display signal. Therefore, the amplitudes of the first and second display signals can be signals generated by adjusting the intermediate display signal according to actual needs, such as by taking the inverse of the intermediate display signal. For example, in this embodiment, the intermediate display signal can be a signal with a potential range of -0.5 to 6.5 V, and the first and second display signals can be signals with a potential range of -6.5 to 0.5 V.

[0145] According to one embodiment of the present application, Figure 5A In the pixel circuit 500 shown in FIG. 1 , in order to satisfy the requirement that the reference signal is less than the first or second display signal so that the light emitting element emits light, it is necessary to ensure that DATA PWM [y]+V STEP [i]>V th(t51) That is, in this embodiment, the sum of the minimum possible values ​​of the first and second display signals and the maximum value of the reference signal should be less than the threshold voltage V th(t51) Similarly, in order to satisfy the requirement that the reference signal is greater than the first or second display signal to turn off the light emitting element, the sum of the maximum possible values ​​of the first and second display signals and the minimum value of the reference signal should be greater than the threshold voltage V th Specifically, the conditions shown in formula (6) need to be met:

[0146]

[0147] Among them, DATA PWM [y] includes the first display signal DATA PWM1 [y1] and the second display signal DATA PWM2 [y2].

[0148] According to one embodiment of the present application, the constant current module 502 may include transistors T54 and T57. The control electrode of the transistor T54 receives the enable signal EM[i], the first electrode of the transistor T54 is coupled to the second electrode of the transistor T59, the control electrode of the transistor T57 receives the enable signal EM[i], and the first electrode of the transistor T57 receives the high level VGH, so as to provide the constant light-emitting current I required by the light-emitting element 503. LED [i,j].

[0149] The constant current module 502 may further include transistors T58, T59, and a capacitor C52. The first electrode of transistor T59 is coupled to the second electrode of transistor T57, the second electrode is coupled to the first electrode of transistor T54, and the control electrode is coupled to the second electrode of transistor T58 and the second end of capacitor C52 to point D. The first end of capacitor C52 is grounded. The control electrode of transistor T58 receives a constant current scan signal SCAN. PAM [i], the first electrode receives the constant current display signal DATA PAM .

[0150] According to one embodiment of the present application, the pixel circuit 500 may further include a switching transistor T504, whose control electrode is coupled to the first electrode of the transistor T51 at point B, receives the PWM signal output by the PWM signal generating module 501, the first electrode is coupled to the second electrode of the transistor T54, and the second electrode is coupled to the anode of the light-emitting element 503.

[0151] Figure 5B yes Figure 5A The pixel circuit 500 is shown as a schematic diagram of two sub-frame operation timings. According to an embodiment of the present application, the pixel circuit 500 includes a charging phase, a writing phase, and a light emitting phase in one sub-frame.

[0152] Taking the display pixel circuit of the first row of the pixel array as an example, in the charging stage, the enable signal EM[1] is at a low level and the charging signal CHG[1] is at a high level. At this time, the transistor T52 is turned on, and the potential V IN At this time, VGH-V th(t52) , to realize the charging of point B in the PWM signal generating module 501. th(52) is the threshold voltage of transistor T52. This operation can reduce the correlation between the previous and next display frames.

[0153] In the write phase, the enable signal EM[1] continues to be low, the charge signal CHG[1] jumps to a low level, and the scan signal SCAN PWM1 [1] jumps to high level. At this time, transistor T53a is turned on and receives the second display signal DATA PWM1 [y1].

[0154] According to one embodiment, Figure 5B As shown, the present application adopts a mechanism of writing and emitting light row by row, so the pixel circuit of row 1 receives the scan signal SCAN after receiving the charging signal CHG[1] in the first subframe. PWM1 [1], and complete the writing operation of the display signal. The second row display pixel circuit receives the scan signal SCAN after the first row display pixel circuit receives the scan signal SCAN PWM1 [1] Immediately after receiving the scan signal SCAN PWM1 [2], complete the writing operation of the display signal of the second row, and so on until the I row.

[0155] After the display pixel circuits in the first row complete the writing operation of the display signal, that is, after the pixel circuits in this row receive the first display signal of the first subframe, the pixel circuits are turned on during the light emitting phase of the first subframe.

[0156] According to an embodiment of the present application, the constant current module 502 may further include transistors T58, T59 and C52 for adjusting the light emitting current of the light emitting element 503. At this time, the transistor T58 receives the constant current scanning signal DATA PAM And conduction, the potential of point D becomes DATA PAM .

[0157] In the light-emitting stage, the enable signal EM[1] of the pixel circuit in row 1 jumps to a high level, and the other signals are all low levels. At this time, transistors T57 and T54 are turned on, point B is at a high level, the switch transistor T504 is turned on, and the light-emitting element 503 starts to emit light. According to one embodiment of the present application, the light-emitting current I required by the light-emitting element 503 at this time is LED [1,j] is provided by the conducting transistor T59, and the conduction condition of the transistor T59 is affected by the constant current display signal DATA PAM According to other embodiments of the present application, the light-emitting currents of different columns may be different, and the light-emitting currents of the same column may be the same to meet display requirements.

[0158] According to an embodiment of the present application, when the display pixel circuits in the first row enter the light-emitting stage, the display pixel circuits in other rows, for example, the i-th row, can receive the scan signal SCAN of the row. PWM1 [i], then the writing operation is completed and the light-emitting stage begins. The same process is repeated for other rows until row I.

[0159] When EM[1] jumps to high level, point A receives the reference signal V STEP [1], reference signal V STEP [1] is a step waveform that increases with time. According to one embodiment, if before EM[1] jumps to a low level, when the reference signal V STEP [1] Jump to a certain step, so that VIN -V th(t51) >0, transistor T51 is turned on, and point B discharges through transistor T51, where V th(t51) is the threshold voltage of the transistor T51. The switching transistor 504 is turned off, and the light emitting element 503 stops emitting light.

[0160] According to one embodiment of the present application, if before EM[1] jumps to a low level, V IN -V th(t51) The value is always less than zero, transistor T51 is turned off, and point B maintains a high level and transmits it to the control electrode of switching transistor 504. At this time, because the enable signal EM[1] jumps to a low level, transistor T54 is turned off, and light-emitting element 503 stops emitting light. In other words, the pixel circuit 500 continues to emit light for the longest possible emission time in this subframe until the writing phase of the next subframe begins.

[0161] According to one embodiment of the present application, the transistor T53b in the display pixel circuit of the first row starts to receive the second scan signal SCAN of the first row after the light emitting phase of the first subframe ends. PWM2 [1] Turn on the second subframe and conduct, and send the second display signal DATA with the middle display data of the second subframe PWM2 [2] is transmitted to point A. At this time, the pixel circuit 500 starts the writing phase of the second subframe. After the pixel circuit in the first row completes the writing operation, the scanning signal SCAN of the pixel circuit in the second row is PWM2 [2] Turn on and start the writing phase until row I.

[0162] According to an embodiment of the present application, in a pixel array having I rows and J columns of display pixel circuits, the writing phase of the y2-th subframe of the pixel circuit 500 in the i-th row and j-th column can start before the last row of pixel circuits in the display pixel array where it is located ends the writing phase of the y1-th subframe, and end before the first row of pixel circuits starts the writing phase of the (y2+1)-th subframe, where i is an integer greater than 1 and less than I, and j is an integer greater than 1 and less than J.

[0163] According to embodiments of the present application, when a pixel circuit uses a single transistor as a comparator to compare signals, the threshold voltage of the transistor may drift, potentially affecting the grayscale control accuracy of the PWM signal generation module. Therefore, a more preferred embodiment includes a threshold voltage compensation circuit and a corresponding signal driving method.

[0164] Figure 6A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 6AAs shown, the pixel circuit 600 located in the i-th row and the j-th column may include a PWM signal generating module 601 , a constant current module 602 , a light emitting element 603 and a switch module such as a switch transistor T604 .

[0165] According to an embodiment of the present application, the PWM signal generation module 601 may include transistors T61, T62, T63a, T63b, T65, and T66. The control electrode of transistor T61 is coupled to the second electrode of transistor T66 and the second end of capacitor C61. The first electrode of transistor T61 is coupled to the second electrode of transistor T62 at point B, and the second electrode of transistor T65 is coupled to the first electrode of transistor T65, serving as a comparison transistor. The control electrode of transistor T66 receives a reset signal RST[i], and the first electrode of transistor T61 is coupled to point B. The control electrode of transistor T62 receives a charge signal CHG[i], and the first electrode of transistor T62 receives a high level.

[0166] According to one embodiment, the control electrode of the transistor T63a receives the first scan signal SCAN of the row where the pixel is located. PWM1 [i], the first electrode receives the first display signal DATA PWM1 [y1], the second electrode of which is coupled to the second electrode of transistor T61 and the first electrode of transistor T65. y1 is any integer between 1 and Y, and refers to the subframe number corresponding to the intermediate display data included in the first display signal DATAPWM1[y1]. DATAPWM1[y1] represents the inverse value of the display signal corresponding to the data of the y1th subframe within the Y-bit K-ary intermediate display data received by transistor T63a.

[0167] According to one embodiment, the control electrode of the transistor T63b receives the second scan signal SCAN of the row where the pixel is located. PWM2 [i], the first electrode receives the second display signal DATA PWM2 The second electrode of transistor T61 is coupled to the second electrode of transistor T61 and the first electrode of transistor T65. Wherein, y2 is any integer between 1 and Y and refers to the subframe number corresponding to the intermediate display data included in the second display signal DATAPWM2[y2]. DATAPWM2[y2] represents the inverse value of the display signal corresponding to the data of the y2-th subframe in the Y-bit K-ary intermediate display data received by transistor T33b.

[0168] like Figure 6AIn the illustrated pixel circuit 600, the comparison unit does not directly determine the magnitude relationship between the reference signal and the intermediate display signal, or the difference between them. Instead, it processes the intermediate display signal when generating the first and second display signals based on the intermediate display signal, performing a comparison operation based on the sum of the reference signal and the first or second display signal. Therefore, the amplitude of the first or second display signal can be a signal generated by adjusting the intermediate display signal according to actual needs, for example, including a voltage value that is the inverse of the intermediate display signal. For example, in this embodiment, the intermediate display signal can be a signal with a potential range of -0.5 to 6.5 V, and the first and second display signals can be signals with a potential range of -6.5 to 0.5 V.

[0169] According to one embodiment, the control electrode of the transistor T65 receives the enable signal EM[i], and the second electrode is grounded. The first terminal of the capacitor C61 receives the reference signal V STEP [i] According to one embodiment of the present application, the reference signal may be a step signal with a potential range of 0-6 V. According to an embodiment of the present application, the transistors T61, T62, T63a, T63b, T65, and T66 may be N-type transistors.

[0170] According to one embodiment of the present application, Figure 6A In the pixel circuit 600 shown in FIG. 1 , in order to satisfy the requirement that the reference signal is less than the first or second display signal so that the light emitting element emits light, it is necessary to ensure that DATA PWM [y]+V STEP [i]>0, that is, in this embodiment, the sum of the minimum possible values ​​of the first and second display signals and the maximum value of the reference signal should be less than 0. Similarly, in order to satisfy the requirement that the reference signal is greater than the first or second display signal to turn off the light-emitting element, the sum of the maximum possible values ​​of the first and second display signals and the minimum value of the reference signal should be greater than 0. Specifically, the condition shown in formula (7) needs to be satisfied:

[0171]

[0172] Among them, DATA PWM [y] includes the first display signal DATA PWM1 [y1] and the second display signal DATA PWM2 [y2].

[0173] According to an embodiment of the present application, the constant current module 602 may include a transistor T64 and a current bias unit. The control electrode of the transistor T64 receives an enable signal EM[i], and the second electrode is coupled to the first electrode of the switch transistor T604 to control the light emission of the light emitting element 603. The first electrode of the transistor T64 is coupled to the current bias unit to receive a constant current signal to provide a light emitting current I to the light emitting element 603. LED[i,j].

[0174] According to one embodiment of the present application, the pixel circuit 600 may further include a switching transistor T604, whose control electrode is coupled to the first electrode of the comparison transistor T61 at point B and receives the PWM signal output by the PWM signal generation module 601. The first electrode of the switching transistor T604 is coupled to the second electrode of the transistor T64, and the second electrode is coupled to the anode of the light-emitting element 603. According to an embodiment of the present application, the transistors T64 and T604 may be N-type transistors.

[0175] According to one embodiment of the present application, the transistors T61 , T62 , T63 a , T63 b , T64 , T65 , T66 , and T604 may be N-type thin film transistors (TFTs).

[0176] Figure 6B yes Figure 6A The pixel circuit 600 is shown as a schematic diagram of two sub-frame operation timings. According to an embodiment of the present application, the pixel circuit 600 includes a charging phase, a writing and compensation phase, a recharging phase, and a light emitting phase in one sub-frame.

[0177] Taking the display pixel circuit in the pixel circuit of the first row of the pixel array as an example, in the reset phase, the enable signal EM[1] is at a low level, the charge signal CHG[1] is at a high level, and the reset signal RST[1] is at a high level. At this time, the transistor T62 is turned on, the transistor T66 is turned on, and the potential V IN At this time, VGH-V th(m) , to achieve the reset of point A in the PWM signal generating module 601. th(m) is the threshold voltage of the transistor, and m is the number of the transistor. According to the embodiment of the present application, m here can be one of 62 or 66, and the potential of point A is the difference between the high level VGH and the larger threshold voltage of transistor T62 or T66. Taking transistor T62 as an example, when the threshold voltage of transistor T62 is greater than that of transistor T66, the potential of point A is VGH-V th(t62) This operation can reduce the correlation between the previous and next display frames, and prepare for the subsequent writing of the threshold voltage compensation voltage of the transistor T61.

[0178] According to one embodiment, Figure 6B As shown, the present application adopts a row-by-row writing and row-by-row lighting mechanism. Therefore, the pixel circuits in rows 1 to 1 receive reset signals RST[1] to RST[I] and charging signals CHG[1] to CHG[I] row by row, and each row of pixel circuits starts the subframe when receiving the reset signal. In other words, the subframe start time of each row of pixel circuits is different, starting from the time when the pixel circuits in the previous row receive the reset signal RST[i], and so on until row 1.

[0179] In the writing and compensation phase, the enable signal EM[1] continues to be low, the charging signal CHG[1] jumps to a low level, and the reset signal RST[1] remains high. PWM1 [1] Jumps to high level.

[0180] In SCAN PWM1 When [1] is high, in the pixel circuit 600, transistors T66 and T63a are turned on. Since the potential V IN VGH-V th(t62) , at this time, transistor T61 is also turned on. Transistor T63a receives the first display signal DATA PWM1 [y1], the potential of point A is DATA PWM1 [y1]+V th(t61) Among them, V th(t61) is the threshold voltage of transistor T61.

[0181] In the pre-charge phase, the charging signal CHG[1] is high, the enable signal EM[1] and the reset signal RST[1] are low. At this time, the transistor T62 is turned on again, and the potential of point B is charged to VGH-V th(t62) Among them, V th(t62) is the threshold voltage of transistor T62.

[0182] During the light-emitting phase, the enable signal EM[1] jumps to a high level, and all other signals are low. At this point, transistor T65 is turned on, and transistor T64 is turned on. Since point B is charged to a high level during the pre-charging phase, the switching transistor T604 is also turned on, and the light-emitting element 603 begins to emit light.

[0183] According to an embodiment of the present application, when the display pixel circuits in the first row enter the light-emitting stage, the display pixel circuits in other rows, for example, the i-th row, can receive the scan signal SCAN of the row. PWM1 [i], then the writing operation is completed and the light-emitting stage begins. The same process is repeated for other rows until row I.

[0184] When EM[1] jumps to high level, point A receives the reference signal V STEP [1], reference signal V STEP [1] is a step waveform that increases with time. Specifically, the potential at point A becomes V IN =DATA PWM1 [y1]+V th(t61) +V STEP [1], where V th(t61) is the threshold voltage of transistor T61.

[0185] According to one embodiment, if before EM[1] jumps to a low level, when the reference signal V STEP [1] Jump to a certain step, so that V IN -V th(t61) >0, which is DATA PWM1 [y1]+V STEP When [1]>0, transistor T61 is turned on, and point B discharges through transistors T61 and T65. When the potential of point B is less than the threshold voltage of switching transistor T604, switching transistor T604 is turned off, and light-emitting element 603 stops emitting light.

[0186] According to one embodiment of the present application, if before EM[1] jumps to a low level, V IN -V th(t61) Always less than zero, that is, DATA PWM1 [y1]+V STEP [1] < 0, transistor T61 is turned off, and point B maintains a high level and transmits it to the control electrode of switching transistor T604. At this time, because the enable signal EM[1] jumps to a low level, transistor T64 is turned off, and light-emitting element 603 stops emitting light. In other words, at this time, pixel circuit 600 continues to emit light for the longest possible emission time in this subframe until the next subframe begins.

[0187] According to one embodiment of the present application, the transistor T63b in the display pixel circuit of the first row starts to receive the second scan signal SCAN of the first row after the light emitting phase of the first subframe ends. PWM2 [1] Turn on the second subframe and conduct, and send the second display signal DATA with the middle display data of the second subframe PWM2 [2] is transmitted to point A. At this time, the pixel circuit 600 starts the writing phase of the second subframe. After the pixel circuit in the first row completes the writing operation, the scanning signal SCAN of the pixel circuit in the second row is PWM2 [2] Turn on and start the writing phase until row I.

[0188] According to an embodiment of the present application, in a pixel array having I rows and J columns of display pixel circuits, the writing phase of the y2-th subframe of the pixel circuit 600 in the i-th row and j-th column can start before the last row of pixel circuits in the display pixel array where it is located ends the writing phase of the y1-th subframe, and end before the first row of pixel circuits starts the writing phase of the (y2+1)-th subframe, where i is an integer greater than 1 and less than I, and j is an integer greater than 1 and less than J.

[0189] Figure 7A FIG. 1 is a structural diagram of an active display pixel circuit according to another embodiment of the present application. Figure 7AAs shown, the pixel circuit 700 may include a PWM signal generating module 701 , a constant current module 702 , a light emitting element 703 , and a switch module such as a switch transistor T704 .

[0190] like Figure 7A As shown, the PWM signal generating module 701 may include transistors T71, T72, T73a, T73b, T75, and T76. Among them, the transistor T71 is used as a comparison transistor, the control electrode and the second end of the capacitor C71 and the second electrode of the transistor T76 are coupled to point A, the first electrode and the second electrode of the transistor T72 are coupled at point B, and the second electrode is coupled to the first electrode of the transistor T75. The first end of the capacitor C71 receives the reference signal V STEP [i]. The control electrode of transistor T76 receives reset signal RST[i]. The first electrode of transistor T76 is coupled to point B along with the first electrode of transistor T71 and the second electrode of transistor T72. The control electrode of transistor T72 receives charging signal CHG, and the first electrode of transistor T72 receives high voltage level VGH. According to one embodiment of the present application, the reference signal can be a step signal with a potential range of 0-6V.

[0191] According to one embodiment, the control electrode of the transistor T73a receives the scan signal SCAN. PWM1 [i], the first electrode receives the second display signal DATA PWM1 [y1], the second electrode of which is coupled to the second electrode of transistor T71. y1 is any integer between 1 and Y, and refers to the subframe number corresponding to the intermediate display data included in the first display signal DATAPWM1[y1]. DATAPWM1[y1] represents the inverse value of the display signal corresponding to the data of the y1th subframe within the Y-bit K-ary intermediate display data received by transistor T53a.

[0192] According to one embodiment, the control electrode of the transistor T73b receives the scan signal SCAN PWM2 [i], the second electrode receives the second display signal DATA PWM2 [y2] has a first electrode coupled to the second electrode of transistor T71. y2 is any integer between 1 and Y that is different from y1 and represents the subframe number corresponding to the intermediate display data included in the second display signal DATAPWM2[y2]. DATAPWM2[y2] represents the inverse value of the display signal corresponding to the data of the y2-th subframe in the Y-bit K-ary intermediate display data received by transistor T53b.

[0193] According to one embodiment, a control electrode of transistor T75 receives an enable signal EM[i], and a second electrode thereof is grounded. According to an embodiment of the present application, transistors T71, T72, T73a, T73b, T75, and T76 may be N-type transistors.

[0194] like Figure 7A In the illustrated pixel circuit 700, the comparison unit does not directly determine the magnitude relationship between the reference signal and the intermediate display signal, nor does it calculate the difference between the two. Instead, the comparison operation is performed based on the sum of the reference signal and the first or second display signal. Therefore, the amplitudes of the first and second display signals can be signals generated by adjusting the intermediate display signal according to actual needs. For example, they can include a voltage value that is the inverse of the intermediate display signal. For example, in this embodiment, the intermediate display signal can be a signal with a potential range of -0.5 to 6.5 V, and the first and second display signals can be signals with a potential range of -6.5 to 0.5 V.

[0195] According to one embodiment of the present application, Figure 7A In the pixel circuit 700 shown in FIG. 1 , in order to satisfy the requirement that the reference signal is less than the first or second display signal so that the light emitting element emits light, it is necessary to ensure that DATA PWM [y]+V STEP [i]>0, that is, in this embodiment, the sum of the minimum possible values ​​of the first and second display signals and the maximum value of the reference signal should be less than 0. Similarly, in order to satisfy the requirement that the reference signal is greater than the first or second display signal to turn off the light-emitting element, the sum of the maximum possible values ​​of the first and second display signals and the minimum value of the reference signal should be greater than 0. Specifically, the condition shown in formula (8) needs to be satisfied:

[0196]

[0197] Among them, DATA PWM [y] includes the first display signal DATA PWM1 [y1] and the second display signal DATA PWM2 [y2].

[0198] According to one embodiment of the present application, the constant current module 702 may include transistors T74, T77, and T79. The control electrode of transistor T74 receives an enable signal EM[i], the second electrode is coupled to the first electrode of the switch transistor 704, and the first electrode is coupled to the second electrode of transistor T79, thereby controlling the light emission of the light-emitting element 703 together with the switch transistor 704. The first electrode of transistor T79 and the second electrode of transistor T77 are coupled to point E. The control electrode of transistor T77 receives an enable signal EM[i], and the first electrode receives a high level VGH to provide a constant light-emitting current I required by the light-emitting element 703. LED [i, j]. According to one embodiment of the present application, the transistors T74, T77, and T79 may be N-type transistors.

[0199] Optionally, the constant current module 702 may further include transistors T710 and T711, and a capacitor C72. The second terminal of capacitor C72 is coupled to the control electrode of transistor T79 at point D, and the first terminal is grounded. The control electrode of transistor T711 receives a reset signal RST[i], the first terminal is coupled to the second terminals of transistors T710 and T77 at point E, and the second terminal is coupled to the second terminal of capacitor C72 at point D. The control electrode of transistor T710 receives a charge signal CHG, and the first terminal receives a high voltage level VGH.

[0200] Optionally, the constant current module 702 may further include a transistor T78. The control electrode of the transistor T78 receives a constant current scan signal SCAN. PAM [i], the first electrode receives the constant current display signal DATA PAM The second electrode is coupled to the second electrode of transistor T79. The constant current display signal received by transistor T78 can adjust the control electrode voltage of transistor T79, thereby changing the light-emitting current I transmitted by the light-emitting elements 703 in different rows. LED The size of [i, j] satisfies the needs of the device. The light-emitting current I of the light-emitting element 703 LED The size of [i, j] may be different in different columns and the same in the same column. According to an embodiment of the present application, T78, T710 and T711 may be pure N-type transistors.

[0201] According to one embodiment of the present application, the pixel circuit 700 may further include a switching transistor T704, whose control electrode is coupled to the first electrode of the transistor T71 at point B and receives the PWM signal output by the PWM signal generating module 701. The first electrode of the switching transistor T704 is coupled to the second electrode of the transistor T74, and the second electrode is coupled to the anode of the light-emitting element 703.

[0202] According to an embodiment of the present application, some or all transistors in the pixel circuit 700 may include pure N-type thin film transistors (TFTs).

[0203] According to an embodiment of the present application, the first and second display signals are signals obtained by processing the intermediate display signal. The intermediate display signal includes a voltage or other electrical signal corresponding to each value of the intermediate display data. Each intermediate display data corresponds to the actual non-luminous time within the longest possible luminous time of the subframe. Taking the octal data 1420 as an example, the intermediate display data written in each subframe is 1420 in sequence. The octal display data corresponding to the actual luminous time of the pixel circuit 700 in these subframes is 6357 (from the highest bit, that is, 8 3 to 8 0 ).

[0204] According to one embodiment of the present application, when displaying grayscale numbers, that is, when the initial display data received by the pixel circuit 700 is a 10-bit binary number, the 10-bit binary data is first converted into a 4-bit octal number, so that the corresponding frame will be divided into 4 sub-frames. Since 3-bit octal data corresponds to 9-bit binary data, the 10-bit binary data corresponds to a 4-bit octal number after conversion, and the most significant bit corresponds to the 1-bit most significant bit in the binary number (rather than each bit in other octal numbers corresponding to 3 bits in the binary number). That is, the value of the most significant bit in the 4-bit octal number can only be 0 or 1.

[0205] According to one embodiment, the unit luminous time of each subframe can be increased step by step from low to high according to the corresponding intermediate display data. For octal display data, the relative relationship between the unit luminous time of each subframe is 8 3 , 8 2 , 8 1 , 8 0 (from most significant bit to least significant bit).

[0206] According to one embodiment, the relative relationship between the possible longest luminous time of each subframe in a frame can be 8 3 *(2-1), 8 2 *(8-1), 8 1 *(8-1), 8 0 *(8-1)(from most significant bit to least significant bit).

[0207] According to an embodiment of the present application, each of subframes SF0-SF2 corresponding to the first three bits of the octal display data (from lowest to highest) can represent eight grayscales, and the first display data of each subframe can be any one of 0-7. The subframe corresponding to the most significant bit of the octal display data can only represent two grayscales, and the first display data of the subframe can only be 0 or 1.

[0208] Figure 7B The figure shows a schematic diagram of the working timing of a pixel circuit in one frame when the intermediate display data is an octal number. It is understood that for the sake of convenience, the length of the luminous time of each subframe in the figure is only for illustration.

[0209] According to an embodiment of the present application, a pixel circuit receives first and second display signals, respectively, via two display signal lines, controlled by first and second scan signals. Therefore, the first and second subframe data of the pixel circuit must be fully written before writing the third subframe data of the corresponding display pixel array begins. This requires that the subframe corresponding to the second display signal written by the first row of pixel circuits must emit light for a longer period than the end time of the writing operation for the second display data of the last row of pixels.

[0210] According to the embodiments of the present application, Figure 7BAs shown, the longest possible light emitting time of the first subframe of the pixel circuit can be the product of the first intermediate display data and the shortest unit writing time T SF0 =(8 0 T LSB )·x0, the longest possible luminous time of the second subframe can be the product of the second intermediate display data and the theoretical third subframe unit writing time, that is, the longer subframe unit writing time among the four subframes. SF2 =(8 2 T LSB ) x1. Specifically, the total luminous time of one frame is T EM(8) It can be expressed by formula (9).

[0211] T EM(8) =(8 3 T LSB )·x3+(8 2 T LSB )·x1+(8 1 T LSB )·x2+(8 0 T LSB )·x0 (9)

[0212] Among them, T LSB The length of the luminous time in the smallest subframe when the display frame is divided into multiple subframes according to binary data. x corresponds to the data corresponding to the luminous time in different subframes, where x3 is 6, x2 is 3, x1 is 5, and x0 is 7.

[0213] by Figure 7B Taking the embodiment in as an example, that is, the pixel array has 1080 rows, the display frame rate is 120Hz, the display data bit depth is 10bit, and the display pixel circuit write time is 0.2μs, after converting the 10-bit binary display data into 4-bit octal display data, the maximum possible light-emitting time corresponding to the four sub-frames is: Because the display data corresponding to the fourth subframe is converted from 1-bit binary data, it does not conform to the ratio of the longest possible luminous time of the other subframes, which is obtained by calculating the remaining time. Among them, the longest possible luminous time of the third and fourth subframes exceeds the length of (1-2) writing times. In other words, to ensure that only two pixels in the same column but different rows are writing two bits of display data from different subframes at the same time, the luminous time corresponding to the first display signal and the second display signal of each pixel circuit in the pixel array can be the shorter and longer subframes of the four subframes, such as SF0 and SF2, respectively, rather than the consecutive subframes SF0 and SF1.

[0214] According to one embodiment of the present application, Figure 7B As shown, the operation of the pixel circuit 700 in the i-th row and j-th column in the y-th subframe specifically includes the following stages:

[0215] Phase (1): Reset phase

[0216] In the reset phase, the enable signal EM[i] is low, the charge signal CHG[i] is high, and the reset signal RST[i] is high. At this time, transistors T72 and T710 are turned on, transistors T76 and T711 are turned on, and the potential V at point A is IN At this time, VGH-V th(m1) , the potential at point D is VGH-V th(m2) , to achieve the reset of point A in the PWM signal generating module 701 and point D in the constant current module 702. th(m1) and V th(m2) are the threshold voltages of the transistors, and m1 and m2 are the numbers of the transistors. According to the embodiment of the present application, taking m1 as 72 as an example, m1 can be either 72 or 76, and the potential of A can be the difference between the high level VGH and the larger threshold voltage of the transistor T72 or T76. When the threshold voltage of the transistor T72 is greater than that of the transistor T76, the potential of point A is VGH-V th(t72) According to one embodiment of the present application, V th(m1) and V th(m2) It can be the threshold voltage V of transistors T72 and T710 th(t72) and V th(t710) This operation can reduce the correlation between the previous and next display frames, and prepare for the subsequent writing of the threshold voltage compensation voltage into the transistors T71 and T79.

[0217] Phase (2): Writing and compensation phase

[0218] In the writing and compensation phase, the enable signal EM[i] continues to be low, the charging signal CHG[i] jumps to a low level, and the reset signal RST[i] remains high. PWM1 [i] jumps to high level.

[0219] In SCAN PWM1 When [i] is high, in the pixel circuit 700, transistors T76 and T73a are turned on. Since the potential V IN VGH-V th(72) , at this time, the transistor T71 is also turned on. The transistor T73a receives the first display signal DATA PWM1 [y1], the potential of point A is DATA PWM1 [y1]+V th(t71) .

[0220] According to an embodiment of the present application, the constant current module 702 may further include a transistor T78 for adjusting the light emitting current of the light emitting element 703. At this time, the transistors T711 and T78 are turned on, the transistor T79 is turned on under the high level control of the D point, and the transistor T78 receives the constant current display signal DATA PAM , the potential of point D becomes DATA PAM +V th(t79) .

[0221] According to an embodiment of the present application, the potential at point A is determined by the first scan signal SCAN. PWM1 [i] Control, complete the data writing of the first display signal and the preparation for threshold voltage compensation, and point D also performs constant current data writing and threshold voltage compensation preparation at this stage, so that the threshold voltage compensation of the transistor T79 that drives the light-emitting element 703 to emit light is more accurate.

[0222] Stage (3): Pre-charge stage

[0223] In the pre-charge phase, the charging signal CHG[i] is high, the enable signal EM[i] and the reset signal RST[i] are low. At this time, the transistors T72 and T710 are turned on again, and the potential of point B is charged to VGH-V th(t72) , the potential of point E is charged to VGH-V th(t710) Among them, V th(t72) and V th(t710) are the threshold voltages of transistors T72 and T710 respectively.

[0224] Stage (4): Lighting stage

[0225] In the light-emitting stage, the enable signal EM[i] jumps to a high level, and the other signals are all low levels. At this time, transistors T77 and T75 are turned on, and transistor T74 is turned on. Since point B is charged to a high level in the pre-charging stage, the switching transistor T704 is also turned on, and the light-emitting element 703 begins to emit light. According to one embodiment of the present application, the light-emitting current I required by the light-emitting element 703 at this time is LED [i, j] is provided by the conducting transistor T79, and the conduction condition of the transistor T79 is affected by the constant current display signal DATA received by the transistor T78. PAM impact.

[0226] When EM[i] jumps to high level, point A receives the reference signal V STEP [i], reference signal V STEP [i] is the step waveform V that increases with time STEP [i](t)=nΔV STEP , n is an integer from 0 to (K-1). Where, VSTEP [i] There are n=(K-1) possible step potentials, for example 8-1=7. At this time, the potential at point A becomes V IN =DATA PWM1 [y1]+V th(71) +V STEP [i].

[0227] According to one embodiment, if before EM[i] jumps to a low level, when the reference signal V STEP [i] Jump to a certain step, so that V IN -V th(71) >0, which is DATA PWM [y]+V STEP When [y]>0, transistor T71 is turned on, and point B is discharged through transistors T71 and T77. Switching transistor T704 is turned off, and light emitting element 703 stops emitting light.

[0228] According to one embodiment of the present application, if before EM[i] jumps to a low level, V IN -V th(71) Always less than zero, that is, DATA PWM1 [y1]+V STEP When [i] < 0, transistor T71 remains off, and point B maintains a high level, transmitting the signal to the control electrode of switching transistor T704. At this point, because enable signal EM[i] transitions to a low level, transistor T74 is turned off, and light-emitting element 703 ceases to emit light. In other words, at this point, the first display data does not limit the light-emitting time of pixel circuit 700 in this subframe. Pixel circuit 700 continues to emit light for the longest possible light-emitting time in this subframe until the next subframe begins.

[0229] According to an embodiment of the present application, the threshold voltages of the transistors T71 and T79 may gradually increase as the pixel circuit 700 operates. The threshold voltages of the transistors T72, T76, T710, and T711 may be equal and constant.

[0230] According to one embodiment of the present application, the transistor T73b starts to receive the second scan signal SCAN of the i-th row after the light emitting phase of the y1-th subframe ends. PWM2 [i] and turned on, the second display signal DATA of the y2 subframe PWM2 [y2] is transmitted to point A. At this time, the pixel circuit 700 starts the writing phase of the y2-th subframe.

[0231] like Figure 7BAs shown, the pixel circuit 700 in the i-th row and j-th column emits light immediately after the recharging phase of the first subframe is completed, and immediately starts the reset phase of the second subframe after the longest possible lighting time ends, and starts writing the display data of the second subframe. At this time, data of the pixel circuits in other rows of the j-th column can also be written at the same time, for example Figure 7B As shown, during the SF2 time period of the pixel circuits in the first row, the pixel circuits in the first row may be emitting light during the light-emitting time of SF0.

[0232] According to an embodiment of the present application, in a pixel array having I rows and J columns of display pixel circuits, the writing phase of the y2-th subframe of the pixel circuit 700 in the i-th row and j-th column can start before the last row of pixel circuits in the display pixel array where it is located ends the writing phase of the y1-th subframe, and end before the first row of pixel circuits starts the writing phase of the (y2+1)-th subframe, where i is an integer greater than 1 and less than I, and j is an integer greater than 1 and less than J.

[0233] According to an embodiment of the present application, when the base number of the multi-base PWM driving method is higher and the number of subframes included in each display frame is smaller, the time used for writing the first display data line by line in each display frame is shorter and the time used for luminescence is longer.

[0234] According to the above and other embodiments of the present application, other devices, such as P-type oxide LTPS TFT, complementary oxide LTPO TFT, CMOS, etc., can be used to design a PWM signal generating module and a constant current module respectively, and other circuits can be derived from this to realize the functions of the above-mentioned PWM signal generating module and constant current module.

[0235] According to other embodiments of the present application, the comparison unit in the PWM signal generation module and the constant current module of the pixel circuit may also include other circuit structures, which are not limited by the present application and are determined according to actual production needs. The devices are not limited to N-type TFT transistors or certain transistors and may also include LTPO, CMOS and other devices.

[0236] Figure 8 FIG. 1 is a schematic diagram of a display device structure according to an embodiment of the present application. Figure 8 As shown, the present application also provides a display device, including a Micro-LED display pixel array with I rows and J columns, wherein the Micro-LED display pixel array includes any of the display pixel circuits described above. The display device also includes a timing control circuit (Timing Control, TCON), a gate driver circuit (Gate Driver), and a data driver circuit (Data Driver).

[0237] According to an embodiment of the present application, the timing control circuit receives external data and control signals, and transmits a display signal to the data driver circuit, and a scan signal and a reference signal to the gate driver circuit. According to one embodiment of the present application, the pixel circuits in the same column of the pixel array receive their respective first and second display signals from the data driver circuit via two display signal lines, and the pixel circuits in the same row of the pixel array receive scan signals from the gate driver circuit via two scan signal lines. The pixel circuits in the same row of the pixel array also receive a common reference signal from the gate driver circuit.

[0238] According to an embodiment of the present application, the pixel circuit of the display device may be driven by using the aforementioned multi-bit pulse width modulation driving method.

[0239] The present application also provides an electronic device, which also includes the display device as described above.

[0240] The present application also provides a new pulse width modulation driving method, which may include the following operations.

[0241] receiving initial display data, wherein for a display pixel circuit, the initial display data of each frame includes an X-bit L-ary number, where X and L are both integers greater than or equal to 2;

[0242] Converting the initial display data into intermediate display data, the intermediate display data comprising a K-ary number having Y bits, wherein Y is an integer greater than 0, X is greater than Y, and K is greater than L and an integer greater than or equal to 3; wherein the intermediate display data corresponds to one frame, each frame is divided into Y subframes, each subframe corresponds to one bit of the intermediate display data, each subframe comprises a writing time and a maximum light-emitting time, and the maximum light-emitting time in each subframe is at least a function of K and a sequence number y of the subframe, wherein y is an integer greater than 0 and less than or equal to Y;

[0243] writing intermediate display data of the first subframe of each row into the display pixel circuit using the first data line during the writing time of the first subframe of each row, so that the light-emitting elements in the display pixels of each row emit light based on the intermediate display data of the first subframe immediately after the intermediate display data of the first subframe is written;

[0244] After the longest light-emitting time of the first subframe of each row ends, the intermediate display data of the second subframe of the corresponding row is written into the display pixel circuit using the second data line, and the light-emitting elements in the display pixels of each row emit light based on the intermediate display data of the second subframe immediately after the intermediate display data of the second subframe is written;

[0245] The sum of the writing time and the longest luminous time of the first subframe of the first row and the writing time and the longest luminous time of the second subframe is greater than or equal to the sum of the writing time of the first subframes of each row;

[0246] The actual luminous time of the luminous element in each subframe is at least a function of the value of the corresponding bit of the intermediate display data, K and the sequence number y of the subframe, and the actual luminous time is less than or equal to the longest luminous time of the subframe.

[0247] In particular, the intermediate display signal is compared with the reference signal in each subframe, and when the relative relationship between the intermediate display signal and the reference signal changes, the luminous state of the light-emitting element changes, wherein the intermediate display signal includes the voltage corresponding to the value of each bit of the intermediate display data.

[0248] In particular, when the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

[0249] The driving method disclosed in this application has the advantages of high precision, long effective luminescence time, and good stability. It has a wide range of uses and can be applied to active organic light-emitting diode displays (AM-OLED) and active micro-diode displays (AM-Micro-LED) to form smartphone displays, flat panel displays, and TV display products; it can also be applied to micro-displays with single-crystal silicon CMOS backplanes to form wearable watch displays, helmet displays, and glasses displays, serving diverse scenarios such as augmented reality / virtual reality / fused reality (AR / VR / MR). In addition, by adopting the solution of this application, the luminescence time ratio of the pixel circuit can be effectively improved while improving the accuracy of grayscale control, thereby improving the display quality of the pixel circuit, improving the working efficiency of the display device, reducing the display drive power consumption, and enabling the display device to achieve better performance.

[0250] The present application can be applied to various types of displays, such as active displays entirely integrated with TFTs, active displays integrated with single-crystal silicon CMOS, active displays integrated with TFTs and single-crystal silicon CMOS, or some field-effect transistors can use GaN materials of the same nature as Micro-LEDs as their active layers, etc.

[0251] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A pulse width modulation driving method for a display pixel circuit, comprising: receiving initial display data, wherein for a display pixel circuit, the initial display data of each frame includes an X-digit L-ary number, where X and L are both integers greater than or equal to 2; Converting the initial display data into intermediate display data, the intermediate display data comprising a K-ary number having Y bits, wherein Y is an integer greater than 0, X is greater than Y, and K is greater than L and an integer greater than or equal to 3; wherein the intermediate display data corresponds to one frame, each frame is divided into Y subframes, each subframe corresponds to one bit of the intermediate display data, each subframe comprises a writing time and a maximum light-emitting time, and the maximum light-emitting time in each subframe is at least a function of K and a sequence number y of the subframe, wherein y is an integer greater than 0 and less than or equal to Y; writing intermediate display data of the first subframe of each row into the pixel circuit using the first data line during the writing time of the first subframe of each row, so that the light-emitting elements in the display pixels of each row emit light based on the intermediate display data of the first subframe immediately after the intermediate display data of the first subframe is written; After the longest light-emitting time of the first subframe of each row ends, the intermediate display data of the second subframe of the corresponding row is written into the pixel circuit using the second data line, and the light-emitting elements in the display pixels of each row emit light based on the intermediate display data of the second subframe immediately after the intermediate display data of the second subframe is written; The sum of the writing time and the longest luminous time of the first subframe of the first row and the writing time and the longest luminous time of the second subframe is greater than or equal to the sum of the writing time of the first subframes of each row; The actual luminous time of the luminous element in each subframe is at least a function of the value of the corresponding bit of the intermediate display data, K and the sequence number y of the subframe, and the actual luminous time is less than or equal to the longest luminous time of the subframe.

2. The driving method according to claim 1, further comprising An intermediate display signal is compared with a reference signal in each subframe. When the relative relationship between the intermediate display signal and the reference signal changes, the luminous state of the light-emitting element changes, wherein the intermediate display signal includes a voltage corresponding to each bit value of the intermediate display data.

3. The driving method according to claim 2, wherein When the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

4. An active display pixel circuit comprising: Light-emitting element; a PWM signal generating module configured to receive a first scanning signal, a second scanning signal, and a reference signal; The PWM signal generating module includes at least two data lines; the PWM signal generating module is further configured to receive a first display signal using the first data line or receive a second display signal using the second data line under the control of the first scan signal and the second scan signal, and output a PWM signal; wherein the PWM signal generating module includes a comparing unit, the comparing unit being configured to compare the first display signal or the second display signal with the reference signal, and to cause the PWM signal to jump when the comparison result changes; a constant current module, configured to provide a light-emitting current to the light-emitting element; a switch module, coupled between the constant current module and the light-emitting element, and configured to be turned on or off under the control of the PWM signal; The intermediate display data includes a K-ary number having Y bits, where Y is an integer greater than 0 and K is an integer greater than or equal to 3; the intermediate display data corresponds to one frame, each frame is divided into Y subframes, each subframe corresponds to one bit of the intermediate display data, and each subframe includes a writing time and a maximum light-emitting time; writing intermediate display data of the first subframe of each row into the pixel circuit using the first data line during a writing time of the first subframe of each row, and causing the light-emitting elements in the display pixels of each row to emit light based on the intermediate display data of the first subframe immediately after the intermediate display data of the first subframe is written; wherein the first display signal corresponds to the first subframe; After the longest light-emitting time of the first subframe of each row ends, intermediate display data of the second subframe of the corresponding row is written into the pixel circuit using the second data line, and the light-emitting elements in the display pixels of each row emit light based on the intermediate display data of the second subframe immediately after the intermediate display data of the second subframe is written; wherein the second display signal corresponds to the second subframe; The sum of the writing time and the longest luminous time of the first subframe of the first row and the writing time and the longest luminous time of the second subframe is greater than or equal to the sum of the writing time of the first subframes of each row; The actual luminous time of the luminous element in each subframe is at least a function of the value of the corresponding bit of the intermediate display data, K and the sequence number y of the subframe, and the actual luminous time is less than or equal to the longest luminous time of the subframe.

5. The pixel circuit according to claim 4, wherein When the reference signal is a step signal, the reference signal includes (K-1) steps of equal height, each step has the same duration, and the longest luminous time of each subframe is evenly divided into (K-1) parts.

6. The pixel circuit according to claim 5, wherein The switch module includes a switch transistor (304, 404, 504, 604 or 704), a control electrode of the switch transistor (304, 404, 504, 604 or 704) is coupled to the PWM signal generating module to receive the PWM signal, a first electrode is coupled to the constant current module, and a second electrode is coupled to the anode of the light-emitting element; and The constant current module includes a first transistor (T34, T44, T54, T64 or T74), wherein a control electrode of the first transistor (T34, T44, T54, T64 or T74) receives an enable signal, a first electrode is configured to receive a high level, and a second electrode is coupled to the first electrode of the switch transistor (304, 404, 504, 604 or 704); The switch transistor and the first transistor are of the same type.

7. The pixel circuit according to claim 6, wherein The comparison unit in the PWM signal generating module includes a second transistor (T51, T61 or T71) and a first capacitor (C51, C61 or C71); a first end of the first capacitor (C51, C61 or C71) is configured to receive the reference signal; a control electrode of the second transistor (T51, T61 or T71) is coupled to the second end of the first capacitor (C51, C61 or C71), and a first electrode is coupled to the control electrode of the first transistor (T54, T64 or T74); The PWM signal generating module further includes a third transistor (T52, T62, T72), a first electrode of which is configured to receive a high level, a second electrode coupled to the first electrode of the second transistor (T51, T61 or T71) and serving as an output terminal of the PWM signal generating module, and a control electrode of which is configured to receive a charging signal; The second transistor and the third transistor are of the same type.

8. The pixel circuit according to claim 7, wherein the PWM signal generating module further comprises a fourth transistor (T63a, T73a), wherein a control electrode of the fourth transistor (T63a, T73a) receives the first scanning signal, a first electrode receives the first display signal, and a second electrode is coupled to the second electrode of the second transistor (T61, T71); a fifth transistor (T63b, T73b), wherein a control electrode of the fifth transistor (T63b, T73b) receives the second scanning signal, a first electrode receives the second display signal, and a second electrode is coupled to the second electrode of the second transistor (T61, T71); a sixth transistor (T66, T76), a first electrode of which is coupled to the second electrode of the third transistor, a second electrode of which is coupled to the control electrode of the second transistor (T51, T61, or T71) and the second end of the first capacitor (C51, C61, or C71), and a control electrode of which is configured to receive a reset signal; a seventh transistor (T65, T75), a first electrode of which is coupled to the second electrode of the second transistor (T51, T61 or T71), a second electrode of which is grounded, and a control electrode of which receives an enable signal; The fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are of the same type.

9. The pixel circuit according to claim 8, wherein the constant current module further comprises an eighth transistor (T710), a ninth transistor (T77), a tenth transistor (T711), an eleventh transistor (T79), a twelfth transistor (T78) and a second capacitor (C72), wherein The control electrode of the eighth transistor (T710) receives the charging signal, and the first electrode receives a high level; The control electrode of the ninth transistor (T77) receives an enable signal, the first electrode receives a high level, the second electrode is coupled to the second electrode of the eighth transistor (T710), and the control electrode receives the enable signal; The control electrode of the tenth transistor (T711) receives a reset signal, and the first electrode is coupled to the second electrodes of the eighth transistor (T710) and the ninth transistor (T77); The first electrode of the eleventh transistor (T79) is coupled to the second electrodes of the eighth transistor (T710) and the ninth transistor (T77), and the second electrode is coupled to the first electrode of the first transistor (T74); A first end of the second capacitor (C72) is grounded, and a second end is coupled to the control electrode of the eleventh transistor (T79); The control electrode of the twelfth transistor (T78) receives a constant current scanning signal, the second electrode is coupled to the first electrode of the first transistor (T74), and the first electrode receives a constant current display signal; The eighth transistor, the ninth transistor, the tenth transistor, the eleventh transistor and the twelfth transistor are of the same type.

10. The pixel circuit according to claim 8, wherein the constant current module further comprises a first current bias unit, a first end of which receives a high level, and a second end of which is coupled to the first electrode of the first transistor (T64).

11. The pixel circuit according to claim 7, wherein the PWM signal generating module further comprises a thirteenth transistor (T53a), a first electrode of which receives the first display signal, a second electrode of which is coupled to the control electrode of the second transistor (T51), and a control electrode of which receives the first scan signal; as well as a fourteenth transistor (T53b), a first electrode of which receives a second display signal, a second electrode of which is coupled to a control electrode of the second transistor (T51), and a control electrode of which receives a second scan signal; The thirteenth transistor and the fourteenth transistor are of the same type.

12. The pixel circuit according to claim 11, wherein the constant current module further comprises The constant current module further includes a fifteenth transistor (T57), a sixteenth transistor (T59), a seventeenth transistor (T58), and a third capacitor (C52), wherein The first electrode of the fifteenth transistor (T57) receives a high level, and the control electrode receives an enable signal; A first electrode of the sixteenth transistor (T59) is coupled to a second electrode of the fifteenth transistor (T57), and a second electrode thereof is coupled to a first electrode of the first transistor (T54); A first end of the third capacitor (C52) is grounded, and a second end is coupled to the control electrode of the sixteenth transistor (T59); The control electrode of the seventeenth transistor (T58) receives a constant current scanning signal, the first electrode receives a constant current display signal, and the second electrode is coupled to the second end of the third capacitor (C52); The fifteenth transistor, the sixteenth transistor, and the seventeenth transistor are of the same type.

13. The pixel circuit according to claim 6, wherein The comparison unit includes an eighteenth transistor (T31) and a nineteenth transistor (T32), wherein a control electrode of the eighteenth transistor (T31) and a control electrode of the nineteenth transistor (T32) are coupled to each other as an input terminal of the comparison unit, a second electrode of the nineteenth transistor (T32) receives a high level, a second electrode of the eighteenth transistor (T31) is grounded, and a first electrode of the nineteenth transistor (T32) and a first electrode of the eighteenth transistor (T31) are coupled to each other as an output terminal of the comparison unit; and The PWM signal generating module includes a fourth capacitor (C31), a first end of which is configured to receive the reference signal and a second end of which is coupled to the input end of the comparison unit; The PWM signal generating module includes a twentieth transistor (T33a) and a twenty-first transistor (T33b), wherein a first electrode of the twentieth transistor (T33a) receives a first display signal, a first electrode of the twenty-first transistor (T33b) receives a second display signal, second electrodes of the twentieth transistor (T33a) and the twenty-first transistor (T33b) are coupled to an input terminal of the comparing unit, a control electrode of the twentieth transistor (T33a) receives a first scanning signal, and a control electrode of the twenty-first transistor (T33b) receives a second scanning signal; in, The nineteenth transistor (T32) is complementary to the eighteenth transistor (T31), the twentieth transistor, and the twenty-first transistor.

14. The pixel circuit according to claim 13, wherein The constant current module further includes a second current bias unit, a first end of the second current bias unit receives a high level, and a second end is coupled to the first electrode of the first transistor (T34).

15. The pixel circuit according to claim 6, wherein The PWM signal generating module includes a twenty-second transistor (T43a) and a twenty-third transistor (T43b), wherein the second electrode of the twenty-second transistor (T43a) is coupled to the first electrode of the twenty-third transistor (T43b), the control electrode of the twenty-second transistor (T43a) receives the first scanning signal, the control electrode of the twenty-third transistor (T43b) receives the second scanning signal, the first electrode of the twenty-second transistor (T43a) receives the first display signal, and the second electrode of the twenty-third transistor (T43b) receives the second display signal; The PWM signal generating module further includes a fifth capacitor (C41), a first end of which is grounded, and a second end of which is coupled to the second electrode of the twenty-second transistor (T43a) and the first electrode of the twenty-third transistor (T43b); The PWM signal generating module further comprises a buffer, wherein the input end of the buffer is coupled to the output end of the comparison unit, and the output end of the buffer is coupled to the control electrode of the switching transistor (T404); The comparison unit includes a twenty-fourth transistor (T41), a twenty-fifth transistor (T42), a twenty-sixth transistor (T46), a twenty-seventh transistor (T45), a twenty-eighth transistor (T47), a twenty-ninth transistor (T48) and a third current bias unit; wherein The control electrode and the first electrode of the twenty-fourth transistor (T41) are coupled to the control electrode of the twenty-fifth transistor (T42); the second electrodes of the twenty-fourth transistor (T41) and the twenty-fifth transistor (T42) are coupled to each other and receive a high level; the first electrode of the twenty-fifth transistor (T42) is coupled to the input end of the buffer and serves as the output end of the comparison unit; The control electrode of the twenty-seventh transistor (T45) receives the reference signal, the first electrode of the second-seventh transistor (T45) is coupled to the first electrode of the twenty-fourth transistor (T41), and the second electrode of the second-sixth transistor (T46) is coupled to the second end of the fifth capacitor (C41), the first electrode of the second-sixth transistor (T46) is coupled to the first electrode of the twenty-fifth transistor (T42), and the second electrode of the second-sixth transistor (T47) is coupled to the first electrode of the twenty-eighth transistor (T47); the second electrode of the twenty-eighth transistor (T47) is grounded, the control electrode is coupled to the control electrode and the first electrode of the twenty-ninth transistor (T48), and the second electrode of the twenty-ninth transistor (T48) is coupled to the first end of the fifth capacitor (C41); the first end of the third current bias unit receives a high level, and the second end is coupled to the first electrode of the twenty-ninth transistor (T48); in, The twenty-fourth transistor (T41) and the twenty-fifth transistor (T42) are of the same type and are complementary to the other transistors in the comparison unit and the PWM signal generation module.

16. The pixel circuit according to claim 15, wherein The constant current module further includes a fourth current bias unit, a first end of which receives a high level, and a second end of which is coupled to the first electrode of the first transistor (T44).

17. A display device comprising a display pixel array, wherein the display pixel array comprises any one of the pixel circuits according to claims 4 to 16, and further comprises a timing control circuit, a gate drive circuit, and a data drive circuit; The gate driving circuit is coupled to the timing control circuit and the display pixel array, and is configured to provide an enable signal, a scan signal, and a reference signal to the display pixel array under the control of the timing control circuit; the data driving circuit is coupled to the timing control circuit and the display pixel array, and is configured to provide a display signal to the display pixel array under the control of the timing control circuit.

18. An electronic device comprising the display device according to claim 17.

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