Semiconductor device and method using lead frame interposer in bump continuity test

Abstract

A semiconductor device has an electrical component having a bump structure. A conductive layer is formed over the electrical component, wherein a first segment of the conductive layer is coupled between the first and second bumps. The electrical components are disposed on the pads of the leadframe interposer. A first bond wire is coupled between the first lead and the first bump. A second bond wire is coupled between the second lead and the second bump. A third bond wire is coupled between the third lead and the third bump, and a fourth bond wire is coupled between the fourth lead and the fourth bump. A fifth bond wire is coupled between the second lead and the third lead, and a second segment of the conductive layer is coupled between the third bump and the fourth bump to form a daisy chain loop to test continuity of the bump structure.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods using a leadframe interposer for bump continuity testing for WLCSP. Background Art

[0002] Semiconductor devices are commonly found in modern electrical products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electrical devices, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices often include a semiconductor die or substrate with an electrical interconnect structure, for example, a redistribution layer (RDL) formed over one or more surfaces of the semiconductor die or substrate to perform necessary electrical functions. Multiple bumps are formed on the surface of the semiconductor die, while in wafer form for external electrical interconnection with the RDL. The bumps should be tested for electrical continuity to identify defects and provide known good dies. Bump continuity testing is particularly challenging for fine pitch bumps (e.g., about 40.0 microns (μm) or greater). BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1i A semiconductor wafer having a plurality of semiconductor dies having bump structures is illustrated; Figure 2a-2c illustrates forming a conductive segment on a surface of a semiconductor die between a pair of bump structures; Figure 3a-3b illustrates forming conductive segments on a surface of a semiconductor die prior to forming a bump structure; Figure 4a-4c A lead frame interposer is illustrated; Figure 5a-5e A leadframe interposer is illustrated having electrical components disposed on pads and bond wires connecting leads to bump structures; Figure 6 illustrates electrical continuity testing of a bump structure using bond wires and conductive segments; Figure 7a-7c Illustration of electrical continuity testing in a daisy chain loop arrangement; Figure 8 illustrates a bump structure of an electrical component logically arranged in a region for electrical continuity testing; Fig. 9 Diagram showing electrical continuity testing of a daisy chain loop for smaller electrical components; Fig.10 illustrates cutting of a conductive segment after an electrical continuity test; Fig.11 illustrates electrical continuity testing of the RDL using electrical components; and Fig.12 A printed circuit board (PCB) is illustrated, wherein different types of packages are arranged on a surface of the PCB. DETAILED DESCRIPTION

[0005] The present invention is described in one or more embodiments in the following description with reference to the accompanying drawings, in which like reference numerals represent identical or similar elements. Although the present invention is described with respect to the best mode for achieving the purposes of the present invention, it should be appreciated by those skilled in the art that it is intended to cover alternatives, modifications and equivalents as may be included in the spirit and scope of the present invention as defined by the attached claims and their equivalents as supported by the following disclosure and the accompanying drawings. The features shown in the figures do not have to be drawn to scale. Elements with similar functions are assigned the same reference numerals in the figures. The term "semiconductor die" as used herein refers to words in both singular and plural forms, and accordingly may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0006] Semiconductor devices are generally manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components (such as transistors and diodes) have the ability to control the flow of electrical current. Passive electrical components (such as capacitors, inductors, and resistors) create the relationship between voltage and current necessary to perform the circuit function.

[0007] Back-end manufacturing refers to cutting or singulating the finished wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scored and decomposed along the non-functional area of ​​the wafer called saw road or scribing. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor dies are arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed above the semiconductor die are then connected to the contact pads in the package. Electrical connections can be made using conductive layers, bumps, columnar bumps, conductive pastes, or bonding wires. Encapsulants or other molding materials are deposited above the package to provide physical support and electrical isolation. The finished package is then inserted into the electrical system, and the functionality of the semiconductor device is made available to other system components.

[0008] Figure 1aA semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed over the wafer 100 separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0009] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back surface or inactive surface 108 and an active surface 110 containing analog or digital circuits, which are implemented as active devices, passive devices, conductive layers, and dielectric layers formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as a digital signal processor (DSP), an application specific integrated circuit (ASIC), memory, or other signal processing circuits. The semiconductor die 104 may also include an IPD for RF signal processing, such as an inductor, a capacitor, and a resistor. The semiconductor die 104 on the wafer 100 is considered a wafer-level chip scale package (WLCSP).

[0010] Conductive layer 112 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to a circuit on or within active surface 110.

[0011] exist Figure 1cIn the embodiment, the conductive bump material is deposited on the conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. In the case of an optional flux solution, the bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 118. In one embodiment, the bump 118 is formed above an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. The bump 118 can also be compression bonded or thermally compression bonded to the conductive layer 112. The bump 118 represents a type of interconnect structure that can be formed above the conductive layer 112. The interconnect structure can also use bonding wires, conductive pastes, columnar bumps, microbumps or other electrical interconnects. The bump 118 is a type of bump structure. The bump 118 has a fine bump pitch, ie, 40.0 micrometers (μm) or more.

[0012] In another embodiment of forming the bump structure, Figure 1b Next, a solder resist or photoresist layer 121 is formed over the active surface 110, such as Figure 1d As shown in Figure 1e In the process, a plurality of openings 125 are formed in the solder resist / photoresist 121 using an etching process or laser direct ablation (LDA) by means of a laser 123 .

[0013] exist Figure 1f In the embodiment, the opening 125 is filled with a conductive material to form a conductive pillar or column 120. Figure 1g , removing the remaining solder resist / photoresist 121, thereby leaving a conductive pillar or pillar or column 120. The conductive pillar or pillar or column 120 can be Al, Cu, Sn, Ni, Au, Ag, a multilayer combination or other suitable conductive material. The conductive pillar 120 can have a height H1 of 35.0 μm to compensate for thickness variations in different technologies (such as surface mounting and flip chip). In one embodiment, the conductive pillar 120 can have a Cu organic solderability preservative (OSP), or electroless nickel electroless palladium immersion gold (ENEPIG), or electroless nickel immersion gold (ENIG), or immersion tin, or a solder cap finish or layer 127 formed on an exposed pad or metal surface.

[0014] exist Figure 1hIn the embodiment of the present invention, the conductive bump material is deposited on the conductive pillar 120 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. In the case of an optional flux solution, the bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to the conductive pillar 120 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 122. The solder cap finish or layer 127 will dissolve with the formation of the bump 122. In another embodiment, the bump 122 is formed on the UBM having a wetting layer, a barrier layer and an adhesive layer. The bump 122 can also be compression bonded or thermally compression bonded to the conductive pillar 120. The bump 122 represents a type of interconnect structure that can be formed above the conductive pillar 120. The interconnect structure may also use conductive paste, stud bumps, micro bumps or other electrical interconnects. The combination of conductive pillars 120 and bumps 122 constitutes a bump structure 124. Bump structure 124 has a fine bump pitch, ie, 40.0 μm or greater.

[0015] exist Figure 1i In the embodiment of the present invention, a semiconductor wafer 100 is singulated into individual semiconductor dies 104 through saw streets 106 using a saw blade or laser cutting tool. The individual semiconductor dies 104 can be inspected and electrically tested for identifying known good dies or known good units (KGD / KGU) after singulation. Figure 1c This occurs to extract individual semiconductor die 104 having bumps 118 .

[0016] Figure 2a A cross-sectional view of semiconductor die 104 having a plurality of bump structures 124 formed over active surface 110 is illustrated. Figure 2b is a top view of a semiconductor die 104 having a plurality of bump structures 124 formed above an active surface 110. Although the remainder of the disclosure relates to Figure 1h-1i The bump structure 124, but the discussion applies to Figure 1c The bump 118 is provided.

[0017] Conductive layer 130 is formed over active surface 110 using PVD, CVD, electrolytic plating, electroless plating processes, or other suitable metal deposition processes. Conductive layer 130 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. In particular, portions or segments of conductive layer 130 are electrically and mechanically connected between pairs of bump structures 124. For example, conductive segment 130a is mechanically and electrically coupled between bump structures 124a and 124b. Conductive segment 130b is mechanically and electrically coupled between bump structures 124c and 124d. Conductive segment 130c is mechanically and electrically coupled between bump structures 124e and 124f. Each pair of bump structures 124 will have a corresponding conductive segment 130, such as Figure 2b . Otherwise, the plurality of conductive segments 130 are physically isolated and electrically isolated. In other words, bump structures 124a and 124b are connected by conductive segment 130a, bump structures 124c and 124d are connected by conductive segment 130b, and bump structures 124e and 124f are connected by conductive segment 130c. However, at least with respect to conductive segments 130a-130c, bump structures 124a and 124b are physically isolated and electrically isolated from bump structures 124c and 124d, and bump structures 124c and 124d are physically isolated and electrically isolated from bump structures 124e and 124f. Conductive segment 130a is physically isolated and electrically isolated from conductive segment 130b, and conductive segment 130b is physically isolated and electrically isolated from conductive segment 130c. Pairs of bump structures may be adjacent or separated in a pattern or by a pattern (e.g., in a diagonal or alternating pattern).

[0018] Figure 2c Further details of a portion of semiconductor die 104 having an adjacent pair of bump structures 124a and 124b and an interconnecting conductive segment 130a are shown. Conductive segment 130a physically and electrically contacts a bottom portion of a conductive pillar 120 of each of the pair of bump structures 124a and 124b and conductive layer 112. That is, one end of conductive segment 130a is connected to a bottom portion of conductive pillar 120 of bump structure 124a and conductive layer 112 below bump structure 124a. A distal end of conductive segment 130a is connected to a bottom portion of conductive pillar 120 of bump structure 124b and conductive layer 112 below bump structure 124b. Conductive segment 130a provides an electrical path between bump structures 124a and 124b. In a similar manner, conductive segment 130 b provides an electrical path between bump structures 124 c and 124 d , and conductive segment 130 c provides an electrical path between bump structures 124 e and 124 f .

[0019] In another embodiment, conductive layer 130 is formed over active surface 110 of semiconductor die 104 as a WLCSP before forming bump structure 124 . Figure 3a FIG. 1 shows a conductive layer 130 formed over the active surface 110 without a bump structure. After forming the conductive layer 130, a bump structure 124 will be formed, similar to FIG. Figure 1d-1i ,like Figure 3b The bump structures 124 make physical and electrical connections to corresponding conductive segments 130 .

[0020] Figure 4a-4c A leadframe interposer 140 is illustrated. In one embodiment, the leadframe interposer 140 is an etched quad flat no-lead (QFN) frame. Figure 4a is a cross-sectional view of a leadframe interposer 140 having leads 142 and flags or pads 144 . Figure 4b is a top view of a leadframe interposer 140 with leads 142 and flags or pads 144 and flag or pad supports 145 . Figure 4c is a perspective view of a leadframe interposer 140 having leads 142 and flags or pads 144 and flag or pad supports 145. As is well known, the leads 142 and pad supports 145 will be connected to a peripheral frame (not shown).

[0021] exist Figure 5a In the embodiment, the electrical component 146 is disposed above the surface 147 of the pad 144 of the lead frame interposer 140. The electrical component 146 may be from Figure 2a The semiconductor die 104 has a back surface 108 oriented toward a surface 147 of the pad 144. Alternatively, the electrical component 146 may include another semiconductor die, a semiconductor package, a surface mount device, an RF component, a discrete electrical device, or an integrated passive device (IPD).

[0022] A pick and place operation is used to position the electrical component 146 over the pad 144. The electrical component 146 is brought into contact with the pad 144 and secured with an adhesive or other bonding layer. Figure 5b An electrical component 146 is illustrated bonded to the pad 144 as an assembly 150 . Figure 5c is a perspective view of an assembly 150 having an electrical component 146 bonded to a pad 144 of a leadframe interposer 140 .

[0023] exist Figure 5dIn the embodiment of the present invention, a plurality of bonding wires 148 are connected between the leads 142 and the bump structures 124. In particular, the bonding wires 148 are attached to the top surface of the bumps 122. The bonding wires 148 can take a variety of forms, including ball-safe bumps (BSBs) on pins, stud stitch bonds (SSBs), ball bonds, and reverse isolated stitch bonds (RSSBs).

[0024] Figure 5e Further details are shown of a first end of a bond wire 148a electrically and mechanically connected to a surface of lead 142a and a second distal end of bond wire 148a electrically and mechanically connected to a top surface of bump 122 of bump structure 124a.

[0025] The leadframe interposer 140 , the bond wires 148 , and the conductive segments 130 are used in a daisy chain loop for bump continuity testing of the bump structures 124 or the bumps 118 . Figure 6 Further details of the bump continuity test are illustrated. In a simplified explanation, lead 142a is connected to bump 122 of bump structure 124a using bonding wire 148a. Conductive pillar 120 of bump structure 124a is connected to conductive pillar 120 of bump structure 124b using conductive segment 130a. Bump 122 of bump structure 124b is connected to lead 142b using bonding wire 148b. Voltage source 152 is applied to lead 142a. Current measuring device or instrument 154 is coupled to lead 142b. If there is continuity, the current will flow along the conductive path 156, which flows from the voltage source 152 through the lead 142a, the bonding wire 148a, the bump 122 of the bump structure 124a, the conductive pillar 120 of the bump structure 124a, the conductive segment 130a, the conductive pillar 120 of the bump structure 124b, the bump 122 of the bump structure 124b, the bonding wire 148b and the lead 142b to the current measuring device or instrument 154. If the bump structures 124a and 124b have electrical continuity, then the current will be detected by the current measuring device or instrument 154 and the bump continuity test is considered to be passed. If no current is detected, it is assumed that electrical discontinuity may exist in the bump structure 124a and / or 124b. A failure analysis can be performed, rework may occur if indicated, and a retest of the bump continuity is performed.

[0026] The bump continuity test can be expanded to use more leads 142 and more bond wires 148 to test multiple pairs of bump structures 124 simultaneously. Figure 7a In the embodiment of the present invention, the bump structures 124 are connected or arranged in series in a daisy chain loop having bond wires 148 to the leads 142 to perform bump continuity testing on multiple pairs of bump structures 124 simultaneously. Figure 7bis a perspective view of a daisy chain loop having bond wires 148 to leads 142 to perform bump continuity testing on multiple pairs of bump structures 124 simultaneously.

[0027] Figure 7c Further details of a portion of a leadframe interposer 140 and electrical components 146 for performing bump continuity testing on multiple pairs of bump structures 124 using a daisy chain loop 159 including leads 142, bonding wires 148, and conductive segments 130 are shown. The daisy chain loop 159 can continue completely around the leadframe interposer 140. Assume that a voltage source 152 is coupled to lead 142a. Bonding wires 158 are coupled between alternating and adjacent leads that extend the daisy chain loop. For example, bonding wire 158a is coupled between lead 142a and lead 142b. Lead 142a, bonding wire 158a, lead 142b, bonding wire 148a, bump structure 124a, conductive segment 130a, bump structure 124b, bonding wire 148b, lead 142c, bonding wire 158b, lead 142d, bonding wire 148c, bump structure 124c, conductive segment 130b, bump structure 124d, bonding wire 148d, lead 142e, bonding wire 158c, lead 142 The combination of bonding wire 148e, bump structure 124e, conductive segment 130c, bump structure 124f, bonding wire 148f, lead 142g, bonding wire 158d, lead 142h, bonding wire 148g, bump structure 124g, conductive segment 130d, bump structure 124h, bonding wire 148h and lead 142i forms a daisy chain loop 159, which can continue or repeat around the lead frame interposer 140.

[0028] If there is continuity, current will flow from voltage source 152 through lead 142a, bond wire 158a, lead 142b, bond wire 148a, bump structure 124a, conductive segment 130a, bump structure 124b, bond wire 148b, and lead 142c. Current will continue and flow through bond wire 158b, lead 142d, bond wire 148c, bump structure 124c, conductive segment 130b, bump structure 124d, bond wire 148d, and lead 142e. Current will continue and flow through bond wire 158c, lead 142f, bond wire 148e, bump structure 124e, conductive segment 130c, bump structure 124f, bond wire 148f, and lead 142g. The current will continue and pass through bond wire 158d, lead 142g, bond wire 158d, lead 142h, bond wire 148g, bump structure 124g, conductive segment 130d, bump structure 124h, bond wire 148h, and lead 142i. The daisy chain loop 159 can continue completely around the lead frame interposer 140 for any number of bump structures 124 or until there are no more available leads 142 on the lead frame interposer 140.

[0029] As in Figure 6 As in, if Figure 7c The bump structures 124a-124h and Figure 7a-7b If more of the bump structures 124 in the bump structure 124 have electrical continuity, then the current will be detected by the current measuring device or instrument 154 and the bump continuity test is considered to have passed. If no current is detected, it is assumed that the electrical discontinuity may exist in one or more of the bump structures 124a-124h or Figure 7a-7b More bump structures 124 in. Electrical component 146 fails continuity test. Failure analysis may be performed, rework may occur if indicated, and retesting of bump continuity may be performed.

[0030] In the event that there are more bump structures 124 on the electrical components 146 than available leads 142 on the leadframe interposer 140, then the electrical components 146 may be logically organized into partitions or zones. Figure 8 , electrical components 146 are organized such that region 162 includes bump structures 124 outside of line 160. Region 166 includes bump structures 124 between line 160 and line 168. Region 170 includes bump structures 124 inside line 168. Regions 162, 166, and 170 are logically organized to have a sufficient number of available leads 142 to accommodate the bump structures within the defined regions. Bond wires 148 and 158 are connected to leads 142 and bump structures 124 within region 162, similar to Figure 7a-7c A bump continuity test is performed for region 162, such as Figure 6 and 7a -7c. Remove the bonding wire 148 and reconnect the bonding wire 148 to the lead 142 and the bump structure 124 in the region 166, similar to Figure 7a-7c A bump continuity test is performed on region 166, such as Figure 6 and 7a -7c. Remove the bonding wire 148 and reconnect the bonding wire 148 to the lead 142 and the bump structure 124 in the region 170, similar to Figure 7a-7c A bump continuity test is performed for region 170, such as Figure 6 and 7a -7c.

[0031] exist Fig. 9 In the embodiment of the present invention, a smaller electrical component 180 is placed on the pad 144. In this case, there may be a sufficient number of leads 142 to connect to all bump structures 124. Otherwise, it would be necessary to establish partitions or zones to perform bump continuity testing on the electrical component 180, similar to Figure 8 .

[0032] exist Fig.10 , after the continuity test, the bonding wires 148 are removed and the conductive segments 130 are cut to physically and electrically isolate the bump structures 124, so that the electrical components 146 can perform their intended electrical functions. The conductive segments 130 can be cut by a laser or saw. Depending on the normal electrical function of the electrical components 146, some or all of the conductive segments 130 may still exist. The electrical components 146 are removed from the lead frame interposer 140 where the continuity of the bump structures 124 is tested and confirmed. The electrical components 146 can be sealed with the bump structures 124 exposed for further functional probe testing and normal operation.

[0033] The leadframe interposer 140 with the bond wires 148 and the conductive layer 130 provides a cost-effective and efficient means of performing continuity testing of the bump structures 124. The bond wires 148 provide flexibility and configurability in routing to the fine pitch bump structures 124.

[0034] In another embodiment, the redistribution layer 188 in the active surface 110 will provide electrical connections between the bump structures 124a and 124b, such as Fig.11 as shown in .

[0035] Fig.12 An electrical device 400 is illustrated having a chip carrier substrate or PCB 402 with a plurality of semiconductor packages, including electrical components 146, disposed on a surface of the PCB 402. The electrical device 400 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0036] The electrical device 400 can be an independent system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 can be a subcomponent of a larger system. For example, the electrical device 400 can be a part of a tablet, a cellular phone, a digital camera, a communication system, or other electrical devices. Alternatively, the electrical device 400 can be a network interface card, or other signal processing cards that can be inserted into a computer. The semiconductor package can include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are necessary for products to be accepted by the market. The distance between semiconductor devices can be reduced to achieve higher density.

[0037] exist Fig.124, PCB 402 provides a general substrate for structural support and electrical interconnection for semiconductor packages disposed on the PCB. Conductive signal traces 404 are formed over the surface of PCB 402 or within the layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.

[0038] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, the semiconductor device may have a first level packaging, in which the die is mechanically and electrically disposed directly on the PCB. For purposes of illustration, several types of first level packaging are shown on PCB 402, including wire bonding packages 406 and flip chips 408. In addition, several types of second level packaging disposed on PCB 402 are shown, including ball grid arrays (BGA) 410, bump chip carriers (BCC) 412, land grid arrays (LGA) 416, multi-chip modules (MCM) or SIP modules 418, quad flat no-lead packages (QFN) 420, quad flat packages 422, embedded wafer-level ball grid arrays (eWLB) 424, and wafer-level chip-scale packages (WLCSP) 426. In one embodiment, the eWLB 424 is a fan-out wafer level package (Fo-WLP) and the WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured using any combination of first and second level packaging styles and other electrical components can be connected to the PCB 402. In some embodiments, the electrical device 400 includes a single attached semiconductor package, while other embodiments advocate multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-made components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost for the consumer.

[0039] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations to those embodiments may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, comprising: an electrical component including a first bump structure and a second bump structure formed over a surface of the electrical component; a conductive layer formed over a surface of the electrical component, wherein a first segment of the conductive layer is electrically coupled between the first bump structure and a second bump structure; a lead frame interposer, wherein the electrical component is disposed on a pad of the lead frame interposer; a first bonding wire coupled between a first lead of the leadframe interposer and the first bump structure; as well as A second bonding wire is coupled between a second lead of the lead frame interposer and the second bump structure.

2. The semiconductor device according to claim 1, further comprising: a third bonding wire coupled between a third lead of the leadframe interposer and a third bump structure of the electrical component; a fourth bonding wire coupled between a fourth lead of the leadframe interposer and a fourth bump structure of the electrical component; as well as a fifth bonding wire coupled between the second lead and the third lead; The second section of the conductive layer is coupled between the third bump structure and the fourth bump structure.

3. The semiconductor device of claim 2 , wherein a serial combination of the first lead, the first bonding wire, the first bump structure, the first segment of the conductive layer, the second bump structure, the second bonding wire, the second lead, the fifth bonding wire, the third lead, the third bonding wire, the third bump structure, the second segment of the conductive layer, the fourth bump structure, the fourth bonding wire and the fourth lead constitutes a daisy chain loop to test the continuity of the first bump structure, the second bump structure, the third bump structure and the fourth bump structure.

4. The semiconductor device according to claim 3, further comprising: a voltage source coupled to the first lead; as well as A current measuring device is coupled to the fourth lead to test the continuity of the first bump structure, the second bump structure, the third bump structure and the fourth bump structure. The semiconductor device according to claim 1 , wherein the first bump structure comprises a bump.

6. A semiconductor device comprising: an electrical component including a plurality of bump structures formed over a surface of the electrical component; a conductive layer formed over a surface of the electrical component, wherein a first segment of the conductive layer is electrically coupled between a first bump structure and a second bump structure of the plurality of bump structures; a first electrical connection coupled to the first bump structure; as well as A second electrical connection is coupled to the second bump structure.

7. The semiconductor device of claim 6, further comprising a lead frame interposer, wherein the electrical component is disposed on a pad of the lead frame interposer, and the first electrical connection comprises a first bonding wire coupled between a first lead of the lead frame interposer and the first bump structure, and the second electrical connection comprises a second bonding wire coupled between a second lead of the lead frame interposer and the second bump structure.

8. The semiconductor device according to claim 7, further comprising: a third bonding wire coupled between a third lead of the leadframe interposer and a third bump structure of the plurality of bump structures; a fourth bonding wire coupled between a fourth lead of the leadframe interposer and a fourth bump structure of the plurality of bump structures; as well as a fifth bonding wire coupled between the second lead and the third lead; The second section of the conductive layer is coupled between the third bump structure and the fourth bump structure.

9. A semiconductor device as described in claim 8, wherein a serial combination of the first lead, the first bonding wire, the first bump structure, the first segment of the conductive layer, the second bump structure, the second bonding wire, the second lead, the fifth bonding wire, the third lead, the third bonding wire, the third bump structure, the second segment of the conductive layer, the fourth bump structure, the fourth bonding wire and the fourth lead constitutes a daisy chain loop to test the continuity of the first bump structure, the second bump structure, the third bump structure and the fourth bump structure.

10. The semiconductor device according to claim 9, further comprising: a voltage source coupled to the first lead; as well as A current measuring device is coupled to the fourth lead to test the continuity of the first bump structure, the second bump structure, the third bump structure and the fourth bump structure.

11. A method for manufacturing a semiconductor device, comprising: providing an electrical component including a plurality of bump structures formed over a surface of the electrical component; forming a conductive layer over a surface of the electrical component, wherein a first segment of the conductive layer is electrically coupled between a first bump structure and a second bump structure of the plurality of bump structures; forming a first electrical connection to the first bump structure; and A second electrical connection is formed to the second bump structure.

12. The method of claim 11 , further comprising providing a lead frame interposer, wherein the electrical component is disposed on a pad of the lead frame interposer, and the first electrical connection comprises a first bonding wire coupled between a first lead of the lead frame interposer and the first bump structure, and the second electrical connection comprises a second bonding wire coupled between a second lead of the lead frame interposer and the second bump structure.

13. The method of claim 12, further comprising: providing a third bonding wire between a third lead of the lead frame interposer and a third bump structure of the plurality of bump structures; providing a fourth bonding wire between a fourth lead of the lead frame interposer and a fourth bump structure of the plurality of bump structures; as well as Disposing a fifth bonding wire between the second lead and the third lead; The second section of the conductive layer is coupled between the third bump structure and the fourth bump structure.

14. The method of claim 13, wherein a serial combination of the first lead, the first bonding wire, the first bump structure, the first segment of the conductive layer, the second bump structure, the second bonding wire, the second lead, the fifth bonding wire, the third lead, the third bonding wire, the third bump structure, the second segment of the conductive layer, the fourth bump structure, the fourth bonding wire and the fourth lead constitutes a daisy chain loop to test the continuity of the first bump structure, the second bump structure, the third bump structure and the fourth bump structure. The method of claim 11 , wherein the first bump structure comprises forming a bump.

Images