Protection circuit and protection method

Abstract

The protection circuit comprises a voltage division circuit, a first comparator, a first switch, a second comparator and a logic gate delay circuit. The voltage division circuit generates a first divided voltage and a second divided voltage based on a power supply voltage. The first comparator is used for comparing the reference voltage and the first partial voltage to generate a first comparison result. The second comparator is used for comparing the reference voltage and the second partial voltage to generate a second comparison result. The logic gate delay circuit receives the first comparison result and the second comparison result. Wherein, according to a plurality of different states of the first comparison result and the second comparison result, the first switch is turned on to conduct a part of the current of the power supply voltage to the reference voltage end, or the first switch is turned off from on.

Description

Technical Field

[0001] The present invention relates to a protection circuit and a protection method, and in particular to a protection circuit and a protection method for protecting a resonance state of a power supply. Background Art

[0002] In the circuit, the parasitic elements will form a series resonant circuit in the circuit. In this case, when the power is plugged in and out quickly, a resonant state will be generated. This resonant state may cause the circuit components at the back end of the power supply voltage to be burned due to excessive harmonic voltage.

[0003] In the prior art, a snubber circuit composed of capacitors and resistors is often used, and through appropriate adjustment, the voltage waveform generated by resonance can be eliminated, thereby reducing the generation of surges. However, this approach requires not only additional external circuit components, but also different states of adjustment actions for different circuits, which increases the complexity of implementation. Summary of the invention

[0004] The invention provides a plurality of protection circuits and protection methods, which can reduce the risk of damage of components in the circuit due to the resonance phenomenon of the power supply.

[0005] A protection circuit according to an embodiment of the present invention includes a voltage divider circuit, a first comparator, a first switch, a second comparator, and a logic gate delay circuit. The voltage divider circuit generates a first voltage divider and a second voltage divider based on a power supply voltage. The first comparator is coupled to the voltage divider circuit to compare a reference voltage and the first voltage divider to generate a first comparison result. The first switch is coupled to the first comparator. The second comparator is coupled to the voltage divider circuit to compare the reference voltage and the second voltage divider to generate a second comparison result. The logic gate delay circuit is coupled to the first comparator and the second comparator to receive the first comparison result and the second comparison result. When the first state or the second state occurs, the first switch is turned on to direct part of the current of the power supply voltage to the reference voltage terminal. When the third state or the fourth state occurs, the first switch changes from on to off. The first state is: the first voltage divider is greater than the reference voltage; the second state is: the first voltage divider is less than or equal to the reference voltage, and the second voltage divider is greater than the reference voltage. The third state is: the first voltage divider is less than or equal to the reference voltage, and the second voltage divider is greater than the reference voltage and after a delay time of the logic gate delay circuit. The fourth state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is less than or equal to the reference voltage.

[0006] The protection method of the present invention includes: providing a reference voltage; generating a first divided voltage and a second divided voltage based on a power supply voltage; comparing the reference voltage with the first divided voltage and the second divided voltage respectively, and generating a first comparison result and a second comparison result respectively; when the first state or the second state occurs, directing part of the current of the power supply voltage to the reference voltage terminal; when the third state or the fourth state occurs, stopping directing part of the current to the reference voltage terminal. The first state is: the first divided voltage is greater than the reference voltage; the second state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage; the third state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage and after a delay time of the logic gate delay circuit; the fourth state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is less than or equal to the reference voltage.

[0007] A protection circuit according to another embodiment of the present invention includes a voltage divider circuit, a comparator, a switch, and a logic gate delay circuit. The voltage divider circuit generates a voltage divider based on a power supply voltage. The comparator is coupled to the voltage divider circuit, and the comparator is used to compare the voltage divider with a first reference voltage and a second reference voltage to generate a comparison result, wherein the first reference voltage is greater than the second reference voltage. The switch is coupled to the comparator. The logic gate delay circuit is coupled to the comparator to receive the comparison result. When the first state or the second state occurs, the switch is turned on to conduct part of the current of the power supply voltage to the reference voltage terminal. When the third state or the fourth state occurs, the switch changes from on to off. The first state is: the voltage divider is greater than the first reference voltage; the second state is: the voltage divider is less than or equal to the first reference voltage, and the voltage divider is greater than the second reference voltage; the third state is: the voltage divider is less than or equal to the first reference voltage, and the voltage divider is greater than the second reference voltage, and after a delay time of the logic gate delay circuit; the fourth state is: the voltage divider is less than or equal to the second reference voltage.

[0008] Based on the above, the protection circuit and protection method of the present invention divide the power supply voltage, and turn on or off the switch coupled between the power supply voltage and the reference voltage terminal by automatically detecting the change state of the generated divided voltage. When the switch is turned on, the rising trend of the power supply voltage can be suppressed by discharging current, thereby controlling the amplitude of the resonant state of the power supply voltage and reducing the risk of damage to the components in the circuit. In addition, the protection circuit of the present invention can be integrated into a chip to reduce the number of additional external circuit components, thereby reducing the device area. Furthermore, the protection circuit and protection method of the present invention are convenient for setting and adjusting the judgment mechanism through a programmable operation mode, which is conducive to application in various power supply fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A schematic diagram showing a protection circuit according to an embodiment of the present invention. Figure 2A schematic diagram showing the operation of a protection circuit according to an embodiment of the present invention. Figure 3 A flowchart showing a protection method according to an embodiment of the present invention is shown. Figure 4 A schematic diagram showing a protection circuit according to another embodiment of the present invention. Figure 5 Show the invention Figure 4 Operation flow chart of the embodiment. Figure 6 A flowchart showing a protection method according to another embodiment of the present invention. Figure 7 A schematic diagram showing a protection circuit according to another embodiment of the present invention. Figure 8 A schematic diagram showing a protection circuit according to another embodiment of the present invention.

Explanation of symbols

[0010] Please refer to Figure 1 , Figure 1 A schematic diagram of a protection circuit according to an embodiment of the present invention is shown. The protection circuit 100 includes a voltage divider circuit 110, comparators CM1, CM2, a switch S1, and a logic gate delay circuit 120. The voltage divider circuit 110 receives a power supply voltage VP, and is used to divide the power supply voltage VP to generate a first divided voltage VD1 and a second divided voltage VD2. In this embodiment, the voltage divider circuit 110 can divide the power supply voltage VP according to different voltage division ratios, and respectively generate different first divided voltages VD1 and second divided voltages VD2. Among them, the first divided voltage VD1 can be less than the second divided voltage VD2. In this embodiment, the power supply voltage VP is, for example, a DC power supply voltage.

[0011] The comparator CM1 is coupled to the voltage divider circuit 110. The negative input terminal of the comparator CM1 can receive the reference voltage VBG, and the positive input terminal of the comparator CM1 can receive the first divided voltage VD1 generated by the voltage divider circuit 110. The comparator CM1 is used to compare the voltage magnitudes of the reference voltage VBG and the first divided voltage VD1, and thereby generate a first comparison result CR1. The comparator CM1 is further coupled to the switch S1 and the logic gate delay circuit 120. The comparator CM1 can provide the generated first comparison result CR1 to the control terminal EM13 of the switch S1, and the enable terminal EN of the comparator CM1 can receive an indication signal FG from the logic gate delay circuit 120. The comparator CM1 can operate or stop operating according to the indication signal FG.

[0012] The switch S1 is coupled between the power supply voltage VP and the reference voltage terminal GND (for example, the ground terminal). The switch S1 can be constructed by a transistor M1 and is a transistor switch. The transistor M1 can be a transistor of any form, for example, a bipolar junction transistor (BJT) or a field-effect transistor (FET), but is not limited thereto. In the present embodiment, the transistor M1 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Further, the transistor M1 has a first terminal EM11, a second terminal EM12 and the aforementioned control terminal EM13, the first terminal EM11 receives the power supply voltage VP, the second terminal EM12 is coupled to the reference voltage terminal GND, the control terminal EM13 is coupled to the comparator CM1 to receive the comparison result CR1, and the transistor M1 is turned on or off according to the comparison result CR1. The first terminal EM11 may be a drain terminal, the second terminal EM12 may be a source terminal, and the control terminal EM13 may be a gate terminal. When the transistor M1 is turned on, the transistor M1 may provide a current discharge path between the power supply voltage VP and the reference voltage terminal GND, and conduct part of the current of the power supply voltage VP to the reference voltage terminal GND, thereby suppressing the rise of the power supply voltage VP. When the transistor M1 is turned off, the above-mentioned current discharge path is cut off.

[0013] Another comparator CM2 is coupled to the voltage divider circuit 110 and the logic gate delay circuit 120. The negative input terminal of the comparator CM2 can receive the reference voltage VBG, and the positive input terminal of the comparator CM2 can receive the second divided voltage VD2 generated by the voltage divider circuit 110. The comparator CM2 is used to compare the voltage magnitudes of the reference voltage VBG and the second divided voltage VD2, and thereby generate a second comparison result CR2.

[0014] On the other hand, the comparators CM1 and CM2 can transmit the comparison results CR1 and CR2 respectively generated to the logic gate delay circuit 120. The logic gate delay circuit 120 can start a timing action according to the comparison results CR1 and CR2 to time a delay time. The logic gate delay circuit 120 also generates an indication signal FG according to the delay time and the comparison results CR1 and CR2, and provides the indication signal FG to the enable terminal EN of the comparator CM1.

[0015] Please refer to the following Figure 2 , Figure 2A schematic diagram showing the operation of the protection circuit of an embodiment of the present invention. The protection circuit of the embodiment of the present invention performs a protection action by detecting the harmonic state of the power supply voltage VP. Among them, in the protection mechanism set by the protection circuit, the protection circuit can set thresholds V1 and V2 as detection benchmarks for the power supply voltage VP, wherein the threshold V1 is greater than the threshold V2. Among them, when the peak value of the power supply voltage VP is greater than the threshold V1, the protection circuit can determine that the power supply voltage VP is in an excessively high state. At this time, the protection circuit can turn on the switch S1 between the power supply voltage VP and the reference voltage terminal GND, and thereby conduct part of the current of the power supply voltage VP to the reference voltage terminal GND, so as to suppress the rising trend of the power supply voltage VP, so as to reduce the risk of components in the circuit being damaged by the excessively high harmonics of the power supply voltage VP.

[0016] Afterwards, when the peak value of the power supply voltage VP is less than the threshold value V1 and greater than the threshold value V2, the protection circuit can determine that the power supply voltage VP has dropped but is still in an excessively high state. At this time, the protection circuit can continuously turn on the switch S1 between the power supply voltage VP and the reference voltage terminal GND to allow the power supply voltage VP to continue to drop.

[0017] Next, when the peak value of the power supply voltage VP is less than the threshold value V2 (necessarily less than the threshold value V1), the protection circuit can determine that the power supply voltage VP is in a normal state. The protection circuit can turn off the switch S1 between the power supply voltage VP and the reference voltage terminal GND. Alternatively, in other embodiments, when it is detected that the peak value of the power supply voltage VP is less than the threshold value V1 and greater than the threshold value V2, the protection circuit can maintain the switch S1 between the power supply voltage VP and the reference voltage terminal GND on for a delay time, and after the delay time, the protection circuit can turn off the switch S1 between the power supply voltage VP and the reference voltage terminal GND. The significance of setting the delay time is that based on the property that the harmonic amplitude decreases with the passage of time, it can be predicted that when the peak value of the power supply voltage VP is less than the threshold value V1 and greater than the threshold value V2, the power supply voltage VP can be reduced to a normal state as long as a period of time passes. Therefore, the timing of turning off the switch S1 between the power supply voltage VP and the reference voltage terminal GND can be determined by setting the above delay time.

[0018] Please refer to the following synchronously Figure 1 as well as Figure 2 ,exist Figure 1In the embodiment of the present invention, the protection circuit 100 divides the power supply voltage VP, and determines the magnitude relationship between the peak value of the power supply voltage VP and the voltages V1 and V2 by comparing the first divided voltage VD1 and the second divided voltage VD2 with the reference voltage VBG. When the peak value of the power supply voltage VP is greater than the voltage V1, the first divided voltage VD1 and the second divided voltage VD2 are both greater than the reference voltage VBG; when the peak value of the power supply voltage VP is less than or equal to the voltage V1 and greater than the voltage V2, the second divided voltage VD2 is greater than the reference voltage VBG, and the first divided voltage VD1 is less than or equal to the reference voltage VBG; when the peak value of the power supply voltage VP is less than or equal to the voltage V2, the first divided voltage VD1 and the second divided voltage VD2 are both less than the reference voltage VBG.

[0019] According to the above description, the first, second, third and fourth states defined by the relationship between the power supply voltage VP, the voltages V1 and V2, and the relationship between the first divided voltage VD1, the second divided voltage VD2 and the reference voltage VBG, and the comparison results CR1 and CR2 corresponding to the comparators CM1 and CM2 can be shown in the following table:

[0020] Referring to the above table, if the first divided voltage VD1 is greater than the reference voltage VBG, the comparison result CR1 is a logic value of 1, and if the first divided voltage VD1 is not greater than the reference voltage VBG, the comparison result CR1 is a logic value of 0. If the second divided voltage VD2 is greater than the reference voltage VBG, the comparison result CR2 is a logic value of 1, and if the second divided voltage VD2 is not greater than the reference voltage VBG, the comparison result CR2 is a logic value of 0.

[0021] It is worth mentioning that in the above table, when it is detected that the first divided voltage VD1 is greater than the reference voltage VBG, it is the first state, and at this time, the second divided voltage VD2 should also be greater than the reference voltage VBG. When it is detected that the first divided voltage VD1 is less than or equal to the reference voltage VBG, and the second divided voltage VD2 is greater than the reference voltage VBG, the protection circuit 100 can enter the second state. In addition, in the second state, after a delay time Td measured by the logic gate delay circuit 120, based on the property that the harmonic amplitude decreases over time, it is determined that the protection circuit 100 can enter the third state. On the other hand, when the first divided voltage VD1 is less than or equal to the reference voltage VBG, and the second divided voltage VD2 is also less than or equal to the reference voltage VBG, the protection circuit 100 can enter the fourth state.

[0022] It is worth mentioning that when the protection circuit 100 is in the first state or the second state, the comparator CM1 can turn on the switch S1 through the comparison result CR1.

[0023] Incidentally, in the third state and the fourth state, the logic gate delay circuit 120 can generate an indication signal FG correspondingly, and stop the comparator CM1 by transmitting the indication signal FG to the enable terminal EN of the comparator CM1. In other words, when the protection circuit 100 is in the third and fourth states, the comparator CM1 can stop working according to the indication signal FG, and stop providing the comparison result CR1 that can turn on the switch S1, and turn off the switch S1. By stopping the comparator CM1, the power consumption of the protection circuit 100 can be reduced, and the requirements of energy saving and carbon reduction can be achieved.

[0024] To further explain, in order to ensure that the power voltage VP stably enters the normal mode, the delay time mentioned above can be set by engineers according to the actual operation status of the circuit without any specific restrictions.

[0025] In this embodiment, the logic gate delay circuit 120 may have a delay time counter and a logic circuit. The delay time counter is used to count the delay time Td, and the logic circuit is used to generate an indication signal FG according to the comparison results CR1 and CR2. The truth table used may refer to the following table, for example:

[0026] Referring to the above table, the input logic value A is based on judging whether the first divided voltage VD1 is greater than the reference voltage VBG, and the input logic value B is based on judging whether the second divided voltage VD2 is greater than the reference voltage VBG. In other words, the input logic value A and the input logic value B can be determined according to the comparison results CR1 and CR2. The input logic value C is based on judging whether the delay time Td has ended when the input logic value A is 0 (the first divided voltage VD1 is less than or equal to the reference voltage VBG) and the input logic value B is 1 (the second divided voltage VD2 is greater than the reference voltage VBG). The output logic value D corresponds to the output indicating whether the switch S1 is turned on, which is equivalent to the indication signal FG. For example, when the input logic value A is 0 and the input logic value B is 1, if the delay time Td has not ended, the input logic value C is 0, and the output logic value D is 1, indicating that the instruction given by the logic gate delay circuit 120 is to keep the switch S1 in the on state; and when the input logic value A is 0 and the input logic value B is 1, if the delay time Td has ended, the input logic value C is 1, and the output logic value D is 0, indicating that the instruction given by the logic gate delay circuit 120 is to keep the switch S1 in the off state.

[0027] In the present embodiment, the length of the delay time Td can be determined based on the resonant waveform generated by the power supply voltage VP. On the other hand, in a circuit architecture, there is a relationship Q=CV=IT, where Q is the charge Q, C is the capacitance value, V is the voltage of the reference point, I is the current of the charging current, and T is the length of the delay time Td. Further, the corresponding resonant waveform can be changed by adjusting the above parameters C, V, and I, and the length of the delay time Td can be calculated based on the parameters C, V, and I. In addition, in other embodiments, considering the nature that the harmonic amplitude decreases over time, the timing of turning off the switch S1 between the power supply voltage VP and the reference voltage terminal GND can also be determined by calculating whether the number of times the peak value of the resonant waveform exceeds the set threshold reaches a predetermined number.

[0028] Incidentally, the comparators CM1 and CM2 of the present embodiment can be implemented by using any comparison circuit known to those skilled in the art without any particular limitation.

[0029] Please refer to the following Figure 3 ,in Figure 3 A flow chart showing a protection method according to an embodiment of the present invention is used to provide a protection function for components in a circuit to reduce the risk of damage to the components in the circuit. In step S310, a reference voltage is provided. In step S320, a first divided voltage and a second divided voltage are generated based on the power supply voltage. In step S330, the reference voltage is compared with the first divided voltage and the second divided voltage, respectively, to generate a first comparison result and a second comparison result, respectively. In step S340, when the first state or the second state occurs, part of the current of the power supply voltage is directed to the reference voltage terminal to reduce the risk of damage to the components in the circuit due to the influence of excessive harmonics of the power supply voltage; in step S350, when the third state or the fourth state occurs, stop directing part of the current to the reference voltage terminal. Among them, the first state is: the first divided voltage is greater than the reference voltage; the second state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage; the third state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage and after a delay time timing by the logic gate delay circuit; the fourth state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is less than or equal to the reference voltage.

[0030] Please refer to Figure 4 , Figure 4A schematic diagram of a protection circuit according to another embodiment of the present invention is shown. The protection circuit 400 includes a voltage divider circuit 410, comparators CM1, CM2, switches S1, S2, a logic gate delay circuit 420, and a reference voltage circuit 430. In this embodiment, the voltage divider circuit 410 includes sub-voltage divider circuits 411 and 412. The sub-voltage divider circuit 411 includes a resistor string composed of resistors R1 and R2, and the sub-voltage divider circuit 411 is coupled between the power supply voltage VP and the switch S2. The sub-voltage divider circuit 412 includes a resistor string composed of resistors R3 and R4, and the sub-voltage divider circuit 412 is coupled between the power supply voltage VP and the reference voltage terminal GND.

[0031] In addition, the switch S2 is coupled between the sub-voltage divider circuit 411 and the reference voltage terminal GND. The switch S2 is constructed by a transistor M2. The transistor M2 can be any type of transistor, such as a bipolar junction transistor (BJT) or a field-effect transistor (FET), but is not limited thereto. In the present embodiment, the transistor M2 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). Further, the transistor M2 has a first terminal EM21, a second terminal EM22, and a control terminal EM23. The first terminal EM21 is coupled to the last series resistor of the sub-voltage divider circuit 411. In the present embodiment, the first terminal EM21 is, for example, coupled to the resistor R2. The second terminal EM22 is coupled to the reference voltage terminal GND. The control terminal EM23 is coupled to the logic gate delay circuit 420 and receives the indication signal FG generated by the logic gate delay circuit 420. The transistor M2 is turned on or off according to the indication signal FG. The first end EM21 is, for example, a drain end, the second end EM22 is, for example, a source end, and the control end EM23 is, for example, a gate end.

[0032] In this embodiment, the reference voltage VBG is provided by a reference voltage circuit 430. The reference voltage circuit 430 generates the reference voltage VBG according to the power voltage VP. The reference voltage circuit 430 may be a band gap voltage generating circuit.

[0033] The protection circuit 400 of this embodiment is Figure 1 The operating details of the protection circuit 100 of the embodiment are substantially the same and will not be repeated here. Figure 4 Example and Figure 1 The operational differences of the embodiments are as follows. Figure 4In the embodiment, in the third state or the fourth state, the logic gate delay circuit 420 can generate an indication signal FG to stop the comparator CM1 and turn off the switch S2. By turning off the switch S2, the DC path of the sub-voltage divider circuit 411 can be cut off, and unnecessary current loss can be further reduced.

[0034] For further information, please refer to the following Figure 4 as well as Figure 5 ,in Figure 5 Show the invention Figure 4 Operation flow chart of the embodiment. In step S510, when the comparators CM1 and CM2 detect that the first divided voltage VD1 and the second divided voltage VD2 are both greater than the reference voltage VBG, it means that the peak value of the power supply voltage VP is greater than the voltage V1 (refer to Figure 2 ). At this time, in step S520, the switch S1 can be turned on according to the comparison result CR1 generated by the comparator CM1. And through the turned-on switch S1, part of the current on the power voltage VP is directed to the reference voltage terminal GND (for example, the ground terminal), so that the power voltage VP gradually decreases. Then, in step S530, the peak value of the power voltage VP can gradually decrease to between the voltages V1 and V2 (refer to Figure 2 In step S540, after the peak value of the power supply voltage VP drops to a delay time Td between the voltages V1 and V2, or when the power supply voltage VP is less than or equal to the voltage V2, the switch S1 can be turned off, and step S550 is executed to enable the logic gate delay circuit 420 to generate an indication signal FG to turn off the comparator CM1 and cut off the switch S2 to achieve the purpose of power saving.

[0035] Since the harmonics of the power supply voltage VP may occur repeatedly, in step S560, when the protection circuit 400 detects that the power supply voltage VP is greater than the voltage V2 again, the protection circuit 400 may execute step S570 to turn on the switch S2 and the comparator CM1 again, and allow the comparator CM1 to turn on the switch S1 again. The protection circuit 400 returns to step S530 to perform a detection operation to determine whether the power supply voltage VP is between the voltages V1 and V2.

[0036] It is worth noting that in the embodiment of the present invention, when the switch S1 is turned off, the comparator CM2 can continue to operate and detect whether the second divided voltage VD2 is greater than the reference voltage VBG. Once the second divided voltage VD2 is greater than the reference voltage VBG again, it means that the power supply voltage VP is greater than the voltage V2 again. The logic gate delay circuit 420 can execute step S570 to reawaken the switch S2 and the comparator CM1 according to the comparison result CR2. The comparator CM1 can also re-turn on the switch S1 through the comparison result CR1 to suppress the rise of the harmonics of the power supply voltage VP.

[0037] Please refer to it synchronously Figure 4 as well as Figure 6 ,in Figure 6 A flowchart showing a protection method according to another embodiment of the present invention can be used with Figure 4 The protection circuit 400 of the embodiment is operated. In step S610, the circuit performs a power-on action. Then, in step S620, the reference voltage circuit 430 in the protection circuit 400 receives the power supply voltage VP, and generates a reference voltage VBG according to the power supply voltage VP. In step S630, the sub-voltage divider circuits 411 and 412 receive the power supply voltage VP, and divide the power supply voltage VP to generate a first divided voltage VD1 and a second divided voltage VD2. And, in step S640, the comparator CM1 can compare the first divided voltage VD1 with the reference voltage VBG, and execute step S641 when the first divided voltage VD1 is greater than the reference voltage VBG; and execute step S650 when the first divided voltage VD1 is not greater than the reference voltage VBG.

[0038] In step S640, when the comparator CM1 determines that the first divided voltage VD1 is greater than the reference voltage VBG, it indicates that the harmonics of the power supply voltage VP are too high, and step S641 is performed. In step S641, the switch S1 can be turned on according to the comparison result CR1 of the comparator CM1, and a part of the current of the power supply voltage VP is conducted to the reference voltage terminal GND (for example, the ground terminal), so as to reduce the risk of damage to the components in the circuit due to the influence of the high harmonics of the power supply voltage.

[0039] In step S650, the comparator CM2 compares the second divided voltage VD2 and the reference voltage VBG. When the second divided voltage VD2 is greater than the reference voltage VBG, it indicates that the harmonics of the power supply voltage VP are still too high, and step S660 can be executed. Conversely, if the second divided voltage VD2 is not greater than the reference voltage VBG, it indicates that the power supply voltage VP is in a normal state, and step S651 can be executed.

[0040] In step S660, the logic gate delay circuit 420 performs a timing operation for the delay time Td. At the same time, the power supply voltage VP continues to discharge through the switch S1 (referring to the above-mentioned conduction of part of the current of the power supply voltage VP to the reference voltage terminal GND). Next, in step S661, when it is determined that the condition that the second divided voltage VD2 is less than or equal to the reference voltage VBG is met, or after the condition that the delay time Td is met, step S651 can be executed. Conversely, if neither of the above two conditions is met, step S662 is executed.

[0041] In step S662, the process continues to wait for the condition that the second divided voltage VD2 is less than or equal to the reference voltage VBG to be met, or the condition that the delay time Td is over to be met, and after one of the conditions is met, step S651 is executed.

[0042] In step S651, the logic gate delay circuit 420 sends the indication signal FG to the switch S2 and the comparator CM1, and in step S652, the switch S2 is turned off and the comparator CM1 is turned off. In step S653, the operation of the sub-voltage divider circuit 312 and the comparator CM2 is kept.

[0043] In step S670, when the comparator CM2 determines that the second divided voltage VD2 is greater than the reference voltage VBG again, step S672 is executed. If the comparator CM2 determines that the second divided voltage VD2 is greater than the reference voltage VBG does not occur again, the status quo is maintained (step S671).

[0044] In step S672 , the logic gate delay circuit 420 sends the indication signal FG to the switch S2 and the comparator CM1 , and turns on the switch S2 and restarts the comparator CM1 . Then, step S640 is re-executed to continue the subsequent step flow.

[0045] Please refer to the following Figure 7 , Figure 7 A schematic diagram showing a protection circuit according to another embodiment of the present invention. The protection circuit 700 includes a voltage divider circuit 710, a logic gate delay circuit 720, a reference voltage circuit 730, comparators CM1, CM2, switches S1, S3 and S4, and an inverter IV1. In the present embodiment, the reference voltage circuit 730 generates a reference voltage VBG based on a power supply voltage VP. The voltage divider circuit 710 divides the power supply voltage VP and generates a first divided voltage VD1 and a second divided voltage VD2, wherein the first divided voltage VD1 is greater than the second divided voltage VD2. The voltage divider circuit 710 is formed by resistors R71 to R73 connected in series in sequence, wherein the node where the resistors R71 and R72 are coupled generates the first divided voltage VD1, and the node where the resistors R72 and R73 are coupled generates the second divided voltage VD2.

[0046] The negative input terminals of the comparators CM1 and CM2 receive the reference voltage VBG in common. The positive input terminals of the comparators CM1 and CM2 receive the first divided voltage VD1 and the second divided voltage VD2 respectively. The comparators CM1 and CM2 generate comparison results CR1 and CR2 respectively, wherein the comparison result CR1 is provided to the control terminal of the switch S1 and an input terminal of the logic gate delay circuit 720, and the comparison result CR2 is provided to the other input terminal of the logic gate delay circuit 720.

[0047] The output terminal of the logic gate delay circuit 720 generates the indication signal FG. The inverter IV1 is coupled to the output terminal of the logic gate delay circuit 720 to receive the indication signal FG and generate an inverted indication signal FGb.

[0048] The operation of the protection circuit 700 of the present embodiment is roughly similar to the operation of the protection circuits 100 and 300 described above, and will not be described in detail here. Unlike the above embodiments, the protection circuit 700 further has switches S3 and S4. The switch S3 is coupled between the voltage divider circuit 710 and the positive input terminal of the comparator CM1, and the switch S4 is coupled between the reference voltage terminal GND and the positive input terminal of the comparator CM1. The switches S3 and S4 are constructed by transistors M3 and M4, respectively, for example. The transistors M3 and M4 can be any form of transistors, such as field effect transistors (Bipolar Junction Transistor, BJT) or bipolar transistors (Field-Effect Transistor, FET), but are not limited thereto. In the present embodiment, the transistors M3 and M4 are, for example, metal-oxide-semiconductor field-effect transistors (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The transistor M3 has a first terminal EM31, a second terminal EM32 and a control terminal EM33. The first terminal EM31 is coupled to a node where resistors R71 and R72 of the voltage divider circuit 710 are coupled to receive a first divided voltage VD1. The second terminal EM22 is coupled to a positive input terminal of the comparator CM1 to provide the first divided voltage VD1 to the comparator CM1. The control terminal EM33 receives an inverted indication signal FGb. The transistor M4 has a first terminal EM41, a second terminal EM42 and a control terminal EM43. The first terminal EM41 is coupled between the transistor M3 and the comparator CM1. The second terminal EM22 is coupled to a reference voltage terminal GND. The control terminal EM33 receives an indication signal FG. The first terminals EM31 and EM41 are, for example, drain terminals, the second terminals EM32 and EM42 are, for example, source terminals, and the control terminals EM33 and EM43 are, for example, gate terminals. The switches S3 and S4 are controlled by the indication signal FG and the inverted indication signal FGb, respectively. Among them, when the comparator CM1 operates normally according to the indication signal FG, the switch S3 is turned on and the switch S4 is turned off. At this time, the voltage divider circuit 710 can normally output the first divided voltage VD1 to the positive input terminal of the comparator CM1, and the operation setting of the switch S4 being turned off at this time is to prevent the first divided voltage VD1 from being led to the reference voltage terminal GND. Conversely, when the comparator CM1 stops operating according to the indication signal FG, the switch S3 is turned off and the switch S4 is turned on. At this time, the positive input terminal of the comparator CM1 receives the voltage on the reference voltage terminal GND (for example, the ground voltage) because the switch S4 is turned on, so that the switch S1 can be automatically turned off.

[0049] Please refer to the following Figure 8 , Figure 8 A schematic diagram showing a protection circuit of another embodiment of the present invention. The protection circuit 800 includes a voltage divider circuit 810, a logic gate delay circuit 820, a comparator CM1, and a switch S1. In the present embodiment, the comparator CM1 has thresholds V1 and V2, and receives a divided voltage VD generated by the voltage divider circuit 810, wherein the threshold V1 is greater than the threshold V2. In the present embodiment, the voltage divider circuit 810 includes, for example, a plurality of resistors connected in series. The voltage divider circuit 810 receives a power supply voltage VP, and divides the power supply voltage VP to generate a divided voltage VD. The comparator CM1 can compare the divided voltage VD with the thresholds V1 and V2, and thereby determine the state of the power supply voltage VP. When the divided voltage VD is greater than the threshold V1, it is in the first state; when the divided voltage VD is less than or equal to the threshold V1 and greater than the threshold V2, it is in the second state; when the divided voltage VD is less than or equal to the threshold V1 and greater than the threshold V2, and after a delay time of the logic gate delay circuit 820, it is in the third state; when the divided voltage VD is less than or equal to the threshold V2, it is in the fourth state. The operation of the logic gate delay circuit 820 is similar to the logic gate delay circuit 120 or the logic gate delay circuit 420 of the aforementioned embodiment.

[0050] In the first state and the second state, the switch S1 can be turned on according to the comparison result CR1 provided by the comparator CM1, so that part of the current of the power supply voltage VP is directed to the reference voltage terminal GND (for example, the ground terminal). In the third state and the fourth state, the logic gate delay circuit 820 can provide an indication signal FG to stop the comparator CM1 from working. At the same time, the comparator CM1 stops providing the comparison result CR1 that can turn on the switch S1, and the switch S1 is turned off.

[0051] In this embodiment, the thresholds V1 and V2 can also be provided by using a bandgap voltage generating circuit.

[0052] In summary, the protection circuit and protection method of the present invention automatically detect multiple possible states of the harmonics of the power supply voltage by dividing the power supply voltage and comparing the divided voltage generated by the voltage dividing circuit with the reference voltage. The protection circuit of the present invention can determine whether to turn on the switch coupled to the power supply voltage and the reference ground terminal according to the different states of the power supply voltage harmonics. By turning on the above-mentioned switch to vent part of the current of the power supply voltage, the rising state of the harmonics of the power supply voltage can be suppressed, thereby reducing the risk of damage to the components in the circuit. In addition, the protection circuit of the present invention can be integrated into a chip to reduce the number of additional external circuit elements, thereby reducing the device area. Furthermore, the protection circuit and protection method of the present invention facilitate the setting and adjustment of the judgment mechanism through a programmable operation mode, which is conducive to application in various power supply fields.

Claims

1. A protection circuit, characterized in that: include: A voltage divider circuit generates a first divided voltage and a second divided voltage based on a power supply voltage; a first comparator, coupled to the voltage divider circuit, for comparing a reference voltage and the first divided voltage to generate a first comparison result; a first switch coupled to the first comparator; a second comparator, coupled to the voltage divider circuit, for comparing the reference voltage and the second divided voltage to generate a second comparison result; as well as a logic gate delay circuit, coupled to the first comparator and the second comparator, receiving the first comparison result and the second comparison result, When a first state or a second state occurs, the first switch is turned on to conduct part of the current of the power supply voltage to a reference voltage terminal, wherein The first state is: the first divided voltage is greater than the reference voltage; The second state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage; When a third state or a fourth state occurs, the first switch changes from on to off, wherein The third state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage and after a delay time of the logic gate delay circuit; The fourth state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is less than or equal to the reference voltage.

2. The protection circuit according to claim 1, characterized in that: When the third state or the fourth state occurs, the first comparator stops operating.

3. The protection circuit according to claim 2, characterized in that: When the third state or the fourth state occurs, the second comparator keeps operating.

4. The protection circuit according to claim 3, characterized in that: When the first comparator stops operating and the second comparator detects that the second divided voltage is greater than the reference voltage, the first comparator is activated again to change the first switch from being cut off to being turned on.

5. The protection circuit according to claim 1, characterized in that: The voltage divider circuit includes: a first sub-voltage dividing circuit, coupled to the first comparator, for generating the first divided voltage; and A second sub-voltage-dividing circuit is coupled to the second comparator and is used to generate the second divided voltage, wherein the first divided voltage is smaller than the second divided voltage.

6. The protection circuit according to claim 5, characterized in that: Also includes: A second switch is coupled between the reference voltage terminal and the first sub-voltage divider circuit and is coupled to the logic gate delay circuit. When the third state or the fourth state occurs, the second switch changes from being on to being off.

7. The protection circuit according to claim 6, characterized in that: When the first comparator stops operating and the second comparator detects that the second divided voltage is greater than the reference voltage, the second switch changes from being cut off to being turned on.

8. The protection circuit according to claim 5, characterized in that: The first voltage-dividing sub-circuit includes a first resistor and a second resistor connected in series, and the second voltage-dividing sub-circuit includes a third resistor and a fourth resistor connected in series.

9. The protection circuit according to claim 1, characterized in that: The voltage divider circuit includes a fifth resistor, a sixth resistor and a seventh resistor connected in series, a first node coupled between the fifth resistor and the sixth resistor generates the first divided voltage, and a second node coupled between the sixth resistor and the seventh resistor generates the second divided voltage.

10. The protection circuit according to claim 9, characterized in that: Also includes a third switch and a fourth switch, The third switch is coupled between the first node and the first comparator, the first end of the fourth switch is coupled between the third switch and the first comparator, and the second end of the fourth switch is coupled between the voltage divider circuit and the reference voltage end.

11. The protection circuit according to claim 10, characterized in that: in, When the first state or the second state occurs, the third switch is turned on, and when the third state or the fourth state occurs, the third switch changes from being turned on to being turned off.

12. The protection circuit according to claim 10, characterized in that: in, When the first state or the second state occurs, the fourth switch is turned off, and when the third state or the fourth state occurs, the third switch changes from being turned off to being turned on.

13. The protection circuit according to claim 1, characterized in that: The delay time is determined based on the resonant waveform generated by the power supply voltage.

14. The protection circuit according to claim 1, characterized in that: When the power supply voltage is greater than a first threshold, the first divided voltage is greater than the reference voltage; when the power supply voltage is less than or equal to the first threshold and greater than a second threshold, the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage; when the power supply voltage is less than or equal to the second threshold, the second divided voltage is less than or equal to the reference voltage, wherein the first threshold is greater than the second threshold.

15. The protection circuit according to claim 1, characterized in that: The invention also comprises a reference voltage generating circuit for receiving the power supply voltage to generate the reference voltage.

16. A protection method, characterized in that: include: Providing a reference voltage; Generating a first divided voltage and a second divided voltage based on a power supply voltage; Comparing the reference voltage with the first divided voltage and the second divided voltage respectively, and generating a first comparison result and a second comparison result respectively; When a first state or a second state occurs, part of the current of the power supply voltage is directed to a reference voltage terminal, wherein The first state is: the first divided voltage is greater than the reference voltage; The second state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage; and When a third state or a fourth state occurs, part of the current is stopped from being directed to the reference voltage terminal, wherein The third state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is greater than the reference voltage and after a delay time of the logic gate delay circuit; The fourth state is: the first divided voltage is less than or equal to the reference voltage, and the second divided voltage is less than or equal to the reference voltage.

17. The protection method according to claim 16, characterized in that: Also includes: When the third state or the fourth state occurs, the comparison between the reference voltage and the first divided voltage is stopped, and the comparison between the reference voltage and the second divided voltage is continued.

18. The protection method according to claim 17, characterized in that: When the comparison between the reference voltage and the first divided voltage stops and the second divided voltage is again greater than the reference voltage, part of the current is directed to the reference voltage terminal again.

19. The protection method according to claim 18, characterized in that: When the third state or the fourth state occurs, the voltage value of the first divided voltage is equal to the voltage value of the power supply voltage.

20. A protection circuit, characterized in that: include: A voltage divider circuit generates a divided voltage based on a power supply voltage; a comparator coupled to the voltage divider circuit, for comparing the divided voltage with a first reference voltage and a second reference voltage to generate a comparison result, wherein the first reference voltage is greater than the second reference voltage; a switch coupled to the comparator; as well as a logic gate delay circuit, coupled to the comparator, and receiving the comparison result; When a first state or a second state occurs, the switch is turned on to conduct part of the current of the power supply voltage to a reference voltage terminal, wherein The first state is: the divided voltage is greater than the first reference voltage; The second state is: the divided voltage is less than or equal to the first reference voltage, and the divided voltage is greater than the second reference voltage; When a third state or a fourth state occurs, the switch changes from on to off, wherein, The third state is: the divided voltage is less than or equal to the first reference voltage, and the divided voltage is greater than the second reference voltage, and after a delay time of the logic gate delay circuit; The fourth state is: the divided voltage is less than or equal to the second reference voltage.

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