Amplifier device with multiple bias networks

Abstract

An amplifier device includes a first input terminal, a second input terminal, a first transistor having a first control electrode radio frequency (RF) coupled to the first input terminal and DC coupled to a first bias network electrically coupled to the first control electrode, and first and second current carrying electrodes, wherein the first bias network is configured to apply a first direct current (DC) bias to and RF isolated from the first control electrode. The amplifier device further includes a second transistor including a second control electrode RF coupled to the second input; and a second bias network electrically coupled to the second transistor, where the second bias network is configured to apply a second DC bias to and RF isolated from the second transistor.

Description

Technical Field

[0001] Embodiments of the subject matter described herein relate generally to RF amplifiers. Background Art

[0002] High efficiency radio frequency (RF) amplifiers are increasingly used in communication applications. These high efficiency RF amplifiers are needed because lower system size and cost are achieved due to less cooling capacity required, and because the energy required to power these communication applications is reduced. Conventional high efficiency amplifiers (e.g., tuned class AB) operate at a constant supply voltage. In addition, conventional high efficiency RF amplifiers operate under back-off power conditions. This back-off power condition reduces amplifier efficiency.

[0003] Conventional high efficiency RF amplifiers may experience periods of low traffic conditions. This generally means that the efficiency of the amplifier decreases as the amplifier back-off amount increases. This decreased efficiency results in excessive energy usage. Therefore, there is a need for an amplifier device with improved efficiency. Summary of the invention

[0004] According to an embodiment, in one aspect, an amplifier device may include: a first amplifier, the first amplifier being electrically coupled to a first input terminal and a first output terminal, wherein the first amplifier may include a first transistor, the first transistor including a first control electrode, a first current carrying electrode, and a second current carrying electrode, configured to support current flow between the first current carrying electrode and the second current carrying electrode, wherein the first control electrode is configured to control current flow between the first current carrying electrode and the second current carrying electrode, wherein the first control electrode may be radio frequency (RF) coupled to the first input terminal, and wherein the first current carrying electrode may be electrically coupled to the first output terminal. In an embodiment, a first bias network may be electrically coupled to the first control electrode, wherein the first bias network may be configured to apply a first direct current (DC) bias to the first control electrode and may be RF isolated from the first control electrode. In an embodiment, the amplifier arrangement may include a second transistor, the second transistor including a second control electrode, a third current carrying electrode and a fourth current carrying electrode, configured to support current flow between the third current carrying electrode and the fourth current carrying electrode, wherein the second control electrode is configured to control current flow between the third current carrying electrode and the fourth current carrying electrode, wherein the second control electrode may be RF coupled to the first input terminal, wherein the third current carrying electrode may be electrically coupled to the first output terminal. According to an embodiment, a second bias network may be electrically coupled to the second control electrode, wherein the second bias network may be configured to apply a second DC bias to the second control electrode and may be RF isolated from the second control electrode.

[0005] According to an embodiment, the amplifier arrangement may further comprise a second amplifier, the second amplifier being electrically coupled to the second input and the second output, wherein the second amplifier may comprise a third transistor, the third transistor comprising a third control electrode, a fifth current carrying electrode and a sixth current carrying electrode, being configured to support a current flow between the fifth current carrying electrode and the sixth current carrying electrode, wherein the third control electrode is configured to control a current flow between the fifth current carrying electrode and the sixth current carrying electrode, wherein the third control electrode may be RF coupled to the second input, and wherein the fifth current carrying electrode may be electrically coupled to the second output. According to an embodiment, a third bias network may be electrically coupled to the third control electrode, wherein the third bias network may be configured to apply a third DC bias to the third control electrode and may be RF isolated from the third control electrode. According to an embodiment, a fourth transistor, comprising a fourth control electrode, a seventh current carrying electrode and an eighth current carrying electrode, being configured to support a current flow between the seventh current carrying electrode and the eighth current carrying electrode, wherein the fourth control electrode is configured to control a current flow between the seventh current carrying electrode and the eighth current carrying electrode, wherein the fourth control electrode may be radio frequency (RF) coupled to the second input, and wherein the seventh current carrying electrode may be electrically coupled to the second output. In an embodiment, a fourth bias network may be electrically coupled to the fourth control electrode, wherein the fourth bias network may be configured to apply a fourth DC bias to the second control electrode and may be RF isolated from the fourth control electrode.

[0006] In an embodiment, the amplifier device may further include a transmission line having a phase shift and may be configured to electrically couple the first output terminal and the second output terminal.The impedance transformer may be electrically coupled to a summing node at an element selected from the group consisting of the first output terminal and the second output terminal.

[0007] In an embodiment, the amplifier device may include a splitter device having a splitter input and a first splitter output and a second splitter output, and is configured to divide a signal delivered to the splitter input between the first splitter output and the second splitter output using a splitter phase difference between the first splitter output and the second splitter output, wherein the difference between the phase difference and the phase shift of the transmission line is less than 20%, wherein the first input terminal is electrically coupled to the first splitter output, and the second input terminal is electrically coupled to the second splitter output.

[0008] In an embodiment, the first amplifier may be configured as a carrier amplifier and the second amplifier may be configured as a peaking amplifier.

[0009] In an embodiment, according to an embodiment, the first amplifier may be configured to operate in a first state and in a second state. In an embodiment, according to an embodiment, when in the first state, the first transistor and the second transistor may be configured to operate under the following conditions: a first bias is applied to the first bias network, a second bias is applied to the second bias network, wherein when the first transistor is operated at a saturated output power, the first bias and the second bias allow an RF current of at least 50% of the maximum current of the second transistor to flow from the third current-carrying electrode of the second transistor to the fourth current-carrying element; and a third bias is applied to the first current-carrying electrode and the third current-carrying electrode. According to an embodiment, when operating in the second state, the first transistor and the second transistor may be configured to operate under the following conditions: a first bias is applied to the first bias network, a fourth bias is applied to the second bias network, such that when the first transistor is operated at a saturated output power, the fourth bias allows an RF current of less than 10% of the maximum current of the second transistor to flow through the second transistor; and a fifth bias is applied to the first current-carrying electrode and the third current-carrying electrode.

[0010] In an embodiment, the first transistor may be configured as a field effect transistor, wherein the first control terminal may be configured as a gate electrode, wherein the first current carrying element may be configured as a drain electrode, and wherein the second current carrying element may be configured as a source electrode.

[0011] Embodiments may include a first coupling element having a first end and a second end, wherein the second end may be electrically coupled to the first control electrode.

[0012] Embodiments may include a second coupling element having a third end and a fourth end, wherein the fourth end may be electrically coupled to the second control electrode, and wherein the first end may be electrically coupled to the third end.

[0013] A driver amplifier including a transistor may be electrically coupled to the first end of the first coupling element and the third end of the second coupling element.

[0014] Embodiments may include a first input harmonic matching network configured to provide harmonic termination for a first transistor at a harmonic frequency, and may also include a second harmonic matching network configured to provide harmonic termination for a second transistor at a harmonic frequency.

[0015] In another aspect, an embodiment may include a power amplifier device comprising a first amplifier electrically coupled to a first input terminal and a first output terminal. According to an embodiment, the first amplifier may include a first field effect transistor, the first field effect transistor including a first gate electrode, a first drain electrode, and a first source electrode, configured to support current flow between the first drain electrode and the first source electrode, wherein the first gate electrode may be configured to control current flow between the first drain electrode and the first source electrode, wherein the gate electrode may be radio frequency (RF) coupled to the first input terminal, and wherein the first drain electrode may be electrically coupled to the first output terminal. In an embodiment, a first bias network may be electrically coupled to the first gate electrode, wherein the first bias network may be configured to apply a first direct current (DC) bias to the first gate electrode and may be RF isolated from the first gate electrode. In an embodiment, the second field effect transistor may include a second gate electrode, a second drain electrode, and a second source electrode, configured to support current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be configured to control current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be RF coupled to the first input terminal, wherein the second drain electrode may be electrically coupled to the first output terminal. According to an embodiment, a second bias network may be electrically coupled to the second gate electrode, wherein the second bias network may be configured to apply a second DC bias to the second gate electrode and may be RF isolated from the second gate electrode.

[0016] In an embodiment, a first capacitor having a first terminal and a second terminal may be electrically coupled to the first gate electrode via its second terminal. According to an embodiment, a second capacitor having a third terminal and a fourth terminal, wherein the fourth terminal may be electrically coupled to the second gate electrode, and wherein the first terminal may be electrically coupled to the third terminal. In an embodiment, a first input matching network may be electrically coupled to the first gate electrode and configured to provide impedance matching for the first field effect transistor at a fundamental frequency, and a second input matching network may be electrically coupled to the second gate electrode and configured to provide impedance matching for the second transistor at a fundamental frequency.

[0017] According to an embodiment, the second amplifier may be electrically coupled to the second input and the second output. In an embodiment, the second amplifier may include a third field effect transistor, the third field effect transistor including a third gate electrode, a third drain electrode, and a third source electrode, configured to support current flow between the third drain electrode and the third source electrode, wherein the third gate electrode is configured to control current flow between the third drain electrode and the third source electrode, wherein the third gate electrode may be RF coupled to the second input, and wherein the third drain electrode may be electrically coupled to the second output. A third bias network may be electrically coupled to the third gate electrode, wherein the third bias network may be configured to apply a third DC bias to the third gate electrode and may be RF isolated from the third gate electrode. An embodiment may include a fourth field effect transistor, the fourth field effect transistor including a fourth gate electrode, a fourth drain electrode, and a fourth source electrode, configured to support current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode is configured to control current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode may be radio frequency (RF) coupled to the second input, and wherein the fourth drain electrode may be electrically coupled to the second output. According to an embodiment, a fourth bias network may be electrically coupled to a fourth gate electrode, wherein the fourth bias network may be configured to apply a fourth DC bias to the fourth gate electrode and may be RF isolated from the fourth gate electrode. In an embodiment, a transmission line having a phase shift may be configured to electrically couple a first output terminal and a second output terminal. According to an embodiment, an impedance transformer may be electrically coupled to a summing node at one of the first output terminal and the second output terminal. In an embodiment, a splitter device has a splitter input and a first splitter output and a second splitter output, and is configured to divide a signal delivered to the splitter input between the first splitter output and the second splitter output using a splitter phase difference between the first splitter output and the second splitter output, wherein the difference between the splitter phase difference and the phase shift of the transmission line may be less than 20%, and the splitter device may be electrically coupled to the first input terminal at the first splitter output, and the second input terminal may be electrically coupled to the second splitter output. According to an embodiment, in a Doherty amplifier configuration, the first amplifier may be configured as a carrier amplifier, and the second amplifier may be configured as a peak amplifier.

[0018] Embodiments may include a first input harmonic matching network configured to provide harmonic termination for a first transistor at a harmonic frequency and a second harmonic matching network configured to provide harmonic termination for a second transistor at a harmonic frequency.

[0019] According to an embodiment, a driver amplifier including a transistor may be electrically coupled to the first end of the first capacitor and the third end of the second capacitor.

[0020] In another aspect, an embodiment may include a device comprising a base substrate, a first amplifier die coupled to the base substrate and electrically coupled to a first input and a first output. In an embodiment, the first amplifier die may include a first field effect transistor, the first field effect transistor may include a first gate electrode, a first drain electrode, and a first source electrode, configured to support current flow between the first drain electrode and the first source electrode, wherein the first gate electrode is configured to control current flow between the first drain electrode and the first source electrode, wherein the gate electrode may be radio frequency (RF) coupled to the first input, and wherein the first drain electrode is electrically coupled to the first output. According to an embodiment, a first bias network may be electrically coupled to the first gate electrode, wherein the first bias network may be configured to apply a first direct current (DC) bias to the first gate electrode and may be RF isolated from the first gate electrode. In an embodiment, the second field effect transistor may include a second gate electrode, a second drain electrode, and a second source electrode, configured to support current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be configured to control current flow between the second drain electrode and the second source electrode, wherein the second gate electrode may be RF coupled to the first input terminal, wherein the second drain electrode may be electrically coupled to the first output terminal. According to an embodiment, a second bias network may be electrically coupled to the second gate electrode, wherein the second bias network may be configured to apply a second DC bias to the second gate electrode and may be RF isolated from the second gate electrode. An embodiment may include a first capacitor having a first end and a second end, wherein the second end may be electrically coupled to the first gate electrode. An embodiment may include a second capacitor element having a third end and a fourth end, and wherein the fourth end may be electrically coupled to the second gate electrode, and wherein the first end may be electrically coupled to the third end. According to an embodiment, a first input matching network may be electrically coupled to the first gate electrode and configured to provide impedance matching for the first field effect transistor at a fundamental frequency, and a second input matching network may be configured to provide impedance matching for the second field effect transistor at a fundamental frequency.

[0021] In an embodiment, the first field effect transistor and the second field effect transistor may be integrally formed on a first substrate, and wherein the first capacitor and the second capacitor may be formed on the first substrate.

[0022] In an embodiment, the first field effect transistor and the second field effect transistor may be formed on a first substrate, and the first capacitor and the second capacitor may be formed on a second substrate.

[0023] Embodiments may include a driver amplifier including a transistor formed on a second substrate, wherein the driver amplifier may be electrically coupled to a first end of the first capacitor and may be coupled to a third end of the second capacitor. According to embodiments, a first bias network may be formed on the second substrate, and a second bias network may be formed on the second substrate.

[0024] In an embodiment, a second amplifier may be coupled to a base substrate and may be electrically coupled to a second input and a second output, wherein the second amplifier may include a third transistor, the third transistor including a third gate electrode, a third drain electrode, and a third source electrode, configured to support current flow between the third drain electrode and the third source electrode. According to an embodiment, the third gate electrode is configured to control current flow between the third drain electrode and the third source electrode, wherein the third control electrode is RF coupled to the second input, and wherein the third drain electrode may be electrically coupled to the second output. In an embodiment, a third bias network may be electrically coupled to the third gate electrode, wherein the third bias network may be configured to apply a third DC bias to the third gate electrode and may be RF isolated from the third gate electrode. According to an embodiment, a fourth transistor may include a fourth gate electrode, a fourth drain electrode, and a fourth source electrode, configured to support current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode may be configured to control current flow between the fourth drain electrode and the fourth source electrode, wherein the fourth gate electrode may be radio frequency (RF) coupled to the second input, and wherein the fourth drain electrode may be electrically coupled to the second output. In an embodiment, a fourth bias network may be electrically coupled to a fourth gate electrode, wherein the fourth bias network may be configured to apply a fourth DC bias to the fourth gate electrode and may be RF isolated from the fourth gate electrode. According to an embodiment, a transmission line formed above a base substrate has a phase shift and may be configured to electrically couple a first output terminal and a second output terminal. According to an embodiment, an impedance transformer may be formed above a base substrate and may be electrically coupled to a summing node at one of the first output terminal and the second output terminal. In an embodiment, a splitter device may be formed above a base substrate, having a splitter input and a first splitter output and a second splitter output, and configured to divide a signal delivered to the splitter input between the first splitter output and the second splitter output using a splitter phase difference between the first splitter output and the second splitter output, wherein the difference between the phase difference and the phase shift of the transmission line is less than 20%, wherein the first input terminal may be electrically coupled to the first splitter output, and the second input terminal may be electrically coupled to the second splitter output. According to an embodiment, in a Doherty amplifier configuration, the first amplifier may be configured as a carrier amplifier, and the second amplifier may be configured as a peak amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] A more complete understanding of the subject matter may be gained by referring to the detailed description and claims when considered in conjunction with the following drawings, wherein like reference numerals refer to similar elements throughout the various figures.

[0026] Figure 1A and 1B is a simplified schematic diagram of an amplifier arrangement according to an example embodiment;

[0027] Figure 2 It is a depiction Figure 1A and 1B A graphical representation of the operation of the amplifier device;

[0028] Figure 3 is a schematic diagram of an amplifier device according to an embodiment;

[0029] Figure 4 is a schematic diagram of an amplifier device according to an embodiment;

[0030] Figure 5A is a top plan view of a device according to an embodiment, and Figure 5B According to the embodiment along Figure 5A A cross-sectional side view of the cutting line 5B-5B;

[0031] Fig. 6A is a top plan view of an amplifier device according to an embodiment, and Figure 6B is an isometric view of an amplifier device according to an embodiment;

[0032] Fig. 7A is a top plan view of an amplifier device according to an embodiment, and Figure 7B is an isometric view of an amplifier device according to an embodiment;

[0033] Fig. 8A , 8B , 8C and 8D are graphical representations depicting the operation of the amplifier device of FIG. 5 ; and

[0034] Fig. 9A , 9B , 9C, 9D, 9E and 9F are graphical representations depicting the operation of the amplifier arrangement of FIG. 5 as compared to a conventional amplifier arrangement. DETAILED DESCRIPTION

[0035] The amplifier device embodiments provided herein can overcome some or all of the aforementioned problems using high efficiency amplifiers. Specifically, the amplifier device embodiments described herein are configured to allow transistors within the amplifier device to be biased with a deep Class C bias to effectively reduce the overall size of active transistors within the amplifier. Such biasing of active transistors to reduce the effective size can be useful for improving the efficiency of the amplifier device during low power operating times (e.g., during low traffic periods in a radio network).

[0036] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the words "exemplary" and "example" mean "serving as an example, instance, or illustration". Any embodiment described herein as exemplary or example is not necessarily to be construed as being preferred or advantageous over other embodiments. In addition, it is not intended to be bound by any explicit or implicit theory presented in the foregoing technical field, background technology, or the following detailed description.

[0037] Figure 1A and 1B 1, a simplified schematic diagram of an amplifier device 100 in a high power state 161 (i.e., a "first state") and a low power state 162 (i.e., a "second state"), respectively, according to an example embodiment. In an embodiment, the amplifier device 100 may include a first amplifier 101 electrically coupled to a first input terminal 102 and a first output terminal 127.

[0038] According to an embodiment, the first amplifier 101 may include a first field effect transistor 110 (i.e., a “first transistor”), which may include a first gate electrode 112 (i.e., a “first control electrode”), a first drain electrode 114 (i.e., a “first current carrying electrode”), and a first source electrode 116 (i.e., a “second current carrying electrode”), configured to support current flow between the first drain electrode 114 and the first source electrode 116, wherein the first gate electrode 112 physically and electrically separates the first source electrode 116 and the first drain electrode 114, and may be configured to control current flow in a variable conductivity channel between the first drain electrode 114 and the first source electrode 116, wherein the gate electrode is radio frequency (RF) coupled to the first input terminal 102, and wherein the first drain electrode 114 is electrically coupled to the first output terminal 127. In an embodiment, the first source electrode 116 of the first transistor 110 may be electrically coupled to the ground potential 115.

[0039] In an embodiment, the first bias network 118 may be electrically coupled to the first gate electrode 112, wherein the first bias network 118 may be configured to apply a first direct current (DC) bias 119 (i.e., a "first bias") to the first gate electrode 112 and to be RF-isolated from the first gate electrode 112. As used herein, according to an embodiment, the term "RF isolation" means that the radio frequency (RF) coupling between two components of the RF isolation is less than -20 dB. In other embodiments, the RF coupling between two components of the RF isolation is less than -10 dB, but higher or lower values ​​may be used. In an embodiment, a second field effect transistor 120 (i.e., a "second transistor") including a second gate electrode 122 (i.e., a "second control electrode"), a second drain electrode 124 (i.e., a "third current carrying electrode"), and a second source electrode 126 (i.e., a "fourth current carrying electrode") may be configured to support current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be configured to control current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be RF coupled to the first input terminal 102, wherein the second drain electrode 124 may be electrically coupled to the first output terminal 127. According to an embodiment, a second bias network 128 may be electrically coupled to the second gate electrode 122, wherein the second bias network 128 may be configured to apply a second DC bias 129A / 129B to the second gate electrode 122 and may be RF isolated from the second gate electrode 122. In an embodiment, the source electrode 126 of the second transistor 120 may be electrically coupled to the ground potential 125.

[0040] Still referring to FIG. 1 , in an embodiment, the amplifier device 100 may include a second amplifier 105 electrically coupled to a second input terminal 106 and a second output terminal 137. The second amplifier 105 may include a third transistor 130, which may include a third gate electrode 132, a third drain electrode 134, and a third source electrode 136. According to an embodiment, the third transistor 130 may be configured to support current flow between the third drain electrode 134 and the third source electrode 136, wherein the third gate electrode 132 may be configured to control current flow between the third drain electrode 134 and the third source electrode 136, wherein the third control electrode RF is coupled to the second input terminal 106, and wherein the third drain electrode 134 may be electrically coupled to the second output terminal 137. In an embodiment, a third bias network 138 may be electrically coupled to the third gate electrode 132, wherein the third bias network 138 may be configured to apply a third DC bias 139 to the third gate electrode and may be RF isolated from the third gate electrode. In an embodiment, the source electrode 136 of the third transistor 130 may be electrically coupled to the ground potential 135 .

[0041] In an embodiment, a fourth transistor 140 including a fourth gate electrode 142, a fourth drain electrode 144, and a fourth source electrode 146 may be configured to support current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 may be configured to control current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 may be radio frequency (RF) coupled to the second input terminal 106, and wherein the fourth drain electrode 144 may be electrically coupled to the second output terminal. A fourth bias network 148 is electrically coupled to the fourth gate electrode 142, wherein the fourth bias network 148 may be configured to apply a fourth DC bias 149A / 149B to the fourth gate electrode 142 and may be RF-isolated from the fourth gate electrode 142. In an embodiment, the source electrode 146 of the fourth transistor 140 may be electrically coupled to the ground potential 145.

[0042] In an embodiment, the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 may include field effect transistors (FETs) (e.g., heterojunction FETs (HFETs), metal-semiconductor FETs (MESFETs), or metal oxide semiconductor FETs (MOSFETs)), each of which includes a gate (control terminal), a source (a first current carrying terminal), and a drain (a second current carrying terminal). For ease of explanation and not limitation, GaN HFET active devices for the amplifier device 100 and GaN HFET active devices for the amplifier device 100 will be used. Figure 3 and 4 Various embodiments of the present invention are described with reference to silicon laterally diffused metal oxide semiconductor devices (LDMOS) devices of the driver amplifiers 308, 408, which are preferred. However, many other active device types may also be employed and are intended to be included within the scope of the present invention, such as but not intended to be limited to bipolar devices, junction field effect devices, various insulated gate field effect devices, etc. Alternatively, the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 may include bipolar junction transistors (BJTs) or heterojunction BJTs (HBTs). Therefore, references herein to "gate," "drain," and "source" are not intended to be limiting, as each of these names has similar features of bipolar device implementations (e.g., base, collector, and emitter, respectively).

[0043] In an embodiment, the first transistor 110 may have a total gate width between about 0.5 and about 50 millimeters (mm) (e.g., about 1 mm), although in some embodiments, a total gate width of higher or lower values ​​may be used. In an embodiment, the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 have input capacitance (i.e., gate-source capacitance) between the first gate electrode 112, the second gate electrode 122, the third gate electrode 132, and the fourth gate electrode 142 of the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 and the first source electrode 116, the second source electrode 126, the third source electrode 136, and the fourth source electrode 146. In an example embodiment, the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 have a gate-source capacitance between about 0.5 pF per millimeter of gate periphery (pF / mm) and about 3.5 pF / mm (e.g., 2.5 pF / mm), although higher or lower values ​​may be used. In an embodiment, the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 have an output capacitance (i.e., drain-source capacitance) between the first drain terminal 114, the second drain terminal 124, the third drain terminal 134, and the fourth drain terminal 144 and the first source electrode 116, the second source electrode 126, the third source electrode 136, and the fourth source electrode 146. In one embodiment, the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 have a drain-source capacitance between about 0.2 pF per millimeter of gate periphery (pF / mm) and about 1 pF / mm (e.g., about 0.4 pF / mm), although other higher or lower values ​​may be used.

[0044] In an embodiment, the first amplifier 101 and the second amplifier 105 can be combined in a Doherty configuration. To this end, the transmission line 150 can be used in combination with the output capacitance of the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 to achieve a phase shift between the outputs 127 and 137 of the first amplifier 101 and the second amplifier 105. According to an embodiment, the transmission line 150 can be configured to electrically couple the first output terminal 127 and the second output terminal 137. In an embodiment, the phase shift can be between about 80 and 100 degrees. In an embodiment, the phase shift partially introduced by the transmission line 150 can be added to the phase shift caused by the capacitive load of the output capacitance of the first transistor 110, the second transistor 120, the third transistor 130, and the fourth transistor 140 and the additional inductance (not shown) coupled in series at one or more ends of the transmission line 150. Therefore, the transmission line phase shift caused only by the transmission line 150 can be less than the phase shift, and the desired amount of phase shift can be achieved. For example, the transmission line phase shift may be, for example, 20 to 50 degrees, but due to the output capacitance of transistors 110, 120, 130, 140 and possible additional capacitors and inductors (not shown), the phase shift may be about 90 degrees, such as 80 and 100 degrees. In other embodiments, the phase shift may have higher or lower values, such as 30 to 120 degrees, depending on the application. In an embodiment, the impedance transformer 152 may be electrically coupled to the second output 137 to produce a summing node at the second output 137 and electrically coupled to the output terminal 108. As used herein, the term "summing node" refers to the point at which the peak amplifier is electrically connected to the carrier amplifier or the main amplifier in, for example, a Doherty amplifier configuration.

[0045] In other embodiments, the summing node and the connection to the impedance transformer 152 may be at the first output 127. In these embodiments, the first amplifier 101 may be configured as a carrier amplifier and the second amplifier 105 may be configured as a peaking amplifier. In these embodiments, a transmission line having a phase shift approximating the phase difference of the splitter (e.g., 90 degrees) may be added to the carrier amplifier path and the peaking amplifier path (not shown). According to an embodiment, a splitter 153 having a splitter input 155, a first splitter output 156, and a second splitter output 157 may be configured to divide the signal delivered to the splitter input 155 between the first splitter output 156 and the second splitter output 157 using the splitter phase difference between the first splitter output 156 and the second splitter output 157. In an embodiment, the splitter phase difference may be between about 45 degrees and about 135 degrees. In an embodiment, the difference between the splitter phase difference and the phase shift associated with the transmission line 150 and the second splitter output 157 may be less than 20% of the splitter phase difference. In an embodiment, in a Doherty amplifier configuration, the first amplifier 101 may be configured as a carrier amplifier and the second amplifier 105 may be configured as a peaking amplifier.

[0046] In an embodiment, the first amplifier 101 and the second amplifier 105 may be configured to Figure 1A and in the high power state 161 depicted in FIG. Figure 1B In an embodiment, when operating in the high power state 161, the first transistor 110 and the third transistor 130 and the second transistor 120 and the fourth transistor 140 may operate with the first bias 119 and the third bias 139 applied to the first bias network 118 and the third bias network 138 and the second bias 129A and the fourth bias 149A applied to the second bias network 128 and the fourth bias network 148. According to an embodiment, during saturation operation of the amplifier device 100, when the first transistor 110 and the third transistor 130 operate at a saturated output power, an RF current of at least 50% of the maximum current of the second transistor 120 and the fourth transistor 140 may flow from the second drain electrode 124 and the fourth drain electrode 144 (i.e., the “third and seventh current-carrying electrodes”) of the second transistor 120 and the fourth transistor 140 to the second source electrode 126 and the fourth source electrode 146 (i.e., the “fourth and eighth current-carrying electrodes”), and the fifth bias 109A is applied to the first drain electrode 114, the second drain electrode 124, the third drain electrode 134, and the fourth drain electrode 144 (i.e., the “first, third, fifth, and seventh current-carrying electrodes”). According to an embodiment, when Figure 1B When operating in the low power state 162 of , the first transistor 110 and the third transistor 130 and the second transistor 120 and the fourth transistor 140 may be operated under the following conditions: the first bias 119 and the third bias 139 are applied to the first bias network 118 and the third bias network 138 and the second bias 129B and the fourth bias 149B are applied to the second bias network 128 and the fourth bias network 148, so that when the first transistor 110 and the third transistor 130 operate at the saturated output power, the RF current less than 10% of the maximum current of the second transistor 120 and the fourth transistor 140 flows through the second transistor 120 and the fourth transistor 140. In other embodiments, according to embodiments, when in Figure 1BWhen operating in the low power state 162 of FIG. 1 , the first transistor 110 and the third transistor 130 and the second transistor 120 and the fourth transistor 140 may be operated under the following conditions: the first bias 119 and the third bias 139 are applied to the first bias network 118 and the third bias network 138 and the second bias 129B and the fourth bias 149B are applied to the second bias network 128 and the fourth bias network 148, so that when the first transistor 110 and the third transistor 130 operate at a saturated output power, an RF current less than 1% of the maximum current of the second transistor flows through the second transistor 120 and the fourth transistor 140. In an embodiment, the magnitude of the difference between the saturation efficiency in the high power state 161 (i.e., the “first state”) and the magnitude of the efficiency in the second state 162 may be less than 20% of the efficiency in the high power state 161. According to an embodiment, when operating in the low power state 162, a fifth bias 109B may be applied to the first drain electrode 114, the second drain electrode 124, the third drain electrode 134, and the fourth drain electrode 144 (i.e., "the first current-carrying electrode, the third current-carrying electrode, the fifth current-carrying electrode, and the seventh current-carrying electrode"). In an embodiment, when operating in the low power state 162, the fifth bias 109B may be a lower value (e.g., 28 V) than the fifth bias 109A (e.g., 48 V).

[0047] In an embodiment, the amplifier device 100 may be operated in a transmitter system, wherein individual power supplies (not shown) may be used to supply the first bias 119, the second bias 129, the third bias 139A / 139B, the fourth bias 149A / 149B, and the fifth bias 109A / 109B. According to an embodiment, a bias controller (not shown) may be used to control the voltage levels provided for the first bias 119, the second bias 129A / 129B, the third bias 139, the fourth bias 149A / 149B, and the fifth bias 109A / 109B. In an embodiment, the bias controller may sense the traffic level in the amplifier system, and thus sense the output power required by the amplifier device 100. Therefore, the bias voltages applied to the first bias 119 and the third bias 139, the second bias 129A / 129B and the fourth bias 149A / 149B, and the fifth bias 109A / 109B may be adjusted to optimize the efficiency of the amplifier device 100.

[0048] For example, in an embodiment in which the first amplifier 101 is configured as a carrier amplifier and the second amplifier 105 is configured as a peak amplifier having a first transistor 110, a second transistor 120, a third transistor 130, and a fourth transistor 140 based on gallium nitride (GaN) transistor technology, according to an embodiment, the first bias 119, the second bias 129A, and the fifth bias 109A corresponding to the high power state 161 may include a gate voltage corresponding to a class AB quiescent drain current bias of, for example, less than 5% of the full channel current of the first transistor 110 (e.g., a gate bias of -2.5 V to -2.9 V or approximately 0.1 to 0.5 V higher than a threshold voltage of -3 V), and a fifth bias 109A (e.g., a drain voltage of 48 V) applied to the first drain electrode 114, the second drain electrode 124, the third drain electrode 134, and the fourth drain electrode 144 corresponding to high power operation. Similarly, according to an embodiment, the third bias 139 and the fourth bias 149A of the third transistor 130 and the fourth transistor 140 of the second amplifier 105 may include a gate voltage corresponding to a class C bias (e.g., approximately zero current, where the gate bias is approximately 0.1V to 2V lower than the threshold voltage (e.g., -3.1V to -2V for a -3V threshold voltage)), while a fifth bias 109A (e.g., 50V) is applied to the drain electrodes 134, 144 of the third transistor 130 and the fourth transistor 140.

[0049] For example, in an embodiment where the first amplifier 101 is configured as a carrier amplifier and the second amplifier 105 is configured as a peaking amplifier having first, second, third, and fourth transistors based on gallium nitride (GaN) transistor technology, according to an embodiment, the first bias 119 corresponding to the low power state 162 may include a gate voltage corresponding to a class AB bias (e.g., a gate bias of approximately -2.5V to -2.9V or approximately 0.1 to 0.5V higher than a threshold voltage of -3V), the class AB bias being, for example, a quiescent drain current less than ten percent of the full channel current of the first transistor 110. Similarly, the third bias 139 applied to the third transistor 130 of the second amplifier 105 may include a gate voltage corresponding to a class C bias for the transistor 130 (e.g., approximately zero current, where the gate bias is approximately 0.1V to 1V lower than the threshold voltage (e.g., -3.1V to -4V for a -3V threshold voltage)). The second bias 129B and the fourth bias 149B applied to the second bias network 128 and the fourth bias network 148 may correspond to a deep class C condition (e.g., a gate bias of -8V, 5V below a threshold voltage of about -3V) for the second transistor 120 and the fourth transistor 140. Likewise, according to an embodiment, the fifth bias 109B (e.g., a drain voltage of 28V) applied to the first drain electrode 114, the second drain electrode 124, the third drain electrode 134, the fourth drain electrode 144 corresponds to a low power operation. According to an embodiment, in the low power state 162, the effect of the third bias 129B and the fourth bias 149B biasing the transistors 120, 140 in a deep class C may have the effect of reducing the overall effective gate periphery of the first amplifier 101 and the second amplifier 105 because the devices operate in deep depletion and do not contribute current to the operation of the amplifier device 100.

[0050] Figure 2 It is a diagram illustrating the Figure 1A and Figure 1B A graphical representation 200 of the operation of the amplifier device 100 in the high power state 161 and the low power state 162 is also shown. Figure 1A , 1B and Figure 2, graphical representation 200 shows simulated drain efficiency 212 versus output power 210. Traces 220, 222, 224 represent efficiency versus output power at frequencies of 2.5 gigahertz (GHz), 2.6 GHz, and 2.7 GHz, respectively, when amplifier device 100 is operated in high power state 161. Traces 230, 232, 234 represent efficiency versus output power at frequencies of 2.5 GHz, 2.7 GHz, and 2.6 GHz, respectively, when amplifier device 100 is operated in low power state 162. In this example, first transistor 110 and second transistor 120 each have a total gate width (i.e., unit gate width multiplied by the number of fingers) of 1 millimeter (mm), while third transistor 130 and fourth transistor 140 each have a total gate width of 1.75 mm. According to an embodiment, traces 220, 222, 224 show that during the high power state 161, where the first bias 119 and the second bias 129A are set to achieve 8.5 mA / mm at a drain voltage of 48 V, a class C bias of -3.9 V at a drain bias of 48 V is applied to the third transistor 130 and the fourth transistor 140, an efficiency of greater than 60% can be achieved within a power range of 40 dBm to 47 dBm. According to an embodiment, traces 230, 232, 234 show that during the low power state 162, where the first bias 119 is set to achieve 8.5 mA / mm at a drain voltage of 28 V, applied to the first transistor 110; the third bias 139 is set to a class C bias of -3.9 V at a drain bias of 28 V, applied to the third transistor 130; and a deep class C bias of -8 V is applied to the second bias 129B and the fourth bias 149B to bias the second transistor 120 and the fourth transistor 140 to deep class C, an efficiency of greater than 58% can be achieved in a power range of 35 dBm to 42 dBm. Therefore, according to an embodiment, the dynamic range of the amplifier device 100 for achieving an efficiency of greater than 58% can be extended from about 8 dB to about 14 dB.

[0051] Figure 3is a schematic diagram of a first power amplifier device 300 according to an embodiment. The first power amplifier device 300 (i.e., "first amplifier") may include a first amplifier 101 electrically coupled to a first input terminal 302 and a first output terminal 127, and a driver and bias circuit system 301 coupled to the first amplifier 101. The first amplifier 101 may include a first field effect transistor 110, the first field effect transistor 110 including a first gate electrode 112, a first drain electrode 114, and a first source electrode 116. According to an embodiment, the first field effect transistor 110 may be configured to support current flow between the first drain electrode 114 and the first source electrode 116, wherein the first gate electrode 112 may be configured to control current flow between the first drain electrode 114 and the first source electrode 116, wherein the gate electrode 112 may be RF coupled to a first external input terminal 305, and wherein the first drain electrode 114 may be electrically coupled to the first output terminal 127 and the first external output terminal 309 via an output wire bond 307. In an embodiment, the first bias network 370 includes an RF bypass capacitor 372 coupled to ground 373 and an inductor 376 that can be electrically coupled to the first gate electrode 112, and can be configured to apply a first direct current (DC) bias via terminal 374, inductor 376, terminal 378, bonding wire 379, and wherein the first bias network 370 is to the first gate electrode 112 and can be RF-isolated from the first gate electrode 112. In an embodiment, the RF bypass capacitor 372 can have a value between about 5 picofarads and about 100 picofarads, but other higher or lower values ​​can be used. According to an embodiment, the inductor 376 can have a value between about 5 nanohenrys and about 100 nanohenrys, but other higher or lower values ​​can be used.

[0052] In an embodiment, the second field effect transistor 120 may include a second gate electrode 122, a second drain electrode 124, and a second source electrode 126, configured to support current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be configured to control current flow between the second drain electrode 124 and the second source electrode 126, wherein the second gate electrode 122 may be RF coupled to the first input terminal 302, wherein the second drain electrode 124 may be electrically coupled to the first output terminal 127. According to an embodiment, a second bias network 380 including an RF bypass capacitor 382 coupled to ground 383 and an inductor 386 may be electrically coupled to the first gate electrode through the inductor 386, may be electrically coupled to the second gate electrode 122, wherein the second bias network 380 may be configured to apply a second DC bias to the second gate electrode 122 through the terminal 384, the inductor 386, the terminal 388, and the bonding wire 389, and may be RF isolated from the second gate electrode 122. In an embodiment, the values ​​of the components of the second bias network 380 (eg, the RF bypass capacitor 382 and the inductor 386 ) may be similar to the values ​​of the components of the first bias network 370 .

[0053] In an embodiment, a circuit system 390 including a first capacitor 394 (i.e., a "first coupling element") having a first end 394A and a second end 394B may be electrically coupled to the first gate electrode 112 by its second end 394B through a terminal 395 and a bonding wire 398. A second capacitor 396 (i.e., a "second coupling element") having a third end 396A and a fourth end 396B may be electrically coupled to the second gate electrode 122 through a terminal 397 via a fourth terminal 396B and a bonding wire 399. According to an embodiment, the first terminal 394A may be electrically coupled to the third terminal 396A. In an embodiment, a first input matching network, which may include bonding wires 369, 379, and 398, may be electrically coupled to the first gate electrode 112 through terminals 368, 378, 395, and may be configured to provide impedance matching for the first transistor 110 at a fundamental frequency. A second input matching network, which may include bond wires 359 , 389 , and 399 , may be electrically coupled to the second gate electrode 122 and may be configured to provide impedance matching for the second transistor 120 at a fundamental frequency.

[0054] Embodiments may include first and input harmonic matching networks 350, 360 including capacitors 352, 362 and inductors 354, 364 connected in series and electrically coupled to grounds 356, 366, and may be configured to provide harmonic termination at harmonic frequencies for the first transistor 110. Embodiments may also include input harmonic matching networks 350, 360 including capacitors 352, 362 and inductors 354, 364 connected in series and electrically coupled to grounds 356, 366 and terminals 358, 368, and may be configured to provide harmonic termination at harmonic frequencies for the first transistor 110 and the second transistor 120. In embodiments, the capacitors 352, 362 may have values ​​between about 0.3 picofarads and about 5 picofarads, although other higher or lower values ​​may be used. According to an embodiment, inductors 354, 364 may have values ​​between about 0.3 nanohenry and about 2 nanohenry, although other higher or lower values ​​may be used.

[0055] The driver amplifier 308 may be electrically coupled to the first terminal 394A of the first capacitor and the third terminal 396A of the second capacitor, and may be RF coupled to the first input terminal 302 through the series capacitor 312 and RF coupled from the first input terminal 302 to the first external input terminal 305. The transistor 330 is the main active device of the driver amplifier 308, and includes a gate electrode 332, a source terminal 334, and a drain electrode 336. In an embodiment, the driver amplifier 308 may be coupled to the first external input terminal 305 through the bonding wire 303, and may include an input matching network 310 coupled to the gate electrode 332 of the transistor 330, an input bias network 320 coupled to the gate electrode 332, and a driver drain bias network 340 coupled to the drain electrode 336 of the transistor 330. According to an embodiment, the driver amplifier 308 may be coupled to the first capacitor 394 and the second capacitor 396 through the inductor 392, and the inductor 392 may be configured to provide impedance matching.

[0056] In an embodiment, the input matching network 310 may include a "T" network including input matching inductors 314, 318 electrically coupled together in series at a point coupled to ground through an input matching capacitor 316. According to an embodiment, the input matching inductors 314, 318 may have values ​​between about 0.1 nanohenry and about 5 nanohenry. According to an embodiment, the input matching capacitor may have a value between about 0.5 picofarad and about 2 picofarad. In an embodiment, the input bias network 320 may include a DC block 321 including an RF bypass capacitor 322 and a DC ground 323, which may be electrically coupled to a gate electrode 332 through an inductor 325 and a resistor 327, wherein the input bias network 320 may be configured to apply a first direct current (DC) bias to the gate electrode 332. In an embodiment, the RF bypass capacitor 322 may have a value between about 2 picofarad and about 50 picofarad, although other higher or lower values ​​may be used. According to an embodiment, the inductor 325 may have a value between about 5 nanohenries and about 100 nanohenries, but other higher or lower values ​​may be used. According to an embodiment, the resistor 327 may have a value between about 1 ohm and about 1000 ohms. Terminal 328 is used to provide a connection of the input bias network to the DC gate bias. In an embodiment, the driver drain bias network 340 may include a DC block 341, which includes an RF bypass capacitor 342 and an RF ground 343, and may be electrically coupled to the drain electrode 336 through the inductor 345, wherein the driver drain bias network 340 may be configured to apply a first direct current (DC) bias to the drain electrode 336 through the terminal 348. In an embodiment, the RF bypass capacitor 342 may have a value between about 2 picofarads and about 50 picofarads, but other higher or lower values ​​may be used. According to an embodiment, the inductor 345 may have a value between about 5 nanohenries and about 100 nanohenries, but other higher or lower values ​​may be used.

[0057] Figure 4is a schematic diagram of a second power amplifier device 400 (i.e., "second amplifier") according to an embodiment. According to an embodiment, the second power amplifier device 400 may include a second amplifier 105 and a driver and bias circuit system 401 that may be electrically coupled to a second input terminal 402 and a second output terminal 137. In an embodiment, the second amplifier 105 may include a third transistor 130, the third transistor 130 including a third gate electrode 132, a third drain electrode 134, and a third source electrode 136, wherein the third gate electrode 132 may be RF coupled to the second input terminal, and wherein the third drain electrode may be electrically coupled to the second output terminal. A third bias network 470 including a DC blocking capacitor 472, a ground 473, and an inductor 476 may be electrically coupled to the third gate electrode 132, wherein the third bias network 470 may be configured to apply a third DC bias to the third gate electrode 132 and may be RF isolated from the third gate electrode 132. Embodiments may include a fourth transistor 140 including a fourth gate electrode 142, a fourth drain electrode 144, and a fourth source electrode 146, configured to support current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 is configured to control current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 may be radio frequency (RF) coupled to the second input terminal, and wherein the fourth drain electrode 144 may be electrically coupled to the second output terminal 137. According to embodiments, a fourth bias network 480 including a DC block 481, a ground 483, and an inductor 486 may be electrically coupled to the fourth gate electrode 142, wherein the fourth bias network 480 may be configured to apply a fourth DC bias applied at the terminal 484 to the fourth gate electrode 142 through the terminal 488 and may be RF isolated from the fourth gate electrode 142.

[0058] In an embodiment, other components included in the second power amplifier device 400 (e.g., the second external input terminal 405, the bonding wire 403, the second input terminal 402, the bonding wire 407, the driver amplifier 408, the output terminal 409, the input matching network 410, the input matching inductors 414, 418, the input matching capacitor 416, the input bias network 420, the DC block 421, the RF bypass capacitor 422, the DC ground 423, the inductor 425, the resistor 426, the RF bypass capacitor 427, the DC ground 428, the inductor 429, the resistor 430, the RF bypass capacitor 431, the RF bypass capacitor 432, the RF bypass capacitor 433, the RF bypass capacitor 434, the RF bypass capacitor 435, the RF bypass capacitor 436, the RF bypass capacitor 437, the RF bypass capacitor 438, the RF bypass capacitor 439, the RF bypass capacitor 440, the RF bypass capacitor 441, the RF bypass capacitor 442, the RF bypass capacitor 443, the RF bypass capacitor 444, the RF bypass capacitor 445, the RF bypass capacitor 446, the RF bypass capacitor 447, the RF bypass capacitor 448, the RF bypass capacitor 449, the RF bypass capacitor 450, the RF bypass capacitor 451, the RF bypass capacitor 452, the RF bypass capacitor 453, the RF bypass capacitor 454, the RF bypass capacitor 455, the RF bypass capacitor 456, the RF bypass capacitor 457, the RF bypass capacitor 458, the RF bypass capacitor 459, the RF bypass capacitor 460, the RF bypass capacitor 461, the RF bypass capacitor 46 27, driver terminals 428, 448, transistor 430, transistor gate electrode 432, transistor drain electrode 436, transistor source electrode 434, output bias network 440, DC block 441, RF bypass capacitor 442, RF ground 443, inductor 445, series capacitor 412, coupling circuit system 490, inductor 492, first capacitor 494, second capacitor 496, bonding wires 479, 489, 498, 499) have been combined Figure 3The first power amplifier device 300 is described in detail.

[0059] In this example embodiment, the second power amplifier arrangement 400 does not include Figure 3 The input harmonic termination network (eg, input harmonic termination networks 350, 360) included in the first power amplifier device 300. In other embodiments, the harmonic termination circuitry may be included in the second power amplifier device 400 (not shown).

[0060] Figure 5A is a top plan view of an apparatus 500 according to an embodiment, and Figure 5B According to the embodiment along Figure 5A A cross-sectional side view of the cutting line 5B-5B. Fig. 6A , 6B 7A and 7B are top plan and isometric views of a portion of the device 500 according to an embodiment. Figure 5A , 5B , 6A, 6B, 7A and 7B, the features of device 500 can be best understood.

[0061] The apparatus 500 may include a base substrate 510, a first power amplifier device 300 coupled to the base substrate 510 and electrically coupled to a first input terminal 302 and to a first output terminal 127 through a driver and bias circuit system 301. In an embodiment, the first amplifier 101 may include a first field effect transistor 110, which may include a first gate electrode 112, a first drain electrode 114, and a first source electrode 116 (not shown). According to an embodiment, a first bias network 370 (within the driver and bias circuit system 301, not shown) may be connected via a bonding wire 379, a terminal 378, a first bias network 370 (at a Figure 3 ) is electrically coupled to the first gate electrode 112, and may be configured to apply a first direct current (DC) bias to the first gate electrode 112 from the module terminal 574A through the terminal 374, and may be RF isolated from the first gate electrode. In an embodiment, the second field effect transistor 120 formed integrally with the first field effect transistor 110 may include a second gate electrode 122, a second drain electrode 124, and a second source electrode 126 (not shown). In an embodiment, the second gate electrode 122 may be RF coupled to the first input terminal 302, wherein the second drain electrode 124 may be electrically coupled to the first output terminal. According to an embodiment, the second bias network 380 (at Figure 3The driver and bias circuit system 301 shown in FIG. 304 can be electrically coupled to the second gate electrode 122 via a bonding wire 389 and a terminal 388, wherein the second bias network 380 can be configured to apply a second DC bias provided via the terminal 384 to the second gate electrode 122 from the module terminal 584A and can be RF isolated from the second gate electrode 122.

[0062] In an embodiment, the second power amplifier device 400 may be coupled to the base substrate 510 and may be electrically coupled to the second input terminal 402 and the second output terminal 137, wherein the second power amplifier device 400 may include a third transistor 130, the third transistor 130 including a third gate electrode 132, a third drain electrode 134 and a third source electrode 136 (not shown), configured to support current flow between the third drain electrode 134 and the third source electrode 136 (see Figure 4 and 7A ). In an embodiment, a third bias network 470 (within the driver and bias circuit system 401, not shown) can be electrically coupled to the third gate electrode 132 via a terminal 478 and a bonding wire 479, wherein the third bias network 470 can be configured to apply a third DC bias provided to the terminal 474 from the module terminal 574B to the third gate electrode 132 and can be RF-isolated from the third gate electrode 132. According to an embodiment (see Figure 4 and 7A), the fourth transistor 140 may include a fourth gate electrode 142, a fourth drain electrode 144, and a fourth source electrode 146 (not shown), and is configured to support current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 may be configured to control the current flow between the fourth drain electrode 144 and the fourth source electrode 146, wherein the fourth gate electrode 142 may be radio frequency (RF) coupled to the second input terminal 402 (via the driver and bias circuit system 401), and wherein the fourth drain electrode 144 may be electrically coupled to the second output terminal 137. In an embodiment, a fourth bias network 480 may be electrically coupled to the fourth gate electrode 142 via terminal 488 and a bonding wire 489, wherein the fourth bias network may be configured to apply a fourth DC bias to the fourth gate electrode 142 from the module terminal 584B via terminal 484 and may be RF isolated from the fourth gate electrode 142. According to an embodiment, the transmission line 150 formed over the base substrate 510 may be configured to electrically couple the first output terminal 127 and the second output terminal 137. According to an embodiment, the impedance transformer 152 may be formed over the base substrate 510 and may be electrically coupled to a summing node at one of the first output terminal 127 and the second output terminal 137. According to an embodiment, the module drain terminal 506 may be coupled to the impedance transformer 152 through a bias network 529 including an RF choke 528 and a bypass capacitor 527. In the embodiment shown here, the summing node is at the second output terminal 137. The output terminal 508 may be coupled to the impedance transformer 152 using a coupling capacitor 507.

[0063] In an embodiment, the first transistor 110 and the second transistor 120 may be integrally formed on the first substrate 509A, and the first capacitor 394 and the second capacitor 396 may be formed on the second substrate 511A, wherein the terminals 395 and 397 are formed as part of the driver and bias circuit system 301. In other embodiments, the first transistor 110 and the second transistor 120 may be formed on the first substrate 509A, and the first capacitor and the second capacitor may be formed on the first substrate 509A (not shown). Similarly, in an embodiment, the third transistor 130 and the fourth transistor 140 may be integrally formed on the third substrate 509B, and the first capacitor 494 and the second capacitor 496 may be formed on the fourth substrate 511B, wherein the terminals 495 and 497 are respectively formed as part of the driver and bias circuit system 401.

[0064] Embodiments may include driver and bias circuitry 301, 401 including transistors 330, 430 formed on a third substrate 509B and a fourth substrate 511B, wherein a driver amplifier may be electrically coupled to a first end of a first capacitor and may be coupled to a third end of a second capacitor. According to an embodiment, a first bias network 370 and a second bias network 380 may be formed on the second substrate 511A. According to an embodiment, a third bias network 470 and a fourth bias network 480 may be formed on the fourth substrate 511B. Terminals 328, 348 and 428, 448 providing bias to transistors 330 and 430 may be coupled to module terminals 528A, 548A and 528B and 548B, respectively, to connect to an external power source.

[0065] In an embodiment, the splitter 153 may be formed over the base substrate 510, have a splitter input 155, a first splitter output 156, and a second splitter output 157, and is configured to divide a signal delivered to the splitter input 155 between the first splitter output 156 and the second splitter output 157 using a splitter phase difference between the first splitter output and the second splitter output, wherein the difference between the splitter phase difference and the phase shift associated with the transmission line 150 is less than 20%, wherein the first input 102 may be electrically coupled to the first splitter output 156, and the second input 106 is electrically coupled to the second splitter output 157. In other words, the phase shift of the transmission line 150 may approximate the splitter phase difference, such that the difference between the phase shift and the splitter phase difference is less than about 20%. As used herein, "phase shift of a transmission line" means the phase shift encountered by a signal, and includes the phase shift of the transmission line as well as the effects of any loading (e.g., capacitance and inductance) of other circuit components on the transmission line. Thus, in an embodiment, the phase shift of the transmission line 150 also includes the effect of the output capacitance of the third transistor 130 and the fourth transistor 140 and / or additional matching elements (not shown) seen at the output 137. According to an embodiment, in a Doherty amplifier configuration, the first power amplifier device 300 may be configured as a carrier amplifier and the second power amplifier device 400 may be configured as a peaking amplifier. In an embodiment, the splitter 153 may be implemented using a compact hybrid coupler, wherein the branches of the compact hybrid coupler are implemented in a compact form factor using a lumped element capacitor 558, an inductor 559, and a terminating resistor 554. The coupling capacitor 555 may RF couple the second splitter output 157 to the second power amplifier device 400. In other embodiments, the splitter 153 may be implemented using a branch line coupler. In other embodiments, the splitter 153 may be implemented using a Lange coupler. In still other embodiments, splitter 153 may be implemented using a Wilkinson power divider with additional transmission line length for achieving a phase difference between first splitter output 156 and second splitter output 157. Splitter input 155 may be coupled to module input 502 using coupling capacitor 504.

[0066] refer to Figure 5A and 5BAccording to an embodiment, the base substrate 510 may include a multi-layer structure including a first ground plane layer 512, a first metal layer 514, a second ground plane layer 516, a second metal layer 518, and a third metal layer 520. In an embodiment, the first via 513 may connect the first ground plane layer to the first metal layer 514. According to an embodiment, the second via 515 may connect the first metal layer 514 to the second ground plane layer 516. In an embodiment, the third via 517 may connect the second ground plane layer 516 to the second metal layer 518. According to an embodiment, the fourth via 519 may connect the second metal layer 518 to the third metal layer 520. According to an embodiment, heat sink areas 522 and 524 may be formed under the driver and bias circuitry 301 and the first amplifier 101 by stacking the first ground plane layer 512, the first metal layer 514, the second ground plane layer 516, the second metal layer 518, and the third metal layer 520 using the first via 513, the second via 515, the third via 517, and the fourth via 519. In an embodiment, the first ground plane layer 512 may be used to implement a microstrip line (e.g., the transmission line 150) in conjunction with the third metal layer 520. The second ground plane 516 layer may be used in conjunction with the third metal layer 520 to implement a transmission line of a narrower width (e.g., the splitter input 155 and the second output 157).

[0067] Fig. 8A , 8B , 8C and 8D, collectively referred to as FIG8, are graphical representations 810, 820, 850, 870 depicting simulated operation of the device 500 of FIG5. According to an embodiment, the graphs 810, 820, 850, 870 depict the gain 812, final stage efficiency 832, insertion phase 852, and multi-stage efficiency 872 of the device 500 versus average output power 814, 834, 854, 874. Traces 821, 822, 823, 841, 842, 843, 861, 862, 863, 881, 882, 883 depict gain, efficiency, normalized insertion phase, and multi-stage performance efficiency in high power mode. The triple traces 821-823, 841-843, 861-863, 881-883 represent performance at 2.5, 2.6, and 2.7 GHz, respectively. According to an embodiment, in the high power mode, the bias conditions include: a 48V bias applied to the drain terminals 114, 124, 134, 144 of the first power amplifier device 300 and the second power amplifier device 400, wherein for the first power amplifier device 300, a quiescent current (I DQ) is evenly distributed between the first transistor 110 and the second transistor 120; and a gate bias of -3.9V applied to the third gate terminal 132 and the fourth gate terminal 142 of the third transistor 130 and the fourth transistor 140. In an embodiment, traces 826, 827, 828, 846, 847, 848, 866, 867, 868, 886, 887, 888 depict the relationship between the gain, efficiency, insertion phase and multi-stage efficiency of the device 500 in low power mode and the average output power. The triple traces 826-828, 846-848, 866-868, 886-888 represent 2.5, 2.6 and 2.7 GHz respectively. According to an embodiment, in the low power mode, the bias conditions include: a 28V bias applied to the drain terminals 114, 124, 134, 144 of the first power amplifier device 300 and the second power amplifier device 400, wherein the quiescent current (I DQ ) is 8.5 mA, and the quiescent current of the second transistor 120 is 0 mA, which is due to the -8V gate bias applied to the second gate 122 through the second bias network 380 for the first power amplifier device 300; and the -3.9V gate bias applied to the third gate terminal 132 of the third transistor 130; and the -8V gate bias applied to the gate of the fourth transistor 140. According to an embodiment, because the second and fourth transistors are biased in deep class C, the second and fourth transistors are effectively "off" when the first and third transistors operate in class AB and class C.

[0068] exist Fig. 8A , graph 810 shows the transducer gain (G) expressed in dB relative to 1 milliwatt (dBm). T ) versus output power in decibels. Traces 826-828 show a gain of approximately 3 dB less from 15 to 40 dBm output power than traces 821-823, which correspond to low power operation in which the first transistor 110 and the third transistor 130 are biased in class AB and class C, respectively, at a drain voltage of 28 V, and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28 V, and traces 821-823 correspond to the first transistor 110 and the second transistor 120 biased in class AB, the third transistor 130 and the fourth transistor 140 biased in class C, all operating in a high power state at a drain voltage of 48 V.

[0069] exist Figure 8B8, a graph 820 shows the relationship between the final stage drain efficiency in percent and the output power in dBm. At an output power of 35 dBm, traces 846-848 are shown as being approximately 20 percentage points more efficient than traces 841-843, which correspond to low power operation in which the first transistor 110 and the third transistor 130 are biased in class AB and class C, respectively, at a drain voltage of 28 V and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28 V, and traces 841-843 correspond to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C are all biased at a drain voltage of 48 V in a high power state.

[0070] exist Figure 8C , a graph 850 shows the relationship between the insertion phase distortion in degrees and the output power in dBm in response to amplitude modulation (AM-PM). Traces 866-868 corresponding to low power operation in which the first transistor 110 and the third transistor 130 are biased in class AB and class C, respectively, at a drain voltage of 28V and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28V show an increased AM-PM distortion of approximately 3-12 degrees compared to traces 861-863 corresponding to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C in a high power state are all biased at a drain voltage of 48V.

[0071] exist Fig.8D 8, a graph 870 shows the relationship between the multi-stage drain efficiency in percent and the output power in dBm. At an output power of 35 dBm, traces 886-888 show about 10-12 percentage points higher efficiency than traces 881-883, which correspond to low power operation in which the first transistor 110 and the third transistor 130 are biased in class AB and class C, respectively, at a drain voltage of 28 V and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28 V, and 881-883 correspond to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C are all biased at a drain voltage of 48 V in a high power state.

[0072] Fig. 9A , 9B, 9C, 9D, 9E, and 9F, collectively referred to as FIG9, are graphical representations 900, 910, 920, 930, 940, 950 depicting simulated operation of the device 500 of FIG5. According to an embodiment, graphs 900, 910, 920, 930, 940, and 950 depict gain, final stage drain efficiency, AM-PM, final stage drain efficiency, multi-stage drain efficiency, and tertiary drain efficiency for the device 500 configured with all transistors active at 28V in a low power mode (i.e., the first transistor 110 and the third transistor 130 operate in class AB and class C, and the second transistor 120 and the fourth transistor 140 are biased off) to compare performance. Traces 903, 904, 905, 906, 907, 908, 913, 914, 915, 916, 917, 918, 923, 924, 925, 926, 927, 928, 933, 934, 935, 936, 937, 938, 943, 944, 945, 946, 947, 948, 953, 954, 955, 956, 957, and 958. 58 are arranged so that each triple trace (e.g., 903-905, 906-908, 913-915, 916-918, 923-925, 926-928, 933-935, 936-938, 943-945, 946-948, 953-955, and 956-958) represents performance at 2.5 GHz, 2.6 GHz, and 2.7 GHz, respectively. Here, similar to the traces of FIG. 8, according to an embodiment, in low power mode, the bias conditions include: a 28 V bias applied to the drain terminals 114, 124, 134, 144 of the first power amplifier device 300 and the second power amplifier device 400, wherein the quiescent current (I DQ ) is 8.5mA, and the quiescent current of the second transistor 120 is 0mA. This is because for the first power amplifier device 300, a gate bias of -8V is applied to the second gate 122 through the second bias network 380; and a gate bias of -3.9V is applied to the third gate terminal 132 of the third transistor 130; and a gate bias of -8V is applied to the gate of the fourth transistor 140.

[0073] exist Fig. 9A , graph 900 shows the transducer gain (G T) 901 versus output power 902 in dBm. The gain of traces 903-905 from 15 to 40 dBm output power is shown to be approximately 1 dB less than traces 906-908, which correspond to low power operation in which the first transistor 110 and the third transistor 130 are both biased in class AB and class C, respectively, at a drain voltage of 28 V and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28 V, and traces 906-908 correspond to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C, all biased in a high power state at a drain voltage of 28 V.

[0074] exist Fig. 9B , a graph 910 shows the relationship between the final stage drain efficiency 911 in percent and the output power 912 in dBm. At an output power of 35 dBm, traces 913-915, which correspond to low power operation in which the first transistor 110 and the third transistor 130 are biased in class AB and class C, respectively, at a drain voltage of 28 V and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28 V, show an efficiency that is approximately 3-5 percentage points higher than traces 916-918, which correspond to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C, all biased in a high power state at a drain voltage of 28 V.

[0075] exist Fig. 9C 8, a graph 920 shows final stage drain efficiency 921 in percent versus output back-off power (OBO) 922 in dB, with the saturated power of the high power 48V state of FIG8 as a reference. Traces 923-925, corresponding to low power operation where the first transistor 110 and the third transistor 130 are biased in class AB and class C, respectively, at a drain voltage of 28V, and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28V, show the efficiency as a function of back-off power approximately 5-10 percentage points higher than traces 926-928, which correspond to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C, all biased at a drain voltage of 28V in the high power state.

[0076] exist Fig.9D, a graph 930 shows an insertion phase modulation 931 in degrees in response to amplitude modulation (AM-PM) versus an output power 932 in dBm. Traces 933-935 corresponding to low power operation where the first transistor 110 and the third transistor 130 are both biased in class AB and class C, respectively, at a drain voltage of 28V and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28V show an increased AM-PM distortion of approximately 3-5 degrees compared to traces 936-938 corresponding to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C, all biased at a drain voltage of 28V in a high power state.

[0077] exist Fig.9E , a graph 940 shows the relationship between the multi-stage drain efficiency 941 in percent and the output power 942 in dBm. At an output power of 35 dBm, traces 943-945, which correspond to low power operation in which the first transistor 110 and the third transistor 130 are biased in class AB and class C, respectively, at a drain voltage of 28 V and the second transistor 120 and the fourth transistor 140 are also biased off at a drain voltage of 28 V, show about three percentage points higher efficiency than traces 946-948, which correspond to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C, all biased at a drain voltage of 28 V in a low power state.

[0078] exist Fig.9F , a graph 950 shows multi-stage drain efficiency 951 in percent versus output power back-off 952 in dB, with the saturated output power of the 48V high power state as a reference. At a 10 dB back-off level, traces 953-955, corresponding to low power operation where the first transistor 110 and the third transistor 130 are both biased in class AB and class C, respectively, at a 28V drain voltage, and the second transistor 120 and the fourth transistor 140 are also biased off at a 28V drain voltage, traces 956-958, corresponding to the first transistor 110 and the second transistor 120 biased in class AB and the third transistor 130 and the fourth transistor 140 biased in class C, are all biased at a 28V drain voltage in the high power state.

[0079] An amplifier device includes a first input terminal, a second input terminal, a first transistor having a first control electrode and first and second current carrying electrodes, wherein the first control electrode is radio frequency (RF) coupled to the first input terminal and DC coupled to a first bias network, the first bias network is electrically coupled to the first control electrode, wherein the first bias network is configured to apply a first direct current (DC) bias to the first control electrode and is RF-isolated from the first control electrode. The amplifier device further includes: a second transistor, the second transistor including a second control electrode RF coupled to the second input terminal; and a second bias network, the second bias network is electrically coupled to the second transistor, wherein the second bias network is configured to apply a second DC bias to the second transistor and is RF-isolated from the second transistor.

[0080] For the sake of brevity, certain terminology may also be used herein for reference purposes only and, therefore, is not intended to be limiting, and the terms "first," "second," and other such numerical terms referring to structures do not imply a sequence or order unless the context clearly indicates otherwise.

[0081] As used herein, "node" means any internal or external reference point, connection point, junction, signal line, conductive element, etc., at which a given signal, logic level, voltage, data pattern, current or quantity exists. In addition, two or more nodes may be implemented by one physical element (and two or more signals may be multiplexed, modulated, or otherwise distinguished despite being received or output at a common node).

[0082] The foregoing description refers to elements or nodes or features being "connected" or "coupled" together. As used herein, unless otherwise expressly stated, "connected" means that one element is directly joined to (or directly communicates with) another element, and not necessarily mechanically joined. Likewise, unless otherwise expressly stated, "coupled" means that one element is directly or indirectly joined to (or directly or indirectly communicates with) another element, and not necessarily mechanically joined. Thus, although the schematic diagrams shown in the figures depict an exemplary arrangement of elements, additional intervening elements, devices, features, or assemblies may be present in the embodiments of the depicted subject matter.

[0083] Although at least one exemplary embodiment has been presented in the foregoing specific embodiments, it should be understood that there are a large number of variations. It should also be understood that one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing specific embodiments will provide a convenient guide for implementing the described one or more embodiments to those skilled in the art. It should be understood that various changes may be made to the function and arrangement of the elements without departing from the scope defined by the claims, and the scope defined by the claims includes known equivalents and foreseeable equivalents at the time of filing this patent application.

Claims

1. An amplifier device, characterized in that: include: A first amplifier is electrically coupled to the first input terminal and the first output terminal, wherein the first amplifier comprises: a first transistor comprising a first control electrode, a first current carrying electrode, and a second current carrying electrode, configured to support current flow between the first current carrying electrode and the second current carrying electrode, wherein the first control electrode is configured to control the current flow between the first current carrying electrode and the second current carrying electrode, wherein the first control electrode is radio frequency (RF) coupled to the first input terminal, and wherein the first current carrying electrode is electrically coupled to the first output terminal; a first bias network electrically coupled to the first control electrode, wherein the first bias network is configured to apply a first direct current (DC) bias to the first control electrode and is RF isolated from the first control electrode; a second transistor including a second control electrode, a third current carrying electrode, and a fourth current carrying electrode, configured to support current flow between the third current carrying electrode and the fourth current carrying electrode, wherein the second control electrode is configured to control the current flow between the third current carrying electrode and the fourth current carrying electrode, wherein the second control electrode is RF coupled to the first input terminal, wherein the third current carrying electrode is electrically coupled to the first output terminal; and A second bias network is electrically coupled to the second control electrode, wherein the second bias network is configured to apply a second DC bias to the second control electrode and is RF isolated from the second control electrode.

2. The amplifier device according to claim 1, characterized in that Also includes: A second amplifier electrically coupled to the second input terminal and the second output terminal, wherein the second amplifier comprises: a third transistor comprising a third control electrode, a fifth current carrying electrode, and a sixth current carrying electrode, configured to support current flow between the fifth current carrying electrode and the sixth current carrying electrode, wherein the third control electrode is configured to control the current flow between the fifth current carrying electrode and the sixth current carrying electrode, wherein the third control electrode is RF coupled to the second input terminal, and wherein the fifth current carrying electrode is electrically coupled to the second output terminal; a third bias network electrically coupled to the third control electrode, wherein the third bias network is configured to apply a third DC bias to the third control electrode and to be RF isolated from the third control electrode; a fourth transistor comprising a fourth control electrode, a seventh current carrying electrode, and an eighth current carrying electrode, configured to support current flow between the seventh current carrying electrode and the eighth current carrying electrode, wherein the fourth control electrode is configured to control the current flow between the seventh current carrying electrode and the eighth current carrying electrode, wherein the fourth control electrode is radio frequency (RF) coupled to the second input terminal, and wherein the seventh current carrying electrode is electrically coupled to the second output terminal; and A fourth bias network is electrically coupled to the fourth control electrode, wherein the fourth bias network is configured to apply a fourth DC bias to the fourth control electrode and to be RF isolated from the fourth control electrode.

3. The amplifier device according to claim 2, characterized in that Also includes: a transmission line having a phase shift and configured to electrically couple the first output terminal and the second output terminal; as well as An impedance transformer is electrically coupled to a summing node at a group consisting of the first output terminal and the second output terminal.

4. The amplifier device according to claim 3, characterized in that Also included is a splitter device having a splitter input and a first splitter output and a second splitter output, and configured to divide a signal delivered to the splitter input between the first splitter output and the second splitter output using a phase difference between the first splitter output and the second splitter output, wherein the difference between the phase difference and the phase shift of the transmission line is less than 20%, wherein the first input end is electrically coupled to the first splitter output, and the second input end is electrically coupled to the second splitter output.

5. The amplifier device according to any one of claims 2 to 4, characterized in that In a Doherty amplifier configuration, the first amplifier is configured as a carrier amplifier and the second amplifier is configured as a peaking amplifier.

6. An amplifier device according to any of the preceding claims, characterized in that The first amplifier is configured to operate in a first state and to operate in a second state, wherein: When in the first state, the first transistor and the second transistor are configured to operate under the following conditions: a first bias is applied to the first bias network and a second bias is applied to the second bias network, so that when the first transistor is operated at a saturated output power, the first bias and the second bias allow an RF current of at least 50% of a maximum current of the second transistor to flow through the second transistor; and a third bias is applied to the first current carrying electrode and the third current carrying electrode; and When in the second state, the first transistor and the second transistor are configured to operate under the following circumstances: the first bias is applied to the first bias network, and a fourth bias is applied to the second bias network, so that when the first transistor operates at a saturated output power and the current is greater than 50% of the maximum current of the first transistor, the fourth bias allows an RF current less than 10% of the maximum current of the second transistor to flow from the third current carrying electrode of the second transistor to the fourth current carrying electrode of the second transistor; and a fifth bias is applied to the first current carrying electrode and the third current carrying electrode.

7. An amplifier device according to any of the preceding claims, characterized in that The first transistor is configured as a field effect transistor, wherein: The first control electrode is configured as a gate electrode; The first current carrying electrode is configured as a drain electrode; and The second current carrying element is configured as a source electrode.

8. An amplifier device according to any of the preceding claims, characterized in that Also includes: a first coupling element having a first end and a second end, wherein the second end is electrically coupled to the first control electrode; as well as A second coupling element having a third end and a fourth end, wherein the fourth end is electrically coupled to the second control electrode, and wherein the first end is electrically coupled to the third end.

9. The amplifier device according to claim 8, characterized in that A driver amplifier including a transistor is electrically coupled to the first end of the first coupling element and the third end of the second coupling element.

10. The amplifier device according to claim 8 or 9, characterized in that It also includes a first input matching network configured to provide impedance matching for the first transistor at a fundamental frequency and a second input matching network configured to provide impedance matching for the second transistor at a fundamental frequency, the first input matching network being coupled to the first control electrode and the second input matching network being coupled to the second control electrode.

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