Systems and methods for providing analog output signals using class D amplifiers

Abstract

The invention relates to a system and method for providing an analog output signal using a class D amplifier. A method for providing an analog output signal includes (a) amplifying a digital first internal signal using a first class D amplifier to produce a digital first output signal, (b) filtering the digital first output signal to produce an analog first output signal, (c) providing the analog first output signal to a first load, (d) sensing the analog first output signal to generate an analog first feedback signal, (e) converting the analog first feedback signal into a digital first feedback signal, and (f) configuring the first class D amplifier for an impedance of the first load by generating the digital first internal signal based at least in part on the digital first feedback signal.

Description

Background Art

[0001] Analog communications are widely used in factory automation applications and process control applications. For example, programmable logic controllers, programmable automation controllers, and digital control systems frequently used in factory automation applications and process control applications are typically configured to generate analog output signals. Summary of the invention

[0002] In an embodiment, a method for providing an analog output signal includes: (i) using a first class-D amplifier to amplify a digital first internal signal to generate a digital first output signal, (ii) filtering the digital first output signal to generate an analog first output signal, (iii) providing the analog first output signal to a first load, (iv) sensing the analog first output signal to generate an analog first feedback signal, (v) converting the analog first feedback signal into a digital first feedback signal, and (vi) configuring the first class-D amplifier for the impedance of the first load by generating a digital first internal signal based at least in part on the digital first feedback signal.

[0003] In an embodiment, a programmable controller includes: (i) a processing system configured to generate a digital first internal signal based at least in part on (a) programming instructions provided to the processing system and (b) a digital first feedback signal; (ii) a first Class-D amplifier configured to amplify the digital first internal signal to generate a digital first output signal; (iii) a first filter configured to filter the digital first output signal to generate an analog first output signal; (iv) a first sensing circuit system configured to sense the analog first output signal to generate an analog first feedback signal; and (v) a first analog-to-digital converter (ADC) configured to convert the analog first feedback signal into a digital first feedback signal.

[0004] In an embodiment, an electrical environment includes a programmable controller and a first load. The programmable controller includes: (i) a processing system configured to generate a digital first internal signal based at least in part on (a) programming instructions provided to the processing system and (b) a digital first feedback signal; (ii) a first class-D amplifier configured to amplify the digital first internal signal to generate a digital first output signal; (iii) a first filter configured to filter the digital first output signal to generate an analog first output signal; (iv) a first sensing circuit system configured to sense the analog first output signal to generate an analog first feedback signal; and (v) a first analog-to-digital converter (ADC) configured to convert the analog first feedback signal into a digital first feedback signal. The first load is powered by the analog first output signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 It is a block diagram of the electrical environment including the programmable controller and the load.

[0006] Figure 2 is a block diagram of an electrical environment including a system using a Class-D amplifier to provide an analog output signal according to an embodiment.

[0007] Figure 3 It is shown Figure 2 A graph of the voltage of a digital output signal in one example of operation of an embodiment of an electrical environment.

[0008] Figure 4 It is shown Figure 2 A graph of the current of a digital output signal in one example of operation of an embodiment of an electrical environment.

[0009] Figure 5 yes Figure 2 Schematic diagram of one embodiment of a Class D amplifier of the electrical environment.

[0010] Figure 6 yes Figure 2 Schematic diagram of one embodiment of a filter for an electrical environment.

[0011] Figure 7 yes Figure 2 Schematic diagram of one embodiment of electrical environment sensing circuitry.

[0012] Figure 8 is a block diagram of an electrical environment including a programmable controller including a Class D amplifier according to an embodiment.

[0013] Fig. 9is a flow chart of a method for generating an analog output signal using a class D amplifier according to an embodiment.

[0014] Fig.10 is a block diagram of an electrical environment including a Figure 8 Alternative embodiments of programmable controllers.

[0015] Fig.11 Show Fig.10 An embodiment of an output module of a programmable controller.

[0016] Fig.12 yes Fig.10 Block diagram of an alternative embodiment of an electrical environment. DETAILED DESCRIPTION

[0017] Analog signals generated by a programmable controller, such as a programmable logic controller (PLC), a programmable automation controller (PAC), or a digital control system (DCS), may need to drive loads with a wide range of possible impedance values. For example, Figure 1 1 is a block diagram of an electrical environment 100 including a programmable controller 102 and a load 104. The programmable controller 102 is composed of a fixed voltage V s The programmable controller 102 is powered by a power supply, and the programmable controller 102 is configured to generate an analog output current signal I with a value of up to 20 milliamperes (mA) by controlling an amplifier within the programmable controller 102. o , the amplifier includes one or more transistors (not shown) operating in their respective saturation regions. In this example, the impedance of the load 104 can be in the range of zero ohms to 1,000 ohms. Therefore, the voltage V across the load 104 is o may vary significantly depending on the impedance of the load 104. For example, if the analog output current signal I o has a value of 20 mA, and the load 104 has an impedance of 1,000 ohms, then the voltage V o The value of is 20 volts. At the other extreme, if the analog output current signal I o has a value of 20 mA, and the load 104 has zero impedance, then the voltage V o The value of is zero.

[0018] Voltage V o Low values ​​of may result in significant power dissipation in the programmable controller 102. For example, assuming the analog output current signal I o With a value of 20mA, the voltage V s The value of is 20 volts, and the load 104 has zero impedance, so that the voltage V oThe value of is zero. In this case, the power dissipation (P) in the programmable controller 102 is equal to P = (I o )(V s ), and thus the power dissipation in the programmable controller 102 is P = (20 mA) (20 volts) = 0.400 watts (W) = 400 milliwatts (mW). While a power dissipation of 400 mW in the programmable controller 102 is acceptable in some applications, this relatively large power dissipation may limit the number of output channels that can be supported by a single programmable controller because the programmable controller cannot be adequately cooled if multiple channels are driving low impedance loads. For example, assume that the programmable controller 102 is modified to support eight output channels, i.e., the programmable controller 102 is configured to generate eight different analog output current signals for powering eight different loads. In this case, the power dissipation in the programmable controller 102 may be as high as 3.2 watts, and thus adequately cooling the programmable controller 102 may be challenging, particularly in applications where the programmable controller 102 is located within a cabinet that limits heat transfer from the programmable controller 102. The cooling challenge may be particularly severe in applications of the programmable controller 102 where forced air cooling is not desired, such as in dusty applications or noise-sensitive applications.

[0019] Disclosed herein are systems and methods for providing analog output signals using a Class D amplifier, which can help alleviate the above-mentioned problems. Specific embodiments of the new system and method configure the Class D amplifier for the impedance of the load by controlling the operation of the Class D amplifier based at least in part on the voltage across the load and / or the current flowing through the load, thereby helping to minimize power dissipation when the load has a low impedance. In addition, some embodiments do not require a dedicated power supply for the Class D amplifier, which promotes low system cost, small system, and system simplicity. In addition, certain embodiments share one or more analog-to-digital converters (ADCs) between multiple output channels, thereby promoting low system cost, small system size, and system simplicity. Therefore, the new system and method can enable a programmable controller to support a larger number of output channels than is feasible using conventional technology.

[0020] Figure 22 is a block diagram of an electrical environment 200 that includes an embodiment of a new system for providing an analog output signal using a class D amplifier. The electrical environment 200 includes a class D amplifier 202, a filter 204, a logic and interface circuit system 206, a sensing circuit system 208, an ADC 210, and a load 212. The class D amplifier 202 is electrically coupled between an internal node 214 and a digital output node 216, and the filter 204 is electrically coupled between the digital output node 216 and the analog output node 218. The load 212 is electrically coupled between the analog output node 218 and a reference node 220, wherein the reference node 220 is depicted as a ground node, such as an earth ground node or a chassis ground node. However, it should be understood that the reference node 220 need not be a ground node, and the reference node 220 can therefore be at a different potential than the earth ground or the chassis ground. The class D amplifier 202 is powered at least in part by a first power rail 222 and a second power rail 224. In some embodiments, the first power rail 222 is at a positive voltage relative to the reference node 220, and the second power rail 224 is at a negative voltage relative to the reference node 220, so that the first power rail 222 and the second power rail 224 together form a split power supply. In some other embodiments, the second power rail 224 is the same as the reference node 220, and the first power rail 222 is at a positive voltage or a negative voltage relative to the reference node 220, so that the first power rail 222 and the second power rail 224 together form a unipolar power supply.

[0021] Logic and interface circuitry 206 (hereinafter referred to as circuitry 206) is configured to generate a digital internal signal D at internal node 214. int The circuit system 206 is optionally configured to generate a digital internal signal D based at least in part on one or more input signals 226 to the circuit system 206. int The class D amplifier 202 is configured to amplify the digital internal signal D int , to generate a digital output signal D at the digital output node 216 o . Digital output signal D o (a) The current I flowing from the class D amplifier 202 to the filter 204 via the digital output node 216 do and (b) the voltage V on the digital output node 216 relative to the reference node 220 do The voltage V as a digital voltage do has an average value, which may alternatively be referred to as the voltage V do The direct current (DC) component of , which can be positive, negative, or zero relative to the reference node 220.

[0022] For example, Figure 3 is the voltage V doThe graph 300 of time shows that the first power rail 222 and the second power rail 224 together form a voltage V with respect to the reference node 220. 222 and voltage V 224 An exemplary operation of the electrical environment 200 in an embodiment of a split power supply. Figure 3 In the example of FIG. 1 , the class D amplifier 202 responds to the digital internal signal D int The digital output node 216 is driven between the first power rail 222 and the second power rail 224. Figure 3 In the example, for 75% of each switching cycle of the class D amplifier 202, the voltage V do At voltage V 222 , and for 25% of each switching cycle of the Class D amplifier 202, the voltage V do At voltage V 224 Therefore, for Figure 3 For example, the voltage V do The average value (V do_avg ) is given by the following equation 1.

[0023] V do_avg =(0.75)·(V 222 -V 224 )+V 224 (Equation 1)

[0024] In addition, the class D amplifier 202 repeatedly drives the current I do reaches a maximum and a minimum value, with a finite slope between these two values. The current I do It also has an average value, which is alternatively called the current I do The DC component of , which can be positive, negative, or zero. For example, Figure 4 is the current I do The graph 400 of the current I do is an example of the operation of the continuous electrical environment 200. The current I do The current I do With I do_avg The average value of .

[0025] Figure 5 is a schematic diagram of a class D amplifier 500, the class D amplifier is Figure 2, but it should be understood that the class D amplifier 202 may be implemented in other ways without departing from the scope thereof. The class D amplifier 500 includes a modulator 502, a first switching device 504, and a second switching device 506. The first switching device 504 is electrically coupled between the first power rail 222 and the digital output node 216, and the second switching device 506 is electrically coupled between the digital output node 216 and the second power rail 224. Each of the first switching device 504 and the second switching device 506 includes, for example, one or more transistors and a driving circuit system that drives the one or more transistors. The first switching device 504 is controlled by a first control signal φ1 generated by the modulator 502, and the second switching device 506 is controlled by a second control signal φ2 generated by the modulator 502. The modulator 502 is responsive to the digital internal signal D int The first control signal φ1 and the second control signal φ2 are generated so that the digital output signal D o is the digital internal signal D int . Certain embodiments of the modulator 502 use a pulse width modulation (PWM) technique or a pulse frequency modulation (PFM) technique to generate the first control signal φ1 and the second control signal φ2. In some embodiments, the modulator 502 is a sigma delta modulator. It should be noted that the first switching device 504 and the second switching device 506 repeatedly switch between their respective on states (conductive states) and their respective off states (non-conductive states) in response to the control signal φ1 and the control signal φ2, respectively, so that the first switching device 504 and the second switching device 506 do not operate in their saturation regions.

[0026] Reference again Figure 2 , the filter 204 is configured to convert the digital output signal D o Converted into analog output signal A o . Analog signal A o Ideally equal to the digital output signal D o The average value of the analog signal A o will not be exactly equal to the digital output signal D o The average value of the filter 204 cannot be obtained from the analog output signal A o The switching frequency component of the class D amplifier 202 is completely removed. The analog output signal A o The current I flowing out of the filter 204 to the analog output node 218 (a) ao and (b) the voltage V on the analog output node 218 relative to the reference node 220 ao In some embodiments, the filter 204 includes an inductor-capacitor filter. For example, Figure 66 is a schematic diagram of a filter 600, which is one possible embodiment of the filter 204, but it should be understood that the filter 204 may be implemented in other ways without departing from its scope. The filter 600 includes an inductor 602 and a capacitor 604. The inductor 602 is electrically coupled between the digital output node 216 and the analog output node 218, and the capacitor 604 is electrically coupled between the analog output node 218 and the reference node 220.

[0027] Reference again Figure 2 , the filter 204 provides an analog output signal A to the load 212 via the analog output node 218 o , and therefore the voltage across the load 212 is equal to the voltage across the analog output node 218 V ao In addition, the current I ao Flows through the load 212. In some embodiments, the impedance of the load 212 may be independent of the analog output signal A. o The impedance of the load 212 may vary within a wide range of values ​​independently of the analog output signal A. o The magnitude and / or phase of the load 212 may vary. For example, in some embodiments, the impedance of the load 212 may be in the range from zero ohms to 750 ohms. As another example, in some other embodiments, the impedance of the load 212 may be in the range from zero ohms to 1,000 ohms. However, it should be understood that the load 212 is not limited to any particular impedance range. For example, in some embodiments, the impedance of the load 212 may be greater than 1,000 ohms. As another example, in some embodiments, the minimum impedance of the load 212 is greater than zero. In addition, in some embodiments, the impedance of the load 212 may be unknown before the class D amplifier 202 is deployed in the electrical environment 200. In some embodiments, the load 212 includes industrial devices such as actuators, valves, motors, motor starters, solenoids, alarms, lights, relays, counters, pumps, fans, printers, heaters, compressors, sequencers, etc.

[0028] The sensing circuit system 208 is configured to detect the analog output signal A o Sensing to generate an analog feedback signal A fb . Analog feedback signal A fb For example, the voltage V ao and current I ao One or more of . Figure 2 The connection between the sensing circuit system 208 and the analog output node 218 is not shown. In some embodiments, the sensing circuit system 208 includes: one or more components (not shown), such as a aoand one or more switches for enabling the sensing circuit system 208 to selectively sense the voltage V in response to a control signal c generated by the circuit system 206; ao and current I ao One of them is sensed.

[0029] For example, Figure 7 is a schematic diagram of a sensing circuit system 700, which is one possible embodiment of the sensing circuit system 208, but it should be understood that the sensing circuit system 208 can be implemented in other ways without departing from its scope. The sensing circuit system 700 includes an amplifier 702, a first switch 704, a second switch 706, and a current sensing resistor 708. The current sensing resistor 708 is electrically coupled between the filter 204 and the analog output node 218, and therefore the voltage V across the current sensing resistor 708 is r With current I ao The amplifier 702 is configured to generate an analog feedback signal A proportional to the magnitude of the voltage across its input terminals. fb . The first switch 704 is configured to: (a) electrically couple the non-inverting input of the amplifier 702 to the side of the current sensing resistor 708 connected to the filter 204 when the control signal c is de-asserted; and (b) electrically couple the non-inverting input of the amplifier 702 to the side of the current sensing resistor 708 connected to the analog output node 218 when the control signal c is asserted. The second switch 706 is configured to: (a) electrically couple the inverting input of the amplifier 702 to the side of the current sensing resistor 708 connected to the analog output node 218 when the control signal c is de-asserted; and (b) electrically couple the inverting input of the amplifier 702 to the reference node 220 when the control signal c is asserted. In this way, when the control signal c is de-asserted, the analog feedback signal A fb Indicates current I ao , and when the control signal c is asserted, the analog feedback signal A fb Indicates voltage V ao In some alternative embodiments, the first switch 704 and the second switch 706 are controlled by different respective control signals instead of being controlled by a common control signal c.

[0030] Reference again Figure 2 ADC 210 is configured to convert the analog feedback signal A fb Converted into digital feedback signal D fb , the digital feedback signal D fb is provided to the circuit system 206. The circuit system 206 is configured to fband generating a digital internal signal D based on one or more input signals 226 int The class D amplifier 202 is configured for the impedance of the load 212 so as to amplify the digital internal signal D int While adjusting the current I ao or voltage V ao In other words, the electrical environment 200 not only amplifies the internal digital signal D int , and the electrical environment 200 can also realize the current I ao or voltage V ao The digital signal D is amplified in the manner of the expected value int , regardless of the impedance of the load 212. For example, some embodiments of the circuit system 206 are configured to generate the error signal ERR according to the following equation 2, where K is a proportionality constant, D ref is a digital reference value, such as the current I ao The desired value or voltage V ao For example, in some embodiments, the digital reference value D ref Equal to the current I ao The desired value or voltage V ao Specific embodiments of the circuit system 206 are configured to generate the digital internal signal D based on one or more of the input signals 226 in a manner that minimizes the error signal ERR. int , so that the current I ao or voltage V ao Therefore, in these embodiments, the electrical environment 200 implements a closed loop control system to regulate the current I ao and voltage V ao One or more of (such as in response to a change in the impedance of load 212) to configure class-D amplifier 202 for the impedance of load 212.

[0031] ERR=K·(D fb -D ref ) Equation 2

[0032] For example, assume that (a) the circuit system 206 determines the current I according to the input signal 226 ao The magnitude of D should be 20 mA, and (b) the impedance of load 212 can vary between zero ohms and 1,000 ohms. fb Will represent the current I ao The value of the digital reference value D ref The circuit system 206 will generate a digital internal signal D as required. int , to achieve a 20mA current Iao The magnitude of the digital internal signal D is determined regardless of the impedance of the load 212. For example, if the load 212 has an impedance of 50 ohms, the circuit system 206 will generate the digital internal signal D as required. int , so that the voltage V od The average value is 1 volt, which will result in a current of I ao The magnitude of is 20 mA, thereby configuring the Class D amplifier for a 50 ohm load. As another example, if the load 212 has an impedance of 750 ohms, the circuit system 206 will generate the digital internal signal D as required. int , so that the voltage V od The average value is 15 volts, which will result in a current of I ao The value of is 20mA, thus configuring the Class D amplifier for a 750 ohm load.

[0033] As another example, assume that (a) circuit system 206 determines voltage V according to input signal 226 ao The magnitude of D should be 5 volts, and (b) the impedance of load 212 can vary between 200 ohms and 1,000 ohms. fb Will represent the voltage V ao The value of the digital reference value D ref will represent 5 volts. The circuit system 206 will generate the digital internal signal D as required int , to achieve a voltage of 5 volts V ao The magnitude of , regardless of the impedance of load 212. For example, if load 212 has an impedance of 200 ohms, circuit system 206 will generate digital internal signal D as required. int , so that the current I od The average value is 25mA, which will result in a voltage of V ao The magnitude of is 5 volts, thereby configuring the Class D amplifier for a 200 ohm load. As another example, if the load 212 has an impedance of 1,000 ohms, the circuit system 206 will generate the digital internal signal D as required. int , so that the current I od The average value is 5 mA, which will result in a voltage of V ao The magnitude of is 5 volts, thus configuring the Class D amplifier for a 1,000 ohm load.

[0034] It should be understood that a Class D amplifier, such as Class D amplifier 202 of electrical environment 200, does not include transistors that operate continuously in their saturation region. Therefore, even when load 212 has a low impedance, Class D amplifier 202 does not dissipate a large amount of power. In addition, Class D amplifier 202 is able to power load 212 when load 212 has a high impedance. This ability of Class D amplifier 202 to drive loads having a wide range of possible impedances may be particularly advantageous in embodiments where the impedance of load 212 is unknown prior to deploying Class D amplifier 202 in electrical environment 200.

[0035] One possible application of the new system and method using a Class D amplifier to provide an analog output signal is a programmable controller application, such as a PLC application, a PAC application, or a DCS application. For example, Figure 8 8 is a block diagram of an electrical environment 800 that includes an example of a programmable controller 802, a cable 804, and a load 212. The cable 804 electrically couples the filter 204 to the load 212, and thus the cable 804 is part of the analog output node 218. In some embodiments, the cable 804 is relatively long, for example, tens of meters long, hundreds of meters long, or even longer.

[0036] Programmable controller 802 includes instances of class D amplifier 202, filter 204, sensing circuitry 208, and ADC 210. In addition, Figure 2 The circuit system 206 is implemented by the processing system 806, the input module 808, the storage system 810, the digital interface 812 and the optional programming interface 814 in the programmable controller 802. Two or more of the aforementioned elements of the programmable controller 802 may be combined in part or in whole without departing from the scope of the present invention. The input module 808 is configured to receive one or more input signals 226 from outside the programmable controller 802 and use the one or more input signals as digital input signals D inp Provided to the processing system 806. The input signal 226 can be an analog input signal, a digital signal, or a combination of an analog input signal and a digital input signal. In embodiments where the input signal 226 includes an analog input signal, the input module 808 includes at least one ADC (not shown). In some embodiments, the input signal 226 is generated by one or more of a switch, a sensor, and an encoder.

[0037] The storage system 810 stores programming instructions 816 (such as in the form of software and / or firmware) for execution by the processing system 806. The storage system 810 is optionally configured to store additional information, such as a digital input signal D for use by the processing system 806. inp The processing system 806 is configured to perform operations based at least in part on the programming instructions 816 and the digital feedback signal Dfb And optionally further according to the digital input signal D inp To generate the digital internal signal D int '. In addition, the processing system 806 is configured to at least partially according to the programming instructions 816 and optionally further according to the digital input signal D inp To generate the control signal c. The digital interface 812 is configured to receive the digital internal signal D from the processing system 806 int ', and the digital interface 812 is configured to convert the digital internal signal D int 'As a digital internal signal D int Provided to the class D amplifier 202. In some embodiments, the digital internal signal D int Equivalent to the digital internal signal D int ', while in other embodiments, the digital internal signal D int is the internal signal D int 'Derived, but not identical to the digital internal signal D int '. In a specific embodiment, the digital internal signal D int ' is a serial communication signal. In some alternative embodiments, the digital interface 812 is omitted, and the processing system 806 is configured to directly generate the digital internal signal D int The class D amplifier 202 and the filter 204 are configured to respond to the digital internal signal D int The analog output signal A is generated o , as mentioned above Figure 2 In addition, the sensing circuit system 208 and the ADC 210 are configured together to generate a digital feedback signal D fb , as mentioned above Figure 2 discussed.

[0038] The programmable controller 802 may be, for example, a programmable logic controller, a programmable automation controller, or a programmable controller of a digital control system, such as based on a configuration of programming instructions 816. For example, the programming instructions 816 may include (a) instructions that cause the programmable controller 802 to operate as a programmable logic controller, (b) instructions that cause the programmable controller 802 to operate as a programmable automation controller, or (c) instructions that cause the programmable controller 802 to operate as a programmable controller of a digital control system.

[0039] The optional programming interface 814 is capable of creating and / or modifying programming instructions 816. Certain embodiments of the programming interface 814 include one or more user input devices and / or user output devices, such as a keyboard, a switch, a mouse, a touch pad, a screen, a monitor, a printer, etc. In addition, some embodiments of the programming interface 814 include one or more interfaces to external systems, such as an electrical interface (e.g., a Universal Serial Bus (USB) electrical interface and / or an Ethernet electrical interface), a wireless interface (e.g., a Bluetooth wireless interface, a Wi-Fi wireless interface, a cellular wireless interface, and / or a satellite wireless interface), an optical interface (e.g., a fiber optic cable interface and / or a free space optical interface), and / or a logical interface (e.g., an application programming interface (API)).

[0040] Fig. 9 is a flow chart of a method 900 for generating an analog output signal using a Class D amplifier, which is one example of the operation of programmable controller 802. However, it should be understood that programmable controller 802 is not limited to operating according to method 900.

[0041] In block 902 of method 900, processing system 806 obtains one or more input signals 226 as digital input signals D inp In block 904 of method 900, processing system 806 processes the digital input signal D inp and programming instruction 816 to determine the digital reference value D ref , where the digital reference value D ref Indicates analog output signal A o In one example of block 904, the processing system 806 executes an algorithm defined by the programming instructions 816, wherein the algorithm generates a signal that varies with the digital input signal D inp The digital reference value D ref In block 906, the processing system 806 executes the programming instruction 816 to convert the digital internal signal D int The initial value of ' is set to follow the digital reference value D ref In one example of block 906, the processing system 806 executes the programming instruction 816 to convert the digital internal signal D int The initial value of ' is set to the digital reference value D ref .

[0042] In block 908 of method 900, processing system 806 receives a digital feedback signal D from ADC 210. fb In block 910 of method 900, processing system 806 executes programming instructions 816 to determine error signal ERR, such as by executing equation 2 above or by executing a variation of equation 2 above, where error signal ERR represents digital feedback signal D fb and digital reference value Dref In decision block 912, processing system 806 executes program instructions 816 to determine whether error signal ERR is equal to zero, or whether error signal ERR is within a predetermined tolerance of zero. If the result of decision block 912 is yes, method 900 proceeds to decision block 914, in which processing system 806 executes program instructions 816 to determine whether digital input signal D inp If the result of decision block 914 is yes, method 900 returns to block 902 to obtain one or more new digital input signals D inp , and if the result of decision block 914 is no, method 900 returns to block 908 to obtain an updated digital feedback signal D fb .

[0043] Referring again to decision block 912, if the result of decision block 912 is negative, method 900 proceeds from decision block 912 to decision block 916 where processing system 806 executes programming instructions 816 to determine the digital feedback signal D fb Is it greater than the digital reference value D? ref If the answer to decision block 916 is yes, then the analog output signal A o The magnitude of is too large, and therefore method 900 proceeds to block 918 where processing system 806 executes programming instruction 816 to convert digital internal signal D int 'Decreases, and thus reduces the analog output signal A o On the other hand, if the result of decision block 916 is no, the analog output signal A o is too small, and therefore method 900 proceeds to block 920 where processing system 806 executes programming instructions 816 to convert digital internal signal D int 'Increases, and thereby increases the analog output signal A o The method 900 proceeds from block 918 or block 920 to decision block 914 (described above). Fig. 9 The method 900 is not shown with a "stop" block, but it is understood that the processing system 806 can interrupt the method 900 at any time, such as in response to disabling the generation of the analog output signal A. o signal.

[0044] Reference again Figure 8 , the programmable controller 802 can be modified to support additional channels, that is, to be able to generate analog output signals A for driving multiple different corresponding loads o For example, Fig.101 is a block diagram of an electrical environment 1000 including a programmable controller 1002 and N loads 212, where N is an integer greater than one. In this document, specific instances of items may be referred to by using numbers in parentheses (e.g., load 212(1)), while numbers without parentheses refer to any such item (e.g., load 212). Programmable controller 1002 is programmable controller 802( Figure 8 ) also includes N output modules 1004 and a multiplexer 1007. Each output module 1004 includes at least a corresponding instance of a class D amplifier 202, a filter 204, and a sensing circuit system 208. The details of the output modules 1004 are not described in detail. Fig.10 However, Fig.11 N output modules 1104 are shown, where output modules 1104 ( 1 )- 1104 (N) are embodiments of output modules 1004 ( 1 )- 1004 (N), respectively.

[0045] Programmable controller 1002 additionally includes processing system 1006 and programming instructions 1016 to replace processing system 806 and programming instructions 816, respectively. In addition, processing system 1006 is configured to generate N digital internal signals D int ', that is, the corresponding digital internal signal D for each output module 1004 int ', rather than a single digital internal signal D int 'In addition, the processing system 1006 is similar to Figure 8 For example, in some embodiments, the processing system 1006 is configured to perform operations based at least in part on the programming instructions 1016 and optionally further based on the digital input signal D inp To generate each digital internal signal D int '. In some embodiments, each digital internal signal D int ' may have different corresponding values ​​at any given time, and in some other embodiments, two or more digital internal signals D int ' have a common value at any given time. In addition to the programming instruction 1016 being able to support N digital internal signals D int Programming instruction 1016 is similar to programming instruction 816 except that the control signal c between processing system 1006 and output module 1004 is not shown in FIG. Fig.10 However, it should be understood that in some embodiments, the processing system 1006 provides corresponding control c to each output module 1004, such as to control the corresponding analog feedback signal A generated by the output module fb It represents the current I ao Or voltage V ao .

[0046] The multiplexer 1007 is configured to couple the analog feedback signal A to the input 1008 of the ADC 210. fb For example, in some embodiments, the multiplexer 1007 is configured to selectively multiplex one analog feedback signal A at a given time in response to a control signal m from the processing system 1006. fb The example is communicatively coupled to the ADC 210, so that the ADC 210 can be shared by all N output modules 1004. For example, in a specific embodiment, the processing system 1006 generates a control signal m to cause the multiplexer 1007 to sequentially transmit the feedback signal A to the multiplexer 1007. fb is communicatively coupled to the ADC 210 so that each feedback signal A fb In contrast to each other feedback signal A fb The different corresponding times are periodically coupled to the ADC 210 in a communicative manner. Therefore, in a particular embodiment, the processing system 1006 sequentially receives the corresponding digital feedback signal D of each output module 1004. fb , and the processing system 1006 is based at least in part on the corresponding digital feedback signal D fb To generate each digital internal signal D int '.

[0047] It should be noted that not only do all channels of the programmable controller 1002 share the ADC 210, but some embodiments of the programmable controller 1002 only require N inductors (i.e., the corresponding inductors of the filter 204 of each output module 1004) and do not include any required power supply inductors. In this way, the configuration of the programmable controller 1002 promotes small size, low complexity, and low cost of the programmable controller.

[0048] The programmable controller 1002 may be modified to omit the multiplexer 1007 and include a corresponding ADC 210 for each channel. For example, Fig.12 is a block diagram of electrical environment 1200, which is a block diagram of electrical environment 1000 ( Fig.10 ), includes a programmable controller 1202 in place of the programmable controller 1002. The programmable controller 1202 differs from the programmable controller 1002 in that: (a) the multiplexer 1007 is omitted from the programmable controller 1202, and (b) the programmable controller 1202 includes a corresponding ADC 210 for each channel. Each ADC 210 is configured to convert a corresponding analog feedback signal A fb Converted into the corresponding digital feedback signal D fb , and each digital feedback signal D fbThe processing system 1006 is communicatively coupled to the processing system 1006. In this way, the processing system 1006 can simultaneously receive multiple digital feedback signals D fb , and certain embodiments of the processing system 1006 are accordingly configured to simultaneously generate a plurality of digital internal signals D int '.

[0049] Function combination

[0050] The above functions can be combined in various ways without departing from the scope of the present invention. The following examples illustrate some possible combinations.

[0051] (A1) A method for providing an analog output signal comprises: (1) using a first class-D amplifier to amplify a digital first internal signal to generate a digital first output signal; (2) filtering the digital first output signal to generate an analog first output signal; (3) providing the analog first output signal to a first load; (4) sensing the analog first output signal to generate an analog first feedback signal; (5) converting the analog first feedback signal into a digital first feedback signal; and (6) configuring the first class-D amplifier for the impedance of the first load by generating a digital first internal signal based at least in part on the digital first feedback signal.

[0052] (A2) In the method denoted as (A1), sensing the analog first output signal may include one of: sensing a voltage across the first load; and sensing a magnitude of a current flowing through the first load.

[0053] (A3) In any of the methods denoted as (A1) and (A2), the impedance of the first load may be varied independently of the state of the analog first output signal.

[0054] (A4) In any of the methods represented as (A1) to (A3), the impedance of the first load may be in the range from zero ohms to 1,000 ohms.

[0055] (A5) In any of the methods represented as (A1) to (A4), the first load may include an industrial device.

[0056] (A6) In any of the methods represented as (A1) to (A5), the analog first output signal may be a current signal.

[0057] (A7) In any of the methods represented as (A1) to (A5), the analog first output signal may be a voltage signal.

[0058] (A8) In any of the methods represented as (A1) to (A7), generating a digital first internal signal based at least in part on a digital first feedback signal may include generating the digital first internal signal to achieve an average value of the digital first output signal, which varies with the impedance of the first load.

[0059] (A9) In any of the methods represented as (A1) to (A8), generating a digital first internal signal based at least in part on a digital first feedback signal may include generating a digital first internal signal based at least in part on a difference between the digital first feedback signal and a first reference value.

[0060] (A10) Any method represented by methods (A1) to (A9) may also include: (1) using a first analog-to-digital converter (ADC) to convert an analog first feedback signal into a digital first feedback signal; and (2) multiplexing the analog first feedback signal with an analog second feedback signal before the input of the first ADC.

[0061] (A11) In the method denoted as (A10), multiplexing the analog first feedback signal with the analog second feedback signal may include: communicatively coupling the analog first feedback signal and the analog second feedback signal to the input of the first ADC at different corresponding times.

[0062] (A12) Any of the methods represented as (A10) and (A11) may also include: (1) using a second Class-D amplifier to amplify a digital second internal signal to generate a digital second output signal; (2) filtering the digital second output signal to generate an analog second output signal; (3) providing the analog second output signal to a second load; and (4) sensing the analog second output signal to generate an analog second feedback signal.

[0063] (A13) The method denoted as (A12) may further include: using the first ADC to convert the analog second feedback signal into a digital second feedback signal.

[0064] (A14) The method denoted as (A13) may further include configuring the second class-D amplifier for an impedance of a second load by generating a digital second internal signal based at least in part on the digital second feedback signal.

[0065] (B1) A programmable controller includes: (1) a processing system configured to generate a digital first internal signal based at least in part on (a) programming instructions provided to the processing system and (b) a digital first feedback signal; (2) a first Class-D amplifier configured to amplify the digital first internal signal to generate a digital first output signal; (3) a first filter configured to filter the digital first output signal to generate an analog first output signal; (4) a first sensing circuit system configured to sense the analog first output signal to generate an analog first feedback signal; and (5) a first analog-to-digital converter (ADC) configured to convert the analog first feedback signal into a digital first feedback signal.

[0066] (B2) In the programmable controller represented as (B1), the processing system can be configured to generate a digital first internal signal at least in part based on the digital first feedback signal to configure the first Class-D amplifier for the impedance of the first load receiving the analog first output signal.

[0067] (B3) In any of the programmable controllers denoted as (B1) and (B2), the first filter may include an inductor-capacitor filter.

[0068] (B4) In any of the programmable controllers represented as (B1) to (B3), the programmable controller can be selected from the group consisting of a programmable logic controller (PLC), a programmable automation controller (PAC), and a digital control system (DCS) controller.

[0069] (B5) Any of the programmable controllers denoted as (B1) to (B4) may also include a programming interface capable of modifying programming instructions provided to the processing system.

[0070] (B6) In any of the programmable controllers represented as (B1) to (B5), the processing system can be further configured to generate a digital first internal signal at least in part based on one or more input signals received by the programmable controller.

[0071] (B7) Any of the programmable controllers represented as (B1) to (B6) may also include a multiplexer configured to multiplex the analog first feedback signal with the analog second feedback signal before the input of the first ADC.

[0072] (B8) In the programmable controller represented as (B7), (1) the processing system can be further configured to generate a digital second internal signal at least in part based on (a) programming instructions provided to the processing system and (b) the digital second feedback signal, and (2) the programmable controller can also include: (i) a second Class-D amplifier, which is configured to amplify the digital second internal signal to generate a digital second output signal; (ii) a second filter, which is configured to filter the digital second output signal to generate an analog second output signal; and (iii) a second sensing circuit system, which is configured to sense the analog second output signal to generate an analog second feedback signal.

[0073] (B9) In the programmable controller represented as (B8), the first ADC may be further configured to convert the analog second feedback signal into a digital second feedback signal.

[0074] (C1) An electrical environment includes a programmable controller and a first load. The programmable controller includes (i) a processing system configured to generate a digital first internal signal based at least in part on (a) programming instructions provided to the processing system and (b) a digital first feedback signal; (ii) a first class-D amplifier configured to amplify the digital first internal signal to generate a digital first output signal; (iii) a first filter configured to filter the digital first output signal to generate an analog first output signal; (iv) a first sensing circuit system configured to sense the analog first output signal to generate an analog first feedback signal; and (v) a first analog-to-digital converter (ADC) configured to convert the analog first feedback signal into a digital first feedback signal. The first load is powered by the analog first output signal.

[0075] (C2) The electrical environment denoted as (C1) may further include a cable electrically coupling the first load to the programmable controller.

[0076] (C3) In either of the electrical environments denoted as (C1) and (C2), the impedance of the first load may range from zero ohms to 1,000 ohms.

[0077] (C4) In any of the electrical environments represented as (C1) to (C3), the programmable controller can be selected from the group consisting of a programmable logic controller (PLC), a programmable automation controller (PAC), and a digital control system (DCS) controller.

[0078] (C5) In any of the electrical environments represented as (C1) to (C4), the processing system can be configured to generate a digital first internal signal at least in part based on the digital first feedback signal to configure the first Class-D amplifier for the impedance of the first load.

[0079] Changes may be made to the above methods, devices, and systems without departing from the scope of the present invention. It should be noted, therefore, that the matters contained in the above description and shown in the accompanying drawings should be interpreted as illustrative and not in a limiting sense. The following claims are intended to cover all statements of the general and specific features described herein and the scope of the present methods and systems, which, as far as language is concerned, can be said to fall between the two.

Claims

1. A method for providing an analog output signal, the method comprising: amplifying the digital first internal signal using a first class-D amplifier to generate a digital first output signal; filtering the digital first output signal to generate an analog first output signal; providing the simulated first output signal to a first load; sensing the analog first output signal to generate an analog first feedback signal; converting the analog first feedback signal into a digital first feedback signal; as well as The first class-D amplifier is configured for an impedance of the first load by generating the digital first internal signal based at least in part on the digital first feedback signal. 2 . The method of claim 1 , wherein sensing the analog first output signal comprises one of: sensing a voltage across the first load; and sensing a magnitude of a current flowing through the first load. 3 . The method of claim 1 , wherein the impedance of the first load is variable independent of a state of the analog first output signal. The method of claim 1 , wherein the analog first output signal is one of a current signal and a voltage signal.

5. The method of claim 1 , wherein generating the digital first internal signal based at least in part on the digital first feedback signal comprises: The digital first internal signal is generated to achieve an average value of the digital first output signal, the average value varying with an impedance of the first load.

6. The method of claim 1 , wherein generating the digital first internal signal based at least in part on the digital first feedback signal comprises: The digital first internal signal is generated based at least in part on a difference between the digital first feedback signal and a first reference value.

7. The method according to claim 1, further comprising: using a first analog-to-digital converter (ADC) to convert the analog first feedback signal into the digital first feedback signal; as well as The analog first feedback signal is multiplexed with an analog second feedback signal before an input of the first ADC.

8. The method of claim 7, wherein multiplexing the analog first feedback signal and the analog second feedback signal comprises: The analog first feedback signal and the analog second feedback signal are communicatively coupled to the input of the first ADC at different respective times.

9. The method according to claim 7, further comprising: amplifying the digital second internal signal using a second class-D amplifier to generate a digital second output signal; filtering the digital second output signal to generate an analog second output signal; providing the simulated second output signal to a second load; as well as The analog second output signal is sensed to generate the analog second feedback signal.

10. The method according to claim 9, further comprising: The analog second feedback signal is converted into a digital second feedback signal using the first ADC.

11. The method according to claim 10, further comprising: The second class-D amplifier is configured for an impedance of the second load by generating the digital second internal signal based at least in part on the digital second feedback signal.

12. A programmable controller comprising: a processing system configured to generate a digital first internal signal based at least in part on (a) programming instructions provided to the processing system and (b) a digital first feedback signal; a first class-D amplifier configured to amplify the digital first internal signal to generate a digital first output signal; a first filter configured to filter the digital first output signal to generate an analog first output signal; first sensing circuitry configured to sense the analog first output signal to generate an analog first feedback signal; as well as A first analog-to-digital converter (ADC) is configured to convert the analog first feedback signal into the digital first feedback signal.

13. A programmable controller according to claim 12, wherein the processing system is configured to generate the digital first internal signal at least in part based on the digital first feedback signal to configure the first Class-D amplifier for the impedance of a first load receiving the analog first output signal.

14. The programmable controller of claim 12, wherein the first filter comprises an inductor-capacitor filter.

15. The programmable controller of claim 12, wherein the processing system is further configured to generate the digital first internal signal based at least in part on one or more input signals received by the programmable controller. 16 . The programmable controller of claim 12 , further comprising a multiplexer configured to multiplex the analog first feedback signal with an analog second feedback signal prior to an input of the first ADC.

17. The programmable controller according to claim 16, wherein: The processing system is further configured to generate a digital second internal signal based at least in part on (a) programming instructions provided to the processing system and (b) a digital second feedback signal; and The programmable controller also includes: a second class-D amplifier configured to amplify the digital second internal signal to generate a digital second output signal, a second filter configured to filter the digital second output signal to generate an analog second output signal, and Second sensing circuitry is configured to sense the analog second output signal to generate the analog second feedback signal. 18 . The programmable controller of claim 17 , wherein the first ADC is further configured to convert the analog second feedback signal into the digital second feedback signal.

19. An electrical environment comprising: Programmable controller, including: a processing system configured to generate a digital first internal signal based at least in part on (a) programming instructions provided to the processing system and (b) a digital first feedback signal, a first class-D amplifier configured to amplify the digital first internal signal to generate a digital first output signal, a first filter configured to filter the digital first output signal to generate an analog first output signal, first sensing circuitry configured to sense the analog first output signal to generate an analog first feedback signal, and a first analog-to-digital converter (ADC) configured to convert the analog first feedback signal into the digital first feedback signal; and A first load is powered by the simulated first output signal.

20. The electrical environment of claim 19, further comprising an electrical cable electrically coupling the first load to the programmable controller.

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