Low-voltage current mode latch, D flip-flop and frequency divider

Abstract

The invention belongs to the field of radio frequency integrated circuits, and particularly relates to a low-voltage current mode latch, a D trigger and a frequency divider. The low-voltage current mode latch comprises a sampling circuit for sampling an input signal and generating a sampling signal; the holding circuit is used for holding the sampling signal and generating an output signal; the parallel control tube adopts a non-logic switching and sampling circuit or holding circuit connection state under the control of a clock signal; the parallel tail current tube is used for independently providing a stable current source for the sampling circuit and the holding circuit under the control of a bias signal; by adopting the parallel control tubes, the working voltage requirement is reduced, and the power consumption and the energy consumption are reduced.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency integrated circuits and specifically relates to a low voltage current mode latch, a D trigger and a frequency divider. Background Art

[0002] In the field of radio frequency integrated circuits, radio frequency dividers are an important circuit component. Conventional radio frequency dividers usually use a CML (Current Mode Logic) latch structure, in which a series control switch is used.

[0003] like Figure 1 As shown, the traditional CML latch structure includes a sampling circuit, a holding circuit, a series control tube and a shared tail current tube, wherein the RF frequency divider mainly solves the frequency division problem of the RF signal, and can divide the input RF signal into a certain ratio and output it. For example, in a wireless communication system, the RF frequency divider can divide the high-frequency RF signal into a lower-frequency signal for subsequent signal processing. However, the RF frequency divider of the traditional CML latch structure has the following disadvantages:

[0004] Higher operating voltage: Due to the use of series control switches, a higher operating voltage is required to ensure the normal operation of the circuit, which increases the power consumption and design complexity of the system;

[0005] High power consumption: High operating voltage leads to high power consumption, which is not conducive to achieving the design goal of low power consumption;

[0006] Limited performance: In a low-voltage working environment, the performance of traditional structures will be greatly affected and may not be able to meet some application scenarios that require low-voltage operation. Summary of the invention

[0007] The purpose of the present invention is to solve the problems of high operating voltage, high power consumption and limited performance in low voltage working environment caused by the series control switch of the traditional CML latch structure in the existing radio frequency divider. Non-logic is realized by using the parallel connection of current, and the switching of the CML latch sampling and holding / state is further controlled. The radio frequency divider of the present invention can operate stably at low operating voltage, reduce system power consumption, improve performance in low voltage application scenarios, and meet the needs of modern electronic equipment for miniaturized, low power consumption, and high performance radio frequency circuit components.

[0008] The present invention provides the following low-voltage current mode latch, D flip-flop and frequency divider solution to achieve the above purpose:

[0009] In a first aspect of the present invention, the present invention provides a low voltage current mode latch, comprising:

[0010] A sampling circuit samples the input signal to generate a sampling signal;

[0011] A holding circuit holds the sampled signal and generates an output signal;

[0012] The parallel control tube uses non-logical switching to connect with the sampling circuit or maintain the circuit under the control of the clock signal;

[0013] The parallel tail current tube, under the control of the bias signal, independently provides a stable current source for the sampling circuit and the holding circuit.

[0014] Furthermore, the size of the parallel control tube is adjustable.

[0015] Furthermore, it also includes a temperature compensation circuit, and the temperature compensation circuit is used to generate a bias signal.

[0016] Furthermore, the temperature compensation circuit includes transistors Q9, Q10, Q11, resistors R5, R6 and capacitor C1; the emitter of Q9 is grounded, the base of Q9 is connected to the emitter of Q10, the collector of Q9 is connected to one end of the resistor R5, one end of the capacitor C1, the base of Q10 and the base of Q11; the collector of Q10 is connected to the other end of the resistor R5, the collector of Q11 and the power supply voltage; the emitter of Q11 is connected to one end of the resistor R6, and the other end of the resistor R6 outputs a bias signal; the other end of the capacitor C1 is grounded.

[0017] In a second aspect of the present invention, the present invention further provides a D flip-flop, comprising a plurality of cascaded low-voltage current-mode latches as described in the first aspect of the present invention.

[0018] Furthermore, a plurality of cascaded low voltage current mode latches share a temperature compensation circuit.

[0019] In a third aspect of the present invention, the present invention further provides a frequency divider, comprising a plurality of cascaded D flip-flops according to the second aspect of the present invention.

[0020] Furthermore, it also includes an input buffer amplifier and an output buffer amplifier.

[0021] Beneficial effects of the present invention:

[0022] ① Reduce the operating voltage: Traditional RF frequency dividers use a series control switch in a CML latch structure, which requires a higher operating voltage. The present invention uses current parallel connection to achieve non-logic, which significantly reduces the operating voltage requirement. This enables low-voltage current mode lockers, D flip-flops, and frequency dividers to work stably in low-voltage environments, and is suitable for application scenarios with strict restrictions on power consumption and voltage, such as portable electronic devices and wireless sensor networks;

[0023] ② Reduce power consumption: Low operating voltage directly leads to reduced power consumption. In addition, the design of current parallel logic makes the current path in the circuit more optimized, reducing unnecessary energy loss. Compared with traditional frequency dividers, the power consumption of the present invention is reduced, which helps to extend the battery life of electronic devices and improve the energy efficiency of the system;

[0024] ③ Improve temperature characteristics: The temperature compensation bias structure is adopted to greatly improve the temperature characteristics of the CML latch. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the structure of the current mode latch of the conventional technology;

[0026] Figure 2 is a schematic diagram of the structure of a low voltage current mode latch according to an embodiment of the present invention;

[0027] Figure 3 1 is a schematic diagram of the structure of a low voltage current mode latch according to a preferred embodiment of the present invention;

[0028] Figure 4 It is a schematic diagram of the circuit structure of the current mode latch of the conventional technology;

[0029] Figure 5 1 is a schematic diagram of the structure of a low-voltage current mode latch circuit according to an embodiment of the present invention;

[0030] Figure 6 1 is a schematic diagram of the structure of a low voltage current mode latch circuit according to a preferred embodiment of the present invention;

[0031] Figure 7 is a schematic diagram of a D flip-flop structure circuit according to an embodiment of the present invention;

[0032] Figure 8 1 is a schematic diagram of a frequency divider structure circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0033] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] It should be noted that, since the embodiments of the present invention focus on the current or voltage of the signal, the current or voltage input / output of each module / unit / device is used for description herein, and it should be understood by those skilled in the art that, in fact, the input / output of each module / unit / device is a signal. In order to make the technical means and creative features of the present invention easy to understand, the present invention is further described in conjunction with the accompanying drawings.

[0035] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0036] The embodiments of the present invention belong to the subdivided technical field of RF signal processing under low operating voltage, and are mainly used in RF communication systems and wireless sensor networks that require RF signal frequency division processing and have strict requirements on the operating voltage. This technical field focuses on the development of high-performance, low-power RF circuit components to meet the needs of modern electronic devices for miniaturization and high efficiency.

[0037] Figure 2 is a schematic diagram of the structure of a low voltage current mode latch according to an embodiment of the present invention; Figure 2 As shown, the low voltage current mode latch comprises:

[0038] A sampling circuit samples the input signal to generate a sampling signal;

[0039] A holding circuit holds the sampled signal and generates an output signal;

[0040] The parallel control tube uses non-logical switching to connect with the sampling circuit or maintain the circuit under the control of the clock signal;

[0041] The parallel tail current tube, under the control of the bias signal, independently provides a stable current source for the sampling circuit and the holding circuit.

[0042] The embodiment of the present invention will be as follows Figure 1The tail current shared by the sampling circuit and the holding circuit in the traditional current mode register shown is divided into two independent tail currents by a parallel tail current tube, which plays a certain isolation role and can improve the reliability and stability of the low-voltage current mode latch.

[0043] In the embodiment of the present invention, the parallel control tube is used to realize non-logic by current parallel connection, so as to realize the state switching control of the sampling circuit and the holding circuit corresponding to the low-voltage current mode latch, without the need for Figure 1 The series switch tube in the traditional current mode register shown in the figure eliminates a part of the voltage drop in the embodiment of the present invention, which can effectively reduce the operating voltage.

[0044] Figure 3 is a schematic diagram of the structure of a low voltage current mode latch according to a preferred embodiment of the present invention. Figure 3 As shown, this embodiment also includes a temperature compensation circuit; the use of a temperature compensation bias structure greatly improves the temperature characteristics of the low-voltage current mode latch of the present invention and expands its application range.

[0045] Figure 4 A typical current mode latch circuit structure diagram in traditional technology is given; Figure 4 As shown, the current mode latch circuit includes a sampling circuit composed of transistors Q1 and Q2, a holding circuit composed of transistors Q3 and Q4, a series control tube composed of transistors Q5 and Q6, and a shared tail current Q7; the input signal in the sampling circuit is a differential signal DP and DN; the output type in the holding circuit is QP and QN; the series control tube controls the switching state in series through the clock signals CLKP and CLKN; the shared tail current is controlled and stabilized by the bias signal BIAS. In this circuit case, the series control tube used requires a higher operating voltage, and the tail current does not have an isolation effect, and the reliability and stability of the circuit cannot be guaranteed.

[0046] Based on the above typical current mode latch circuit, this embodiment improves it, such as Figure 5 As shown, this embodiment will Figure 4 The tail current tube Q7 shared by the series control tubes Q5 and Q6 used for the state switching control of the conventional CML latch is divided into two and improved as follows: Figure 5 Q7 and Q8 shown, and will Figure 4 The series control logic of Q5 and Q6 in the circuit is improved to Figure 5 The parallel control logic in .

[0047] In the embodiment of the present invention, Figure 5 As shown, when CLKP is high, Q5 is turned on, Q1 and Q2 have no tail current supply, and the current I1 flowing through Q5 and the tail current I2 of the sampling circuit composed of Q1 and Q2 form a logical negation relationship, eliminating Figure 4 The voltage drop of part of Q5 and Q6 in the middle can be further reduced by optimizing the design. The same is true for the holding circuit composed of Q3 and Q4 on the right.

[0048] It should be noted that in this embodiment, the series control tube is replaced by a parallel control tube. When the parallel control tube is turned on, the lower tail current is almost entirely provided to the corresponding control tube, causing the upper sampling circuit to be closed. At this time, the clock of the sampling circuit is opposite, and the right tail current is almost entirely provided to the holding circuit. The low-voltage current mode latch of this embodiment can be controlled to switch between sampling and holding states by using a pair of reverse clock signals that are the same as those of the traditional CML latch. At the same time, the two tail current tubes correspond to two independent tail currents, which play a certain isolation role and can improve the reliability and stability of the low-voltage current mode latch.

[0049] In a preferred embodiment of the present invention, adjusting the sizes of Q5 and Q6 can adjust the turn-off strength of the tail current of the sampling circuit and the holding circuit respectively, and adjust the operating frequency of the CML latch.

[0050] In a preferred embodiment of the present invention, this embodiment also provides a low voltage current mode latch circuit, such as Figure 6 As shown, in this embodiment, Q9, Q10, Q11, R5, R6, and C1 form a temperature compensation structure; the emitter of Q9 is grounded, the base of Q9 is connected to the emitter of Q10, the collector of Q9 is connected to one end of the resistor R5, one end of the capacitor C1, the base of Q10, and the base of Q11; the collector of Q10 is connected to the other end of the resistor R5, the collector of Q11, and the power supply voltage; the emitter of Q11 is connected to one end of the resistor R6, and the other end of the resistor R6 outputs a bias signal; the other end of the capacitor C1 is grounded. This embodiment can effectively provide negative temperature coefficient feedback for the CML latch, stabilize the working state of the tail current, and improve the working temperature characteristics of the divider.

[0051] In the embodiment of the present invention, for the convenience of demonstration, the low-voltage current mode latch circuits of the above embodiments are cascaded to form a D flip-flop. Figure 7 As shown, the D flip-flop includes a main latch and a secondary latch. The D flip-flop is an information storage device with a memory function and two stable states of 0 and 1. Its interface can adopt a standard interface, that is, it has a data terminal D, a clock terminal CLK, a positive data output terminal Q, and a negative data output terminal Q non-terminal. The secondary state of the D flip-flop depends on the state of the D terminal before the trigger. When the rising edge of the clock signal (CLK) arrives, the D flip-flop stores the input data of the D terminal to the output terminal Q to achieve data flipping. After that, no matter how the D input changes, as long as there is no new clock signal edge, the state of Q will not change.

[0052] In an embodiment of the present invention, a bias network with a negative feedback structure, that is, a temperature compensation circuit, is used to provide bias signals for the sampling circuit and the holding circuit at the same time, which can achieve better temperature stability, reduce the performance fluctuation range of the low-voltage current mode latch under different temperature working environments, and thus improve the stability of the device working state. In addition, this method can also significantly reduce the number of components in the circuit, thereby simplifying the overall circuit design. This helps to reduce circuit complexity, reduce layout area, and improve circuit reliability.

[0053] In the embodiment of the present invention, for the convenience of demonstration, two D flip-flops in the above embodiment are cascaded to realize a two-way frequency divider; the overall two-way frequency divider circuit diagram is shown in FIG. Figure 8 As shown (the DC power supply and ground are omitted), taking a single-ended input and single-ended output frequency divider as an example, the implementation principle of the frequency divider is to control the clock signal of the D flip-flop and utilize its rising edge triggered characteristics. Each time the rising edge of the clock signal arrives, the output of the D flip-flop will flip (high level → low level or low level → high level). Therefore, a complete cycle signal will appear at the output end every two clock cycles, realizing the frequency divider. In this embodiment, two D flip-flops are connected in series, and the output of the first D flip-flop is connected to the input of the second D flip-flop. In this way, when the first D flip-flop flips, the input of the second D flip-flop changes state, thereby realizing the frequency divider. In actual situations, the number of D flip-flops can also be increased to obtain other types of frequency dividers, such as a four-divider.

[0054] In a preferred embodiment of the present invention, an input buffer amplifier and an output buffer amplifier are also included; the output buffer amplifier uses a resistor voltage division method to achieve mode switching; the bias position of the output stage can be controlled to achieve outputs of different power levels.

[0055] Among them, the input buffer amplifier is an important component in the electronic circuit. It is located between the signal source and the subsequent divider circuit, and plays the role of isolation, impedance matching and signal amplification. Its main function is to receive weak signals from the signal source, amplify and shape them through the internal circuit, and then output them to the subsequent circuit for processing. The input buffer amplifier usually has the characteristics of high input impedance and low output impedance, which enables it to effectively extract signals from the signal source while reducing signal loss and distortion during transmission.

[0056] Among them, the output buffer amplifier is an important component in the electronic circuit, located at the output end of the divider circuit, used to drive the load and provide a stable output signal. Its main function is to receive the signal from the previous circuit, amplify and shape it through the internal circuit, and then output it to the load or subsequent circuit. The output buffer amplifier usually has the characteristics of low output impedance and high driving capability, which enables it to effectively drive various loads such as speakers, motors, etc. Its internal circuit may include components such as power amplifiers and transistors. Through proper circuit design and parameter adjustment, functions such as signal amplification, power output and load driving can be achieved.

[0057] It should be noted that after the external clock signal enters the input buffer amplifier, the input buffer amplifier buffers and amplifies the external clock signal and inputs it into the clock signal terminals CLK and CLKN in each level of D flip-flops respectively; the D, DN, Q and QN signals of each level of D flip-flops will enter the output buffer amplifier for buffering and amplification to improve the signal quality, reduce the impact of the load on the signal source, and enhance the driving capability.

[0058] The embodiment of the present invention performs low voltage optimization design from multiple aspects such as circuit structure, component selection, power consumption analysis, etc., to ensure that the frequency divider can work normally under low operating voltage and has low power consumption and good performance.

[0059] In the embodiment of the present invention, the frequency divider formed by the CML latch using the same conventional series switch switching process operates at a working voltage of 5V, and the frequency divider formed by the CML latch using the parallel switch control structure can operate at a working voltage as low as 2.4V, which significantly reduces its working voltage and expands its application range. The design of a four-frequency divider circuit based on the CML structure can also achieve a higher frequency division frequency and good phase noise. By adjusting the output swing of the CML latch, the buffer amplifier of the intermediate stage can be omitted. In addition, related low-voltage devices can be implemented based on the low-voltage current mode latch.

[0060] Traditional RF frequency dividers use a series control switch in a CML latch structure, which requires a higher operating voltage. The present invention uses the parallel connection of currents to implement a logical negation operation as a state switching switch of the CML latch. By rationally arranging the parallel current paths, the frequency division processing of the RF signal is realized, the voltage drop of the series switch tube is eliminated, the operating voltage requirement is significantly reduced, and the application range of such frequency dividers is expanded.

[0061] In the description of the present invention, it is necessary to understand that the terms "coaxial", "bottom", "one end", "top", "middle", "the other end", "upper", "one side", "top", "inside", "outside", "front", "center", "both ends" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0062] In the present invention, unless otherwise clearly stipulated and limited, the terms such as "installation", "setting", "connection", "fixation" and "rotation" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium; it can be the internal connection of two elements or the interaction relationship between two elements. Unless otherwise clearly defined, ordinary technicians in this field can understand the specific meanings of the above terms in the present invention according to the specific circumstances.

[0063] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A low voltage current mode latch, characterized in that: include: A sampling circuit samples the input signal to generate a sampling signal; A holding circuit holds the sampled signal and generates an output signal; The parallel control tube uses non-logical switching to connect with the sampling circuit or maintain the circuit under the control of the clock signal; The parallel tail current tube, under the control of the bias signal, independently provides a stable current source for the sampling circuit and the holding circuit.

2. The low voltage current mode latch according to claim 1, characterized in that: The size of the parallel control tube is adjustable.

3. The low voltage current mode latch according to claim 1, characterized in that: A temperature compensation circuit is also included, and the temperature compensation circuit is used to generate a bias signal.

4. The low voltage current mode latch according to claim 3, characterized in that: The temperature compensation circuit includes transistors Q9, Q10, Q11, resistors R5, R6 and capacitor C1; the emitter of Q9 is grounded, the base of Q9 is connected to the emitter of Q10, the collector of Q9 is connected to one end of the resistor R5, one end of the capacitor C1, the base of Q10 and the base of Q11; the other end of the capacitor C1 is grounded; the collector of Q10 is connected to the other end of the resistor R5, the collector of Q11 and the power supply voltage; the emitter of Q11 is connected to one end of the resistor R6, and the other end of the resistor R6 outputs a bias signal.

5. A D flip-flop, characterized in that: A low voltage current mode latch comprising a plurality of cascaded ones of claims 1 to 4.

6. The D flip-flop according to claim 5, characterized in that: Multiple cascaded low voltage current mode latches share a temperature compensation circuit.

7. A frequency divider, characterized in that: The invention comprises a plurality of cascaded D flip-flops as claimed in claim 5 or 6.

8. The frequency divider according to claim 7, characterized in that: Also included are an input buffer amplifier and an output buffer amplifier.

9. The frequency divider according to claim 8, characterized in that: The output buffer amplifier uses a resistor voltage division method to achieve mode switching.

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