Low-power power-on reset circuits, modules, and chips covering fast and slow power-on delays

Abstract

The present invention belongs to the field of analog circuits, and specifically relates to a low-power power-on reset circuit, module, and chip covering fast and slow power-on delays. The power-on reset circuit includes three parts: a detection circuit, a delay circuit, and an output circuit. Among them, the detection circuit is used to detect the power-on of VDD and generate a corresponding power-on signal. The delay circuit is used to generate a delay signal with a specified delay by using the output of the existing bandgap reference current source and the bandgap reference voltage source in the power management circuit. The output circuit includes an AND gate, and the two input ends of the AND gate are respectively connected to the output ends of the detection circuit and the delay circuit, and then a reset signal that meets the delay requirement is generated according to the outputs of the two. The power-on reset circuit can cover different power-on modes and can generate a reset signal with a set delay requirement. The output of the detection circuit can also suppress the impact of the jump that is easy to occur in the delay circuit during fast power-on on the circuit reliability.

Description

Technical Field

[0001] The present invention belongs to the field of analog circuits, and in particular relates to a low-power power-on reset circuit, a power-on reset module, a power management circuit and a functional chip covering fast and slow power-on delays. Background Art

[0002] With the development of semiconductor integrated circuits, the chip manufacturing process is becoming more and more advanced, and the corresponding chips need to have lower and lower power consumption. In a complete chip, the power management module accounts for a large part of the power consumption. Therefore, it is very meaningful to reduce the power consumption of the power-on reset circuit in the power management module. Existing power-on reset circuits often face the problem of difficulty in balancing delay and power consumption during the design process. On the one hand, most of the existing power-on reset circuits only support fast power-on mode. In order to further support the slow power-on mode, technicians often need to add a slow power-on part composed of resistors and capacitors to the power-on detection circuit, which will significantly increase the power consumption of the circuit. On the other hand, ultra-low power consumption power-on reset circuits often cannot meet their delay requirements. Therefore, for slow power-on systems, how to improve the delay problem of the power-on reset circuit while maintaining ultra-low power consumption is becoming a technical problem that technicians in this field are eager to solve. Summary of the invention

[0003] In order to solve the problem that the existing power-on reset circuit covering fast and slow power-on is difficult to provide a reset signal that meets the delay requirement, the present invention provides a low-power power-on reset circuit, a power-on reset module, a power management circuit and a functional chip covering fast and slow power-on delays.

[0004] The technical solution provided by the present invention is:

[0005] A low-power power-on reset circuit covering fast and slow power-on delays comprises: a detection circuit, a delay circuit and an output circuit, wherein the detection circuit is used to detect the power-on of VDD and generate a corresponding power-on signal POR.

[0006] The delay circuit includes PMOS tubes P2~P4, capacitors C3~C5, inverters INV1, INV2, and Schmitt trigger SMT2. The circuit connection relationship of the delay circuit is: the gates of P2~P4 are connected to the bandgap reference voltage VBG; the source of P2 and the upper plate of C3 are connected to the bandgap reference current IBG; the drain of P2 is connected to the source of P3; the drain of P3 is connected to the source of P4, the input end of INV1 and the upper plate of C4; INV1, SMT2, and INV2 are cascaded in sequence; the upper plate of C5 is connected to the output end of INV1; the drain of P4 and the lower plates of C3~C5 are grounded; the output end of INV2 is used to output the delay signal DELAY.

[0007] The output circuit receives POR and DELAY as inputs through an AND gate and outputs a reset signal RSTN with a specified delay.

[0008] In the low-power power-on reset circuit that covers fast and slow power-on delays provided by the present invention, when VDD is powered on, VBG serves as the gate voltage of P2 to P4 in the delay circuit, and IBG first charges C3. After the voltage at the C3 terminal gradually increases during the charging process and P2 and P3 are turned on, IBG is used to charge C4; the two charging processes produce a delay in the first stage. After the voltage at the C4 terminal gradually increases during the charging process and P4 is turned on, P4, INV1 and C5 form a delay circuit, thereby producing a delay in the second stage. Finally, the delay length of the delay signal DELAY output by the delay circuit is equal to the sum of the delays in the two stages.

[0009] In a further improvement of the present invention, the capacitance values ​​of C3-C5 in the delay circuit are adjusted to generate a reset signal with a required delay length.

[0010] As a further improvement of the present invention, the detection circuit is composed of capacitors C1 and C2, PMOS tube P1, NMOS tubes N1~N3 and Schmitt trigger SMT1. The circuit connection is: the source of P1 and the upper plate of C1 are connected to VDD; the lower plate of C1 is connected to the gates of N1 and P1 and the drains of N1 and N2; the source of N2 is connected to the drain and gate of N3; the drain of P1, the gate of N2, the upper plate of C2 are connected to the input end of SMT1; the source of N1 and N3 and the lower plate of C2 are grounded; the output end of SMT1 is used to output the power-on signal POR.

[0011] As a further improvement of the present invention, the detection circuit is composed of a capacitor C2, a PMOS tube P1, and a Schmitt trigger SMT1; wherein the source of P1 is connected to VDD, the upper plate of C2 is connected to the gate and drain of P1 and the input end of SMT1; the output end of SMT1 is used to output a power-on signal POR.

[0012] As a further improvement of the present invention, the detection circuit is composed of a PMOS tube P1, an NMOS tube N1, capacitors C1, C2, resistors R1-R4, an inverter INV3 and a Schmitt trigger SMT1. The circuit connection is: the upper ends of R1 and R4, the source of P1 and the upper plate of C1 are connected to VDD; the lower end of R1 and the upper end of R2 are connected to the drain of P1; the gate of P1 is connected to the lower plate of C1; the lower end of R2 is connected to the upper end of R3, the upper plate of C2 and the gate of N1; the lower end of R3, the lower plate of C2 and the source of N1 are grounded; the drain of N1 and the lower end of R4 are connected to the input end of INV3, and the output end of INV3 is connected to the input end of SMT1; the output of SMT1 is used to output a power-on signal POR.

[0013] The present invention also includes a power-on reset module, which supports fast power-on and slow power-on reset modes and is used to generate a reset signal with a specified delay after power-on in any mode. The power-on reset module uses the low-power power-on reset circuit that covers fast and slow power-on delays as described above.

[0014] The power-on reset module provided by the present invention comprises four input ports and one output port. The four input ports are respectively used to connect a power supply VDD, a ground terminal GND, a bandgap reference voltage VBG, and a bandgap reference current IBG; and the output port is used to output a reset signal RSTN.

[0015] The present invention also includes a power management circuit, which includes a bandgap reference voltage source, a bandgap reference current source, and a power-on reset module as described above. The bandgap reference voltage source and the bandgap reference current source are respectively used to provide the required bandgap reference voltage VBG and bandgap reference current IBG for the power-on reset module.

[0016] The present invention also includes an analog chip, which includes an internal power supply module. The internal power supply module adopts the power management circuit as mentioned above.

[0017] The technical solution provided by the present invention has the following beneficial effects:

[0018] The present invention provides a low-power power-on reset circuit covering fast and slow power-on delays. The power-on reset circuit adds a delay circuit on the basis of the detection circuit. The delay circuit is driven by the existing bandgap reference voltage source and bandgap reference current source in the power management module, and can generate a reset signal that is stable and controllable and meets the delay requirements in different power-on modes. Among them, the new design including the delay circuit, the detection circuit and the output circuit provided by the present invention can also achieve stable delay in different power-on scenarios, and suppress the jump phenomenon of the circuit output in the fast power-on stage to improve the reliability of the circuit.

[0019] In addition, combined with the new design of the detection circuit part provided in this embodiment, the present invention also has ultra-low power consumption. Therefore, it can simultaneously meet the dual requirements of low power consumption and controllable delay of the power-on reset circuit in the high-performance chip; thus, it has outstanding practical value and broad market prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a circuit diagram of a low-power power-on reset circuit that covers fast and slow power-on delays provided in Example 1 of the present invention.

[0021] Figure 2 Circuit diagram of another low power power-on reset circuit designed for replacement detection circuit covering fast and slow power-on delays.

[0022] Figure 3Circuit diagram of a third type of low power power-on reset circuit covering fast and slow power-on delays designed for replacement detection circuits.

[0023] Figure 4 This is a module schematic diagram of the power-on reset module provided in Example 2 of the present invention.

[0024] Figure 5 The figure is a signal flow diagram of the power-on reset circuit of the present invention in the fast power-on mode.

[0025] Figure 6 It is a signal flow diagram of the power-on reset circuit of the present invention in the slow power-on mode. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0027] Example 1

[0028] This embodiment provides a low-power power-on reset circuit that covers fast and slow power-on delays. The power-on reset circuit is a component of the power management circuit. Figure 1 As shown, the power-on reset circuit provided in this embodiment includes three parts: a detection circuit, a delay circuit and an output circuit. Among them, the detection circuit is used to detect the power-on of VDD and generate a corresponding power-on signal POR. The delay circuit is used to generate a delay signal DELAY with a specified delay by using the output of the existing bandgap reference current source and the bandgap reference voltage source in the power management circuit. The output circuit includes an AND gate AND, and the two input ends of the AND gate are respectively connected to the output ends of the detection circuit and the delay circuit, and then a reset signal RSTN that meets the delay requirement is generated according to the outputs of the two.

[0029] Among them, in the technical solution provided by this embodiment, the delay circuit includes 3 PMOS tubes P2~P4, 3 capacitors C3~C5, 2 inverters INV1, INV2, and 1 Schmitt trigger SMT2. The circuit connection relationship of the delay circuit is: the gates of P2~P4 are connected to the bandgap reference voltage VBG; the source of P2 and the upper plate of C3 are connected to the bandgap reference current IBG; the drain of P2 is connected to the source of P3; the drain of P3 is connected to the source of P4, the input end of INV1 and the upper plate of C4; INV1, SMT2, and INV2 are cascaded in sequence; the upper plate of C5 is connected to the output end of INV1; the drain of P4 and the lower plates of C3~C5 are grounded; the output end of INV2 is used to output the delay signal DELAY.

[0030] In the low-power power-on reset circuit that covers fast and slow power-on delays provided in this embodiment, the detection circuit usually generates a corresponding power-on signal quickly after the system is powered on; and the delay circuit generates a delay signal with a specified duration using the bandgap reference current IBG and the bandgap reference voltage VBG after the system is powered on; finally, the output circuit performs an AND logic operation on the power-on signal and the delay signal to generate a reset signal. Therefore, the delay length of the reset signal finally output mainly depends on the delay length of the delay signal.

[0031] The following combination Figure 1 The circuit diagram of the delay circuit in Figure 1 analyzes the generation mechanism of the delay signal:

[0032] In the delay circuit part of the low-power power-on reset circuit covering fast and slow power-on delay provided in this embodiment, when VDD is powered on, the bandgap reference voltage source and the bandgap reference current source simultaneously output VBG and IBG. Among them, VBG serves as the gate voltage of P2~P4 in the delay circuit, and makes P2~P4 all in the off state; and IBG will first charge the capacitor C3, and the voltage of the upper plate of C3 (denoted as V) will gradually increase with the charging process. At the same time, the upper plate voltage of C3 also serves as the source voltage of the PMOS tube P2. Therefore, when the difference between the gate-source voltage of P2 (ie, V-VBG) is greater than the threshold voltage Vth of P2, P2 is turned on, and based on the same principle, P3 will also be turned on. At this time, current flows through P2 and P3. When PM2 and PM3 are turned on, IBG will first flow to C4 and continue to be used to charge C4. In the process of IBG charging C3 and C4 twice respectively, the delay circuit generates a first-stage delay.

[0033] Next, the voltage of the upper plate of C4 will gradually increase as the charging process proceeds, and the voltage of the upper plate of C4 is equal to the source voltage of P4; therefore, when the voltage of C4 gradually increases, it will eventually cause the difference between the gate-source voltage of P4 to exceed the threshold voltage of P4, thereby turning on P4. After P4 is turned on, all IBG will flow through P4 and no longer flow to C4; at this time, the source voltage of P4 is fixed. At this time, P2 and P3 work in the linear region, and P4 works in the saturation region. The source voltage of P4 forms a delay circuit through the inverter INV1 and the capacitor C5, which brings about the delay of the second stage in the delay circuit. Finally, the output of INV1 is first shaped by the Schmitt trigger SMT2, and then processed by the inverter INV2 and output as the delay signal DELAY.

[0034] Combined with the analysis of the above circuit principle, it can be found that the delay length of the delay signal DELAY output by the delay circuit provided in this embodiment is equal to the sum of the delays in the two stages. In the first stage, the delay length mainly depends on the charging time of C2 and C3, while in the second stage, the delay length mainly depends on the performance of the delay circuit composed of P4, INV1, and C5. Therefore, by adjusting the capacitance values ​​of C3~C5 in the delay circuit, a reset signal with any desired delay length can be generated.

[0035] In the typical solution provided in this embodiment, the detection circuit can be composed of two capacitors C1 and C2, one PMOS transistor P1, three NMOS transistors N1-N3 and one Schmitt trigger SMT1. Figure 1 As shown, the circuit connection method of the detection circuit is: the source of P1 and the upper plate of C1 are connected to VDD; the lower plate of C1 is connected to the gates of N1 and P1 and the drains of N1 and N2; the source of N2 is connected to the drain and gate of N3; the drain of P1, the gate of N2, the upper plate of C2 are connected to the input end of SMT1; the sources of N1 and N3 and the lower plate of C2 are grounded; the output end of SMT1 is used to output the power-on signal POR.

[0036] Combination Figure 1 As can be seen from the detection circuit part in the embodiment, the working principle of the detection circuit provided in this embodiment is as follows:

[0037] 1. Slow power-on mode

[0038] In the slow power-on stage, VDD will slowly increase to 5V at a fixed slope, and the C1 capacitor will also charge slowly during this process. At this time, due to the low voltage, each branch is not turned on, and the charging current is discharged as a leakage current at the N1 and N2 tubes (so the delay time is long enough, but difficult to control). When the upper plate voltage of capacitor C1 continues to rise with the charging process and makes the difference between the source and gate voltage of P1 greater than the threshold voltage, P1 is turned on. After turning on, P1 and N2 form positive feedback, the gate of P1 is low enough, and the gate of N2 is high enough. The gate voltage of NM2 changes from low to high, and the voltage of Schmitt trigger SMT1 is reversed at the same time, and the output power-on signal is reversed, generating the required high-level POR. At the same time, the N1 and N3 branches are cut off and no current flows.

[0039] 2. Fast power-on mode

[0040] In the fast power-on stage, VDD quickly reaches 5V after power-on. Since the voltage across the capacitor cannot change suddenly, the gate voltage of PM1 follows to 5V. At this time, N1 is turned on and capacitor C1 is charged. Next, the charging current flows through N1 to the ground (the delay time is determined by the capacitor). As the capacitor is charged, the gate voltage of P1 decreases and gradually reaches the threshold voltage of P1, thereby turning on P1. At the same time, N2 is turned on, and positive feedback is formed between P1 and N2. The gate of P1 is low enough and the gate of N2 is high enough. The gate voltage of N2 changes from low to high, and the voltage of Schmitt trigger SMT1 is reversed at the same time. The output power-on signal is reversed, generating the required high-level POR. At the same time, the N1 and N3 branches are cut off and no current flows.

[0041] Combined with the above analysis of the working principle of the detection circuit, it can be seen that the power-on reset circuit of this embodiment can fully cover the scenarios of fast power-on and slow power-on. Regardless of whether it is a fast power-on mode or a slow power-on mode, when the detection circuit is powered on by VDD and outputs the corresponding power-on signal POR, the other branches of VDD to the ground in the circuit will remain cut off. Considering that in other power-on reset circuits, the power consumption on this branch actually accounts for the vast majority of the overall power consumption of the circuit during the entire period, the circuit design of this detection circuit provided in this embodiment can greatly reduce the circuit power consumption of the power-on reset circuit after VDD is powered on.

[0042] The above Figure 1 The power-on reset circuit in the embodiment actually provides an optimal circuit design that can meet both power consumption and delay requirements. In other embodiments, technicians can also further adjust or optimize the detection circuit part. For example, Figure 2 Another scheme of power-on reset circuit using a new detection circuit is given. The detection circuit in this scheme is composed of a capacitor C2, a PMOS tube P1, and a Schmitt trigger SMT1. The source of P1 is connected to VDD, the upper plate of C2 is connected to the gate and drain of P1 and the input end of SMT1; the output end of SMT1 is used to output the power-on signal POR.

[0043] exist Figure 2 In the detection circuit shown in the figure, after VDD is powered on, it passes through an RC charging circuit, which causes a certain delay and then is shaped by a Schmitt trigger to output a POR signal.

[0044] In other schemes, the detection circuit in the power-on reset circuit can also adopt Figure 3 The circuit shown. Figure 3The detection circuit provided in the invention is composed of a PMOS tube P1, an NMOS tube N1, two capacitors C1 and C2, four resistors R1 to R4, an inverter INV3, and a Schmitt trigger SMT1. The circuit connection mode of the detection circuit is as follows: the upper ends of R1 and R4, the source of P1 and the upper plate of C1 are connected to VDD; the lower end of R1 and the upper end of R2 are connected to the drain of P1; the gate of P1 is connected to the lower plate of C1; the lower end of R2 is connected to the upper end of R3, the upper plate of C2 and the gate of N1; the lower end of R3, the lower plate of C2 and the source of N1 are grounded; the drain of N1 and the lower end of R4 are connected to the input end of INV3, and the output end of INV3 is connected to the input end of SMT1; the output of SMT1 is used to output the power-on signal POR.

[0045] exist Figure 3 In the detection circuit shown, VDD is divided by three resistors in series, and the voltage at the resistor end of R3 is compared with the comparator composed of the right branch R4 and N1 (the comparison voltage is the threshold voltage of N1). When the voltage is greater than the threshold voltage of N1, the drain end of N1 outputs a low level, and after passing through an inverter and a Schmitt trigger, a POR signal is output.

[0046] Example 2

[0047] Embodiment 1 provides a power-on reset circuit that can fully cover both fast power-on and slow power-on working scenarios, and generate a reset signal that meets the delay requirements. Several different circuit compositions and topological structures of the corresponding circuit framework are given. Some of the more optimized solutions further reduce the operating power consumption of the circuit, so that the circuit has made great progress in both ultra-low power consumption and longer delay. In practical applications, the above circuit design can be produced and sold in the form of an integrated circuit reset module.

[0048] On this basis, this embodiment provides a power-on reset module, which supports fast power-on and slow power-on reset modes, and is used to generate a reset signal with a specified delay after power-on in any mode. The power-on reset module uses any low-power power-on reset circuit that covers fast and slow power-on delays as in Embodiment 1.

[0049] Specifically, Figure 4 As shown, the power-on reset module provided in this embodiment includes 4 input ports and 1 output port. The 4 input ports are respectively used to connect the power supply VDD, the ground terminal GND, the bandgap reference voltage VBG, and the bandgap reference current IBG; the output port is used to output the reset signal RSTN.

[0050] Example 3

[0051] Considering that the power-on reset circuit is mainly used in various power management circuits, based on embodiments 1 and 2, this embodiment further provides a power management circuit, which includes a bandgap reference voltage source, a bandgap reference current source, and the power-on reset module as described above. The bandgap reference voltage source and the bandgap reference current source are respectively used to provide the required bandgap reference voltage VBG and bandgap reference current IBG for the power-on reset module.

[0052] Furthermore, the present embodiment also includes an analog chip, which includes an internal power supply module, and the internal power supply module adopts the power management circuit as described above.

[0053] Performance Testing

[0054] In order to verify the performance of the power-on reset circuit provided in this embodiment, the technicians formulated an experimental plan. Figure 1 The circuit shown in the figure is simulated. In the simulation experiment, two working modes, fast power-on and slow power-on, are simulated respectively, and the performance of the circuit in different working modes is compared.

[0055] (I) Fast power-on mode

[0056] In fast power-on mode, the power-on time of VDD is 5ns. At this time, the voltage changes of each signal are as follows: Figure 5 As shown, analysis Figure 5 It can be found that:

[0057] The power-on signal POR becomes high level 10us after VDD is powered on; VBG fluctuates after VDD is powered on, and this fluctuation causes the delay signal DELAY to be released early and then fall back to ground. At 245us, the delay signal DELAY brought by VBG works normally, at which time, POR and DELAY are ANDed to output a reset signal.

[0058] (II) Slow power-on mode

[0059] In fast power-on mode, the power-on time of VDD is 280ms. At this time, the voltage changes of each signal are as follows: Figure 6 As shown, analysis Figure 6 It can be found that:

[0060] POR will become high level when VDD reaches the threshold voltage, the bandgap reference will work normally in 120ms, VBG will rise to 1.2V level, and DELAY will become high level after 1ms; at this time, POR and DELAY will output a reset signal.

[0061] In summary, the delay signal required by the power-on reset circuit provided by the present invention in the fast power-on and slow power-on modes is actually provided by the DELAY signal. The main function of the POR signal is to suppress the influence of multiple cycle jumps of the DELAY signal that are prone to occur during fast power-on on the circuit reliability. Instead, it is actually achieved by performing an AND operation on the POR signal and the DELAY signal through the output circuit.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A low-power power-on reset circuit covering fast and slow power-on delays, characterized in that: It includes: A detection circuit, which is used to detect the power-on of VDD and generate a corresponding power-on signal POR; The delay circuit includes PMOS tubes P2-P4, capacitors C3-C5, inverters INV1 and INV2, and Schmitt trigger SMT2; the circuit connection is as follows: the gates of P2-P4 are connected to a bandgap reference voltage VBG; the source of P2 and the upper plate of C3 are connected to a bandgap reference current IBG; the drain of P2 is connected to the source of P3; the drain of P3 is connected to the source of P4, the input end of INV1 and the upper plate of C4; INV1, SMT2 and INV2 are connected in series in sequence; the upper plate of C5 is connected to the output end of INV1; the drain of P4 and the lower plates of C3-C5 are grounded; the output end of INV2 is used to output a delay signal DELAY; The output circuit receives POR and DELAY as inputs through an AND gate and outputs a reset signal RSTN with a specified delay.

2. The low-power power-on reset circuit covering fast and slow power-on delays as claimed in claim 1, characterized in that: When VDD is powered on, VBG serves as the gate voltage of P2 to P4, and IBG first charges C3. After the voltage at C3 gradually increases and P2 and P3 are turned on, IBG is used to charge C4. The two charging processes produce the first stage of delay. After the voltage at C4 gradually increases and P4 is turned on, P4, INV1 and C5 form a delay circuit, which produces the second stage of delay. The delay length of the delay signal output by the delay circuit is equal to the sum of the delays in the two stages.

3. The low-power power-on reset circuit covering fast and slow power-on delays as claimed in claim 2, characterized in that: The capacitance values ​​of C3-C5 in the delay circuit are adjusted to generate a reset signal with a required delay length.

4. The low-power power-on reset circuit covering fast and slow power-on delays as claimed in claim 1, characterized in that: The detection circuit is composed of capacitors C1, C2, PMOS tube P1, NMOS tubes N1-N3 and Schmitt trigger SMT1; the circuit connection is: The source of P1 and the upper plate of C1 are connected to VDD; the lower plate of C1 is connected to the gates of N1 and P1 and the drains of N1 and N2; the source of N2 is connected to the drain and gate of N3; the drain of P1, the gate of N2, the upper plate of C2 are connected to the input end of SMT1; the sources of N1 and N3 and the lower plate of C2 are grounded; the output end of SMT1 is used to output the power-on signal POR.

5. The low-power power-on reset circuit covering fast and slow power-on delays as claimed in claim 1, characterized in that: The detection circuit is composed of a capacitor C2, a PMOS tube P1, and a Schmitt trigger SMT1; wherein the source of P1 is connected to VDD, the upper plate of C2 is connected to the gate and drain of P1 and the input end of SMT1; the output end of SMT1 is used to output a power-on signal POR.

6. The low-power power-on reset circuit covering fast and slow power-on delays as claimed in claim 1, characterized in that: The detection circuit is composed of a PMOS tube P1, an NMOS tube N1, capacitors C1, C2, resistors R1-R4, an inverter INV3, and a Schmitt trigger SMT1; the circuit connection is: The upper ends of R1 and R4, the source of P1 and the upper plate of C1 are connected to VDD; the lower end of R1 and the upper end of R2 are connected to the drain of P1; the gate of P1 is connected to the lower plate of C1; the lower end of R2 is connected to the upper end of R3, the upper plate of C2 and the gate of N1; the lower end of R3, the lower plate of C2 and the source of N1 are grounded; the drain of N1 and the lower end of R4 are connected to the input of INV3, and the output of INV3 is connected to the input of SMT1; the output of SMT1 is used to output the power-on signal POR.

7. A power-on reset module, characterized in that: It supports fast power-on and slow power-on reset modes, and is used to generate a reset signal with a specified delay after power-on in any mode; the power-on reset module adopts a low-power power-on reset circuit covering fast and slow power-on delays as described in any one of claims 4-6.

8. The power-on reset module according to claim 7, characterized in that: It includes 4 input ports and 1 output port; the 4 input ports are respectively used to connect the power supply VDD, the ground terminal GND, the bandgap reference voltage VBG, and the bandgap reference current IBG; The output port is used to output a reset signal RSTN.

9. A power management circuit, characterized in that: It comprises a bandgap reference voltage source, a bandgap reference current source, and a power-on reset module as claimed in claim 7; the bandgap reference voltage source and the bandgap reference current source are respectively used to provide the power-on reset module with the required bandgap reference voltage VBG and bandgap reference current IBG.

10. An analog chip, characterized in that: It comprises an internal power supply module, and the internal power supply module adopts the power management circuit as claimed in claim 9.

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