Printed circuit board

Abstract

The present disclosure relates to a printed circuit board including: a first insulating layer having a through portion; a chip stack includes a first chip having a front surface on which a connection pad is disposed and a rear surface opposite the front surface, and a second chip attached to the rear surface of the first chip and having a different thickness from the first chip, at least one part of the chip stacking body is arranged in the through part; and a second insulating layer covering at least a portion of each of the first insulating layer and the chip stack, and at least a portion of the second insulating layer is disposed in the through portion.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0106257 filed on August 14, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] There is a demand for embedding passive components in a printed circuit board to ensure the power integrity of a server product. However, in the case of a server product, since warpage is substantially difficult to control due to a large body, there is a tendency to use a thick core layer, in which case there is a limit to increasing the thickness of the passive components, and difficulties have arisen when embedding the passive components in the core layer of the substrate due to inconsistent thickness. For example, when embedding a passive component that is relatively thinner than the core layer, difficulties may occur when filling the empty space with a build-up material. Summary of the invention

[0004] An aspect of the present disclosure is to provide a printed circuit board in which chips such as passive elements can be easily embedded even with a thick core layer.

[0005] The solution proposed by the present disclosure is to perform the embedding process by means of a chip stack in which the second chip is attached to the rear surface of the first chip, the thickness of the chip stack matching the thickness of the core layer as closely as possible.

[0006] For example, a printed circuit board according to an example embodiment may include: a first insulating layer having a through portion; a chip stack including a first chip and a second chip, the first chip having a front surface having a connecting pad disposed thereon and a rear surface opposite to the front surface, the second chip being attached to the rear surface of the first chip and having a thickness different from that of the first chip, wherein at least a portion of the chip stack is disposed in the through portion; and a second insulating layer covering at least a portion of each of the first insulating layer and the chip stack, and at least a portion of the second insulating layer is disposed in the through portion.

[0007] Another solution proposed by the present disclosure is to embed the first chip and the second chip in the core layer of the substrate by attaching the first chip and the second chip to each other in an offset manner.

[0008] For example, according to another example embodiment, a printed circuit board may include: a first insulating layer having a through portion; a first chip at least partially disposed in the through portion and having a front surface on which a connecting pad is disposed and a rear surface opposite to the front surface; a second chip at least partially disposed in the through portion and attached to the rear surface of the first chip so that an edge of the second chip is offset from the first chip on a plane; and a second insulating layer covering at least a portion of the first insulating layer and at least a portion of each of the first chip and the second chip, and at least a portion of the second insulating layer is disposed in the through portion.

[0009] For example, according to another example embodiment, a printed circuit board may include: a first insulating layer having a through portion; a stacked body including a chip and a dummy element, the chip having a front surface having a connecting pad disposed thereon and a rear surface opposite to the front surface, the dummy element being attached to the rear surface of the chip, wherein at least a portion of the stacked body is disposed in the through portion; and a second insulating layer covering at least a portion of each of the first insulating layer and the stacked body, and at least a portion of the second insulating layer is disposed in the through portion.

[0010] As one of various effects of the present disclosure, it is possible to provide a printed circuit board in which chips such as passive elements can be easily embedded even with a thick core layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a block diagram schematically illustrating an example of an electronic device system;

[0013] Figure 2 is a perspective view schematically showing an example of an electronic device;

[0014] Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board;

[0015] Figure 4 yes Figure 3 A plan view of the printed circuit board taken along line II';

[0016] Figure 5 It is schematically shown Figure 3 A cross-sectional view of a modified example embodiment of a printed circuit board;

[0017] Figure 6 It is schematically shown Figure 3A process cross-sectional view of an example of manufacturing a printed circuit board;

[0018] Figure 7 It is schematically shown Figure 3 A process cross-sectional view of another manufacturing example of a printed circuit board;

[0019] Figure 8 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board;

[0020] Fig. 9 yes Figure 8 A plan view of the printed circuit board taken along line II-II'; and

[0021] Fig.10 It is schematically shown Figure 8 A cross-sectional view of a modified example embodiment of a printed circuit board. DETAILED DESCRIPTION

[0022] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, the shapes and sizes of the elements may be enlarged or reduced for a clearer description. In the present disclosure, in addition to chips such as memory chips, application processor chips, and logic chips, a chip may also be understood to include elements such as passive elements. However, the present disclosure is not limited thereto.

[0023] Electronic Devices

[0024] Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0025] Reference Figure 1 , the electronic device 1000 accommodates a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, and other components 1040 are physically and / or electrically connected to the mainboard 1010. These components are also connected to other electronic components to be described below through various signal lines 1090.

[0026] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM, flash memory, etc.); application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific ICs (ASICs), etc. However, the chip-related components 1020 are not limited thereto, and may also include other types of chip-related components. In addition, the chip-related components 1020 may be combined with each other. The chip-related components 1020 may have the form of a package including the above-mentioned chips or electronic components.

[0027] The network-related components 1030 may include components that are compatible with or communicate according to protocols such as: Wireless Fidelity (Wi-Fi) (such as the IEEE 802.11 series), Worldwide Interoperability for Microwave Access (WiMAX) (such as the IEEE 802.16 series), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Bluetooth, Wireless Local Area Network (wireless LAN), third generation mobile communication technology (3G) protocol, fourth generation mobile communication technology (4G) protocol and fifth generation mobile communication technology (5G) protocol, as well as any other wireless standards or protocols and wired standards or protocols specified hereafter. However, the network-related component 1030 is not limited thereto, and may also include a component that is compatible with or communicates according to any one of a plurality of other wireless standards or protocols and wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020.

[0028] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components are not limited thereto, and may also include passive components in the form of chip components for various other purposes. In addition, other components 1040 may be combined with chip-related components 1020 and / or network-related components 1030.

[0029] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically and / or electrically connected to the mainboard 1010 or that are not physically and / or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, these other electronic components are not limited thereto, but may also include an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage device (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition to this, depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components for various purposes.

[0030] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automotive component. However, the electronic device 1000 is not limited thereto and may be any other electronic device capable of processing data in addition to the above-mentioned electronic devices.

[0031] Figure 2 is a perspective view schematically showing an example of an electronic device.

[0032] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 may be housed in the smart phone 1100, and various components 1120 may be physically and / or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically and / or electrically connected to the mainboard 1110 or that are not physically and / or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but the present disclosure is not limited thereto. The component package 1121 may have the form of a printed circuit board on which an electronic component including active components and / or passive components is surface mounted. Alternatively, the component package 1121 may have the form of a printed circuit board in which an electronic component including active components and / or passive components is embedded. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and may be other electronic devices as described above.

[0033] Printed Circuit Board

[0034] Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0035] Figure 4 yes Figure 3 A plan view of the printed circuit board taken along line II'.

[0036] Reference Figure 3 and Figure 4, a printed circuit board 100A according to an example embodiment may include: a first insulating layer 111 having a through portion H; a chip stack 150 including a first chip 151 and a second chip 152, the first chip 151 having a front surface on which a connection pad P is provided and a rear surface opposite to the front surface, the second chip 152 being attached to the rear surface of the first chip 151 by an adhesive 153, and at least a portion of the chip stack 150 being disposed in the through portion H; a second insulating layer 112 covering at least a portion of each of the first insulating layer 111 and the chip stack 150 and filling at least a portion of the through portion H; a first wiring layer 121 and a second wiring layer 122 being disposed on an upper surface and a lower surface of the first insulating layer 111, respectively; and a first via layer 131 penetrating the first insulating layer 111 and connecting at least a portion of each of the first wiring layer 121 and the second wiring layer 122 to each other. A thickness t2 of the second chip 152 may be different from a thickness t1 of the first chip 151. Each of the through-portions H and the chip stacks 150 may be provided in plural, and at least a portion of the plurality of chip stacks 150 may be provided in the plurality of through-portions H. For example, each of the plurality of chip stacks 150 is at least partially provided in a corresponding one of the plurality of through-portions H.

[0037] In this way, in the printed circuit board 100A according to the example embodiment, the chip stack 150 in which the first chip 151 and the second chip 152 are vertically stacked by the adhesive 153 can be disposed in the through-portion H of the first insulating layer 111. Therefore, even when the thickness of the first insulating layer 111 is thick, for example, even when the thickness of the first insulating layer 111 is 1.2 mm or more, the thickness of the chip stack 150 can be matched therewith as much as possible. In addition, even when the first insulating layer 111 is composed of one layer instead of multiple layers, the thickness of the chip stack 150 can be increased as needed, for example, 1.2 mm or more, and thus, the warpage stability can be further improved. In addition, since the thickness t2 of the second chip 152 can be adjusted to a thickness different from the thickness t1 of the first chip 151, the chip stack 150 can be more easily controlled to a desired thickness. Therefore, when the through-portion H is filled with the second insulating layer 112 (at least a portion of the second insulating layer 112 is filled in the through-portion H), the filling can be more easily performed. In addition, the process can be simplified, which can have the effect of reducing investment costs.

[0038] In addition, the first chip 151 may include passive components, and more preferably, include silicon capacitors. When the first chip 151 includes a silicon capacitor, the power integrity can be more effectively ensured when the printed circuit board 100A is applied to a server product. In this case, when the first chip 151 includes a silicon capacitor, the second chip 152 may also include a silicon body for warping stability, for example, the second chip 152 may include a silicon dummy. For example, each of the first chip 151 and the second chip 152 may include a silicon chip as a substrate, and the adhesive 153 connecting the first chip 151 and the second chip 152 may be a chip attach film (DAF). If necessary, like the first chip 151, the second chip 152 may include a silicon capacitor having a connection pad disposed on its front surface. In the case where both the first chip 151 and the second chip 152 include silicon capacitors, the first chip 151 and the second chip 152 can be embedded in the following form: the rear surface of the first chip 151 and the rear surface of the second chip 152 are attached to each other by an adhesive 153, and the connecting pads of the first chip 151 and the connecting pads of the second chip 152 face in opposite directions.

[0039] Hereinafter, components of a printed circuit board 100A according to example embodiments will be described in more detail with reference to the accompanying drawings.

[0040] Each of the first insulating layer 111 and the second insulating layer 112 may include an insulating material. The insulating material may include a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a material prepared by impregnating an inorganic filler, an organic filler and / or a glass fiber (such as a glass fabric exemplified by glass cloth) in a thermosetting resin and / or a thermoplastic resin. For example, the insulating material may be a non-photosensitive insulating material such as a copper clad laminate (CCL), an Ajinomoto deposited film (ABF), or a prepreg (PPG), but the present disclosure is not limited thereto. In addition, other polymer materials may be used. In addition, the insulating material may be a photosensitive insulating material such as a photosensitive dielectric (PID). As a non-limiting example, the first insulating layer 111 may include a CCL, and the second insulating layer 112 may include ABF or PPG. The first insulating layer 111 may be a core layer, and the second insulating layer 112 may be a deposited layer. The first insulating layer 111 may be one layer, and the second insulating layer 112 may include multiple layers.

[0041] The first wiring layer 121 and the second wiring layer 122 may each include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the first wiring layer 121 and the second wiring layer 122 may perform various functions according to the design. For example, each of the first wiring layer 121 and the second wiring layer 122 may include a signal pattern, a power pattern, and a ground pattern. Each of these patterns may have various forms such as lines, surfaces, and pads. Each of the first wiring layer 121 and the second wiring layer 122 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121 and the second wiring layer 122 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the first wiring layer 121 and the second wiring layer 122 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the first wiring layer 121 and the second wiring layer 122 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) if necessary.

[0042] The first via layer 131 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. The first via layer 131 may include a through-hole. The through-hole may include a plated through hole (PTH) formed conformally by forming an insulating material on the wall surface of a via hole penetrating the first insulating layer 111 and then plating the above-mentioned metal material thereon. The through-hole of the first via layer 131 may perform various functions according to the design of the corresponding layer. For example, the first via layer 131 may include a ground via, a power via, and a signal via. The first via layer 131 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. The first via layer 131 may include a sputtering layer instead of an electroless plating layer, and may include both a sputtering layer and an electroless plating layer.

[0043] Each of the first chip 151 and the second chip 152 may each include a silicon chip. The silicon chip may include an integrated circuit therein. However, the present disclosure is not limited thereto, and the silicon chip may be only a dummy chip. The silicon chip may be formed based on an effective wafer, in which case silicon (Si) or the like may be used as a substrate for forming the body of the silicon chip. The connection pad P may include a conductive material, such as aluminum (Al) or copper (Cu). The surface on which the connection pad P is provided in each of the first chip 151 and the second chip 152 may be a front surface or an effective surface, and the surface opposite thereto may be a rear surface or an ineffective surface. The first chip 151 may include a silicon capacitor, and the second chip 152 may include a silicon dummy part as a dummy element, but if necessary, the second chip 152 may also include a silicon capacitor. In the case where the second chip 152 is a dummy element, the second chip 152 may be electrically insulated from the first wiring layer 121 and the second wiring layer 122 and the first via layer 131, but the present disclosure is not limited thereto.

[0044] The adhesive 153 may be provided between the first chip 151 and the second chip 152 to connect the first chip 151 and the second chip 152 to each other. For example, the second chip 152 may be attached to the rear surface of the first chip 151 by the adhesive 153. The adhesive 153 may include an adhesive component such as an epoxy resin. The adhesive 153 may have a film type and may include, for example, a chip attach film (DAF), but the present disclosure is not limited thereto. The adhesive 153 may be thinner than the first chip 151 and the second chip 152, respectively.

[0045] Figure 5 It is schematically shown Figure 3 A cross-sectional view of a modified example embodiment of a printed circuit board.

[0046] Reference Figure 5Compared with the printed circuit board 100A according to the example embodiment, the printed circuit board 500A according to the modified example embodiment may further include: a third wiring layer 123 and a fourth wiring layer 124, which are respectively disposed on the upper surface and the lower surface of the second insulating layer 112; a second via layer 132, which penetrates a portion of the upper side of the second insulating layer 112 and connects at least a portion of each of the first wiring layer 121 and the third wiring layer 123 to each other, and connects at least a portion of each of the first wiring layer 121 and the connection pad P to each other; a third via layer 133, which penetrates a portion of the second insulating layer 112; a portion of the lower side, and connecting at least a portion of each of the second wiring layer 122 and the fourth wiring layer 124 to each other; a first resist layer 141 and a second resist layer 142, which are respectively arranged on the upper surface and the lower surface of the second insulating layer 112, and the first resist layer 141 has an opening that exposes at least a portion of the third wiring layer 123, and the second resist layer 142 has an opening that exposes at least a portion of the fourth wiring layer 124; and a semiconductor chip 200, which is arranged on the first resist layer 141 and connected to the exposed portion of the third wiring layer 123 through a connecting member 210.

[0047] In this manner, the printed circuit board 500A according to the modified example embodiment may include the printed circuit board 100A according to the example embodiment as a package substrate in which the chip stack 150 is embedded, and may have the form of a semiconductor package on which the semiconductor chip 200 is mounted.

[0048] Hereinafter, components of a printed circuit board 500A according to a modified example embodiment will be described in more detail with reference to the accompanying drawings.

[0049] Each of the third wiring layer 123 and the fourth wiring layer 124 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the third wiring layer 123 and the fourth wiring layer 124 may perform various functions according to the design. For example, each of the third wiring layer 123 and the fourth wiring layer 124 may include a signal pattern, a power pattern and a ground pattern. Each of these patterns may have various forms such as lines, surfaces and pads. Each of the third wiring layer 123 and the fourth wiring layer 124 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the third wiring layer 123 and the fourth wiring layer 124 may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, each of the third wiring layer 123 and the fourth wiring layer 124 may include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Each of the third wiring layer 123 and the fourth wiring layer 124 may include a sputtering layer instead of an electroless plating layer (e.g., a chemical copper plating layer), and may include both a sputtering layer and an electroless plating layer (e.g., a chemical copper plating layer) if necessary.

[0050] Each of the second via layer 132 and the third via layer 133 may include a metal material. The metal material may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) and / or their alloys. The metal material may preferably include copper (Cu), but the present disclosure is not limited thereto. Each of the second via layer 132 and the third via layer 133 may include a micro via. The micro via may be a filled via formed by filling a via hole with a metal material, or may be a conformal via formed by arranging a metal material along the wall surface of the via hole. The micro via may be arranged as a stacked type and / or an interlaced type. The micro vias of each of the second via layer 132 and the third via layer 133 may perform various functions according to the design of the corresponding layer. For example, each of the second via layer 132 and the third via layer 133 may include a ground via, a power via, and a signal via. Each of the second via layer 132 and the third via layer 133 may include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), but the present disclosure is not limited thereto. Each of the second via layer 132 and the third via layer 133 may include a sputtering layer instead of an electroless plating layer, and may include both a sputtering layer and an electroless plating layer. The second via layer 132 and the third via layer 133 may have a shape that tapers in opposite directions. In the case where the second chip 152 is a dummy element, the second chip 152 may be electrically insulated from the first wiring layer 121 to the fourth wiring layer 124 and the first via layer 131 to the third via layer 133, but the present disclosure is not limited thereto.

[0051] Each of the first resist layer 141 and the second resist layer 142 may include a liquid solder resist or a film type solder resist, but the present disclosure is not limited thereto, and the first resist layer 141 and the second resist layer 142 may include other types of insulating materials such as ABF. The first resist layer 141 may have an opening that exposes at least a portion of the third wiring layer 123, the second resist layer 142 may have an opening that exposes at least a portion of the fourth wiring layer 124, and a surface treatment layer may be formed on the exposed pattern as needed.

[0052] The semiconductor chip 200 may include an integrated circuit (IC) chip in which hundreds to millions of devices are integrated into one chip. In this case, for example, the integrated circuit may be: a logic chip such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, an application processor (AP), an analog-to-digital converter, and an application-specific IC (ASIC), but the present disclosure is not limited thereto, and the integrated circuit may be: a memory chip such as a volatile memory (e.g., DRAM), a non-volatile memory (e.g., ROM), a flash memory, and a high bandwidth memory (HBM); or other types of chips such as a power management IC (PMIC).

[0053] The semiconductor chip 200 may be formed based on an effective wafer, in which case silicon (Si), germanium (Ge) and gallium arsenide (GaAs) may be used as a base material for forming the body of the semiconductor chip 200. Various circuits may be formed in the body. A connection pad may be formed on the body, and the connection pad may include a conductive material such as aluminum (Al) or copper (Cu). The semiconductor chip 200 may be a bare die, in which case a metal bump may be provided on the connection pad. The semiconductor chip 200 may be a packaged chip, in which case a redistribution layer may be additionally formed on the connection pad, and a metal bump may be provided on the redistribution layer.

[0054] The connection member 210 may be formed using a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu) solder, but this is only an example, and its material is not specifically limited thereto. The connection member 210 may be formed as a multilayer or a single layer. When the connection member 210 is formed as a multilayer, the connection member 210 may include a copper column and a solder, and when the connection member 210 is formed as a single layer, the connection member 210 may include a tin-silver solder or copper, but the present disclosure is not limited thereto. The connection member 210 may be provided in plurality.

[0055] The other contents are substantially the same as those described with respect to the printed circuit board 100A according to the above-described example embodiment, and thus a repeated description thereof will be omitted.

[0056] Figure 6 It is schematically shown Figure 3 A cross-sectional view of a process for manufacturing an example of a printed circuit board.

[0057] Reference Figure 6First, a first insulating layer 111 is prepared using CCL or the like, and a through-portion H, a first wiring layer 121, a second wiring layer 122, and a first via layer 131 are formed in the first insulating layer 111. The through-portion H may be formed using mechanical drilling, laser drilling, sandblasting, or the like. A via hole for the first via layer 131 may be formed using mechanical drilling, laser drilling, or the like. The first wiring layer 121, the second wiring layer 122, and the first via layer 131 may be formed by a circuit forming process such as an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), and a sealing hole (TT). When forming the first via layer 131, a plugging process of filling the inside of the through-portion with an insulating material may be included. Next, a tape 310 is attached to the lower side of the first insulating layer 111. The tape 310 may be attached to the first wiring layer 121. The tape 310 may block the lower portion of the through-portion H. Then, according to the thickness of the first insulating layer 111, the chip stack 150 is formed by connecting the first chip 151 and the second chip 152 with an adhesive 153, and the previously formed chip stack 150 is arranged in the through-portion H. For example, the chip stack 150 may be arranged so that the front surface of the first chip 151 on which the connection pad P is arranged is attached to the tape 310. Next, a second-first insulating layer 112-1 that buries the first insulating layer 111, the first wiring layer 121 and the second wiring layer 122, and the chip stack 150 and fills the through-portion H is formed on the tape 310. The second-first insulating layer 112-1 may be formed in a lamination process while being attached to a film such as a polyethylene terephthalate (PET) film. Next, the tape 310 is removed. Then, the second-second insulating layer 112-2 is formed in the region where the tape 310 is removed (for example, under the second-first insulating layer 112-1). The second-second insulating layer 112-2 may also be formed in a lamination process while being attached to a film such as a PET film. The second-first insulating layer 112-1 and the second-second insulating layer 112-2 may be integrated after curing to the extent that their boundaries are indistinguishable from each other and become the second insulating layer 112.

[0058] The printed circuit board 100A according to the above-described example embodiment can be manufactured in a series of processes, and its repeated description will be omitted. In addition, in the series of processes, compared with the printed circuit board 100A according to the above-described example embodiment, the process is described as being performed in a vertical inverted form, and it is obvious that the printed circuit board 100A according to the above-described example embodiment can be manufactured by flipping and removing the two outermost wiring structures located on both sides, each including the first wiring layer 121, the second wiring layer 122 and the first via layer 131, after the series of processes are completed. Here, in the series of processes, seven wiring structures are shown, however, the number of wiring structures can be changed according to design requirements. For example, five wiring structures can be pre-formed and after the series of processes are completed, it is not necessary to remove the wiring structures to manufacture the printed circuit board 100A according to the above-described example embodiment.

[0059] Figure 7 It is schematically shown Figure 3 A cross-sectional view of another manufacturing process of a printed circuit board.

[0060] Reference Figure 7First, a first insulating layer 111 is prepared using CCL or the like, and a through-portion H, a first wiring layer 121, a second wiring layer 122, and a first via layer 131 are formed in the first insulating layer 111. The through-portion H may be formed using mechanical drilling, laser drilling, sandblasting, or the like. A via hole for the first via layer 131 may be formed using mechanical drilling, laser drilling, or the like. The first wiring layer 121, the second wiring layer 122, and the first via layer 131 may be formed by a circuit forming process such as an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), and a sealing hole (TT). When forming the first via layer 131, a plugging process of filling the inside of the through-portion with an insulating material may be included. Next, a tape 310 is attached to the lower side of the first insulating layer 111. The tape 310 may be attached to the first wiring layer 121. The tape 310 may block the lower portion of the through-portion H. Then, a first chip 151 is disposed in the through-portion H. For example, the first chip 151 may be arranged so that the front surface on which the connection pad P is arranged is attached to the tape 310. Next, the second chip 152 is attached to the rear surface of the first chip 151 in the through-portion H using an adhesive 153 to form a chip stack 150. In this case, the second chip 152 may have a thickness arranged so that the thickness of the chip stack 150 substantially matches the thickness of the first insulating layer 111. Next, a second-first insulating layer 112-1 is formed on the tape 310 to bury the first insulating layer 111, the first wiring layer 121, and the second wiring layer 122, and the chip stack 150 and fill the through-portion H. The second-first insulating layer 112-1 may be formed in a lamination process while being attached to a film such as a PET film. Next, the tape 310 is removed. Then, a second-second insulating layer 112-2 is formed in the region where the tape 310 is removed (for example, below the second-first insulating layer 112-1). The second-second insulating layer 112-2 may also be formed in a lamination process while being attached to a film such as a PET film.The second-first insulating layer 112-1 and the second-second insulating layer 112-2 may be integrated after curing to the extent that their boundaries are indistinguishable from each other.

[0061] The printed circuit board 100A according to the above-described example embodiment can be manufactured in a series of processes, and its repeated description is omitted. In addition, in a series of processes, compared with the printed circuit board 100A according to the above-described example embodiment, the process is described as being performed in a vertical inverted form, and it is obvious that the printed circuit board 100A according to the above-described example embodiment can be manufactured by flipping and removing the two outermost wiring structures located on both sides, each including the first wiring layer 121, the second wiring layer 122 and the first via layer 131, after the series of processes are completed. Here, in the series of processes, seven wiring structures are shown, however, the number of wiring structures can be changed according to design requirements. For example, five wiring structures can be pre-formed and after the series of processes are completed, it is not necessary to remove the wiring structures to manufacture the printed circuit board 100A according to the above-described example embodiment.

[0062] Figure 8 is a cross-sectional view schematically illustrating another example embodiment of a printed circuit board.

[0063] Fig. 9 yes Figure 8 A plan view of the printed circuit board taken along line II-II'.

[0064] Fig.10 It is schematically shown Figure 8 A cross-sectional view of a modified example embodiment of a printed circuit board.

[0065] Referring to the drawings, compared with the printed circuit board 100A according to the example embodiment and the printed circuit board 500A according to the modified example embodiment described above, in the printed circuit board 100B according to another example embodiment and the printed circuit board 500B according to the modified example embodiment, the second chip 152 may be attached to the rear surface of the first chip 151 in a state where the second chip 152 is rotated to be offset from the first chip 151 when viewed from above. For example, Fig. 9 As shown in , on a plane, the edge of the second chip 152 may be offset from the edge of the first chip 151. For example, as shown in Figure 8 As shown in , in the cross section, a step difference may be formed between the side surface of the second chip 152 and the side surface of the first chip 151. Therefore, the second chip 152 may be more easily attached to the first chip 151, and the through portion H may also be more easily filled with the second insulating layer 112. In addition, the process may be simplified, which may have the effect of reducing investment costs.

[0066] The other contents are substantially the same as those described in the printed circuit board 100A according to the exemplary embodiment and the printed circuit board 500A according to the modified exemplary embodiment as described above, and thus their repeated description will be omitted. In addition, the above contents can be applied to the manufacturing process in substantially the same manner, and thus their repeated description will also be omitted.

[0067] In the present disclosure, the expression "covering" may include the case of covering at least a part as well as the case of covering the whole, and may also include the case of not only direct covering but also indirect covering. In addition, the expression "filling" may include not only the case of complete filling but also the case of approximately filling, and may include, for example, the case of the presence of some holes or gaps.

[0068] In the present disclosure, the meaning of a cross section may refer to a cross-sectional shape when an object is cut vertically, or a cross-sectional shape when the object is observed in a side view. In addition, the meaning of a plane may refer to a plane shape when an object is cut horizontally, or a plane shape when the object is observed in a top view or an upward view.

[0069] In the present disclosure, the thickness, width, length, depth, etc. can be measured using a scanning microscope or an optical microscope based on a cross section in which the printed circuit board is polished or cut. The cut cross section can be a vertical cross section or a horizontal cross section, and each value thereof can be measured based on the desired cut cross section. When the value is not constant, the value can be determined as the average value of the values ​​measured at any five points. The width of the upper and / or lower ends of the via or groove can be measured on a cross section obtained by cutting the central axis of the via or groove in the thickness direction of the substrate. The depth of the via or groove can be measured as: the distance from the upper end to the lower end of each object on a cross section obtained by cutting the central axis of each object in the thickness direction of the substrate.

[0070] In the present disclosure, "lower" in the lower side, lower part, and lower surface is used to indicate a downward direction relative to the cross section of the drawing, and "upper" in the upper side, upper part, and upper surface is used to indicate a direction opposite thereto. In addition, "side" in the side part, side surface, etc. is used to indicate a direction perpendicular to the upper surface and the lower surface. However, this is to define the direction for the convenience of explanation, and the scope of the right of the claims is not specifically limited by the description of such a direction, and the concepts of upper and lower may be changed at any time.

[0071] In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of electrical connection is a concept including both physical connection and non-physical connection. In addition, expressions such as first and second are used to distinguish one component from another component and do not limit the order and / or importance of the components. In some cases, without departing from the scope of the rights, a first component may be referred to as a second component, or similarly, a second component may be referred to as a first component.

[0072] The expression "exemplary embodiment" used in this disclosure does not mean the same embodiment, and is provided to illustrate different unique features. However, the exemplary embodiments presented above do not exclude being implemented in combination with features of other exemplary embodiments. For example, even if matters described in a particular exemplary embodiment are not described in other exemplary embodiments, they can be understood as descriptions related to other exemplary embodiments unless there are contrary or contradictory descriptions of matters in other exemplary embodiments.

[0073] The terms used in the present disclosure are only used to describe example embodiments and are not intended to limit the present disclosure. In this case, a singular expression includes a plural expression unless they are clearly indicated to be different in the context.

[0074] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: A first insulating layer having a through portion; a chip stack, comprising a first chip and a second chip, the first chip having a front surface on which connection pads are provided and a rear surface opposite to the front surface, the second chip being attached to the rear surface of the first chip and having a different thickness from the first chip, wherein at least a portion of the chip stack is provided in the through portion; as well as A second insulating layer covers at least a portion of each of the first insulating layer and the chip stack, and at least a portion of the second insulating layer is disposed in the through portion.

2. The printed circuit board according to claim 1, wherein: The first chip includes a silicon capacitor.

3. The printed circuit board according to claim 2, wherein: The second chip includes a silicon dummy.

4. The printed circuit board according to claim 1, wherein: The chip stack further includes an adhesive disposed between the first chip and the second chip.

5. The printed circuit board according to claim 4, wherein: The adhesive includes a die attach film.

6. The printed circuit board according to claim 1, wherein The thickness of the first insulating layer is 1.2 mm or greater.

7. The printed circuit board according to claim 1, further comprising: A first wiring layer and a second wiring layer are respectively arranged on the upper surface and the lower surface of the first insulating layer; as well as A first via layer penetrates the first insulating layer and connects at least a portion of each of the first wiring layer and the second wiring layer to each other.

8. The printed circuit board according to claim 7, further comprising: A third wiring layer and a fourth wiring layer are respectively arranged on the upper surface and the lower surface of the second insulating layer; a second via layer penetrating a portion of an upper side of the second insulating layer, connecting at least a portion of each of the first wiring layer and the third wiring layer to each other, and connecting at least a portion of each of the first wiring layer and the connection pads to each other; as well as a third via layer penetrating a portion of a lower side of the second insulating layer and connecting at least a portion of each of the second wiring layer and the fourth wiring layer to each other.

9. The printed circuit board according to claim 8, further comprising: A first resist layer and a second resist layer are respectively arranged on the upper surface and the lower surface of the second insulating layer, and the first resist layer has an opening that exposes at least a portion of the third wiring layer, and the second resist layer has an opening that exposes at least a portion of the fourth wiring layer.

10. The printed circuit board according to claim 9, further comprising: A semiconductor chip is provided on the first resist layer and connected to the exposed portion of the third wiring layer.

11. The printed circuit board according to any one of claims 1 to 10, wherein: Each of the through portion and the chip stack is provided in plural numbers, and Each of the plurality of chip stacks is at least partially disposed in a corresponding one of the plurality of through-portions.

12. A printed circuit board, comprising: A first insulating layer having a through portion; a first chip at least partially disposed in the through-portion and having a front surface on which connection pads are disposed and a rear surface opposite to the front surface; a second chip at least partially disposed in the through-portion and attached to the rear surface of the first chip such that an edge of the second chip is offset from the first chip in a plane; as well as A second insulating layer covers at least a portion of the first insulating layer and at least a portion of each of the first chip and the second chip, and at least a portion of the second insulating layer is disposed in the through-portion.

13. The printed circuit board according to claim 12, wherein: In a cross section, a step difference is formed between a side surface of the second chip and a side surface of the first chip.

14. The printed circuit board according to claim 12, further comprising: An adhesive is disposed between the first chip and the second chip and attaches the second chip to the rear surface of the first chip.

15. The printed circuit board according to claim 14, wherein Each of the first chip and the second chip includes a silicon chip, and The adhesive includes a die attach film.

16. The printed circuit board according to any one of claims 12 to 15, further comprising: A first wiring layer and a second wiring layer are respectively arranged above and below the first insulating layer; as well as A first via layer is at least partially provided in the first insulating layer and connects at least a portion of each of the first wiring layer and the second wiring layer to each other.

17. The printed circuit board according to claim 16, further comprising: A third wiring layer and a fourth wiring layer are respectively arranged above and below the second insulating layer; a second via layer, at least partially disposed in an upper side of the second insulating layer, connecting at least a portion of each of the first wiring layer and the third wiring layer to each other, and connecting at least a portion of each of the first wiring layer and the connection pads to each other; as well as A third via layer is at least partially provided in a lower side of the second insulating layer and connects at least a portion of each of the second wiring layer and the fourth wiring layer to each other.

18. A printed circuit board, comprising: A first insulating layer having a through portion; a stacked body comprising a chip having a front surface on which connection pads are disposed and a rear surface opposite to the front surface, and a dummy element attached to the rear surface of the chip, wherein at least a portion of the stacked body is disposed in the through portion; as well as A second insulating layer covers at least a portion of each of the first insulating layer and the stacked body, and at least a portion of the second insulating layer is disposed in the through portion.

19. The printed circuit board according to claim 18, further comprising: A first wiring layer and a second wiring layer are respectively arranged on the upper surface and the lower surface of the first insulating layer; a first via layer that penetrates the first insulating layer and connects at least a portion of each of the first wiring layer and the second wiring layer to each other; A third wiring layer and a fourth wiring layer are respectively arranged on the upper surface and the lower surface of the second insulating layer; a second via layer penetrating a portion of an upper side of the second insulating layer, connecting at least a portion of each of the first wiring layer and the third wiring layer to each other, and connecting at least a portion of each of the first wiring layer and the connection pads to each other; as well as a third via layer penetrating a portion of a lower side of the second insulating layer and connecting at least a portion of each of the second wiring layer and the fourth wiring layer to each other.

20. The printed circuit board according to claim 19, wherein The dummy element is electrically insulated from the first to fourth wiring layers and the first to third via layers.

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