Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a pull-down transistor formed by a first gate structure, a first channel layer and a first source and drain, and a pull-up transistor formed by the first gate structure, a second channel layer and a second source and drain; the gate plug is located at the top of the first gate structure, and the gate plug is electrically connected with the first gate structure; the dielectric layer is located at the top of the substrate and covers the pull-down transistor, the pull-up transistor and the gate plug; the metal layer is located on the top of the dielectric layer; the groove penetrates through the metal layer, the dielectric layer and a part of thickness of the gate plug; the third channel layer covers the bottom and the side wall of the groove; the second gate structure is located in the remaining space of the groove, the gate plug surrounding the second gate structure is used as a third source drain electrode, the metal layer surrounding the second gate structure is used as a fourth source drain electrode, and the second gate structure, the third channel layer, the third source drain electrode and the fourth source drain electrode form a transmission gate transistor. The integration level of the semiconductor structure is improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three categories: logic, memory and analog circuits, among which memory devices account for a considerable proportion of integrated circuit products. With the development of semiconductor technology, memory devices are more widely used, and it is necessary to form the memory devices and other device areas on a chip at the same time to form an embedded semiconductor storage device. For example, if the memory device is embedded in a central processing unit, it is necessary to make the memory device compatible with the embedded central processing unit platform and maintain the original specifications and corresponding electrical performance of the memory device.

[0003] Generally, the memory device needs to be compatible with the embedded standard logic device. For embedded semiconductor devices, they are usually divided into a logic area and a storage area, the logic area usually includes a logic device, and the storage area includes a memory device. With the development of storage technology, various types of semiconductor memories have emerged, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory (Flash). Since static random access memory has the advantages of low power consumption and faster operating speed, static random access memory and its formation method have received more and more attention.

[0004] Currently, the integration level of SRAM devices still needs to be improved. Summary of the invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby optimizing the performance of the semiconductor device.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate; a channel stack structure, located on the substrate, and the channel stack structure comprises a first channel layer and a second channel layer spaced apart and arranged on the first channel layer; a first gate structure, spanning the channel stack structure, and surrounding and covering the first channel layer and the second channel layer; a first source and drain, located in the first channel layer on both sides of the first gate structure; a second source and drain, located in the second channel layer on both sides of the first gate structure, and the first gate structure, the first channel layer and the first source and drain constitute a pull-down transistor, and the first gate structure, the second channel layer and the second source and drain constitute a pull-up transistor; and a gate structure. a gate plug located on the top of the first gate structure and electrically connected to the first gate structure; a dielectric layer located on the top of the substrate and covering the pull-down transistor, the pull-up transistor and the gate plug; a metal layer located on the top of the dielectric layer; a groove penetrating the metal layer, the dielectric layer and a portion of the thickness of the gate plug; a third channel layer covering the bottom and sidewalls of the groove; a second gate structure located in the remaining space of the groove, and the gate plug surrounding the second gate structure is used as a third source and drain, the metal layer surrounding the second gate structure is used as a fourth source and drain, and the second gate structure, the third channel layer, the third source and drain and the fourth source and drain constitute a transmission gate transistor.

[0007] Correspondingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel stack structure, a first gate structure spanning the channel stack structure, a first source and drain in a first channel layer on both sides of the first gate structure, and a second source and drain in a second channel layer on both sides of the first gate structure on the substrate, wherein the channel stack structure comprises a first channel layer and a second channel layer spaced apart on the first channel layer, the first gate structure surrounds and covers the first channel layer and the second channel layer, wherein the first gate structure, the first channel layer and the first source and drain constitute a pull-down transistor, and the first gate structure, the second channel layer and the second source and drain constitute an upper pull-up transistor. body transistor; forming a gate plug on the top of the first gate structure, and the gate plug is electrically connected to the first gate structure; forming a dielectric layer covering the pull-down transistor, the pull-up transistor and the gate plug; forming a metal layer on the top of the dielectric layer; forming a groove penetrating the metal layer, the dielectric layer and a portion of the gate plug on the top of the first gate structure; forming a third channel layer covering the bottom and sidewalls of the groove; forming a second gate structure in the remaining space of the groove, and the gate plug surrounding the second gate structure is used as a third source and drain, the metal layer surrounding the second gate structure is used as a fourth source and drain, and the second gate structure, the third channel layer, the third source and drain and the fourth source and drain constitute a transmission gate transistor.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure and the method for forming the semiconductor structure provided by the embodiments of the present invention, the first gate structure, the first channel layer and the first source and drain constitute a pull-down transistor, the first gate structure, the second channel layer and the second source and drain constitute a pull-up transistor, a gate plug is formed on the top of the first gate structure, and the gate plug is electrically connected to the first gate structure to form a dielectric layer covering the pull-down transistor, the pull-up transistor and the gate plug, a metal layer is formed on the top of the dielectric layer, a groove penetrating the metal layer, the dielectric layer and a portion of the gate plug is formed on the top of the first gate structure to form a third channel layer covering the bottom and sidewalls of the groove, a second gate structure is formed in the remaining space of the groove, the gate plug surrounding the second gate structure is used as a third source and drain, the metal layer surrounding the second gate structure is used as a fourth source and drain, and the second gate structure, the third channel layer, the third source and drain and the fourth source and drain constitute a transmission gate transistor. Therefore, the semiconductor structure of the embodiment of the present invention adopts a pull-down transistor and a pull-up transistor based on a CFET (complementary FET) structure, and a transfer gate transistor based on a CAA (channel all around) structure to realize the stacking arrangement of the pull-down transistor, the pull-up transistor and the transfer gate transistor. Moreover, the transfer gate transistor in the embodiment of the present invention is arranged in the dielectric layer, that is, the transfer gate transistor utilizes part of the spatial position of the dielectric layer, which can reduce the overall height of the memory and the space area occupied by the memory is smaller, which is conducive to further reducing the overall size of the semiconductor structure (for example, compared with a memory based on a fin field effect transistor, a memory based on a CFET can save about 40% of the chip area without changing the spacing size, and the semiconductor structure of the embodiment of the present invention can save about 20% of the area on this basis), thereby improving the integration of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 to Figure 2 is a structural schematic diagram corresponding to an embodiment of a semiconductor structure of the present invention;

[0011] Figures 3 to 25 It is a schematic structural diagram corresponding to each step in the first embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0012] As can be seen from the background technology, currently, the integration level of SRAM devices still needs to be improved and still occupies a large chip area.

[0013] In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel stack structure, a first gate structure spanning the channel stack structure, a first source and drain in a first channel layer on both sides of the first gate structure, and a second source and drain in a second channel layer on both sides of the first gate structure on the substrate, wherein the channel stack structure comprises a first channel layer and a second channel layer spaced apart on the first channel layer, the first gate structure surrounds and covers the first channel layer and the second channel layer, wherein the first gate structure, the first channel layer and the first source and drain constitute a pull-down transistor, and the first gate structure, the second channel layer and the second source and drain constitute an upper A pull-up transistor is formed; a gate plug is formed on the top of the first gate structure, and the gate plug is electrically connected to the first gate structure; a dielectric layer is formed to cover the pull-down transistor, the pull-up transistor and the gate plug; a metal layer is formed on the top of the dielectric layer; a groove is formed on the top of the first gate structure to penetrate the metal layer, the dielectric layer and a portion of the gate plug; a third channel layer is formed to cover the bottom and sidewalls of the groove; a second gate structure is formed in the remaining space of the groove, and the gate plug surrounding the second gate structure is used as a third source and drain, and the metal layer surrounding the second gate structure is used as a fourth source and drain, and the second gate structure, the third channel layer, the third source and drain, and the fourth source and drain constitute a transmission gate transistor.

[0014] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a first gate structure, a first channel layer, and a first source and drain constitute a pull-down transistor, and a first gate structure, a second channel layer, and a second source and drain constitute a pull-up transistor. A gate plug is formed on the top of the first gate structure, and the gate plug is electrically connected to the first gate structure to form a dielectric layer covering the pull-down transistor, the pull-up transistor, and the gate plug. A metal layer is formed on the top of the dielectric layer, and a groove penetrating the metal layer, the dielectric layer, and a portion of the gate plug is formed on the top of the first gate structure to form a third channel layer covering the bottom and sidewalls of the groove. A second gate structure is formed in the remaining space of the groove, and the gate plug surrounding the second gate structure is used as a third source and drain, and the metal layer surrounding the second gate structure is used as a fourth source and drain. The second gate structure, the third channel layer, the third source and drain, and the fourth source and drain constitute a transmission gate transistor. Therefore, the semiconductor structure of the embodiment of the present invention adopts a pull-down transistor and a pull-up transistor based on a CFET (complementary FET) structure, and a transfer gate transistor based on a CAA (channel all around) structure to realize the stacking arrangement of the pull-down transistor, the pull-up transistor and the transfer gate transistor. Moreover, the transfer gate transistor in the embodiment of the present invention is arranged in the dielectric layer, that is, the transfer gate transistor utilizes part of the spatial position of the dielectric layer, which can reduce the overall height of the memory and the space area occupied by the memory is smaller, which is conducive to further reducing the overall size of the semiconductor structure (for example, compared with a memory based on a fin field effect transistor, a memory based on a CFET can save about 40% of the chip area without changing the spacing size, and the semiconductor structure of the embodiment of the present invention can save about 20% of the area on this basis), thereby improving the integration of the semiconductor structure.

[0015] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and understandable, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0016] Figure 1 to Figure 2 is a schematic structural diagram corresponding to an embodiment of a semiconductor structure of the present invention, wherein: Figure 1 It is a three-dimensional diagram of the semiconductor structure. Figure 2 yes Figure 1 Cross-sectional view along CC direction.

[0017] The semiconductor structure includes: a substrate 200; a channel stack structure 288, which is located on the substrate 200, and the channel stack structure 288 includes a first channel layer 205 and a second channel layer 207 spaced apart on the first channel layer 205; a first gate structure 240, which spans the channel stack structure 288 and surrounds and covers the first channel layer 205 and the second channel layer 207; a first source and drain 231, which is located in the first channel layer 205 on both sides of the first gate structure 240; a second source and drain 230, which is located in the second channel layer 207 on both sides of the first gate structure 240, and the first gate structure 240, the first channel layer 205 and the first source and drain 231 constitute a pull-down transistor, and the first gate structure 240, the second channel layer 207 and the second source and drain 230 constitute a pull-up transistor; a gate plug 290, which is located on the top of the first gate structure 240, and The gate plug 290 is electrically connected to the first gate structure 240; the dielectric layer 229 is located on the top of the substrate 200 and covers the pull-down transistor, the pull-up transistor and the gate plug 290; the metal layer 293 is located on the top of the dielectric layer 229; the groove (not shown) penetrates the metal layer 293, the dielectric layer 229 and a portion of the thickness of the gate plug 290; the third channel layer 239 covers the bottom and sidewalls of the groove (not shown); the second gate structure 295 is located in the remaining space of the groove (not shown), and the gate plug 290 surrounding the second gate structure 295 is used as a third source and drain (not marked), the metal layer 293 surrounding the second gate structure 295 is used as a fourth source and drain (not marked), and the second gate structure 295, the third channel layer 239, the third source and drain (not marked) and the fourth source and drain (not marked) constitute a transmission gate transistor.

[0018] It should be noted that the semiconductor structure of this embodiment adopts a pull-down transistor and a pull-up transistor based on a CFET (complementary FET) structure, and a transfer gate transistor based on a CAA (channel all around) structure to realize the stacking arrangement of the pull-down transistor, the pull-up transistor and the transfer gate transistor. Moreover, the transfer gate transistor in this embodiment is arranged in the dielectric layer 229, that is, the transfer gate transistor utilizes part of the spatial position of the dielectric layer 229, which can reduce the overall height of the memory and the space area occupied by the memory is smaller, which is conducive to further reducing the overall size of the semiconductor structure (for example, compared with a memory based on fin field effect transistors, a memory based on CFET can save about 40% of the chip area without changing the spacing size, and the semiconductor structure of the embodiment of the present invention can save about 20% of the area on this basis), thereby improving the integration of the semiconductor structure.

[0019] The substrate 200 provides a process platform for setting up a semiconductor structure.

[0020] In this embodiment, the base 200 includes a substrate.

[0021] The material of the substrate is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0022] In this embodiment, the substrate 200 includes a first sub-unit region 200A and a second sub-unit region 200B adjacent to each other, and the first sub-unit region 200A and the second sub-unit region 200B adjacent to each other constitute a memory unit region 200C.

[0023] In this embodiment, the semiconductor structure is an SRAM device, and the SRAM device includes a plurality of memory cell areas 200C.

[0024] Specifically, the first sub-unit region 200A and the second sub-unit region 200B each include a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region.

[0025] Specifically, the transmission gate transistor region is used to form a transmission gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. Wherein, the transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0026] Specifically, the channel stack structure 288 is used to provide a conductive channel for the pull-up transistor and the pull-down transistor.

[0027] In this embodiment, the channel stack structure 288 is respectively located on the substrate 200 in the first sub-unit region 200A and the second sub-unit region 200B.

[0028] In this embodiment, the channel stack structure 288 includes a first channel layer 205 and a second channel layer 207 spaced apart from the first channel layer 205 .

[0029] The stacking direction of the first channel layer 205 and the second channel layer 207 is perpendicular to the surface of the substrate 200 .

[0030] In this embodiment, the material of the first channel layer 205 and the second channel layer 207 is the same as the material of the substrate 200 , and the material of the first channel layer 205 and the second channel layer 207 are both Si.

[0031] The first gate structure 240 is used to control the opening and closing of the conductive channel when the SRAM device is working.

[0032] Specifically, the first gate structure 240 is a metal gate structure.

[0033] In this embodiment, the first gate structure 240 includes a first gate dielectric layer (not shown) and a first gate electrode layer (not shown) covering the first gate dielectric layer.

[0034] In this embodiment, the material of the first gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0035] Specifically, the first gate dielectric layer includes a first gate oxide layer and a first high-k gate dielectric layer conformally covering the first gate oxide layer. The material of the first high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0036] The first gate electrode layer is used for subsequent electrical connection with an external structure. The material of the first gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the first gate electrode layer may include a first work function layer and a first electrode layer covering the first work function layer, or the first gate electrode layer may also include only the first work function layer.

[0037] In this embodiment, the first gate structure 240 surrounds and covers the first channel layer 205 and the second channel layer 207 .

[0038] Specifically, the first gate structure 240 surrounds and covers the top and sidewalls of the first channel layer 205 , and the second gate structure 295 surrounds and covers the top, sidewalls and bottom of the second channel layer 207 .

[0039] It should be noted that in an SRAM device, the pull-up transistor and the pull-down transistor are used to store data.

[0040] In this embodiment, the semiconductor structure further includes an inner wall layer 220 located between the first source and drain 231 and the first gate structure 240 , and between the second source and drain 230 and the second gate structure 295 .

[0041] The inner wall layer 220 can isolate the first source drain 231 from the first gate structure 240 , and the second source drain 230 from the first gate structure 240 , which is beneficial to reducing the parasitic capacitance between the first source drain 231 and the first gate structure 240 , and between the second source drain 230 and the first gate structure 240 .

[0042] In this embodiment, the material of the inner wall layer 220 includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

[0043] Specifically, silicon nitride, silicon oxide and silicon oxynitride are all dielectric materials, which can play a role in electrically isolating the first source and drain 231 and the first gate structure 240 formed subsequently, and the second source and drain 230 and the first gate structure 240 .

[0044] The first source-drain electrode 231 is used as the source and drain of the pull-down transistor.

[0045] Specifically, since the pull-down transistor is an N-type transistor, the doping type of the first source and drain 231 is N-type.

[0046] The second source-drain electrode 230 is used as the source and drain of the pull-up transistor.

[0047] Specifically, since the pull-up transistor is a P-type transistor, the doping type of the second source and drain 230 is P-type.

[0048] In this embodiment, on one side of the gate structure, the second source-drain 230 is in contact with the first source-drain 231 thereunder; on the other side of the gate structure, the second source-drain 230 is separated from the first source-drain 231 thereunder.

[0049] It should be noted that, on one side of the gate structure, the second source and drain 230 is in contact with the first source and drain 231 located therebelow, thereby electrically connecting the drain region in the pull-up transistor to the drain region in the pull-down transistor. At the same time, on one side of the gate structure, the second source and drain 230 is in contact with the first source and drain 231 located therebelow, thereby reducing the process difficulty of forming the second source and drain 230 and the first source and drain 231, and eliminating the process step of additionally setting up an interconnection structure connected to the second source and drain 230 and the first source and drain 231, thereby electrically connecting the first source and drain 231 to the second source and drain 230, thereby reducing the process cost and reducing the process steps.

[0050] It should also be noted that, on the other side of the gate structure, the second source-drain 230 is separated from the first source-drain 231 located therebelow, so that another second source-drain 230 in the first sub-unit area 200A can be electrically connected to the first source-drain plug 250, and the first source-drain 231 located therebelow can be electrically connected to the second source-drain plug 252, thereby achieving that in the first sub-unit area 200A, the source region of the pull-up transistor can be connected to the power supply voltage through the second source-drain plug 252, and the source region of the pull-down transistor can be connected to the power supply voltage through the first source-drain plug 250.

[0051] In the present embodiment, the contacting second source drain 230 and the first source drain 231 are an integrated structure. In the steps of forming the second source drain 230 and the first source drain 231, the process step of additionally setting up an interconnection structure connecting the second source drain 230 and the first source drain 231 is omitted, so that the first source drain 231 is electrically connected to the second source drain 230, thereby reducing the process cost and the process steps.

[0052] As an example, the second source-drain electrode 230 away from the junction of the first sub-unit area 200A and the second sub-unit area 200B contacts the first source-drain electrode 231 located therebelow, so that the first source-drain electrode 231 and the second source-drain electrode 230 in the first sub-unit area 200A, and the first source-drain electrode 231 and the second source-drain electrode 230 in the second sub-unit area 200B are arranged to be separate from each other and face each other, which means that an interconnection structure (i.e., a second source-drain plug 252 and a third source-drain plug 251) arranged in an interval stacking manner can be arranged at the junction of the first sub-unit area 200A and the second sub-unit area 200B, so that the interconnection structure can simultaneously provide the pull-up transistor and the pull-down transistor in the first sub-unit area 200A, and the pull-down transistor in the first sub-unit area 200B. The power supply voltage is provided to the pull-up transistor and the pull-down transistor in the second sub-unit area 200B. At the same time, the first source-drain 231 and the second source-drain 230 in the first sub-unit area 200A, and the first source-drain 231 and the second source-drain 230 in the second sub-unit area 200B are arranged to be opposite to each other, so that the distance between the first source-drain 231 and the second source-drain 230 in the first sub-unit area 200A and the first source-drain 231 and the second source-drain 230 in the second sub-unit area 200B can be minimized. In the step of forming the second source-drain plug 252 and the third source-drain plug 251, the sizes of the second source-drain plug 252 and the third source-drain plug 251 can also be minimized, thereby reducing the process cost.

[0053] In this embodiment, the semiconductor structure further includes: a first source-drain plug 250 located on the top of the second source-drain electrode 230 away from the junction of the first sub-unit area 200A and the second sub-unit area 200B, and the first source-drain plug 250 is electrically connected to the second source-drain electrode 230 .

[0054] Specifically, the first source-drain plug 250 is electrically connected to the second source-drain 230. Since the first source-drain 231 of the pull-down transistor is in contact with the second source-drain 230 of the pull-up transistor, the first source-drain plug 250 can electrically lead out the first source-drain 231 of the pull-down transistor and the second source-drain 230 of the pull-up transistor, which means that the transmission gate transistor connected to the first source-drain plug 250 can simultaneously control the pull-up transistor and the pull-down transistor through the first source-drain plug 250.

[0055] In this embodiment, the material of the first source-drain plug 250 is tungsten. In other embodiments, the material of the first source-drain plug 250 may also be cobalt or ruthenium.

[0056] In this embodiment, the semiconductor structure further includes: a second source-drain plug 252, which is located at the junction of the first sub-unit area 200A and the second sub-unit area 200B and connected to the end of the first source-drain electrode 231, and the adjacent first sub-unit area 200A and second sub-unit area 200B share the second source-drain plug 252.

[0057] The second source-drain plug 252 is electrically connected to the first source-drain electrode 231 , so that the source region of the pull-down transistor is connected to the power supply voltage.

[0058] In this embodiment, the second source-drain plug 252 is used to access VSS.

[0059] Specifically, VSS represents an input negative working voltage.

[0060] As an example, the adjacent first sub-unit area 200A and the second sub-unit area 200B share the second source-drain plug 252, so that the second source-drain plug 252 can simultaneously provide a power supply voltage to the pull-down transistors in the first sub-unit area 200A and the second sub-unit area 200B. At the same time, the first sub-unit area 200A and the second sub-unit area 200B share the second source-drain plug 252, which is beneficial for making the space area occupied by the memory smaller, and further beneficial for further reducing the overall size of the semiconductor structure.

[0061] In this embodiment, the material of the second source-drain plug 252 is tungsten. In other embodiments, the material of the second source-drain plug 252 may also be cobalt or ruthenium.

[0062] In this embodiment, the semiconductor structure further includes: a third source-drain plug 251, which is located at the junction of the first sub-unit area 200A and the second sub-unit area 200B and is connected to the end of the second source-drain electrode 230, and the adjacent first sub-unit area 200A and second sub-unit area 200B share the third source-drain plug 251.

[0063] The third source-drain plug 251 is electrically connected to the second source-drain electrode 230 , so that the source region of the pull-up transistor is connected to the power supply voltage.

[0064] The third source-drain plug 251 is used to access VDD.

[0065] Specifically, VDD represents an input positive working voltage.

[0066] As an example, the adjacent first sub-unit area 200A and the second sub-unit area 200B share the third source-drain plug 251, so that the third source-drain plug 251 can simultaneously provide a power supply voltage to the pull-up transistors in the first sub-unit area 200A and the second sub-unit area 200B. At the same time, the first sub-unit area 200A and the second sub-unit area 200B share the third source-drain plug 251, which is beneficial for making the space area occupied by the memory smaller, and further beneficial for further reducing the overall size of the semiconductor structure.

[0067] In this embodiment, the material of the third source-drain plug 251 is tungsten. In other embodiments, the material of the third source-drain plug 251 may also be cobalt or ruthenium.

[0068] It should be noted that the gate plug 290 is used to electrically lead out the first gate structure 240 , thereby achieving control over the conductive channels in the pull-up transistor and the pull-down transistor.

[0069] In this embodiment, the material of the gate plug 290 is tungsten. In other embodiments, the material of the gate plug 290 may also be cobalt or ruthenium.

[0070] Specifically, the dielectric layer 229 provides a process basis for setting up the transmission gate transistor, the first interconnection through-hole structure, the second interconnection through-hole structure, the first interconnection layer 279 and the second interconnection layer 299. At the same time, the dielectric layer 229 is also used to electrically isolate the transmission gate transistor, the first interconnection through-hole structure, the second interconnection through-hole structure, the first interconnection layer 279 and the second interconnection layer 299.

[0071] In this embodiment, the dielectric layer 229 covers the first source-drain plug 250 , and performs electrical isolation for the first source-drain plug 250 .

[0072] In this embodiment, the dielectric layer 229 also covers the second source-drain plug 252 and the third source-drain plug 251 , and performs an electrical isolation function on the second source-drain plug 252 and the third source-drain plug 251 .

[0073] In this embodiment, the material of the dielectric layer 229 includes one or more of silicon oxide, silicon carbide and silicon oxynitride.

[0074] At the same time, the metal layer 293 is also used as a bit line of the SRAM device, and the bit line is used to read and write data in the SRAM device.

[0075] In this embodiment, the material of the metal layer 293 includes one or more of copper, silver, aluminum and gold.

[0076] As an example, the metal layer 293 covers the dielectric layer 229 above the first gate structure 240, exposing the dielectric layer 229 on the side of the first gate structure 240. In the process of forming the first interconnection via structure, the second interconnection via structure, the first interconnection layer 279 and the second interconnection layer 299, the probability of short-circuiting the metal layer 293 with the first interconnection via structure, the second interconnection via structure, the first interconnection layer 279 and the second interconnection layer 299 is reduced.

[0077] The groove (not shown) provides a spatial position for setting up the transfer gate transistor. The transfer gate transistor is set in the dielectric layer 229, that is, the transfer gate transistor utilizes part of the spatial position of the dielectric layer 229, which can reduce the overall height of the memory and the space area occupied by the memory is smaller, which is beneficial to further reduce the overall size of the semiconductor structure (for example, compared with the memory based on fin field effect transistors, the memory based on CFET can save about 40% of the chip area without changing the spacing size, and the semiconductor structure of the embodiment of the present invention can save about 20% of the area on this basis), thereby improving the integration of the semiconductor structure.

[0078] It should be noted that, with the direction perpendicular to the sidewall of the groove (not shown) as the lateral direction, the lateral dimension of the groove (not shown) should not be too large or too small. If the lateral dimension of the groove (not shown) is too large, it is easy to cause the lateral dimension of the transmission gate transistor set in the groove (not shown) to be too large. When the lateral dimension of the gate plug 290 is constant, it is easy to cause the gate plug 290 surrounding the transmission gate transistor to be too small, which means that the third source and drain (not shown) of the transmission gate transistor is too small, thereby affecting the electrical performance of the transmission gate transistor; if the lateral dimension of the groove (not shown) is too small, it is easy to cause the depth-to-width ratio of the groove (not shown) to be too large, increasing the process difficulty of setting the third channel layer 239 and the second gate structure 295 in the groove (not shown), and increasing the risk of voids in the transmission gate transistor. For this reason, in this embodiment, with the direction perpendicular to the sidewall of the groove (not shown) as the lateral direction, the lateral dimension of the groove (not shown) is 10 nanometers to 50 nanometers.

[0079] Specifically, along the normal direction of the surface of the substrate 200, the depth of the groove (not shown) should not be too large or too small. If the depth of the groove (not shown) is too large, the probability of the groove (not shown) penetrating the gate plug 290 is increased, thereby causing the electrical failure of the pull-up transistor electrically connected to the gate plug 290; if the depth of the groove (not shown) is too small, it is easy to cause the groove (not shown) to fail to penetrate part of the gate plug 290, so that the gate plug 290 fails to surround the transmission gate transistor, which means that the transmission gate transistor fails to form the third source and drain (not shown), thereby causing the transmission gate transistor to fail electrically. For this reason, in this embodiment, along the normal direction of the surface of the substrate 200, the depth of the groove (not shown) is 10 nanometers to 200 nanometers.

[0080] The third channel layer 239 is used as a conductive channel of the transfer gate transistor.

[0081] In this embodiment, the material of the third channel layer 239 includes amorphous metal oxide.

[0082] The amorphous metal oxide layer has the function of increasing carrier mobility and can improve the electrical performance of the semiconductor structure.

[0083] In this embodiment, the material of the amorphous metal oxide includes indium gallium zinc oxide, and the indium gallium zinc oxide is composed of indium oxide, gallium oxide and zinc oxide.

[0084] The second gate structure 295 is used to control the opening and closing of the conductive channel when the transmission gate transistor is working.

[0085] Specifically, the second gate structure 295 is a metal gate structure.

[0086] In this embodiment, the second gate structure 295 includes a second gate dielectric layer and a second gate electrode layer covering the second gate dielectric layer.

[0087] In this embodiment, the material of the second gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0088] Specifically, the second gate dielectric layer includes a second gate oxide layer and a second high-k gate dielectric layer conformally covering the second gate oxide layer. The second high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0089] The second gate electrode layer is used for subsequent electrical connection with an external structure. The material of the second gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the second gate electrode layer may include a second work function layer and a second electrode layer covering the second work function layer, or the second gate electrode layer may also include only the second work function layer.

[0090] In this embodiment, the semiconductor structure further includes: a first through-hole interconnection structure 297 located on the top of the first source-drain plug 250 , and the first through-hole interconnection structure 297 is electrically connected to the first source-drain plug 250 .

[0091] The first via interconnect structure 297 is electrically connected to the first source-drain plug 250 , so that the first source-drain plug 250 can electrically lead out the pull-up transistor and the pull-down transistor through the first via interconnect structure 297 .

[0092] In this embodiment, the material of the first through-hole interconnection structure 297 is copper.

[0093] In this embodiment, the semiconductor structure further includes: a second through-hole interconnect structure 298 located on the top of the gate plug 290 and away from the transfer gate transistor.

[0094] The second through-hole interconnect structure 298 is electrically connected to the gate plug 290, so that the gate plug 290 can electrically lead out the first gate structure 240 of the pull-up transistor and the pull-down transistor through the second through-hole structure, thereby achieving the effect of controlling the opening and closing of the conductive channels of the pull-up transistor and the pull-down transistor.

[0095] In this embodiment, the material of the second through-hole interconnection structure 298 is copper.

[0096] In this embodiment, the semiconductor structure further includes: a first interconnection layer 279 connecting the first through-hole interconnection structure 297 of the first sub-unit area 200A and the second through-hole interconnection structure 298 of the second sub-unit area 200B.

[0097] The first interconnect layer 279 is electrically connected to the first through-hole interconnect structure 297 of the first sub-unit area 200A and the second through-hole interconnect structure 298 of the second sub-unit area 200B, so that the transmission gate transistor in the second sub-unit area 200B can be electrically connected to the pull-up transistor and the pull-down transistor in the first sub-unit area 200A, thereby achieving the control of the transfer of data stored in the pull-up transistor and the pull-down transistor.

[0098] In this embodiment, the material of the first interconnection layer 279 is copper.

[0099] In this embodiment, the semiconductor structure further includes: a second interconnect layer 299, connecting the second through-hole interconnect structure 298 of the first sub-unit area 200A and the first through-hole interconnect structure 297 of the second sub-unit area 200B;

[0100] The second interconnect layer 299 is electrically connected to the second through-hole interconnect structure 298 of the first sub-unit area 200A and the first through-hole interconnect structure 297 of the second sub-unit area 200B, so that the transmission gate transistor in the first sub-unit area 200A can be electrically connected to the pull-up transistor and the pull-down transistor in the second sub-unit area 200B, thereby achieving the control of the transfer of data stored in the pull-up transistor and the pull-down transistor.

[0101] In this embodiment, the material of the second interconnection layer 299 is copper.

[0102] Figures 3 to 25 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0103] refer to Figure 3 , providing a substrate 100.

[0104] The substrate 100 provides a process platform for forming a semiconductor structure.

[0105] In this embodiment, the base 100 includes a substrate.

[0106] The material of the substrate is silicon. In other embodiments, the material of the substrate may also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium. The substrate may also be other types of substrates such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0107] In this embodiment, the substrate 100 includes adjacent first and second sub-unit regions 100A and 100B, which form a memory cell region 100C. In this embodiment, the semiconductor structure is an SRAM device, which includes a plurality of memory cell regions 100C.

[0108] In this embodiment, the memory cell region 100C includes a first sub-cell region 100A and a second sub-cell region 100B adjacent to each other.

[0109] Specifically, the first sub-cell region 100A and the second sub-cell region 100B each include a pass gate transistor region, a pull-down transistor region, and a pull-up transistor region.

[0110] Specifically, the transmission gate transistor region is used to form a transmission gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. Wherein, the transmission gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0111] refer to Figures 4 to 9 A channel stack structure (not shown), a first gate structure 140 spanning the channel stack structure, a first source and drain 131 in the first channel layer 105 located on both sides of the first gate structure 140, and a second source and drain 130 in the second channel layer 107 located on both sides of the first gate structure 140 are formed on the substrate 100. The channel stack structure includes a first channel layer 105 and a second channel layer 107 spaced apart on the first channel layer 105. The first gate structure 140 surrounds and covers the first channel layer 105 and the second channel layer 107. The first gate structure 140, the first channel layer 105, and the first source and drain 131 constitute a pull-down transistor, and the first gate structure 140, the second channel layer 107, and the second source and drain 130 constitute a pull-up transistor.

[0112] Specifically, the channel stack structure is used to provide a conductive channel for the pull-up transistor and the pull-down transistor.

[0113] In this embodiment, the channel stack structure is formed on the substrate 100 in the first sub-unit region 100A and the second sub-unit region 100B.

[0114] In this embodiment, the channel stack structure includes a first channel layer 105 and a second channel layer 107 spaced apart from the first channel layer 105 .

[0115] The stacking direction of the first channel layer 105 and the second channel layer 107 is perpendicular to the surface of the substrate 100 .

[0116] In this embodiment, the material of the first channel layer 105 and the second channel layer 107 is the same as the material of the substrate 100 , and the material of the first channel layer 105 and the second channel layer 107 are both Si.

[0117] The first gate structure 140 is used to control the opening and closing of the conductive channel when the SRAM device is working.

[0118] Specifically, the first gate structure 140 is a metal gate structure.

[0119] In this embodiment, the first gate structure 140 includes a first gate dielectric layer and a first gate electrode layer covering the first gate dielectric layer.

[0120] In this embodiment, the material of the first gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0121] Specifically, the first gate dielectric layer includes a first gate oxide layer and a first high-k gate dielectric layer conformally covering the first gate oxide layer. The material of the first high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0122] The first gate electrode layer is used for subsequent electrical connection with an external structure. The material of the first gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the first gate electrode layer may include a first work function layer and a first electrode layer covering the first work function layer, or the first gate electrode layer may also include only the first work function layer.

[0123] In this embodiment, the first gate structure 140 surrounds and covers the first channel layer 105 and the second channel layer 107 .

[0124] Specifically, the first gate structure 140 surrounds and covers the top and sidewalls of the first channel layer 105 , and the second gate structure surrounds and covers the top, sidewalls and bottom of the second channel layer 107 .

[0125] The first source-drain electrode 131 is used as the source and drain of the pull-down transistor.

[0126] Specifically, since the pull-down transistor is an N-type transistor, the doping type of the first source and drain 131 is N-type.

[0127] The second source-drain electrode 130 is used as the source and drain of the pull-up transistor.

[0128] Specifically, since the pull-up transistor is a P-type transistor, the doping type of the second source and drain 130 is P-type.

[0129] It should be noted that, in an SRAM device, a pull-up transistor and a pull-down transistor are used to store data.

[0130] Combined with reference Figures 4 to 9 , the steps of forming the pull-down transistor and the pull-up transistor are described in detail.

[0131] refer to Figures 4 to 5 A channel stack 108 is formed on the top of the substrate 100 in the first sub-unit area 100A and the second sub-unit area 100B. The channel stack 108 includes a first channel layer 105 , a sacrificial layer 106 located on the first channel layer 105 , and a second channel layer 107 located on the sacrificial layer 106 .

[0132] Specifically, the channel stack 108 provides a process basis for setting up the channel stack structure, and the sacrificial layer 106 supports the second channel layer 107, thereby providing a process basis for the subsequent realization of the spaced-apart suspended setting of the first channel layer 105 and the second channel layer 107, so as to occupy a spatial position for the formation of the first gate structure 140, and the first channel layer 105 and the second channel layer 107 are used to provide a conductive channel for the SRAM device.

[0133] In this embodiment, the step of forming the channel stack 108 includes: forming a channel stack material layer 104 on the top of the substrate 100, the channel stack material layer 104 including a first channel material layer 101, a sacrificial material layer 102 located on the first channel material layer 101, and a second channel material layer 103 located on the sacrificial material layer 102; forming a patterned mask layer above the channel stack material layer 104; using the mask layer as a mask, patterning the channel stack material layer 104 to form a channel stack 108 on the top of the substrate 100 in the first sub-unit area 100A and the second sub-unit area 100B.

[0134] It should be noted that the channel stack 108 on the top of the substrate 100 in the first sub-unit region 100A and the second sub-unit region 100B protrudes from the top of the substrate 100 .

[0135] In this embodiment, the material of the sacrificial layer 106 is SiGe. In the subsequent process of removing the sacrificial layer 106, the etching selectivity of SiGe and Si is relatively high. Therefore, by setting the material of the sacrificial layer 106 to SiGe, the impact of the process of removing the sacrificial layer 106 on the first channel layer 105 and the second channel layer 107 can be effectively reduced, thereby improving the quality of the channel stack structure, which is beneficial to improving device performance.

[0136] refer to Figure 6 A dummy gate structure 110 is formed on the substrate 100 and crosses the channel stack 108 . The dummy gate structure 110 covers the top and sidewalls of the channel stack 108 .

[0137] The dummy gate structure 110 occupies a space for the first gate structure 140 to be formed subsequently.

[0138] In this embodiment, the dummy gate structure 110 includes a dummy gate layer, and the material of the dummy gate layer includes polysilicon.

[0139] It should be noted that after forming the dummy gate structure 110 , the process further includes: removing the channel stacks 108 on both sides of the dummy gate structure 110 .

[0140] refer to Figure 7, a portion of the sacrificial layer 106 is laterally etched in a direction parallel to the substrate 100 and perpendicular to the extension direction of the dummy gate structure 110 to form a trench (not shown); and an inner wall layer 120 is formed in the trench (not shown).

[0141] The trench (not shown) is surrounded by the adjacent first channel layer 105 and second channel layer 107 and the remaining sacrificial layer 106 .

[0142] In this embodiment, the process of laterally etching a portion of the sacrificial layer 106 includes a wet etching process.

[0143] Specifically, the inner wall layer 120 is located between the first source and drain 131 and the first gate structure 140, and between the second source and drain 130 and the first gate structure 140, which are formed subsequently. The inner wall layer 120 can isolate the first source and drain 131 from the first gate structure 140, and between the second source and drain 130 and the first gate structure 140, which is beneficial to reducing the parasitic capacitance between the first source and drain 131 and the first gate structure 140, and between the second source and drain 130 and the first gate structure 140.

[0144] In this embodiment, the material of the inner wall layer 120 includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

[0145] Specifically, silicon nitride, silicon oxide and silicon oxynitride are all dielectric materials, which can play a role in electrically isolating the first source and drain 131 and the first gate structure 140 formed subsequently, and the second source and drain 130 and the first gate structure 140 .

[0146] refer to Figure 8 , a first source and drain 131 is formed in the first channel layer 105 on both sides of the dummy gate structure 110 , and a second source and drain 130 is formed in the second channel layer 107 on both sides of the dummy gate structure 110 .

[0147] The first source-drain electrode 131 is used as the source and drain of the pull-down transistor.

[0148] Specifically, since the pull-down transistor is an N-type transistor, the doping type of the first source and drain 131 is N-type.

[0149] The second source-drain electrode 130 is used as the source and drain of the pull-up transistor.

[0150] Specifically, since the pull-up transistor is a P-type transistor, the doping type of the second source and drain 130 is P-type.

[0151] As an example, in the step of forming the second source and drain 130 , one of the second source and drain 130 in the first sub-unit area 100A contacts the first source and drain 131 thereunder, and the other second source and drain 130 is separated from the first source and drain 131 thereunder.

[0152] It should be noted that one of the second source drains 130 in the first sub-unit area 100A is in contact with the first source drain 131 located therebelow, thereby electrically connecting the drain region in the pull-up transistor to the drain region in the pull-down transistor. At the same time, one of the second source drains 130 in the first sub-unit area 100A is in contact with the first source drain 131 located therebelow, thereby reducing the process difficulty of forming the second source drain 130 and the first source drain 131, and eliminating the process step of additionally setting up an interconnection structure connected to the second source drain 130 and the first source drain 131, thereby electrically connecting the first source drain 131 to the second source drain 130, thereby reducing the process cost and reducing the process steps.

[0153] It should also be noted that the other second source-drain 130 in the first sub-unit area 100A is separated from the first source-drain 131 located therebelow, so that the other second source-drain 130 in the first sub-unit area 100A can be electrically connected to the first source-drain plug, and the first source-drain 131 located therebelow can be electrically connected to the second source-drain plug, thereby achieving in the first sub-unit area 100A that the source area of ​​the pull-up transistor can be connected to the power supply voltage through the second source-drain plug, and the source area of ​​the pull-down transistor can be connected to the power supply voltage through the first source-drain plug.

[0154] As an example, one of the second source-drain electrodes 130 in the second sub-unit region 100B contacts the first source-drain electrode 131 thereunder, and the other second source-drain electrode 130 is separated from the first source-drain electrode 131 thereunder.

[0155] It should be noted that one of the second source drains 130 in the second sub-unit area 100B is in contact with the first source drain 131 located thereunder, thereby electrically connecting the drain region in the pull-up transistor to the drain region in the pull-down transistor. At the same time, one of the second source drains 130 in the second sub-unit area 100B is in contact with the first source drain 131 located thereunder, thereby reducing the process difficulty of forming the second source drain 130 and the first source drain 131, and eliminating the process step of additionally setting up an interconnection structure connected to the second source drain 130 and the first source drain 131, thereby achieving the purpose of electrically connecting the first source drain 131 to the second source drain 130, thereby reducing the process cost and reducing the process steps.

[0156] It should also be noted that the other second source-drain 130 in the second sub-unit area 100B is separated from the first source-drain 131 located therebelow, so that the other second source-drain 130 in the second sub-unit area 100B can be electrically connected to the first source-drain plug, and the first source-drain 131 located therebelow can be electrically connected to the second source-drain plug, thereby achieving that in the second sub-unit area 100B, the source area of ​​the pull-up transistor can be connected to the power supply voltage through the second source-drain plug, and the source area of ​​the pull-down transistor can be connected to the power supply voltage through the first source-drain plug.

[0157] As an example, the second source-drain electrode 130 away from the junction of the first sub-unit area 100A and the second sub-unit area 100B contacts the first source-drain electrode 131 located therebelow, so that the first source-drain electrode 131 and the second source-drain electrode 130 in the first sub-unit area 100A, and the first source-drain electrode 131 and the second source-drain electrode 130 in the second sub-unit area 100B are arranged to be separate from each other and face each other, which means that an interconnection structure (i.e., a second source-drain plug and a third source-drain plug formed later) arranged in an interval stacking arrangement can be formed at the junction of the first sub-unit area 100A and the second sub-unit area 100B, so that the interconnection structure can simultaneously provide the pull-up transistor and the pull-down transistor in the first sub-unit area 100A with a plurality of pull-up transistors. The pull-up transistor and the pull-up transistor and the pull-down transistor in the second sub-unit area 100B provide a power supply voltage. At the same time, the first source-drain 131 and the second source-drain 130 in the first sub-unit area 100A, and the first source-drain 131 and the second source-drain 130 in the second sub-unit area 100B are arranged to be opposite to each other, so that the distance between the first source-drain 131 and the second source-drain 130 in the first sub-unit area 100A and the first source-drain 131 and the second source-drain 130 in the second sub-unit area 100B can be minimized. In the subsequent step of forming the second source-drain plug and the third source-drain plug, the sizes of the second source-drain plug and the third source-drain plug can also be minimized, thereby reducing the process cost.

[0158] In this embodiment, the steps of forming the first source and drain 131 and the second source and drain 130 include: forming a first dielectric layer covering the first channel layer and the second channel layer on one side of the first gate structure; forming a first source and drain in the first channel layer on the other side of the first gate structure; forming a second source and drain in the second channel layer on the other side of the first gate structure, and the first source and drain are in contact with the second source and drain; removing the first dielectric layer; forming a first source and drain located in the first channel layer in the area where the first dielectric layer is removed; forming a second dielectric layer covering the first source and drain located in the area where the first dielectric layer is removed, and the second dielectric layer exposes the second channel layer; forming a second source and drain located in the second channel layer in the area where the first dielectric layer is removed; and removing the second dielectric layer.

[0159] As an example, the process of forming the first source and drain 131 includes an epitaxial process.

[0160] Specifically, the epitaxial process is a commonly used growth process for forming source and drain electrodes, and has the characteristics of low process cost and high film growth quality.

[0161] In this embodiment, the process of forming the second source and drain 130 includes an epitaxial growth process.

[0162] refer to Fig. 9 , remove the dummy gate structure 110 and the sacrificial layer 106, and form a first gate structure 140 at the position of the dummy gate structure 110 and the sacrificial layer 106, and after removing the sacrificial layer 106, the first channel layer 105 and the second channel layer 107 spaced apart on the first channel layer 105 constitute a channel stack structure.

[0163] Specifically, the dummy gate structure 110 and the sacrificial layer 106 are removed to provide a process basis for forming the first gate structure 140 .

[0164] In this embodiment, the process of removing the dummy gate structure 110 and the sacrificial layer 106 includes a wet etching process.

[0165] It should be noted that, in order to facilitate Fig. 9 The subsequent three-dimensional schematic diagram clearly shows the structure of each component, so Fig. 9 The first gate structure 140 only shows the first channel layer 105 and the second channel layer 107. In fact, the overall size of the first gate structure 140 is Figure 8 The overall size of the dummy gate structure 110 is consistent.

[0166] refer to Figures 10 to 18 ,in, Fig.10 It is a stereogram. Figures 11 to 18 yes Fig.10The cross-sectional view along the AA direction, after forming the pull-up transistor and the pull-down transistor and before subsequently forming the gate plug, further includes: forming a first source-drain plug 150 at the top of the second source-drain electrode 130 away from the junction of the first sub-unit area 100A and the second sub-unit area 100B, the first source-drain plug 150 being electrically connected to the second source-drain electrode 130; forming a second source-drain plug 152 at the end of the first source-drain electrode 131 at the junction of the first sub-unit area 100A and the second sub-unit area 100B, The second source-drain plug 152 is electrically connected to the first source-drain electrode 131, and the adjacent first sub-unit area 100A and the second sub-unit area 100B share the second source-drain plug 152; a third source-drain plug 151 is formed at the end of the second source-drain electrode 130 at the junction of the first sub-unit area 100A and the second sub-unit area 100B, and the third source-drain plug 151 is electrically connected to the second source-drain electrode 130, and the adjacent first sub-unit area 100A and the second sub-unit area 100B share the third source-drain plug 151.

[0167] Specifically, the first source-drain plug 150 is electrically connected to the second source-drain 130. Since the first source-drain 131 of the pull-down transistor is in contact with the second source-drain 130 of the pull-up transistor, the first source-drain plug 150 can electrically lead out the first source-drain 131 of the pull-down transistor and the second source-drain 130 of the pull-up transistor, which means that the subsequent transfer gate transistor connected to the first source-drain plug 150 can simultaneously control the pull-up transistor and the pull-down transistor through the first source-drain plug 150.

[0168] The second source-drain plug 152 is electrically connected to the first source-drain 131 , and the third source-drain plug 151 is electrically connected to the second source-drain 130 , so that the source regions of the pull-up transistors are both connected to the power supply voltage, and the source regions of the pull-down transistors are both connected to the power supply voltage.

[0169] In this embodiment, the second source-drain plug 152 is used to access VSS, and the third source-drain plug 151 is used to access VDD.

[0170] Specifically, VDD represents an input positive working voltage, and specifically, VSS represents an input negative working voltage.

[0171] As an example, the adjacent first sub-unit area 100A and the second sub-unit area 100B share the second source-drain plug 152, so that the second source-drain plug 152 can simultaneously provide a power supply voltage to the pull-down transistors in the first sub-unit area 100A and the second sub-unit area 100B. At the same time, the first sub-unit area 100A and the second sub-unit area 100B share the second source-drain plug 152, which is beneficial for making the space area occupied by the memory smaller, and further beneficial for further reducing the overall size of the semiconductor structure.

[0172] As an example, the adjacent first sub-unit area 100A and the second sub-unit area 100B share the third source-drain plug 151, so that the third source-drain plug 151 can simultaneously provide a power supply voltage to the pull-up transistors in the first sub-unit area 100A and the second sub-unit area 100B. At the same time, the first sub-unit area 100A and the second sub-unit area 100B share the third source-drain plug 151, which is beneficial to making the space area occupied by the memory smaller, and further beneficial to further reducing the overall size of the semiconductor structure.

[0173] In this embodiment, the materials of the first source drain plug 150, the second source drain plug 152 and the third source drain plug 151 are all tungsten. In other embodiments, the materials of the first source drain plug 150, the second source drain plug 152 and the third source drain plug 151 may also be cobalt or ruthenium.

[0174] In this embodiment, the steps of forming the first source-drain plug 150, the second source-drain plug 152, and the third source-drain plug 151 include: forming a first auxiliary layer 170 on the top of the substrate 100, the first auxiliary layer 170 covering the sidewalls and tops of the first source-drain electrode 131 and the second source-drain electrode 130; forming a first opening 160 in the first auxiliary layer 170 at the junction of the adjacent first sub-unit area 100A and the second sub-unit area 100B, exposing the end of the first source-drain electrode 131 and the end of the second source-drain electrode 130; forming a second opening 160 in the first opening 160 covering the end of the first source-drain electrode 131 A source-drain plug 152 is formed; a second auxiliary layer 171 covering the top of the second source-drain plug 152 is formed in the first opening 160, and the second auxiliary layer 171 exposes the end of the second source-drain electrode 130; a third source-drain plug 151 is formed in the remaining space of the first opening 160; after the third source-drain plug 151 is formed, a second opening 180 exposing the second source-drain electrode 130 is formed in the first auxiliary layer 170 away from the top of the second source-drain electrode 130 at the junction of the first sub-unit area 100A and the second sub-unit area 100B; and a first source-drain plug 150 is formed in the second opening 180.

[0175] In this embodiment, the materials of the first auxiliary layer 170 and the second auxiliary layer 171 are both organic materials, which facilitates the subsequent removal of the first auxiliary layer 170 and the second auxiliary layer 171 through an etching process, thereby reducing the process difficulty of the remaining first auxiliary layer 170 and the second auxiliary layer 171.

[0176] As an example, the material of the first auxiliary layer 170 is BARC.

[0177] It should be noted that after forming the first source-drain plug 150 , the second source-drain plug 152 and the third source-drain plug 151 , the process further includes: removing the first auxiliary layer 170 and the second auxiliary layer 171 .

[0178] Removing the first auxiliary layer 170 and the second auxiliary layer 171 provides a space for subsequently forming a dielectric layer covering the pull-down transistor and the pull-up transistor.

[0179] In this embodiment, the process of removing the first auxiliary layer 170 and the second auxiliary layer 171 includes a wet etching process.

[0180] refer to Fig.19 A gate plug 190 is formed on the top of the first gate structure 140 , and the gate plug 190 is electrically connected to the first gate structure 140 .

[0181] It should be noted that the gate plug 190 is used to electrically lead out the first gate structure 140 , thereby achieving control over the conductive channels in the pull-up transistor and the pull-down transistor.

[0182] It should also be noted that the gate plug 190 also provides a process basis for the subsequent formation of a groove, which is conducive to the subsequent formation of a second gate structure in the groove, and the gate plug 190 surrounding the second gate structure is used as a third source and drain.

[0183] In this embodiment, the material of the gate plug 190 is tungsten. In other embodiments, the material of the gate plug 190 may also be cobalt or ruthenium.

[0184] refer to Fig. 20 , a dielectric layer 129 covering the pull-down transistor and the pull-up transistor and the gate plug 190 is formed.

[0185] Specifically, the dielectric layer 129 provides a process basis for the subsequent formation of a transmission gate transistor, a first interconnection via structure, a second interconnection via structure, a first interconnection layer, and a second interconnection layer. At the same time, the dielectric layer 129 is also used to electrically isolate the subsequently formed transmission gate transistor, the first interconnection via structure, the second interconnection via structure, the first interconnection layer, and the second interconnection layer.

[0186] In this embodiment, the process of forming the dielectric layer 129 includes a chemical vapor deposition process or an atomic layer deposition process.

[0187] In this embodiment, during the process of forming the dielectric layer 129 , the dielectric layer 129 covers the first source-drain plug 150 , the second source-drain plug 152 , and the third source-drain plug 151 .

[0188] Specifically, the dielectric layer 129 covers the first source drain plug 150 , the second source drain plug 152 and the third source drain plug 151 , and is used to electrically isolate the first source drain plug 150 , the second source drain plug 152 and the third source drain plug 151 , thereby electrically isolating the second source drain plug 152 and the third source drain plug 151 .

[0189] In this embodiment, the material of the dielectric layer 129 includes one or more of silicon oxide, silicon carbide and silicon oxynitride.

[0190] refer to Fig.21 , a metal layer 193 is formed on top of the dielectric layer 129.

[0191] It should be noted that, after the second gate structure is subsequently formed, the metal layer 193 is used as the fourth source and drain.

[0192] It should also be noted that the metal layer 193 is also used to interconnect the gate plug 190 with a CFET to be formed subsequently.

[0193] At the same time, the metal layer 193 is also used as a bit line of the SRAM device, and the bit line is used to read and write data in the SRAM device.

[0194] In this embodiment, the material of the metal layer 193 includes one or more of copper, aluminum, silver and gold.

[0195] As an example, the metal layer 193 covers the dielectric layer 129 above the first gate structure 140, exposing the dielectric layer 129 on the side of the first gate structure 140, which is conducive to the subsequent formation of the first interconnection through-hole structure, the second interconnection through-hole structure, the first interconnection layer and the second interconnection layer in the dielectric layer 129, thereby reducing the probability of short-circuiting between the metal layer 193 and the first interconnection through-hole structure, the second interconnection through-hole structure, the first interconnection layer and the second interconnection layer.

[0196] refer to Fig. 22 A groove 194 is formed on the top of the first gate structure 140 , penetrating the metal layer 193 , the dielectric layer 129 , and a portion of the gate plug 190 .

[0197] Specifically, the groove 194 provides a spatial position for the subsequent formation of a transfer gate transistor. The transfer gate transistor is arranged in the dielectric layer 129, that is, the transfer gate transistor utilizes part of the spatial position of the dielectric layer 129, which can reduce the overall height of the memory and the space area occupied by the memory is smaller, which is beneficial to further reduce the overall size of the semiconductor structure (for example, compared with a memory based on fin field effect transistors, a memory based on CFET can save about 40% of the chip area without changing the spacing size, and the semiconductor structure of the embodiment of the present invention can save about 20% of the area on this basis), thereby improving the integration of the semiconductor structure.

[0198] In this embodiment, the process of forming the groove 194 includes a dry etching process.

[0199] It should be noted that the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has good profile controllability, which is beneficial to improving the profile morphology quality of the groove 194, and is beneficial to the subsequent deposition of the third channel layer on the sidewall and bottom of the groove 194, reducing the risk of voids in the third channel layer. In addition, the selected anisotropic dry etching process is conducive to achieving a higher etching selectivity, thereby reducing the probability of causing mis-etching of other film layers.

[0200] It should also be noted that, with the direction perpendicular to the sidewall of the groove 194 as the lateral direction, the lateral dimension of the groove 194 should not be too large or too small. If the lateral dimension of the groove 194 is too large, it is easy to cause the lateral dimension of the transmission gate transistor formed in the groove 194 to be too large. When the lateral dimension of the gate plug 190 is constant, it is easy to cause the gate plug 190 surrounding the transmission gate transistor to be too small, which means that the third source and drain of the transmission gate transistor is too small, thereby affecting the electrical performance of the transmission gate transistor; if the lateral dimension of the groove 194 is too small, it is easy to cause the depth-to-width ratio of the groove 194 to be too large, increasing the difficulty of the subsequent process of forming the third channel layer and the second gate structure in the groove 194, and increasing the risk of voids in the transmission gate transistor. For this reason, in this embodiment, with the direction perpendicular to the sidewall of the groove 194 as the lateral direction, the lateral dimension of the groove 194 is 10 nanometers to 50 nanometers.

[0201] Specifically, along the normal direction of the surface of the substrate 100, the depth of the groove 194 should not be too large or too small. If the depth of the groove 194 is too large, the probability of penetrating the gate plug 190 is increased, thereby causing the electrical failure of the pull-up transistor electrically connected to the gate plug 190; if the depth of the groove 194 is too small, it is easy to cause the groove 194 to fail to penetrate part of the gate plug 190, so that the gate plug 190 fails to surround the transmission gate transistor, which means that the subsequent transmission gate transistor fails to form the third source and drain, thereby causing the transmission gate transistor to fail electrically. For this reason, in this embodiment, along the normal direction of the surface of the substrate 100, the depth of the groove 194 is 10 nanometers to 200 nanometers.

[0202] refer to Figure 23 to Figure 24 ,in, Fig.23 It is a stereogram. Fig.24 yes Fig.23 In the cross-sectional view along the BB direction, a third channel layer 139 is formed to cover the bottom and sidewalls of the groove 194 .

[0203] Specifically, the third channel layer 139 is used as a conductive channel of a subsequently formed transfer gate transistor.

[0204] In this embodiment, the material of the third channel layer 139 includes amorphous metal oxide.

[0205] The amorphous metal oxide layer has the function of increasing carrier mobility and can improve the electrical performance of the semiconductor structure.

[0206] In this embodiment, the material of the amorphous metal oxide includes indium gallium zinc oxide, and the indium gallium zinc oxide is composed of indium oxide, gallium oxide and zinc oxide.

[0207] In this embodiment, the process of forming the third channel layer 139 includes an atomic layer deposition process or physical sputtering.

[0208] Taking physical sputtering as an example, the physical sputtering process uses a high-energy ion beam to bombard the surface of the target material, so that the atoms or molecules on the surface of the target material are separated and deposited on the surface of the substrate to form a thin film. The third channel layer 139 formed by the physical sputtering process has high film quality, high process stability, good process compatibility and other characteristics.

[0209] Continue to refer Figure 23 to Figure 24 A second gate structure 195 is formed in the remaining space of the groove 194, and the gate plug 190 surrounding the second gate structure 195 is used as a third source and drain (not labeled), and the metal layer 193 surrounding the second gate structure 195 is used as a fourth source and drain (not labeled), and the second gate structure 195, the third channel layer 139, the third source and drain, and the fourth source and drain constitute a transmission gate transistor.

[0210] The second gate structure 195 is used to control the opening and closing of the conductive channel when the transfer gate transistor is working.

[0211] Specifically, the second gate structure 195 is a metal gate structure.

[0212] In this embodiment, the second gate structure 195 includes a second gate dielectric layer and a second gate electrode layer covering the second gate dielectric layer.

[0213] In this embodiment, the material of the second gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0214] Specifically, the second gate dielectric layer includes a second gate oxide layer and a second high-k gate dielectric layer conformally covering the second gate oxide layer. The second high-k gate dielectric layer is made of a high-k dielectric material, which refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide.

[0215] The second gate electrode layer is used for subsequent electrical connection with an external structure. The material of the second gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC. Specifically, the second gate electrode layer may include a second work function layer and a second electrode layer covering the second work function layer, or the second gate electrode layer may also include only the second work function layer.

[0216] The semiconductor structure of this embodiment adopts a pull-down transistor and a pull-up transistor based on a CFET (complementary FET) structure, and a transfer gate transistor based on a CAA (channel all around) structure to achieve a stacked arrangement of pull-down transistors, pull-up transistors and transfer gate transistors.

[0217] refer to Fig.25 After forming the transfer gate transistor, the method for forming the semiconductor structure further includes: forming a first through-hole interconnect structure 197 located on top of the first source-drain plug 150 in the dielectric layer 129, the first through-hole interconnect structure 197 being electrically connected to the first source-drain plug 150; forming a second through-hole interconnect structure 198 located on top of the gate plug 190 and away from the transfer gate transistor in the dielectric layer 129, the second through-hole interconnect structure 198 being electrically connected to the gate plug 190.

[0218] The first via interconnect structure 197 is electrically connected to the first source-drain plug 150 , so that the first source-drain plug 150 can electrically lead out the pull-up transistor and the pull-down transistor through the first via interconnect structure 197 .

[0219] In this embodiment, the material of the first through-hole interconnection structure 197 is copper.

[0220] The second through-hole interconnect structure 198 is electrically connected to the gate plug 190, so that the gate plug 190 can electrically lead out the first gate structure 140 of the pull-up transistor and the pull-down transistor through the second through-hole structure, thereby achieving the effect of controlling the opening and closing of the conductive channels of the pull-up transistor and the pull-down transistor.

[0221] In this embodiment, the material of the second through-hole interconnection structure 198 is copper.

[0222] Continue to refer Fig.25 A first interconnection layer 179 is formed in the dielectric layer 129 to connect the first through-hole interconnection structure 197 of the first sub-unit area 100A and the second through-hole interconnection structure 198 of the second sub-unit area 100B; a second interconnection layer 199 is formed in the dielectric layer 129 to connect the second through-hole interconnection structure 198 of the first sub-unit area 100A and the first through-hole interconnection structure 197 of the second sub-unit area 100B.

[0223] The first interconnect layer 179 is electrically connected to the first through-hole interconnect structure 197 of the first sub-unit area 100A and the second through-hole interconnect structure 198 of the second sub-unit area 100B, so that the transmission gate transistor in the second sub-unit area 100B can be electrically connected to the pull-up transistor and the pull-down transistor in the first sub-unit area 100A, thereby achieving the control of the transfer of data stored in the pull-up transistor and the pull-down transistor.

[0224] In this embodiment, the material of the first interconnection layer 179 is copper.

[0225] The second interconnect layer 199 is electrically connected to the second through-hole interconnect structure 198 of the first sub-unit area 100A and the first through-hole interconnect structure 197 of the second sub-unit area 100B, so that the transmission gate transistor in the first sub-unit area 100A can be electrically connected to the pull-up transistor and the pull-down transistor in the second sub-unit area 100B, thereby achieving the control of the transfer of data stored in the pull-up transistor and the pull-down transistor.

[0226] In this embodiment, the material of the second interconnection layer 199 is copper.

[0227] In this embodiment, the steps of forming the first interconnection layer 179 and the second interconnection layer 199 include: forming a third opening in the dielectric layer 129 above the first through-hole interconnection structure 197 of the first sub-unit area 100A and the second through-hole interconnection structure 198 of the second sub-unit area 100B, the third opening exposing the first through-hole interconnection structure 197 of the first sub-unit area 100A and the second through-hole interconnection structure 198 of the second sub-unit area 100B; forming a fourth opening in the dielectric layer 129 above the first through-hole interconnection structure 197 of the second sub-unit area 100B and the second through-hole interconnection structure 198 of the first sub-unit area 100A, the fourth opening exposing the first through-hole interconnection structure 197 of the second sub-unit area 100B and the second through-hole interconnection structure 198 of the first sub-unit area 100A; forming the first interconnection layer 179 in the third opening; and forming the second interconnection layer 199 in the fourth opening.

[0228] As an example, the first interconnect layer 179 and the second interconnect layer 199 are formed in the same step.

[0229] In other embodiments, the first interconnect layer 179 and the second interconnect layer 199 may also be formed in different steps.

[0230] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; A channel stack structure is located on the substrate, and the channel stack structure includes a first channel layer and a second channel layer spaced apart and arranged on the first channel layer; A first gate structure spans across the channel stack structure and surrounds and covers the first channel layer and the second channel layer; A first source and drain electrode is located in the first channel layer on both sides of the first gate structure; A second source and drain is located in the second channel layer on both sides of the first gate structure, and the first gate structure, the first channel layer and the first source and drain constitute a pull-down transistor, and the first gate structure, the second channel layer and the second source and drain constitute a pull-up transistor; A gate plug, located on top of the first gate structure, and the gate plug is electrically connected to the first gate structure; a dielectric layer located on top of the substrate and covering the pull-down transistor, the pull-up transistor and the gate plug; a metal layer located on top of the dielectric layer; A groove penetrating the metal layer, the dielectric layer and a portion of the thickness of the gate plug; a third channel layer, covering the bottom and sidewalls of the groove; The second gate structure is located in the remaining space of the groove, and the gate plug surrounding the second gate structure is used as a third source and drain, the metal layer surrounding the second gate structure is used as a fourth source and drain, and the second gate structure, the third channel layer, the third source and drain and the fourth source and drain constitute a transmission gate transistor.

2. The semiconductor structure according to claim 1, wherein: The substrate comprises a first sub-unit region and a second sub-unit region adjacent to each other, and the channel stacking structure is respectively located on the substrate of the first sub-unit region and the second sub-unit region; On one side of the gate structure, the second source and drain are in contact with the first source and drain located therebelow; On the other side of the gate structure, the second source and drain are separated from the first source and drain located therebelow.

3. The semiconductor structure according to claim 2, wherein: The second source and drain electrode, which is far away from the boundary between the first sub-unit region and the second sub-unit region, contacts the first source and drain electrode located therebelow.

4. The semiconductor structure according to claim 2 or 3, characterized in that: The second source and drain electrodes that are in contact with the first source and drain electrodes are an integrated structure.

5. The semiconductor structure according to claim 2 or 3, characterized in that: The semiconductor structure further includes: a first source-drain plug, located on the top of the second source-drain electrode away from the junction of the first sub-unit area and the second sub-unit area, the first source-drain plug being electrically connected to the second source-drain electrode; The dielectric layer covers the first source-drain plug.

6. The semiconductor structure according to claim 5, characterized in that The semiconductor structure further includes: a first through-hole interconnect structure, located on top of the first source-drain plug, and the first through-hole interconnect structure is electrically connected to the first source-drain plug; a second through-hole interconnect structure located on top of the gate plug and away from the transfer gate transistor; a first interconnection layer, connecting a first through-hole interconnection structure of the first sub-unit region and a second through-hole interconnection structure of the second sub-unit region; The second interconnection layer connects the second through-hole interconnection structure of the first sub-unit area and the first through-hole interconnection structure of the second sub-unit area.

7. The semiconductor structure according to claim 2, wherein: The semiconductor structure further includes: a second source-drain plug, located at the junction of the first sub-unit region and the second sub-unit region, and connected to the end of the first source-drain electrode, and the adjacent first sub-unit region and the second sub-unit region share the a second source-drain plug; A third source-drain plug is located at the junction of the first sub-unit area and the second sub-unit area and is connected to the end of the second source-drain electrode, and the third source-drain plug is shared by the adjacent first sub-unit area and the second sub-unit area; The dielectric layer also covers the second source-drain plug and the third source-drain plug.

8. The semiconductor structure according to claim 1, wherein: The material of the metal layer includes one or more of copper, aluminum, silver and gold.

9. The semiconductor structure according to claim 1, wherein: The material of the third channel layer includes amorphous metal oxide.

10. The semiconductor structure according to claim 1, wherein: Taking the direction perpendicular to the sidewall of the groove as the lateral direction, the lateral dimension of the groove is 10 nanometers to 50 nanometers.

11. The semiconductor structure according to claim 1, wherein: Along the normal direction of the substrate surface, the depth of the groove is 10 nanometers to 200 nanometers.

12. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; A channel stack structure, a first gate structure spanning the channel stack structure, a first source and drain in a first channel layer on both sides of the first gate structure, and a second source and drain in a second channel layer on both sides of the first gate structure are formed on the substrate, wherein the channel stack structure comprises a first channel layer and a second channel layer spaced apart on the first channel layer, and the first gate structure surrounds and covers the first channel layer and the second channel layer, wherein the first gate structure, the first channel layer, and the first source and drain constitute a pull-down transistor, and the first gate structure, the second channel layer, and the second source and drain constitute a pull-up transistor; forming a gate plug on the top of the first gate structure, wherein the gate plug is electrically connected to the first gate structure; forming a dielectric layer covering the pull-down transistor, the pull-up transistor and the gate plug; forming a metal layer on top of the dielectric layer; forming a groove penetrating the metal layer and the dielectric layer and a portion of the gate plug on the top of the first gate structure; forming a third channel layer covering the bottom and sidewalls of the groove; A second gate structure is formed in the remaining space of the groove, and the gate plug surrounding the second gate structure is used as a third source and drain, and the metal layer surrounding the second gate structure is used as a fourth source and drain, and the second gate structure, the third channel layer, the third source and drain, and the fourth source and drain constitute a transmission gate transistor.

13. The method for forming a semiconductor structure according to claim 12, wherein: The substrate includes adjacent first and second subunit regions; In the step of forming the channel stack structure, the channel stack structure is formed on a substrate of the first sub-unit region and the second sub-unit region; The step of forming the pull-down transistor and the pull-up transistor comprises: forming a channel stack on the top of the substrate of the first sub-unit area and the second sub-unit area, the channel stack comprising a first channel layer, a sacrificial layer located on the first channel layer, and a second channel layer located on the sacrificial layer; forming a dummy gate structure across the channel stack on the substrate, wherein the dummy gate structure covers the top and sidewalls of the channel stack; forming a first source-drain doped layer in the first channel layer on both sides of the dummy gate structure, and forming a second source-drain doped layer in the second channel layer on both sides of the dummy gate structure; The dummy gate structure and the sacrificial layer are removed, and a first gate structure is formed at the position of the dummy gate structure and the sacrificial layer. After the sacrificial layer is removed, the first channel layer and the second channel layer spaced apart on the first channel layer constitute the channel stack structure.

14. The method for forming a semiconductor structure according to claim 13, wherein: In the step of forming the second source and drain, one of the second source and drain in the first sub-unit region is in contact with the first source and drain located thereunder, and the other second source and drain is separated from the first source and drain located thereunder; One of the second source and drain electrodes in the second sub-unit region is in contact with the first source and drain electrode located thereunder, and the other second source and drain electrode is separated from the first source and drain electrode located thereunder.

15. The method for forming a semiconductor structure according to claim 14, wherein: The second source and drain electrode, which is far away from the boundary between the first sub-unit region and the second sub-unit region, contacts the first source and drain electrode located therebelow.

16. The method for forming a semiconductor structure according to claim 14, wherein: The steps of forming the first source and drain and the second source and drain include: forming a first dielectric layer covering the first channel layer and the second channel layer on one side of the first gate structure; forming a first source and drain in the first channel layer on the other side of the first gate structure; forming a second source and drain in the second channel layer on the other side of the first gate structure, and the first source and drain are in contact with the second source and drain; removing the first dielectric layer; forming a first source and drain located in the first channel layer in an area where the first dielectric layer is removed; forming a second dielectric layer covering the first source and drain located in an area where the first dielectric layer is removed, and the second dielectric layer exposes the second channel layer; forming a second source and drain located in the second channel layer in an area where the first dielectric layer is removed; and removing the second dielectric layer.

17. The method for forming a semiconductor structure according to claim 14, wherein: The process of forming the first source and drain includes an epitaxial growth process; the process of forming the second source and drain includes an epitaxial growth process.

18. The method for forming a semiconductor structure according to claim 15, wherein: After forming the pull-up transistor and the pull-down transistor and before forming the gate plug, the method further includes: forming a first source-drain plug on the top of the second source-drain electrode away from the junction of the first sub-unit area and the second sub-unit area, wherein the first source-drain plug is electrically connected to the second source-drain electrode; A second source-drain plug is formed at the first source-drain end portion at the junction of the first sub-unit region and the second sub-unit region, the second source-drain plug is electrically connected to the first source-drain electrode, and the adjacent first sub-unit region and the second sub-unit region share the second source-drain plug; A third source-drain plug is formed at the second source-drain end portion at the junction of the first sub-unit area and the second sub-unit area, the third source-drain plug is electrically connected to the second source-drain, and the adjacent first sub-unit area and the second sub-unit area share the third source-drain plug; In the process of forming the dielectric layer, the dielectric layer covers the first source-drain plug, the second source-drain plug and the third source-drain plug.

19. The method for forming a semiconductor structure according to claim 18, wherein: The steps of forming the first source-drain plug, the second source-drain plug and the third source-drain plug include: forming a first auxiliary layer on the top of the substrate, the first auxiliary layer covering the side walls and the top of the first source-drain and the second source-drain; forming a first opening in the first auxiliary layer at the junction of the first sub-unit area and the second sub-unit area adjacent to each other to expose the first source-drain terminal end and the second source-drain terminal end; forming a second source-drain plug covering the first source-drain terminal end in the first opening; forming a second auxiliary layer covering the top of the second source-drain plug in the first opening, the second auxiliary layer exposing the end of the second source-drain; forming a third source-drain plug in the remaining space of the first opening; and removing the first auxiliary layer and the second auxiliary layer.

20. The method for forming a semiconductor structure according to claim 18, wherein: After forming the transfer gate transistor, the method for forming the semiconductor structure further includes: forming a first through-hole interconnect structure located on top of the first source-drain plug in the dielectric layer, the first through-hole interconnect structure being electrically connected to the first source-drain plug; forming a second through-hole interconnect structure located on top of the gate plug and away from the transfer gate transistor in the dielectric layer, the second through-hole interconnect structure being electrically connected to the gate plug; forming a first interconnect layer in the dielectric layer connecting a first through-hole interconnect structure of the first sub-unit region and a second through-hole interconnect structure of the second sub-unit region; A second interconnection layer connecting the second through-via interconnection structure of the first sub-unit area and the first through-via interconnection structure of the second sub-unit area is formed in the dielectric layer.

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