Data reading circuit and method of memory and memory

Abstract

The invention discloses a data reading circuit and method of a memorizer and the memorizer, the circuit comprises a comparison output unit and a circuit control unit, the comparison output unit comprises a pseudo current tube and a latch pair tube, and the comparison output unit is used for obtaining a pre-charging signal and a data signal; the pre-charging signal is used for controlling the output node voltage of the latch pair transistor to be in a pre-charging state or a data reading state according to the pre-charging signal; the current control unit comprises a transmission gate, and is used for obtaining a control signal of the transmission gate, so as to control the voltage of an output node of the latch pair transistor to discharge through the pseudo current tube according to the control signal, a pre-charging signal and a data signal, or control the voltage of the output node of the latch pair transistor to be stabilized at a first voltage and a second voltage, data reading is facilitated; therefore, by introducing the transmission gate circuit, the voltages of the output nodes are rapidly discharged, and the voltages of the two output nodes are respectively stabilized at the first voltage and the second voltage through the latch pair transistors, so that the power consumption of the circuit is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a data reading circuit of a memory, a data reading method of a memory, and a memory. Background Art

[0002] In the related art, the memory includes a storage unit and a read circuit. The read circuit is used to perform a data read operation. By comparing the data voltage and the reference voltage, the value of the data stored in the storage unit can be obtained. The read circuit generally includes a comparator, that is, a comparator is used to read data. However, the power consumption of reading data using the existing comparator circuit structure is high. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems in the above-mentioned technology to a certain extent. To this end, one purpose of the present invention is to provide a data reading circuit of a memory, which introduces a transmission gate circuit so that during the data reading process, the voltages of the two output nodes are stabilized at a first voltage and a second voltage respectively, thereby avoiding the overcurrent problem of the pseudo current tube and achieving a significant reduction in circuit power consumption.

[0004] To achieve the above-mentioned purpose, an embodiment of the present invention proposes a data reading circuit of a memory, comprising a comparison output unit and a circuit control unit, wherein the comparison output unit comprises a pseudo current tube and a latch pair tube, wherein the comparison output unit is used to obtain a pre-charge signal and a data signal, so as to control the output node voltage of the latch pair tube to be in a pre-charge state or a data reading state according to the pre-charge signal; the current control unit comprises a transmission gate, and the current control unit is used to obtain a control signal of the transmission gate, so as to control the output node voltage of the latch pair tube to discharge through the pseudo current tube according to the control signal, the pre-charge signal and the data signal, or control the output node voltage of the latch pair tube to be stable at a first voltage and a second voltage, so as to perform data reading; thus, by introducing a transmission gate circuit, the output node voltage is discharged quickly, and at the same time, the voltages of the two output nodes are stabilized at the first voltage and the second voltage respectively through the latch pair tube, thereby avoiding the overcurrent problem of the pseudo current tube and achieving a significant reduction in circuit power consumption.

[0005] In addition, the data reading circuit of the memory proposed in the embodiment of the present invention may also have the following additional technical features:

[0006] Optionally, the comparison output unit further includes a first MOS tube, a second MOS tube, a seventh MOS tube and an eighth MOS tube, and the latch pair tubes include a first latch pair tube and a second latch pair tube, the first latch pair tube includes a third MOS tube and a fifth MOS tube, and the second latch pair tube includes a fourth MOS tube and a sixth MOS tube; wherein the source of the pseudo current tube is connected to a first voltage, the gate of the pseudo current tube is used to receive a precharge signal, the drain of the pseudo current tube is connected to the source of the first MOS tube and the second MOS tube, the gate of the first MOS tube is used to receive a reference voltage, the drain of the first MOS tube is connected to the source of the third MOS tube, the gate of the second MOS tube is connected to a storage unit to receive a data signal, the drain of the second MOS tube is connected to the source of the fourth MOS tube, and the drain of the third MOS tube is connected to the source of the fourth MOS tube. The gate of the fifth MOS tube is connected to the source of the fifth MOS tube, the drain of the fifth MOS tube is connected to the second voltage, the gate of the fifth MOS tube is connected to the gate of the third MOS tube, the drain of the fourth MOS tube is connected to the source of the sixth MOS tube, the drain of the sixth MOS tube is connected to the second voltage, the gate of the fifth MOS tube is also connected to the source of the sixth MOS tube, the gate of the sixth MOS tube is also connected to the source of the fifth MOS tube, the source of the seventh MOS tube is connected to the source of the fifth MOS tube, the drain of the seventh MOS tube is connected to the second voltage, the gate of the seventh MOS tube is used to receive a pre-charge signal, the source of the eighth MOS tube is connected to the source of the sixth MOS tube, the drain of the eighth MOS tube is connected to the second voltage, and the gate of the eighth MOS tube is used to receive a pre-charge signal.

[0007] Optionally, the transmission gate includes a first transmission gate and a second transmission gate, the first transmission gate includes a ninth MOS tube and an eleventh MOS tube, and the second transmission gate includes a tenth MOS tube and a twelfth MOS tube; wherein, the drains of the ninth MOS tube and the eleventh MOS tube are connected and then connected to the source of the seventh MOS tube, the sources of the ninth MOS tube and the eleventh MOS tube are connected and then connected to the source of the third MOS tube, the gate of the ninth MOS tube is used to receive a first control signal, and the gate of the eleventh MOS tube is used to receive a second control signal; the drains of the tenth MOS tube and the twelfth MOS tube are connected and then connected to the source of the eighth MOS tube, the sources of the tenth MOS tube and the twelfth MOS tube are connected and then connected to the source of the fourth MOS tube, the gate of the tenth MOS tube is used to receive the first control signal, and the gate of the twelfth MOS tube is used to receive the second control signal.

[0008] Optionally, when the pre-charge signal is 0, the output node voltage of the latch pair is in a pre-charge state; when the pre-charge signal is 1, the output node voltage of the latch pair is in a data reading state.

[0009] Optionally, the output node voltage of the latch pair includes a first output node voltage and a second output node voltage, and when the output node voltage of the latch pair is in a pre-charge state, the first output node voltage and the second output node voltage are both charged to the second voltage.

[0010] Optionally, when the pre-charge signal is 1, the first control signal is 0, and the second control signal is 1, the output node voltage of the latch pair is discharged through the pseudo current tube; when the pre-charge signal is 1, the first control signal is 1, and the second control signal is 0, the output node voltage of the latch pair is stabilized at the first voltage and the second voltage to facilitate data reading.

[0011] Optionally, when the pre-charge signal is 1, the first control signal is 1, and the second control signal is 0, if the reference voltage is greater than the data signal, the first output node voltage is stabilized at the second voltage, and the second output node voltage is stabilized at the first voltage; if the reference voltage is less than or equal to the data signal, the first output node voltage is stabilized at the first voltage, and the second output node voltage is stabilized at the second voltage.

[0012] Optionally, the pseudo current tube, the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the eleventh MOS tube, and the twelfth MOS tube are all NMOS tubes; the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube, and the tenth MOS tube are all PMOS tubes.

[0013] To achieve the above-mentioned purpose, the second aspect of the present invention proposes a data reading method for a memory, comprising: using a comparison output unit to obtain a pre-charge signal and a data signal; controlling the output node voltage of the latch pair to be in a pre-charge state or a data reading state according to the pre-charge signal; when the output node voltage of the latch pair is controlled to be in a data reading state, obtaining a control signal through the transmission gate of the current control unit; controlling the output node voltage of the latch pair to discharge through a pseudo current tube according to the control signal, the pre-charge signal and the data signal, or controlling the output node voltage of the latch pair to be stable at a first voltage and a second voltage, so as to perform data reading; thus, by introducing a transmission gate circuit, during the data reading process, the voltages of the two output nodes are respectively stabilized at the first voltage and the second voltage, thereby avoiding the overcurrent problem of the pseudo current tube and achieving a significant reduction in circuit power consumption.

[0014] To achieve the above-mentioned purpose, the third aspect of the present invention proposes a memory, including a data reading circuit of the memory as described above; thereby, by introducing a transmission gate circuit, the output node voltage is discharged quickly, and at the same time, the voltages of the two output nodes are stabilized at the first voltage and the second voltage respectively through the latch pair tube, thereby avoiding the overcurrent problem of the pseudo current tube and achieving a significant reduction in circuit power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A circuit block diagram of a data reading circuit of a memory according to an embodiment of the present invention;

[0016] Figure 2 A schematic diagram of a curve of an output node voltage relative to time of a data reading circuit of a memory according to an embodiment of the present invention;

[0017] Figure 3 A schematic diagram of a curve of an output node voltage relative to time of a data reading circuit of a memory according to another embodiment of the present invention;

[0018] Figure 4 FIG. 4 is a flow chart of a method for reading data from a memory according to another embodiment of the present invention. DETAILED DESCRIPTION

[0019] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and should not be construed as limiting the present invention.

[0020] In order to better understand the above technical solution, exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0021] In order to better understand the above technical solution, the above technical solution will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0022] The data reading circuit of the memory according to the embodiment of the present invention will be described below with reference to the accompanying drawings.

[0023] refer to Figure 1 As shown, the data reading circuit of the memory provided by the embodiment of the present invention includes a comparison output unit and a current control unit.

[0024] Among them, the comparison output unit includes a pseudo current tube NM0 and a latch pair tube, and the comparison output unit is used to obtain a pre-charge signal SAE and a data signal SAIN to control the output node voltage of the latch pair tube to be in a pre-charge state or a data reading state according to the pre-charge signal SAE.

[0025] That is to say, a precharge signal is obtained through an external circuit so as to control the output node voltage of the latch pair to precharge or read data according to the precharge signal. When in the precharge state, the output node of the latch pair is charged to the second voltage.

[0026] As an embodiment, the comparison output unit further includes a first MOS tube NM1, a second MOS tube NM2, a seventh MOS tube PM7 and an eighth MOS tube PM8, and the latch pair tubes include a first latch pair tube and a second latch pair tube, the first latch pair tube includes a third MOS tube NM3 and a fifth MOS tube PM5, and the second latch pair tube includes a fourth MOS tube NM4 and a sixth MOS tube PM6.

[0027] Specifically, the source of the pseudo current tube NM0 is connected to the first voltage VS, the gate of the pseudo current tube is used to receive the pre-charge signal SAE, the drain of the pseudo current tube NM0 is connected to the source of the first MOS tube NM1 and the second MOS tube NM2, the gate of the first MOS tube NM1 is used to receive the reference voltage VREF, the drain of the first MOS tube NM1 is connected to the source of the third MOS tube NM3, the gate of the second MOS tube NM2 is connected to the storage unit to receive the data signal SAIN, the drain of the second MOS tube NM2 is connected to the source of the fourth MOS tube NM4, the drain of the third MOS tube NM3 is connected to the source of the fifth MOS tube PM5, the drain of the fifth MOS tube PM5 is connected to the second voltage VD, and the gate of the fifth MOS tube PM5 is connected to The gate of the third MOS tube NM3 and the drain of the fourth MOS tube NM4 are connected to the source of the sixth MOS tube PM6, the drain of the sixth MOS tube PM6 is connected to the second voltage, the gate of the fifth MOS tube PM5 is also connected to the source of the sixth MOS tube PM6, the gate of the sixth MOS tube PM6 is also connected to the source of the fifth MOS tube, the source of the seventh MOS tube PM7 is connected to the source of the fifth MOS tube, the drain of the seventh MOS tube PM7 is connected to the second voltage, the gate of the seventh MOS tube PM7 is used to receive the pre-charge signal SAE, the source of the eighth MOS tube PM8 is connected to the source of the sixth MOS tube PM6, the drain of the eighth MOS tube PM8 is connected to the second voltage, and the gate of the eighth MOS tube PM8 is used to receive the pre-charge signal SAE.

[0028] As a specific embodiment, when the pre-charge signal SAE is 0, the output node voltage of the latch pair is in a pre-charge state; when the pre-charge signal SAE is 1, the output node voltage of the latch pair is in a data reading state.

[0029] As a specific embodiment, the output node voltage of the latch pair includes a first output node voltage OUT and a second output node voltage OUTb. When the output node voltage of the latch pair is in a pre-charge state, the first output node voltage OUT and the second output node voltage OUTb are both charged to the second voltage VD.

[0030] It should be noted that the pseudo current transistor NM0, the first MOS transistor NM1, the second MOS transistor NM2, the third MOS transistor NM3 and the fourth MOS transistor NM4 are NMOS transistors, and the fifth MOS transistor PM5, the sixth MOS transistor PM6, the seventh MOS transistor PM7 and the eighth MOS transistor PM8 are NMOS transistors.

[0031] That is to say, the latch pair is composed of two complementary transistors, one is an NMOS tube and the other is a PPMOS tube, which can be used to store one bit of information, that is, binary 0 or 1; the pre-charge signal SAE acts as a pre-charge switch, and when it is 0, the first output node voltage OUT and the second output node voltage OUTb of the latch pair are pre-charged.

[0032] Among them, the current control unit includes a transmission gate, and the current control unit is used to obtain a control signal of the transmission gate to control the output node voltage of the latch pair to discharge through the pseudo current tube according to the control signal, the pre-charge signal SAE and the data signal SAIN, or to control the output node voltage of the latch pair to be stable at the first voltage VS and the second voltage VD for data reading.

[0033] That is to say, when the pre-charge signal SAE is 1, the output node voltage of the latch pair is in a data reading state, and the data reading state also includes a discharge state and a reading state. The transmission gate can switch the current path under the control of the control signal to make it in a discharge state or a reading state; when reading data, the voltage states of the first output node OUT and the second output node OUTb are controlled by the transmission gate, so that they are respectively stabilized at the first voltage VS and the second voltage VD, thereby avoiding the overcurrent problem of the pseudo current tube, while reducing the circuit power consumption and ensuring the correct reading of data.

[0034] As an embodiment, the transmission gate includes a first transmission gate and a second transmission gate, the first transmission gate includes a ninth MOS transistor PM9 and an eleventh MOS transistor NM11, and the second transmission gate includes a tenth MOS transistor PM10 and a twelfth MOS transistor NM12.

[0035] Specifically, the drains of the ninth MOS transistor PM9 and the eleventh MOS transistor NM11 are connected to the source of the seventh MOS transistor, the sources of the ninth MOS transistor PM9 and the eleventh MOS transistor NM11 are connected to the source of the third MOS transistor NM3, the gate of the ninth MOS transistor PM9 is used to receive the first control signal Latchb, and the gate of the eleventh MOS transistor NM11 is used to receive the second control signal Latch; the drains of the tenth MOS transistor PM10 and the twelfth MOS transistor NM12 are connected to the source of the eighth MOS transistor, the sources of the tenth MOS transistor PM10 and the twelfth MOS transistor NM12 are connected to the source of the fourth MOS transistor NM4, the gate of the tenth MOS transistor PM10 is used to receive the first control signal Latchb, and the gate of the twelfth MOS transistor NM12 is used to receive the second control signal Latch.

[0036] It should be noted that the eleventh MOS transistor NM11 and the twelfth MOS transistor NM12 are NMOS transistors; the ninth MOS transistor PM9 and the tenth MOS transistor PM10 are PMOS transistors.

[0037] As a specific embodiment, when the pre-charge signal is 1, the first control signal is 0, and the second control signal is 1, the output node voltage of the latch pair is discharged through the pseudo current tube; when the pre-charge signal is 1, the first control signal is 1, and the second control signal is 0, the output node voltage of the latch pair is stabilized at the first voltage and the second voltage to facilitate data reading.

[0038] As an example, Figure 2 As shown, when the pre-charge signal SAE is 0, the first control signal Latchb is 1, and the second control signal Latch is 0, the first output node voltage OUT and the second output node voltage OUTb are pre-charged to the second voltage VD; when the pre-charge signal SAE is 1, the first control signal Latchb is 0, the second control signal Latch is 1, and the reference voltage VREF is greater than the data signal SAIN, the first output node voltage OUT and the second output node voltage OUTb are discharged through the pseudo current tube NM0, and the first output node voltage OUT is greater than the second output node voltage OUTb; when the pre-charge signal SAE is 1, the first control signal Latchb is 1, and the second control signal Latch is 0, the first output node voltage OUT is stabilized at the second voltage VD, and the second output node voltage OUTb is stabilized at the first voltage VS. At this time, there is no pseudo current and the data is read out.

[0039] As another example, Figure 3As shown, when the pre-charge signal SAE is 0, the first control signal Latchb is 1, and the second control signal Latch is 0, the first output node voltage OUT and the second output node voltage OUTb are pre-charged to the second voltage VD; when the pre-charge signal SAE is 1, the first control signal Latchb is 0, the second control signal Latch is 1, and the reference voltage VREF is less than or equal to the data signal SAIN, the first output node voltage OUT and the second output node voltage OUTb are discharged through the pseudo current tube NM0, and the first output node voltage OUT is less than the second output node voltage OUTb; when the pre-charge signal SAE is 1, the first control signal Latchb is 1, and the second control signal Latch is 0, the first output node voltage OUT is stabilized at the first voltage VS, and the second output node voltage OUTb is stabilized at the second voltage VD; at this time, there is no pseudo current and the data is read out.

[0040] It should be noted that if Figure 2 The data read out in the example shown is 0, then the corresponding Figure 3 The example shown reads data as 1. On the contrary, if Figure 2 The data read out in the example shown is 1, then the corresponding Figure 3 In the example shown, the data read out is 0; in addition, when the first control signal Latchb is 1, the second control signal Latch is 0, and conversely, when the first control signal Latchb is 0, the second control signal Latch is 1.

[0041] In summary, the data reading circuit of the memory proposed in the embodiment of the present invention includes a comparison output unit and a circuit control unit, the comparison output unit includes a pseudo current tube and a latch pair tube, the comparison output unit is used to obtain a pre-charge signal and a data signal, so as to control the output node voltage of the latch pair tube to be in a pre-charge state or a data reading state according to the pre-charge signal; the current control unit includes a transmission gate, and the current control unit is used to obtain a control signal of the transmission gate, so as to control the output node voltage of the latch pair tube to discharge through the pseudo current tube according to the control signal, the pre-charge signal and the data signal, or control the output node voltage of the latch pair tube to be stable at a first voltage and a second voltage, so as to perform data reading; thus, by introducing a transmission gate circuit, the output node voltage is discharged quickly, and at the same time, the voltages of the two output nodes are stabilized at the first voltage and the second voltage respectively through the latch pair tube, thereby avoiding the overcurrent problem of the pseudo current tube and achieving a significant reduction in circuit power consumption.

[0042] In addition, if Figure 4 As shown, an embodiment of the present invention further provides a method for reading data from a memory, comprising the following steps:

[0043] S101, using a comparison output unit to obtain a pre-charge signal and a data signal.

[0044] S102, controlling the output node voltage of the latch pair to be in a pre-charging state or a data reading state according to the pre-charging signal;

[0045] S103, when the output node voltage of the control latch pair is in a data reading state, a control signal is obtained through a transmission gate of the current control unit.

[0046] S104, according to the control signal, the pre-charge signal and the data signal, the output node voltage of the latch pair is controlled to be discharged through the pseudo current tube, or the output node voltage of the latch pair is controlled to be stable at the first voltage and the second voltage, so as to read the data.

[0047] Therefore, by introducing the transmission gate circuit, the output node voltage is discharged quickly, and at the same time, the voltages of the two output nodes are stabilized at the first voltage and the second voltage respectively through the latch pair tube, thereby avoiding the overcurrent problem of the pseudo current tube and achieving a significant reduction in circuit power consumption.

[0048] It should be noted that the above-mentioned examples of the data reading circuit of the memory are also applicable to the data reading method of the memory of this embodiment, and will not be described in detail here.

[0049] In addition, an embodiment of the present invention further proposes a memory, including a data reading circuit of the memory as described above; thereby, by introducing a transmission gate circuit, the output node voltage is discharged quickly, and at the same time, the voltages of the two output nodes are stabilized at a first voltage and a second voltage respectively through a latch pair tube, thereby avoiding the overcurrent problem of the pseudo current tube and achieving a significant reduction in circuit power consumption.

[0050] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0051] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0052] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0054] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms should not be understood as necessarily being directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification.

[0055] Although the embodiments of the present invention have been shown and described above, it is to be understood that the above embodiments are exemplary and are not to be construed as limitations of the present invention. A person skilled in the art may change, modify, replace and vary the above embodiments within the scope of the present invention.

Claims

1. A data reading circuit of a memory, characterized in that: include: A comparison output unit, the comparison output unit comprising a pseudo current tube and a latch pair tube, the comparison output unit being used to obtain a pre-charge signal and a data signal, so as to control the output node voltage of the latch pair tube to be in a pre-charge state or a data reading state according to the pre-charge signal; A current control unit, the current control unit includes a transmission gate, and the current control unit is used to obtain a control signal of the transmission gate to control the output node voltage of the latch pair to discharge through a pseudo current tube according to the control signal, the pre-charge signal and the data signal, or to control the output node voltage of the latch pair to be stable at a first voltage and a second voltage for data reading.

2. The memory data reading circuit according to claim 1, characterized in that: The comparison output unit further includes a first MOS tube, a second MOS tube, a seventh MOS tube and an eighth MOS tube, and the latch pair tube includes a first latch pair tube and a second latch pair tube, the first latch pair tube includes a third MOS tube and a fifth MOS tube, and the second latch pair tube includes a fourth MOS tube and a sixth MOS tube; Wherein, the source of the pseudo current tube is connected to the first voltage, the gate of the pseudo current tube is used to receive the precharge signal, the drain of the pseudo current tube is connected to the source of the first MOS tube and the second MOS tube, the gate of the first MOS tube is used to receive the reference voltage, the drain of the first MOS tube is connected to the source of the third MOS tube, the gate of the second MOS tube is connected to the storage unit to receive the data signal, the drain of the second MOS tube is connected to the source of the fourth MOS tube, the drain of the third MOS tube is connected to the source of the fifth MOS tube, the drain of the fifth MOS tube is connected to the second voltage, and the gate of the fifth MOS tube is connected to the The gate of the fourth MOS tube is connected to the source of the sixth MOS tube, the drain of the sixth MOS tube is connected to the second voltage, the gate of the fifth MOS tube is also connected to the source of the sixth MOS tube, the gate of the sixth MOS tube is also connected to the source of the fifth MOS tube, the source of the seventh MOS tube is connected to the source of the fifth MOS tube, the drain of the seventh MOS tube is connected to the second voltage, the gate of the seventh MOS tube is used to receive a pre-charge signal, the source of the eighth MOS tube is connected to the source of the sixth MOS tube, the drain of the eighth MOS tube is connected to the second voltage, and the gate of the eighth MOS tube is used to receive a pre-charge signal.

3. The data reading circuit of the memory according to claim 2, characterized in that: The transmission gate includes a first transmission gate and a second transmission gate, the first transmission gate includes a ninth MOS transistor and an eleventh MOS transistor, and the second transmission gate includes a tenth MOS transistor and a twelfth MOS transistor; Among them, the drains of the ninth MOS tube and the eleventh MOS tube are connected to the source of the seventh MOS tube, the sources of the ninth MOS tube and the eleventh MOS tube are connected to the source of the third MOS tube, the gate of the ninth MOS tube is used to receive the first control signal, and the gate of the eleventh MOS tube is used to receive the second control signal; the drains of the tenth MOS tube and the twelfth MOS tube are connected to the source of the eighth MOS tube, the sources of the tenth MOS tube and the twelfth MOS tube are connected to the source of the fourth MOS tube, the gate of the tenth MOS tube is used to receive the first control signal, and the gate of the twelfth MOS tube is used to receive the second control signal.

4. The data reading circuit of the memory according to claim 3, characterized in that: When the pre-charge signal is 0, the output node voltage of the latch pair is in a pre-charge state; when the pre-charge signal is 1, the output node voltage of the latch pair is in a data reading state.

5. The data reading circuit of the memory according to claim 4, characterized in that: The output node voltage of the latch pair includes a first output node voltage and a second output node voltage. When the output node voltage of the latch pair is in a pre-charge state, the first output node voltage and the second output node voltage are both charged to a second voltage.

6. The data reading circuit of the memory according to claim 5, characterized in that: When the pre-charge signal is 1, the first control signal is 0, and the second control signal is 1, the output node voltage of the latch pair is discharged through the pseudo current tube; when the pre-charge signal is 1, the first control signal is 1, and the second control signal is 0, the output node voltage of the latch pair is stabilized at the first voltage and the second voltage to facilitate data reading.

7. The data reading circuit of the memory according to claim 6, characterized in that: When the pre-charge signal is 1, the first control signal is 1, and the second control signal is 0, if the reference voltage is greater than the data signal, the first output node voltage is stabilized at the second voltage, and the second output node voltage is stabilized at the first voltage; if the reference voltage is less than or equal to the data signal, the first output node voltage is stabilized at the first voltage, and the second output node voltage is stabilized at the second voltage.

8. The data reading circuit of the memory according to claim 3, characterized in that: The pseudo current tube, the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube, the eleventh MOS tube and the twelfth MOS tube are all NMOS tubes; the fifth MOS tube, the sixth MOS tube, the seventh MOS tube, the eighth MOS tube, the ninth MOS tube and the tenth MOS tube are all PMOS tubes.

9. A method for reading data from a memory, characterized in that: The following steps are involved: A comparison output unit is used to obtain a precharge signal and a data signal; Control the output node voltage of the latch pair to be in a pre-charging state or a data reading state according to the pre-charging signal; When the output node voltage of the latch pair is controlled to be in a data reading state, a control signal is obtained through the transmission gate of the current control unit; According to the control signal, the pre-charge signal and the data signal, the output node voltage of the latch pair is controlled to discharge through the pseudo current tube, or the output node voltage of the latch pair is controlled to be stable between the first voltage and the second voltage for data reading.

10. A memory, characterized in that: A data reading circuit comprising the memory as claimed in any one of claims 1 to 8.

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