Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a method for forming the same, the structure comprising: a first gate structure, a first channel layer and a first source / drain to form a pull-down transistor, the first gate structure, a second channel layer and a second source / drain to form a pull-up transistor; a gate plug on top of the first gate structure and electrically connected to the first gate structure; a dielectric layer on top of the substrate and covering the pull-down transistor, the pull-up transistor and the gate plug; a metal layer on top of the dielectric layer; a recess through the metal layer, the dielectric layer and a portion of the gate plug; a third channel layer covering the bottom and sidewalls of the recess; a second gate structure in the remaining space of the recess, the gate plug surrounding the second gate structure to serve as a third source / drain, the metal layer surrounding the second gate structure to serve as a fourth source / drain, the second gate structure, the third channel layer, the third source / drain and the fourth source / drain to form a pass gate transistor. The integration of the semiconductor structure is improved.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and particularly to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In the current semiconductor industry, integrated circuit products can be mainly divided into three types: logic, memory and analog circuit, wherein the memory device accounts for a considerable proportion in the integrated circuit products. With the development of semiconductor technology, the memory device is applied more widely, and it is required to form the memory device and other devices in a chip at the same time to form an embedded semiconductor memory device. For example, the memory device is embedded in a central processing unit, and it is required to make the memory device compatible with the embedded central processing unit platform, and to keep the original specifications and corresponding electrical properties of the memory device.

[0003] Generally, it is required to make the memory device compatible with the embedded standard logic device. For the embedded semiconductor device, it is usually divided into a logic region and a memory region, the logic region usually includes logic devices, and the memory region includes memory devices. With the development of memory technology, various types of semiconductor memories appear, such as static random access memory (SRAM), dynamic random access memory (DRAM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM) and flash memory. Since the static random access memory has the advantages of low power consumption and fast working speed, the static random access memory and the forming method thereof are paid more and more attention.

[0004] At present, the integration of the SRAM device still needs to be improved. SUMMARY

[0005] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which optimizes the performance of the semiconductor device.

[0006] To solve the above problems, the embodiment of the present application provides a semiconductor structure, comprising: a substrate; a channel stack structure located on the substrate, and the channel stack structure comprising a first channel layer and a second channel layer arranged on the first channel layer in a spaced manner; a first gate structure crossing the channel stack structure and surrounding the first channel layer and the second channel layer; a first source-drain electrode located in the first channel layer on both sides of the first gate structure; a second source-drain electrode located in the second channel layer on both sides of the first gate structure, and the first gate structure, the first channel layer and the first source-drain electrode forming a pull-down transistor, the first gate structure, the second channel layer and the second source-drain electrode forming a pull-up transistor; a gate plug located on the top of the first gate structure and electrically connected with the first gate structure; a dielectric layer located on the top of the substrate and covering the pull-down transistor, the pull-up transistor and the gate plug; a metal layer located on the top of the dielectric layer; a groove penetrating through the metal layer, the dielectric layer and part of the thickness of the gate plug; a third channel layer covering the bottom and the sidewall of the groove; a second gate structure located in the remaining space of the groove, and the gate plug surrounding the second gate structure serving as a third source-drain electrode, the metal layer surrounding the second gate structure serving as a fourth source-drain electrode, the second gate structure, the third channel layer, the third source-drain electrode and the fourth source-drain electrode forming a transmission gate transistor.

[0007] Correspondingly, the embodiment of the present application also provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a channel stack structure, a first gate structure crossing the channel stack structure, a first source-drain electrode located in the first channel layer on both sides of the first gate structure, and a second source-drain electrode located in the second channel layer on both sides of the first gate structure on the substrate, the channel stack structure comprising a first channel layer and a second channel layer arranged on the first channel layer in a spaced manner, and the first gate structure surrounding and covering the first channel layer and the second channel layer, wherein the first gate structure, the first channel layer and the first source-drain electrode form a pull-down transistor, and the first gate structure, the second channel layer and the second source-drain electrode form a pull-up transistor; forming a gate plug on the top of the first gate structure and electrically connected with the first gate structure; forming a dielectric layer covering the pull-down transistor, the pull-up transistor and the gate plug; forming a metal layer on the top of the dielectric layer; forming a groove penetrating through the metal layer and the dielectric layer and part of the gate plug on the top of the first gate structure; forming a third channel layer covering the bottom and the sidewall of the groove; forming a second gate structure in the remaining space of the groove, and the gate plug surrounding the second gate structure serving as a third source-drain electrode, the metal layer surrounding the second gate structure serving as a fourth source-drain electrode, the second gate structure, the third channel layer, the third source-drain electrode and the fourth source-drain electrode forming a transmission gate transistor.

[0008] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0009] The semiconductor structure and the forming method of the semiconductor structure provided by the embodiment of the present application have the following advantages: the first gate structure, the first channel layer and the first source / drain electrode constitute a pull-down transistor, the first gate structure, the second channel layer and the second source / drain electrode constitute a pull-up transistor, the gate plug is formed on the top of the first gate structure and electrically connected with the first gate structure, the dielectric layer covering the pull-down transistor, the pull-up transistor and the gate plug is formed, the metal layer is formed on the top of the dielectric layer, the recess is formed in the metal layer, the dielectric layer and part of the gate plug on the top of the first gate structure, the third channel layer covering the bottom and the sidewall of the recess is formed, the second gate structure is formed in the remaining space of the recess, the gate plug surrounding the second gate structure is used as the third source / drain electrode, the metal layer surrounding the second gate structure is used as the fourth source / drain electrode, and the second gate structure, the third channel layer, the third source / drain electrode and the fourth source / drain electrode constitute a transfer gate transistor. Therefore, the semiconductor structure of the embodiment of the present application adopts the pull-down transistor and the pull-up transistor based on the CFET (complementary FET, complementary field effect transistor) structure and the transfer gate transistor based on the CAA (channel all around, vertical channel all around) structure, so as to realize the stacked arrangement of the pull-down transistor, the pull-up transistor and the transfer gate transistor. In addition, the transfer gate transistor in the embodiment of the present application is arranged in the dielectric layer, that is, the transfer gate transistor utilizes part of the space position of the dielectric layer, so that the overall height of the memory can be reduced, the memory occupies a smaller space area, and thus the overall size of the semiconductor structure can be further reduced (for example, compared with the memory based on the fin field effect transistor, the memory based on the CFET can save about 40% of the chip area without changing the pitch size, and the semiconductor structure of the embodiment of the present application can save about 20% of the area on this basis), and the integration of the semiconductor structure is improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figures 1-2 is a structure diagram corresponding to an embodiment of the semiconductor structure of the present application.

[0011] Figures 3-25 is a structure diagram corresponding to each step in the first embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0012] As known from the background, at present, the integration of the SRAM device still needs to be improved, and the chip area is still large.

[0013] To solve the technical problems, the embodiment of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate; forming a channel stack structure, a first gate structure across the channel stack structure, a first source-drain electrode in a first channel layer on both sides of the first gate structure, and a second source-drain electrode in a second channel layer on both sides of the first gate structure on the substrate, the channel stack structure comprising the first channel layer and the second channel layer arranged on the first channel layer in a spaced manner, and the first gate structure surrounding and covering the first channel layer and the second channel layer, wherein the first gate structure, the first channel layer and the first source-drain electrode constitute a pull-down transistor, the first gate structure, the second channel layer and the second source-drain electrode constitute a pull-up transistor; forming a gate plug on the top of the first gate structure, and the gate plug being electrically connected with the first gate structure; forming a dielectric layer covering the pull-down transistor and the pull-up transistor and the gate plug; forming a metal layer on the top of the dielectric layer; forming a groove penetrating through the metal layer and the dielectric layer and part of the gate plug on the top of the first gate structure; forming a third channel layer covering the bottom and the sidewall of the groove; forming a second gate structure in the remaining space of the groove, and the gate plug surrounding the second gate structure being used as a third source-drain electrode, the metal layer surrounding the second gate structure being used as a fourth source-drain electrode, and the second gate structure, the third channel layer, the third source-drain electrode and the fourth source-drain electrode constituting a transmission gate transistor.

[0014] The forming method of the semiconductor structure provided by the embodiment of the present application comprises the following steps: forming a first gate structure, a first channel layer and a first source / drain electrode to form a pull-down transistor; forming a second channel layer and a second source / drain electrode to form a pull-up transistor; forming a gate plug on the top of the first gate structure, and the gate plug is electrically connected with the first gate structure; forming a dielectric layer covering the pull-down transistor, the pull-up transistor and the gate plug; forming a metal layer on the top of the dielectric layer; forming a groove penetrating through the metal layer, the dielectric layer and part of the gate plug on the top of the first gate structure; forming a third channel layer covering the bottom and the sidewall of the groove; forming a second gate structure in the remaining space of the groove, and the gate plug surrounding the second gate structure is used as a third source / drain electrode, and the metal layer surrounding the second gate structure is used as a fourth source / drain electrode; and forming a transmission gate transistor by the second gate structure, the third channel layer, the third source / drain electrode and the fourth source / drain electrode. Therefore, the semiconductor structure of the embodiment of the present application adopts the pull-down transistor and the pull-up transistor based on the CFET (complementary FET, complementary field effect transistor) structure and the transmission gate transistor based on the CAA (channel all around, vertical channel all around) structure, so as to realize the stacked arrangement of the pull-down transistor, the pull-up transistor and the transmission gate transistor. In addition, the transmission gate transistor in the embodiment of the present application is arranged in the dielectric layer, that is, the transmission gate transistor utilizes part of the space position of the dielectric layer, so that the overall height of the memory can be reduced, the space area occupied by the memory is smaller, and thus the overall size of the semiconductor structure can be further reduced (for example, compared with the memory based on the fin field effect transistor, the memory based on the CFET can save about 40% of the chip area without changing the size of the interval, and the semiconductor structure of the embodiment of the present application can save about 20% of the area on this basis), and the integration of the semiconductor structure is improved.

[0015] In order to make the above-mentioned purpose, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0016] Figures 1-2 is a structural schematic diagram of an embodiment of the semiconductor structure of the present application, wherein, Figure 1 is a perspective view of the semiconductor structure, Figure 2 is a sectional view along the CC direction. Figure 1 is a sectional view along the CC direction.

[0017] The semiconductor structure comprises: a substrate 200; a channel stack structure 288 located on the substrate 200, and the channel stack structure 288 comprises a first channel layer 205 and a second channel layer 207 arranged on the first channel layer 205; a first gate structure 240 crossing the channel stack structure 288 and surrounding the first channel layer 205 and the second channel layer 207; a first source-drain electrode 231 located in the first channel layer 205 on both sides of the first gate structure 240; a second source-drain electrode 230 located in the second channel layer 207 on both sides of the first gate structure 240, and the first gate structure 240, the first channel layer 205 and the first source-drain electrode 231 form a pull-down transistor, the first gate structure 240, the second channel layer 207 and the second source-drain electrode 230 form a pull-up transistor; a gate plug 290 located on top of the first gate structure 240, and the gate plug 290 is electrically connected with the first gate structure 240; a dielectric layer 229 located on top of the substrate 200 and covering the pull-down transistor, the pull-up transistor and the gate plug 290; a metal layer 293 located on top of the dielectric layer 229; a groove (not shown) penetrating through the metal layer 293, the dielectric layer 229 and part of the thickness of the gate plug 290; a third channel layer 239 covering the bottom and sidewall of the groove (not shown); a second gate structure 295 located in the remaining space of the groove (not shown), and the gate plug 290 surrounding the second gate structure 295 is used as a third source-drain electrode (not labeled), the metal layer 293 surrounding the second gate structure 295 is used as a fourth source-drain electrode (not labeled), and the second gate structure 295, the third channel layer 239, the third source-drain electrode (not labeled) and the fourth source-drain electrode (not labeled) form a pass-gate transistor.

[0018] It should be noted that the semiconductor structure of the embodiment adopts a pull-down transistor and a pull-up transistor based on a CFET (complementary FET, complementary field effect transistor) structure, and a pass-gate transistor based on a CAA (channel all around, vertical channel all around) structure, so as to realize the stacked arrangement of the pull-down transistor, the pull-up transistor and the pass-gate transistor. Moreover, the pass-gate transistor in the embodiment is arranged in the dielectric layer 229, that is, the pass-gate transistor utilizes part of the space position of the dielectric layer 229, so as to reduce the overall height of the memory and the space area occupied by the memory, thereby facilitating the further reduction of the overall size of the semiconductor structure (for example, compared with the fin field effect transistor-based memory, the CFET-based memory can save about 40% of the chip area without changing the pitch size, and the semiconductor structure of the embodiment can save about 20% of the area on this basis), and further improve the integration of the semiconductor structure.

[0019] The substrate 200 provides a process platform for arranging the semiconductor structure.

[0020] In this embodiment, the substrate 200 comprises a substrate.

[0021] The material of the substrate is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. The material of the substrate can be a material suitable for the process needs or easy to integrate.

[0022] In this embodiment, the substrate 200 comprises adjacent first sub-cell region 200A and second sub-cell region 200B, and the adjacent first sub-cell region 200A and second sub-cell region 200B constitute a memory cell region 200C.

[0023] In this embodiment, the semiconductor structure is an SRAM device, and the SRAM device comprises a plurality of memory cell regions 200C.

[0024] Specifically, the first sub-cell region 200A and the second sub-cell region 200B each comprise a pass gate transistor region, a pull-down transistor region and a pull-up transistor region.

[0025] Specifically, the pass gate transistor region is used to form a pass gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. The pass gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0026] Specifically, the channel stack structure 288 is used to provide a conductive channel for the pull-up transistor and the pull-down transistor.

[0027] In this embodiment, the channel stack structure 288 is located on the substrate 200 of the first sub-cell region 200A and the second sub-cell region 200B, respectively.

[0028] In this embodiment, the channel stack structure 288 comprises a first channel layer 205 and a second channel layer 207 spaced apart on the first channel layer 205.

[0029] The stacking direction of the first channel layer 205 and the second channel layer 207 is perpendicular to the surface of the substrate 200.

[0030] In this embodiment, the material of the first channel layer 205 and the second channel layer 207 is the same as the material of the substrate 200, and the material of the first channel layer 205 and the second channel layer 207 is Si.

[0031] The first gate structure 240 is used to control the opening and closing of the conductive channel when the SRAM device is working.

[0032] Specifically, the first gate structure 240 is a metal gate structure.

[0033] In this embodiment, the first gate structure 240 includes a first gate dielectric layer (not shown in the figure) and a first gate electrode layer (not shown in the figure) covering the first gate dielectric layer.

[0034] In this embodiment, the material of the first gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0035] Specifically, the first gate dielectric layer includes a first gate oxide layer and a first high-k gate dielectric layer conformally covering the first gate oxide layer. The material of the first high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0036] The first gate electrode layer is used for subsequent electrical connection with an external structure. The material of the first gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the first gate electrode layer can include a first work function layer and a first electrode layer covering the first work function layer, or the first gate electrode layer can also include only the first work function layer.

[0037] In this embodiment, the first gate structure 240 surrounds and covers the first channel layer 205 and the second channel layer 207.

[0038] Specifically, the first gate structure 240 surrounds and covers the top and sidewall of the first channel layer 205, and the second gate structure 295 surrounds and covers the top, sidewall, and bottom of the second channel layer 207.

[0039] It should be noted that in an SRAM device, the pull-up transistor and the pull-down transistor are used to store data.

[0040] In this embodiment, the semiconductor structure further includes an inner wall layer 220 located between the first source-drain electrode 231 and the first gate structure 240, and between the second source-drain electrode 230 and the second gate structure 295.

[0041] The inner wall layer 220 can play a role of isolation between the first source-drain electrode 231 and the first gate structure 240, and between the second source-drain electrode 230 and the first gate structure 240, which is conducive to reducing the parasitic capacitance between the first source-drain electrode 231 and the first gate structure 240, and between the second source-drain electrode 230 and the first gate structure 240.

[0042] In this embodiment, the material of the inner wall layer 220 includes one or more of silicon nitride, silicon oxide, and silicon oxynitride.

[0043] Specifically, the silicon nitride, the silicon oxide and the silicon oxynitride are all dielectric materials, and can play an electrical isolation role between the first source / drain 231 and the first gate structure 240 and between the second source / drain 230 and the first gate structure 240 which are formed subsequently.

[0044] The first source / drain 231 is used as a source and a drain of a pull-down transistor.

[0045] Specifically, since the pull-down transistor is an N-type transistor, the doping type of the first source / drain 231 is N-type.

[0046] The second source / drain 230 is used as a source and a drain of a pull-up transistor.

[0047] Specifically, since the pull-up transistor is a P-type transistor, the doping type of the second source / drain 230 is P-type.

[0048] In the embodiment, on one side of the gate structure, the second source / drain 230 is in contact with the first source / drain 231 located thereunder; and on the other side of the gate structure, the second source / drain 230 is separated from the first source / drain 231 located thereunder.

[0049] It should be noted that, on one side of the gate structure, the second source / drain 230 is in contact with the first source / drain 231 located thereunder, so that the drain region in the pull-up transistor is electrically connected with the drain region in the pull-down transistor, and meanwhile, on one side of the gate structure, the second source / drain 230 is in contact with the first source / drain 231 located thereunder, which also reduces the process difficulty of forming the second source / drain 230 and the first source / drain 231, and eliminates the process step of additionally arranging an interconnection structure connected with the second source / drain 230 and the first source / drain 231, so that the first source / drain 231 is electrically connected with the second source / drain 230, thereby reducing the process cost and the process steps.

[0050] It should be further noted that, on the other side of the gate structure, the second source / drain 230 is separated from the first source / drain 231 located thereunder, so that another second source / drain 230 in the first sub-cell region 200A can be electrically connected with the first source / drain plug 250, and the first source / drain 231 located thereunder can be electrically connected with the second source / drain plug 252, thereby realizing that in the first sub-cell region 200A, the source region of the pull-up transistor can be connected to a power supply voltage through the second source / drain plug 252, and the source region of the pull-down transistor can be connected to the power supply voltage through the first source / drain plug 250.

[0051] In the embodiment, the second source-drain electrode 230 and the first source-drain electrode 231 in contact are in an integrated structure. In the forming step of the second source-drain electrode 230 and the first source-drain electrode 231, the process step of additionally arranging an interconnection structure connected with the second source-drain electrode 230 and the first source-drain electrode 231 is omitted, so that the first source-drain electrode 231 and the second source-drain electrode 230 are electrically connected, thereby reducing the process cost and the process steps.

[0052] As an example, the second source-drain electrode 230 away from the junction of the first sub-unit region 200A and the second sub-unit region 200B is in contact with the first source-drain electrode 231 located thereunder, so that the first source-drain electrode 231 and the second source-drain electrode 230 in the first sub-unit region 200A and the first source-drain electrode 231 and the second source-drain electrode 230 in the second sub-unit region 200B are arranged to be separate and opposite to each other, which means that the interconnection structure (i.e., the second source-drain plug 252 and the third source-drain plug 251) arranged in a spaced stack at the junction of the first sub-unit region 200A and the second sub-unit region 200B can provide power supply voltage to the pull-up transistor and the pull-down transistor in the first sub-unit region 200A and the pull-up transistor and the pull-down transistor in the second sub-unit region 200B at the same time. Meanwhile, the first source-drain electrode 231 and the second source-drain electrode 230 in the first sub-unit region 200A and the first source-drain electrode 231 and the second source-drain electrode 230 in the second sub-unit region 200B are arranged to be opposite to each other, which can make the distance between the first source-drain electrode 231 and the second source-drain electrode 230 in the first sub-unit region 200A and the first source-drain electrode 231 and the second source-drain electrode 230 in the second sub-unit region 200B the shortest. In the forming step of the second source-drain plug 252 and the third source-drain plug 251, the size of the second source-drain plug 252 and the third source-drain plug 251 can be the smallest, thereby reducing the process cost.

[0053] In the embodiment, the semiconductor structure further comprises: a first source-drain plug 250 located at the top of the second source-drain electrode 230 away from the junction of the first sub-unit region 200A and the second sub-unit region 200B, and the first source-drain plug 250 is electrically connected with the second source-drain electrode 230.

[0054] Specifically, the first source-drain plug 250 is electrically connected with the second source-drain electrode 230. Since the first source-drain electrode 231 of the pull-down transistor is in contact with the second source-drain electrode 230 of the pull-up transistor, the first source-drain plug 250 can lead out the electrical property of the first source-drain electrode 231 of the pull-down transistor and the second source-drain electrode 230 of the pull-up transistor, which means that the transfer gate transistor connected with the first source-drain plug 250 can control the pull-up transistor and the pull-down transistor at the same time through the first source-drain plug 250.

[0055] In this embodiment, the material of the first source-drain plug 250 is tungsten. In other embodiments, the material of the first source-drain plug 250 can also be cobalt or ruthenium.

[0056] In this embodiment, the semiconductor structure further comprises: a second source-drain plug 252 located at the junction of the first sub-cell region 200A and the second sub-cell region 200B, and connected to the end of the first source electrode 231, and the first sub-cell region 200A and the second sub-cell region 200B adjacent to each other share the second source-drain plug 252.

[0057] The second source-drain plug 252 is electrically connected to the first source electrode 231, so that the source region of the pull-down transistor is connected to the power supply voltage.

[0058] In this embodiment, the second source-drain plug 252 is used to access VSS.

[0059] Specifically, VSS represents the accessed working negative voltage.

[0060] As an example, the first sub-cell region 200A and the second sub-cell region 200B adjacent to each other share the second source-drain plug 252, so that the second source-drain plug 252 can simultaneously provide the power supply voltage for the pull-down transistor in the first sub-cell region 200A and the second sub-cell region 200B, and at the same time, the first sub-cell region 200A and the second sub-cell region 200B share the second source-drain plug 252, which is beneficial to make the space area occupied by the memory smaller, and further beneficial to make the overall size of the semiconductor structure further reduced.

[0061] In this embodiment, the material of the second source-drain plug 252 is tungsten. In other embodiments, the material of the second source-drain plug 252 can also be cobalt or ruthenium.

[0062] In this embodiment, the semiconductor structure further comprises: a third source-drain plug 251 located at the junction of the first sub-cell region 200A and the second sub-cell region 200B, and connected to the end of the second source electrode 230, and the first sub-cell region 200A and the second sub-cell region 200B adjacent to each other share the third source-drain plug 251.

[0063] The third source-drain plug 251 is electrically connected to the second source electrode 230, realizing that the source region of the pull-up transistor is connected to the power supply voltage.

[0064] The third source-drain plug 251 is used to access VDD.

[0065] Specifically, VDD represents the accessed working positive voltage.

[0066] As an example, the first sub-cell region 200A and the second sub-cell region 200B share the third source-drain plug 251, so that the third source-drain plug 251 can simultaneously provide a power supply voltage for the pull-up transistor in the first sub-cell region 200A and the second sub-cell region 200B, and meanwhile, the first sub-cell region 200A and the second sub-cell region 200B share the third source-drain plug 251, which is conducive to making the space area occupied by the memory smaller, and thus is conducive to further reducing the overall size of the semiconductor structure.

[0067] In this embodiment, the material of the third source-drain plug 251 is tungsten. In other embodiments, the material of the third source-drain plug 251 can also be cobalt or ruthenium.

[0068] It should be noted that the gate plug 290 is used to lead out the electrical property of the first gate structure 240, so as to realize the control of the conductive channel in the pull-up transistor and the pull-down transistor.

[0069] In this embodiment, the material of the gate plug 290 is tungsten. In other embodiments, the material of the gate plug 290 can also be cobalt or ruthenium.

[0070] Specifically, the dielectric layer 229 provides a process basis for arranging the pass-gate transistor, the first interconnection via structure, the second interconnection via structure, the first interconnection layer 279 and the second interconnection layer 299, and meanwhile, the dielectric layer 229 is also used for electrically isolating the pass-gate transistor, the first interconnection via structure, the second interconnection via structure, the first interconnection layer 279 and the second interconnection layer 299.

[0071] In this embodiment, the dielectric layer 229 covers the first source-drain plug 250, and plays an electrically isolating role for the first source-drain plug 250.

[0072] In this embodiment, the dielectric layer 229 also covers the second source-drain plug 252 and the third source-drain plug 251, and plays an electrically isolating role for the second source-drain plug 252 and the third source-drain plug 251.

[0073] In this embodiment, the material of the dielectric layer 229 includes one or more of silicon oxide, silicon carbide and silicon oxynitride.

[0074] Meanwhile, the metal layer 293 is also used as a bit line of the SRAM device, and the bit line is used for reading and writing data in the SRAM device.

[0075] In this embodiment, the material of the metal layer 293 includes one or more of copper, silver, aluminum and gold.

[0076] As an example, the metal layer 293 covers the dielectric layer 229 above the first gate structure 240, exposes the dielectric layer 229 on the side of the first gate structure 240, and reduces the probability of short-circuiting between the metal layer 293 and the first interconnection via structure, the second interconnection via structure, the first interconnection layer 279, and the second interconnection layer 299 in the forming process of the first interconnection via structure, the second interconnection via structure, the first interconnection layer 279, and the second interconnection layer 299.

[0077] The recess (not shown in the figure) provides a spatial position for the transmission gate transistor disposed in the dielectric layer 229, that is, the transmission gate transistor uses part of the spatial position of the dielectric layer 229, which can reduce the overall height of the memory and the space area occupied by the memory, thereby facilitating further reduction of the overall size of the semiconductor structure (for example, compared with a memory based on a fin field effect transistor, a memory based on a CFET can save about 40% of the chip area without changing the pitch size, and the semiconductor structure of the embodiment of the present application can save about 20% of the area on this basis), thereby improving the integration of the semiconductor structure.

[0078] It should be noted that in the transverse direction perpendicular to the sidewall of the recess (not shown in the figure), the transverse dimension of the recess (not shown in the figure) should not be too large or too small. If the transverse dimension of the recess (not shown in the figure) is too large, it is easy to cause the transmission gate transistor disposed in the recess (not shown in the figure) to have a transverse dimension that is also too large, and in the case of a certain transverse dimension of the gate plug 290, it is easy to cause the gate plug 290 surrounding the transmission gate transistor to be too small, which means that the third source-drain (not labeled) of the transmission gate transistor is too small, thereby affecting the electrical performance of the transmission gate transistor. If the transverse dimension of the recess (not shown in the figure) is too small, it is easy to cause the recess (not shown in the figure) to have a large aspect ratio, which increases the process difficulty of disposing the third channel layer 239 and the second gate structure 295 in the recess (not shown in the figure), and increases the risk of voids in the transmission gate transistor. Therefore, in the embodiment, in the transverse direction perpendicular to the sidewall of the recess (not shown in the figure), the transverse dimension of the recess (not shown in the figure) is 10-50 nm.

[0079] Specifically, the depth of the recess (not shown) should not be too large or too small along the normal direction of the surface of the substrate 200. If the depth of the recess (not shown) is too large, the probability of the recess (not shown) penetrating the gate plug 290 is increased, thereby causing the pull-up transistor electrically connected with the gate plug 290 to fail. If the depth of the recess (not shown) is too small, the recess (not shown) fails to penetrate part of the gate plug 290, thereby causing the gate plug 290 to fail to surround the pass gate transistor, which means that the pass gate transistor fails to form a third source / drain electrode (not shown), and further causes the pass gate transistor to fail electrically. Therefore, in the embodiment, the depth of the recess (not shown) is 10 nm to 200 nm along the normal direction of the surface of the substrate 200.

[0080] The third channel layer 239 is used as a conductive channel of the pass gate transistor.

[0081] In the embodiment, the material of the third channel layer 239 includes amorphous metal oxide.

[0082] The amorphous metal oxide layer has the effect of improving the carrier mobility and can improve the electrical performance of the semiconductor structure.

[0083] In the embodiment, the material of the amorphous metal oxide includes indium gallium zinc oxide, which is composed of indium oxide, gallium oxide and zinc oxide.

[0084] The second gate structure 295 is used to control the opening and closing of the conductive channel of the pass gate transistor during operation.

[0085] Specifically, the second gate structure 295 is a metal gate structure.

[0086] In the embodiment, the second gate structure 295 includes a second gate dielectric layer and a second gate electrode layer covering the second gate dielectric layer.

[0087] In the embodiment, the material of the second gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0088] Specifically, the second gate dielectric layer includes a second gate oxide layer and a second high-k gate dielectric layer conformally covering the second gate oxide layer. The material of the second high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0089] The second gate electrode layer is used for subsequent electrical connection with an external structure. The material of the second gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the second gate electrode layer can include a second work function layer and a second electrode layer covering the second work function layer, or the second gate electrode layer can also only include the second work function layer.

[0090] In this embodiment, the semiconductor structure further includes a first via interconnection structure 297 located on top of the first source-drain plug 250, and the first via interconnection structure 297 is electrically connected to the first source-drain plug 250.

[0091] The first via interconnection structure 297 is electrically connected to the first source-drain plug 250, so that the first source-drain plug 250 can lead out the electrical properties of the pull-up transistor and the pull-down transistor through the first via interconnection structure 297.

[0092] In this embodiment, the material of the first via interconnection structure 297 is copper.

[0093] In this embodiment, the semiconductor structure further includes a second via interconnection structure 298 located on top of the gate plug 290 and away from the transmission gate transistor.

[0094] The second via interconnection structure 298 is electrically connected to the gate plug 290, so that the gate plug 290 can lead out the electrical properties of the first gate structure 240 of the pull-up transistor and the pull-down transistor through the second via structure, thereby achieving the effect of controlling the opening and closing of the conductive channel of the pull-up transistor and the pull-down transistor.

[0095] In this embodiment, the material of the second via interconnection structure 298 is copper.

[0096] In this embodiment, the semiconductor structure further includes a first interconnection layer 279 connecting the first via interconnection structure 297 of the first sub-unit region 200A and the second via interconnection structure 298 of the second sub-unit region 200B.

[0097] The first interconnection layer 279 is electrically connected to the first via interconnection structure 297 of the first sub-unit region 200A and the second via interconnection structure 298 of the second sub-unit region 200B, so that the transmission gate transistor in the second sub-unit region 200B can be electrically connected to the pull-up transistor and the pull-down transistor in the first sub-unit region 200A, and further can achieve the control of the transmission of the stored data in the pull-up transistor and the pull-down transistor.

[0098] In this embodiment, the material of the first interconnection layer 279 is copper.

[0099] In this embodiment, the semiconductor structure further comprises: a second interconnection layer 299 connected to the second via interconnection structure 298 of the first sub-unit region 200A and the first via interconnection structure 297 of the second sub-unit region 200B

[0100] The second interconnection layer 299 is electrically connected to the second via interconnection structure 298 of the first sub-unit region 200A and the first via interconnection structure 297 of the second sub-unit region 200B, so that the transmission gate transistor in the first sub-unit region 200A is electrically connected to the pull-up transistor and the pull-down transistor in the second sub-unit region 200B, thereby achieving the transmission of the stored data in the pull-up transistor and the pull-down transistor.

[0101] In this embodiment, the material of the second interconnection layer 299 is copper.

[0102] Figures 3-25 is the structure diagram corresponding to each step in an embodiment of the method for forming the semiconductor structure of the present application.

[0103] Referring to Figure 3 , a substrate 100 is provided.

[0104] The substrate 100 provides a process platform for the forming process of the semiconductor structure.

[0105] In this embodiment, the substrate 100 comprises a substrate.

[0106] The material of the substrate is silicon. In other embodiments, the material of the substrate can also be one or more of germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate or other types of substrates. The material of the substrate can be a material suitable for the process requirements or easy to integrate.

[0107] In this embodiment, the substrate 100 comprises adjacent first sub-unit region 100A and second sub-unit region 100B, and the adjacent first sub-unit region 100A and second sub-unit region 100B constitute a storage unit region 100C. In this embodiment, the semiconductor structure is an SRAM device, and the SRAM device comprises a plurality of storage unit regions 100C.

[0108] In this embodiment, the storage unit region 100C comprises adjacent first sub-unit region 100A and second sub-unit region 100B.

[0109] Specifically, the first sub-unit region 100A and the second sub-unit region 100B each comprise a transmission gate transistor region, a pull-down transistor region and a pull-up transistor region.

[0110] Specifically, the pass gate transistor region is used to form a pass gate transistor, the pull-down transistor region is used to form a pull-down transistor, and the pull-up transistor region is used to form a pull-up transistor. The pass gate transistor and the pull-down transistor are both N-type transistors, and the pull-up transistor is a P-type transistor.

[0111] Reference Figures 4-9 The first source-drain 131 in the first channel layer 105 and the second source-drain 130 in the second channel layer 107 are formed on the substrate 100, and the first gate structure 140 is formed across the channel stack structure. The channel stack structure includes the first channel layer 105 and the second channel layer 107 arranged on the first channel layer 105 in a spaced manner, and the first gate structure 140 surrounds and covers the first channel layer 105 and the second channel layer 107. The first gate structure 140, the first channel layer 105, and the first source-drain 131 constitute a pull-down transistor, and the first gate structure 140, the second channel layer 107, and the second source-drain 130 constitute a pull-up transistor.

[0112] Specifically, the channel stack structure is used to provide a conductive channel for the pull-up transistor and the pull-down transistor.

[0113] In this embodiment, the channel stack structure is formed on the substrate 100 of the first sub-unit region 100A and the second sub-unit region 100B.

[0114] In this embodiment, the channel stack structure includes the first channel layer 105 and the second channel layer 107 arranged on the first channel layer 105 in a spaced manner.

[0115] The stacking direction of the first channel layer 105 and the second channel layer 107 is perpendicular to the surface of the substrate 100.

[0116] In this embodiment, the material of the first channel layer 105 and the second channel layer 107 is the same as that of the substrate 100, and the material of the first channel layer 105 and the second channel layer 107 is Si.

[0117] The first gate structure 140 is used to control the opening and closing of the conductive channel when the SRAM device is working.

[0118] Specifically, the first gate structure 140 is a metal gate structure.

[0119] In this embodiment, the first gate structure 140 includes a first gate dielectric layer and a first gate electrode layer covering the first gate dielectric layer.

[0120] In this embodiment, the material of the first gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0121] Specifically, the first gate dielectric layer includes a first gate oxide layer and a first high-k gate dielectric layer covering the first gate oxide layer. The material of the first high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0122] The first gate electrode layer is used for subsequent electrical connection with external structures. The material of the first gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the first gate electrode layer can include a first work function layer and a first electrode layer covering the first work function layer, or the first gate electrode layer can also only include the first work function layer.

[0123] In this embodiment, the first gate structure 140 surrounds and covers the first channel layer 105 and the second channel layer 107.

[0124] Specifically, the first gate structure 140 surrounds and covers the top and sidewall of the first channel layer 105, and the second gate structure surrounds and covers the top, sidewall, and bottom of the second channel layer 107.

[0125] The first source / drain electrode 131 is used as the source and drain of the pull-down transistor.

[0126] Specifically, since the pull-down transistor is an N-type transistor, the doping type of the first source / drain electrode 131 is N-type.

[0127] The second source / drain electrode 130 is used as the source and drain of the pull-up transistor.

[0128] Specifically, since the pull-up transistor is a P-type transistor, the doping type of the second source / drain electrode 130 is P-type.

[0129] It should be noted that in the SRAM device, the pull-up transistor and the pull-down transistor are used to store data.

[0130] In combination with reference Figures 4-9 The steps of forming the pull-down transistor and the pull-up transistor are described in detail.

[0131] In combination with reference Figures 4-5 The channel stack 108 is formed on the top of the substrate 100 in the first subcell region 100A and the second subcell region 100B, and the channel stack 108 includes the first channel layer 105, the sacrificial layer 106 on the first channel layer 105, and the second channel layer 107 on the sacrificial layer 106.

[0132] Specifically, the channel stack 108 provides a process basis for the channel stack structure, and the sacrificial layer 106 supports the second channel layer 107, thereby providing a process basis for subsequent implementation of the spaced suspended setting of the first channel layer 105 and the second channel layer 107 to occupy a space position for the formation of the first gate structure 140, and the first channel layer 105 and the second channel layer 107 are used to provide a conductive channel of an SRAM device.

[0133] In this embodiment, the step of forming the channel stack 108 includes: forming a channel stack material layer 104 on the top of the substrate 100, the channel stack material layer 104 including a first channel material layer 101, a sacrificial material layer 102 located on the first channel material layer 101, and a second channel material layer 103 located on the sacrificial material layer 102; forming a patterned mask layer above the channel stack material layer 104; and performing a patterned treatment on the channel stack material layer 104 with the mask layer as a mask to form the channel stack 108 on the top of the substrate 100 in the first subcell region 100A and the second subcell region 100B.

[0134] It should be noted that the channel stack 108 on the top of the substrate 100 in the first subcell region 100A and the second subcell region 100B protrudes from the top of the substrate 100.

[0135] In this embodiment, the material of the sacrificial layer 106 is SiGe, and the etching selectivity of SiGe and Si is relatively high in the subsequent process of removing the sacrificial layer 106. Therefore, by setting the material of the sacrificial layer 106 as SiGe, the influence of the process of removing the sacrificial layer 106 on the first channel layer 105 and the second channel layer 107 can be effectively reduced, thereby improving the quality of the channel stack structure, and further improving the device performance.

[0136] Reference Figure 6 The pseudo gate structure 110 is formed on the substrate 100 to span the channel stack 108, and the pseudo gate structure 110 covers the top and sidewall of the channel stack 108.

[0137] The pseudo gate structure 110 occupies a space position for the subsequent formation of the first gate structure 140.

[0138] In this embodiment, the pseudo gate structure 110 includes a pseudo gate layer. The material of the pseudo gate layer includes polysilicon.

[0139] It should be noted that after the pseudo gate structure 110 is formed, the channel stack 108 on both sides of the pseudo gate structure 110 is also removed.

[0140] Reference Figure 7The partial sacrificial layer 106 is laterally etched to form a trench (not shown) in a direction parallel to the substrate 100 and perpendicular to the extension direction of the dummy gate structure 110, and the inner wall layer 120 is formed in the trench (not shown).

[0141] The trench (not shown) is surrounded by the adjacent first channel layer 105 and second channel layer 107 and the remaining sacrificial layer 106.

[0142] In this embodiment, the process of laterally etching the partial sacrificial layer 106 includes a wet etching process.

[0143] Specifically, the inner wall layer 120 is located between the first source / drain 131 and the first gate structure 140 and between the second source / drain 130 and the first gate structure 140, and can isolate the first source / drain 131 and the first gate structure 140 and the second source / drain 130 and the first gate structure 140, thereby reducing the parasitic capacitance between the first source / drain 131 and the first gate structure 140 and between the second source / drain 130 and the first gate structure 140.

[0144] In this embodiment, the material of the inner wall layer 120 includes one or more of silicon nitride, silicon oxide and silicon oxynitride.

[0145] Specifically, the silicon nitride, silicon oxide and silicon oxynitride are all dielectric materials, and can electrically isolate the first source / drain 131 and the first gate structure 140 and the second source / drain 130 and the first gate structure 140.

[0146] Reference Figure 8 The first source / drain 131 is formed in the first channel layer 105 on both sides of the dummy gate structure 110, and the second source / drain 130 is formed in the second channel layer 107 on both sides of the dummy gate structure 110.

[0147] The first source / drain 131 is used as the source and drain of the pull-down transistor.

[0148] Specifically, since the pull-down transistor is an N-type transistor, the first source / drain 131 is N-type doped.

[0149] The second source / drain 130 is used as the source and drain of the pull-up transistor.

[0150] Specifically, since the pull-up transistor is a P-type transistor, the second source / drain 130 is P-type doped.

[0151] As an example, in the step of forming the second source-drain electrode 130, one of the second source-drain electrodes 130 in the first sub-unit region 100A is in contact with the first source-drain electrode 131 located thereunder, and the other second source-drain electrode 130 is separated from the first source-drain electrode 131 located thereunder.

[0152] It should be noted that one of the second source-drain electrodes 130 in the first sub-unit region 100A is in contact with the first source-drain electrode 131 located thereunder, so that the drain region in the pull-up transistor is electrically connected to the drain region in the pull-down transistor. Meanwhile, one of the second source-drain electrodes 130 in the first sub-unit region 100A is in contact with the first source-drain electrode 131 located thereunder, which also reduces the process difficulty of forming the second source-drain electrode 130 and the first source-drain electrode 131, and eliminates the process step of additionally setting an interconnection structure connected to the second source-drain electrode 130 and the first source-drain electrode 131, so as to electrically connect the first source-drain electrode 131 to the second source-drain electrode 130, thereby reducing the process cost and the process steps.

[0153] It should be further noted that the other second source-drain electrode 130 in the first sub-unit region 100A is separated from the first source-drain electrode 131 located thereunder, so that the other second source-drain electrode 130 in the first sub-unit region 100A can be electrically connected to the first source-drain plug, and the first source-drain electrode 131 located thereunder can be electrically connected to the second source-drain plug, thereby realizing that in the first sub-unit region 100A, the source region of the pull-up transistor can be connected to the power supply voltage through the second source-drain plug, and the source region of the pull-down transistor can be connected to the power supply voltage through the first source-drain plug.

[0154] As an example, one of the second source-drain electrodes 130 in the second sub-unit region 100B is in contact with the first source-drain electrode 131 located thereunder, and the other second source-drain electrode 130 is separated from the first source-drain electrode 131 located thereunder.

[0155] It should be noted that one of the second source-drain electrodes 130 in the second sub-unit region 100B is in contact with the first source-drain electrode 131 located thereunder, so that the drain region in the pull-up transistor is electrically connected to the drain region in the pull-down transistor. Meanwhile, one of the second source-drain electrodes 130 in the second sub-unit region 100B is in contact with the first source-drain electrode 131 located thereunder, which also reduces the process difficulty of forming the second source-drain electrode 130 and the first source-drain electrode 131, and eliminates the process step of additionally setting an interconnection structure connected to the second source-drain electrode 130 and the first source-drain electrode 131, so as to electrically connect the first source-drain electrode 131 to the second source-drain electrode 130, thereby reducing the process cost and the process steps.

[0156] It should be further noted that the other second source-drain electrode 130 in the second sub-unit region 100B is separated from the first source-drain electrode 131 located thereunder, so that the other second source-drain electrode 130 in the second sub-unit region 100B can be electrically connected with the first source-drain plug, and the first source-drain electrode 131 located thereunder can be electrically connected with the second source-drain plug, thereby realizing that in the second sub-unit region 100B, the source region of the pull-up transistor can be connected to the power supply voltage through the second source-drain plug, and the source region of the pull-down transistor can be connected to the power supply voltage through the first source-drain plug.

[0157] As an example, the second source-drain electrode 130 away from the junction of the first sub-unit region 100A and the second sub-unit region 100B is in contact with the first source-drain electrode 131 located thereunder, so that the first source-drain electrode 131 and the second source-drain electrode 130 in the first sub-unit region 100A, and the first source-drain electrode 131 and the second source-drain electrode 130 in the second sub-unit region 100B are all arranged to be separated from and opposite to each other, which means that the subsequent interconnection structure (i.e., the second source-drain plug and the third source-drain plug formed subsequently) arranged in a spaced manner can be formed at the junction of the first sub-unit region 100A and the second sub-unit region 100B, so that the interconnection structure can provide the power supply voltage to the pull-up transistor and the pull-down transistor in the first sub-unit region 100A and the pull-up transistor and the pull-down transistor in the second sub-unit region 100B at the same time. Meanwhile, the first source-drain electrode 131 and the second source-drain electrode 130 in the first sub-unit region 100A, and the first source-drain electrode 131 and the second source-drain electrode 130 in the second sub-unit region 100B are all arranged to be opposite to each other, which can make the distance between the first source-drain electrode 131 and the second source-drain electrode 130 in the first sub-unit region 100A and the first source-drain electrode 131 and the second source-drain electrode 130 in the second sub-unit region 100B the shortest, and in the subsequent step of forming the second source-drain plug and the third source-drain plug, the size of the second source-drain plug and the third source-drain plug can also be the smallest, thereby reducing the process cost.

[0158] In the embodiment, the step of forming the first source-drain electrode 131 and the second source-drain electrode 130 includes: forming a first dielectric layer covering the first channel layer and the second channel layer on one side of the first gate structure; forming the first source-drain electrode in the first channel layer on the other side of the first gate structure; forming the second source-drain electrode in the second channel layer on the other side of the first gate structure, and the first source-drain electrode is in contact with the second source-drain electrode; removing the first dielectric layer; forming the first source-drain electrode in the first channel layer in the region where the first dielectric layer is removed; forming a second dielectric layer covering the first source-drain electrode in the region where the first dielectric layer is removed, and the second dielectric layer exposes the second channel layer; forming the second source-drain electrode in the second channel layer in the region where the first dielectric layer is removed; removing the second dielectric layer.

[0159] As an example, the process of forming the first source-drain electrode 131 includes an epitaxial process.

[0160] Specifically, the epitaxial process is a common growth process for forming a source-drain electrode, which has the characteristics of low process cost and high film growth quality.

[0161] In this embodiment, the process of forming the second source-drain electrode 130 includes an epitaxial growth process.

[0162] Referring to Figure 9 , the dummy gate structure 110 and the sacrificial layer 106 are removed, and the first gate structure 140 is formed at the positions of the dummy gate structure 110 and the sacrificial layer 106. After the sacrificial layer 106 is removed, the first channel layer 105 and the second channel layer 107 arranged on the first channel layer 105 constitute a channel stack structure.

[0163] Specifically, the dummy gate structure 110 and the sacrificial layer 106 are removed to provide a process basis for forming the first gate structure 140.

[0164] In this embodiment, the process of removing the dummy gate structure 110 and the sacrificial layer 106 includes a wet etching process.

[0165] It should be noted that, in order to facilitate Figure 9 The subsequent three-dimensional schematic view clearly shows the structure of each component, so the Figure 9 The first gate structure 140 in the three-dimensional view only shows the first channel layer 105 and the second channel layer 107, but in fact, the overall size of the first gate structure 140 is consistent with the overall size of the dummy gate structure 110 in the three-dimensional view. Figure 8

[0166] Referring to Figures 10-18 , wherein Figure 10 is a three-dimensional view, Figures 11-18 is a Figure 10 ​The cross-sectional view along the AA direction, after forming the pull-up transistor and the pull-down transistor, before forming the gate plug subsequently, further comprises: forming a first source-drain plug 150 at the top of the second source-drain 130 away from the junction of the first sub-cell region 100A and the second sub-cell region 100B, the first source-drain plug 150 being electrically connected with the second source-drain 130; forming a second source-drain plug 152 at the end of the first source-drain 131 at the junction of the first sub-cell region 100A and the second sub-cell region 100B, the second source-drain plug 152 being electrically connected with the first source-drain 131, and the second source-drain plug 152 being shared by the adjacent first sub-cell region 100A and the second sub-cell region 100B; forming a third source-drain plug 151 at the end of the second source-drain 130 at the junction of the first sub-cell region 100A and the second sub-cell region 100B, the third source-drain plug 151 being electrically connected with the second source-drain 130, and the third source-drain plug 151 being shared by the adjacent first sub-cell region 100A and the second sub-cell region 100B.

[0167] Specifically, the first source-drain plug 150 is electrically connected with the second source-drain 130, and since the first source-drain 131 of the pull-down transistor is in contact with the second source-drain 130 of the pull-up transistor, the first source-drain plug 150 can lead out the electrical property of the first source-drain 131 of the pull-down transistor and the second source-drain 130 of the pull-up transistor, which means that the transmission gate transistor connected with the first source-drain plug 150 can control the pull-up transistor and the pull-down transistor simultaneously through the first source-drain plug 150.

[0168] The second source-drain plug 152 is electrically connected with the first source-drain 131, and the third source-drain plug 151 is electrically connected with the second source-drain 130, so that the source regions of the pull-up transistors are all connected to the power supply voltage, and the source regions of the pull-down transistors are all connected to the power supply voltage.

[0169] In the embodiment, the second source-drain plug 152 is used to access VSS, and the third source-drain plug 151 is used to access VDD.

[0170] Specifically, VDD represents the working positive voltage accessed, and VSS represents the working negative voltage accessed.

[0171] As an example, the second source-drain plug 152 is shared by the adjacent first sub-cell region 100A and the second sub-cell region 100B, so that the second source-drain plug 152 can simultaneously provide the power supply voltage for the pull-down transistors in the first sub-cell region 100A and the second sub-cell region 100B, and the second source-drain plug 152 is shared by the first sub-cell region 100A and the second sub-cell region 100B, which is conducive to making the space area occupied by the memory smaller, and further conducive to making the overall size of the semiconductor structure further smaller.

[0172] As an example, the first sub-unit region 100A and the second sub-unit region 100B adjacent to each other share the third source-drain plug 151, so that the third source-drain plug 151 can simultaneously provide a power supply voltage for the pull-up transistor in the first sub-unit region 100A and the second sub-unit region 100B, and meanwhile, the first sub-unit region 100A and the second sub-unit region 100B share the third source-drain plug 151, which is conducive to making the space area occupied by the memory smaller, and further conducive to making the overall size of the semiconductor structure further reduced.

[0173] In the embodiment, the materials of the first source-drain plug 150, the second source-drain plug 152 and the third source-drain plug 151 are tungsten. In other embodiments, the materials of the first source-drain plug 150, the second source-drain plug 152 and the third source-drain plug 151 can also be cobalt or ruthenium.

[0174] In the embodiment, the steps of forming the first source-drain plug 150, the second source-drain plug 152 and the third source-drain plug 151 include: forming a first auxiliary layer 170 on the top of the substrate 100, the first auxiliary layer 170 covering the sidewalls and the top of the first source-drain 131 and the second source-drain 130; forming a first opening 160 exposing the end of the first source-drain 131 and the end of the second source-drain 130 in the first auxiliary layer 170 at the junction of the first sub-unit region 100A and the second sub-unit region 100B adjacent to each other; forming the second source-drain plug 152 covering the end of the first source-drain 131 in the first opening 160; forming a second auxiliary layer 171 covering the top of the second source-drain plug 152 in the first opening 160, the second auxiliary layer 171 exposing the end of the second source-drain 130; forming the third source-drain plug 151 in the remaining space of the first opening 160; after forming the third source-drain plug 151, forming a second opening 180 exposing the second source-drain 130 in the first auxiliary layer 170 away from the top of the second source-drain 130 at the junction of the first sub-unit region 100A and the second sub-unit region 100B; forming the first source-drain plug 150 in the second opening 180.

[0175] In the embodiment, the materials of the first auxiliary layer 170 and the second auxiliary layer 171 are organic materials, which is conducive to removing the first auxiliary layer 170 and the second auxiliary layer 171 by etching process subsequently, and reduces the process difficulty of residual first auxiliary layer 170 and second auxiliary layer 171.

[0176] As an example, the material of the first auxiliary layer 170 is BARC.

[0177] It should be noted that after forming the first source-drain plug 150, the second source-drain plug 152 and the third source-drain plug 151, it further includes: removing the first auxiliary layer 170 and the second auxiliary layer 171.

[0178] The first auxiliary layer 170 and the second auxiliary layer 171 are removed to provide a space position for a dielectric layer covering the pull-down transistor and the pull-up transistor.

[0179] In this embodiment, the process of removing the first auxiliary layer 170 and the second auxiliary layer 171 includes a wet etching process.

[0180] Reference is made to Figure 19 A gate plug 190 is formed on top of the first gate structure 140, and the gate plug 190 is electrically connected with the first gate structure 140.

[0181] It is to be noted that the gate plug 190 is used to lead out the electrical property of the first gate structure 140, so as to realize the control of the conductive channel in the pull-up transistor and the pull-down transistor.

[0182] It is to be further noted that the gate plug 190 also provides a process basis for forming a recess, which is beneficial to the subsequent formation of a second gate structure in the recess, and the gate plug 190 surrounding the second gate structure is used as a third source / drain electrode.

[0183] In this embodiment, the material of the gate plug 190 is tungsten. In other embodiments, the material of the gate plug 190 can also be cobalt or ruthenium.

[0184] Reference is made to Figure 20 A dielectric layer 129 covering the pull-down transistor and the pull-up transistor and the gate plug 190 is formed.

[0185] Specifically, the dielectric layer 129 provides a process basis for the subsequent formation of a transmission gate transistor, a first interconnection via structure, a second interconnection via structure, a first interconnection layer and a second interconnection layer, and at the same time, the dielectric layer 129 is also used to electrically isolate the transmission gate transistor, the first interconnection via structure, the second interconnection via structure, the first interconnection layer and the second interconnection layer formed subsequently.

[0186] In this embodiment, the process of forming the dielectric layer 129 includes a chemical vapor deposition process or an atomic layer deposition process.

[0187] In this embodiment, in the process of forming the dielectric layer 129, the dielectric layer 129 covers the first source / drain plug 150, the second source / drain plug 152 and the third source / drain plug 151.

[0188] Specifically, the dielectric layer 129 covers the first source / drain plug 150, the second source / drain plug 152 and the third source / drain plug 151, and is used to electrically isolate the first source / drain plug 150, the second source / drain plug 152 and the third source / drain plug 151, and plays an electrical isolation role for the second source / drain plug 152 and the third source / drain plug 151.

[0189] In this embodiment, the material of the dielectric layer 129 includes one or more of silicon oxide, silicon carbide, and silicon oxynitride.

[0190] Referring to Figure 21 A metal layer 193 is formed on top of the dielectric layer 129.

[0191] It should be noted that the metal layer 193 is used as the fourth source / drain after the second gate structure is subsequently formed.

[0192] It should also be noted that the metal layer 193 is also used to interconnect the gate plug 190 and the CFET subsequently formed.

[0193] Meanwhile, the metal layer 193 is also used as a bit line of the SRAM device, which is used for reading and writing data in the SRAM device.

[0194] In this embodiment, the material of the metal layer 193 includes one or more of copper, aluminum, silver, and gold.

[0195] As an example, the metal layer 193 covers the dielectric layer 129 above the first gate structure 140, exposing the dielectric layer 129 on the side of the first gate structure 140, which facilitates the subsequent formation of the first interconnection via structure, the second interconnection via structure, the first interconnection layer, and the second interconnection layer in the dielectric layer 129, reducing the probability of short-circuiting between the metal layer 193 and the first interconnection via structure, the second interconnection via structure, the first interconnection layer, and the second interconnection layer.

[0196] Referring to Figure 22 A groove 194 is formed on top of the first gate structure 140, penetrating through the metal layer 193 and the dielectric layer 129, and part of the gate plug 190.

[0197] Specifically, the groove 194 provides a spatial position for the subsequently formed transfer gate transistor, which is disposed in the dielectric layer 129, i.e., the transfer gate transistor utilizes part of the spatial position of the dielectric layer 129, which can reduce the overall height of the memory and the space area occupied by the memory, thereby facilitating the further reduction of the overall size of the semiconductor structure (for example, compared with the memory based on the fin field effect transistor, the memory based on the CFET can save about 40% of the chip area without changing the pitch size, and the semiconductor structure of the embodiment of the present application can save about 20% of the area on this basis), thereby improving the integration of the semiconductor structure.

[0198] In this embodiment, the process of forming the groove 194 includes a dry etching process.

[0199] It should be noted that the dry etching process is an anisotropic dry etching process. The anisotropic dry etching process has good profile control, which is beneficial to improve the profile quality of the groove 194, facilitate the deposition of the third channel layer on the sidewall and bottom of the groove 194, and reduce the risk of voids in the third channel layer. In addition, the use of the anisotropic dry etching process is beneficial to achieve a high etching selectivity, thereby reducing the probability of mis-etching other film layers.

[0200] It should also be noted that the lateral direction is perpendicular to the sidewall of the groove 194. The lateral size of the groove 194 should not be too large or too small. If the lateral size of the groove 194 is too large, the lateral size of the transfer gate transistor formed in the groove 194 will also be too large. In the case where the lateral size of the gate plug 190 is constant, the gate plug 190 around the transfer gate transistor will be too small, which means that the third source / drain of the transfer gate transistor will be too small, thereby affecting the electrical performance of the transfer gate transistor. If the lateral size of the groove 194 is too small, the aspect ratio of the groove 194 will be too large, which increases the process difficulty of forming the third channel layer and the second gate structure in the groove 194, and increases the risk of voids in the transfer gate transistor. Therefore, in this embodiment, the lateral size of the groove 194 is 10-50 nm in the direction perpendicular to the sidewall of the groove 194.

[0201] Specifically, the depth of the groove 194 should not be too large or too small along the normal direction of the surface of the substrate 100. If the depth of the groove 194 is too large, the probability of penetrating the gate plug 190 will increase, thereby causing the upper pull transistor electrically connected to the gate plug 190 to fail. If the depth of the groove 194 is too small, the groove 194 will not be able to penetrate part of the gate plug 190, thereby causing the gate plug 190 to not surround the transfer gate transistor, which means that the third source / drain of the transfer gate transistor will not be formed, thereby causing the transfer gate transistor to fail electrically. Therefore, in this embodiment, the depth of the groove 194 is 10-200 nm along the normal direction of the surface of the substrate 100.

[0202] Reference Figures 23-24 wherein, Figure 23 is a perspective view, Figure 24 is Figure 23 is a cross-sectional view along the BB direction, forming a third channel layer 139 covering the bottom and sidewall of the groove 194.

[0203] Specifically, the third channel layer 139 is used as a conductive channel of the transfer gate transistor formed subsequently.

[0204] In this embodiment, the material of the third channel layer 139 includes amorphous metal oxide.

[0205] The amorphous metal oxide layer has the effect of improving carrier mobility, and can improve the electrical performance of the semiconductor structure.

[0206] In this embodiment, the material of the amorphous metal oxide includes indium gallium zinc oxide, which is composed of indium oxide, gallium oxide and zinc oxide.

[0207] In this embodiment, the process of forming the third channel layer 139 includes atomic layer deposition or physical sputtering.

[0208] Taking physical sputtering as an example, the physical sputtering process is to use a high-energy ion beam to bombard the surface of the target material, so that the atoms or molecules on the surface of the target material are separated and deposited on the surface of the substrate to form a thin film. The film layer quality of the third channel layer 139 formed by adopting the physical sputtering process is high, and the process has high stability, good process compatibility, etc.

[0209] Continuing to refer to Figures 23-24 The second gate structure 195 is formed in the remaining space of the groove 194, and the gate plug 190 surrounding the second gate structure 195 is used as a third source / drain electrode (not labeled), and the metal layer 193 surrounding the second gate structure 195 is used as a fourth source / drain electrode (not labeled). The second gate structure 195, the third channel layer 139, the third source / drain electrode and the fourth source / drain electrode constitute a pass transistor.

[0210] The second gate structure 195 is used to control the opening and closing of the conductive channel of the pass transistor when the pass transistor works.

[0211] Specifically, the second gate structure 195 is a metal gate structure.

[0212] In this embodiment, the second gate structure 195 includes a second gate dielectric layer and a second gate electrode layer covering the second gate dielectric layer.

[0213] In this embodiment, the material of the second gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2 and La2O3.

[0214] Specifically, the second gate dielectric layer includes a second gate oxide layer and a second high-k gate dielectric layer conformally covering the second gate oxide layer. The material of the second high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide.

[0215] The second gate electrode layer is used for subsequent electrical connection with an external structure. The material of the second gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. Specifically, the second gate electrode layer can include a second work function layer and a second electrode layer covering the second work function layer, or the second gate electrode layer can also only include the second work function layer.

[0216] The semiconductor structure of the embodiment adopts a pull-down transistor and a pull-up transistor based on a CFET (complementary FET) structure and a transmission gate transistor based on a CAA (channel all around) structure to achieve a stacked arrangement of the pull-down transistor, the pull-up transistor, and the transmission gate transistor.

[0217] Reference Figure 25 After the formation of the transmission gate transistor, the method for forming the semiconductor structure further includes: forming a first via interconnection structure 197 in the dielectric layer 129, the first via interconnection structure 197 being located on top of the first source-drain plug 150 and electrically connected with the first source-drain plug 150; and forming a second via interconnection structure 198 in the dielectric layer 129, the second via interconnection structure 198 being located on top of the gate plug 190 and away from the transmission gate transistor and electrically connected with the gate plug 190.

[0218] The first via interconnection structure 197 is electrically connected with the first source-drain plug 150, thereby enabling the first source-drain plug 150 to lead out the electrical properties of the pull-up transistor and the pull-down transistor through the first via interconnection structure 197.

[0219] In the embodiment, the material of the first via interconnection structure 197 is copper.

[0220] The second via interconnection structure 198 is electrically connected with the gate plug 190, thereby enabling the gate plug 190 to lead out the electrical properties of the first gate structure 140 of the pull-up transistor and the pull-down transistor through the second via structure, thereby achieving the effect of controlling the opening and closing of the conductive channel of the pull-up transistor and the pull-down transistor.

[0221] In the embodiment, the material of the second via interconnection structure 198 is copper.

[0222] Continuing to refer to Figure 25 The method for forming the semiconductor structure further includes: forming a first interconnection layer 179 in the dielectric layer 129, the first interconnection layer 179 connecting the first via interconnection structure 197 of the first sub-unit region 100A and the second via interconnection structure 198 of the second sub-unit region 100B; and forming a second interconnection layer 199 in the dielectric layer 129, the second interconnection layer 199 connecting the second via interconnection structure 198 of the first sub-unit region 100A and the first via interconnection structure 197 of the second sub-unit region 100B.

[0223] The first interconnection layer 179 is electrically connected with the first via interconnection structure 197 of the first sub-unit area 100A and the second via interconnection structure 198 of the second sub-unit area 100B, so that the transfer gate transistor in the second sub-unit area 100B can be electrically connected with the pull-up transistor and the pull-down transistor in the first sub-unit area 100A, and then the transmission of the stored data in the pull-up transistor and the pull-down transistor can be controlled.

[0224] In the embodiment, the material of the first interconnection layer 179 is copper.

[0225] The second interconnection layer 199 is electrically connected with the second via interconnection structure 198 of the first sub-unit area 100A and the first via interconnection structure 197 of the second sub-unit area 100B, so that the transfer gate transistor in the first sub-unit area 100A can be electrically connected with the pull-up transistor and the pull-down transistor in the second sub-unit area 100B, and then the transmission of the stored data in the pull-up transistor and the pull-down transistor can be controlled.

[0226] In the embodiment, the material of the second interconnection layer 199 is copper.

[0227] In the embodiment, the steps of forming the first interconnection layer 179 and the second interconnection layer 199 include: forming a third opening in the dielectric layer 129 above the first via interconnection structure 197 of the first sub-unit area 100A and the second via interconnection structure 198 of the second sub-unit area 100B, the third opening exposing the first via interconnection structure 197 of the first sub-unit area 100A and the second via interconnection structure 198 of the second sub-unit area 100B; forming a fourth opening in the dielectric layer 129 above the first via interconnection structure 197 of the second sub-unit area 100B and the second via interconnection structure 198 of the first sub-unit area 100A, the fourth opening exposing the first via interconnection structure 197 of the second sub-unit area 100B and the second via interconnection structure 198 of the first sub-unit area 100A; forming the first interconnection layer 179 in the third opening; forming the second interconnection layer 199 in the fourth opening.

[0228] As an example, the first interconnection layer 179 and the second interconnection layer 199 are formed in the same step.

[0229] In other embodiments, the first interconnection layer 179 and the second interconnection layer 199 can also be formed in different steps.

[0230] Although the present application has been disclosed as above, it is not limited to the above. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, and the protection scope of the present application should be defined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a substrate; a channel stack structure on the substrate, and the channel stack structure comprises a first channel layer and a second channel layer spaced apart on the first channel layer; a first gate structure across the channel stack structure and surrounding the first channel layer and the second channel layer; a first source / drain in the first channel layer on both sides of the first gate structure; a second source / drain in the second channel layer on both sides of the first gate structure, and the first gate structure, the first channel layer and the first source / drain form a pull-down transistor, and the first gate structure, the second channel layer and the second source / drain form a pull-up transistor; a gate plug on top of the first gate structure, and the gate plug is electrically connected with the first gate structure; a dielectric layer on top of the substrate and covering the pull-down transistor, the pull-up transistor and the gate plug; a metal layer on top of the dielectric layer; a recess through the metal layer, the dielectric layer and part of the thickness of the gate plug; a third channel layer covering the bottom and sidewall of the recess; a second gate structure in the remaining space of the recess, and the gate plug surrounding the second gate structure is used as a third source / drain, and the metal layer surrounding the second gate structure is used as a fourth source / drain, and the second gate structure, the third channel layer, the third source / drain and the fourth source / drain form a pass gate transistor.

2. The semiconductor structure of claim 1, wherein, The substrate comprises adjacent first and second subcell regions, and the channel stack structure is on the substrate of the first and second subcell regions respectively; On one side of the gate structure, the second source / drain is in contact with the first source / drain below it; On the other side of the gate structure, the second source / drain is separated from the first source / drain below it.

3. The semiconductor structure of claim 2, wherein, The second source / drain away from the junction of the first and second subcell regions is in contact with the first source / drain below it.

4. The semiconductor structure of claim 2 or 3, wherein the first and second semiconductor layers are formed of a same material. The second source / drain in contact with the first source / drain is an integral structure.

5. The semiconductor structure of claim 2 or 3, wherein the first and second semiconductor layers are formed of a same material. The semiconductor structure further comprises a first source / drain plug on top of the second source / drain away from the junction of the first and second subcell regions, and the first source / drain plug is electrically connected with the second source / drain; The dielectric layer covers the first source / drain plug.

6. The semiconductor structure of claim 5, wherein, The semiconductor structure further comprises a first via interconnect structure on top of the first source / drain plug, and the first via interconnect structure is electrically connected with the first source / drain plug; a second via interconnect structure on top of the gate plug and away from the pass gate transistor; a first interconnect layer connecting the first via interconnect structure of the first subcell region and the second via interconnect structure of the second subcell region; a second interconnect layer connecting the second via interconnect structure of the first subcell region and the first via interconnect structure of the second subcell region.

7. The semiconductor structure of claim 2, wherein, The semiconductor structure further comprises a second source / drain plug at the junction of the first and second subcell regions and connected with the end of the first source / drain, and the first and second subcell regions share the A second source-drain plug; A third source-drain plug located at the junction of the first sub-cell region and the second sub-cell region, and connected to the end of the second source-drain electrode, and shared by the first sub-cell region and the second sub-cell region adjacent to the third source-drain plug; The dielectric layer also covers the second source-drain plug and the third source-drain plug.

8. The semiconductor structure of claim 1, wherein, The material of the metal layer includes one or more of copper, aluminum, silver, and gold.

9. The semiconductor structure of claim 1, wherein, The material of the third channel layer includes amorphous metal oxide.

10. The semiconductor structure of claim 1, wherein, The lateral dimension of the recess is 10-50 nm in a direction perpendicular to the sidewall of the recess.

11. The semiconductor structure of claim 1, wherein, The depth of the recess is 10-200 nm along the normal direction of the surface of the substrate.

12. A method of forming a semiconductor structure, comprising: Comprising: Providing a substrate; Forming a channel stack structure, a first gate structure across the channel stack structure, a first source-drain electrode in a first channel layer on both sides of the first gate structure, and a second source-drain electrode in a second channel layer on both sides of the first gate structure on the substrate, the channel stack structure comprising a first channel layer and a second channel layer arranged on the first channel layer, and the first gate structure surrounding and covering the first channel layer and the second channel layer, wherein the first gate structure, the first channel layer, and the first source-drain electrode constitute a pull-down transistor, and the first gate structure, the second channel layer, and the second source-drain electrode constitute a pull-up transistor; Forming a gate plug on the top of the first gate structure, and the gate plug is electrically connected to the first gate structure; Forming a dielectric layer covering the pull-down transistor and the pull-up transistor, and the gate plug; Forming a metal layer on the top of the dielectric layer; Forming a recess through the metal layer and the dielectric layer, and part of the gate plug on the top of the first gate structure; Forming a third channel layer covering the bottom and sidewall of the recess; Forming a second gate structure in the remaining space of the recess, and a gate plug surrounding the second gate structure is used as a third source-drain electrode, and a metal layer surrounding the second gate structure is used as a fourth source-drain electrode, and the second gate structure, the third channel layer, the third source-drain electrode, and the fourth source-drain electrode constitute a transmission gate transistor.

13. The method of forming a semiconductor structure of claim 12, wherein, The substrate comprises a first sub-cell region and a second sub-cell region adjacent to each other; In the step of forming the channel stack structure, the channel stack structure is formed on the substrate of the first sub-cell region and the second sub-cell region; The step of forming the pull-down transistor and the pull-up transistor comprises: forming a channel stack on the top of the substrate of the first sub-cell region and the second sub-cell region, the channel stack comprising a first channel layer, a sacrificial layer on the first channel layer, and a second channel layer on the sacrificial layer; Forming a dummy gate structure across the channel stack on the substrate, the dummy gate structure covering the top and sidewall of the channel stack; Forming a first source-drain doping layer in the first channel layer on both sides of the dummy gate structure, and forming a second source-drain doping layer in the second channel layer on both sides of the dummy gate structure; The dummy gate structure and the sacrificial layer are removed, and a first gate structure is formed at the position of the dummy gate structure and the sacrificial layer. After the sacrificial layer is removed, the first channel layer and the second channel layer arranged on the first channel layer constitute the channel stack structure.

14. The method of forming a semiconductor structure of claim 13, wherein, In the step of forming the second source-drain electrode, one of the second source-drain electrodes in the first sub-unit region is in contact with the first source-drain electrode located thereunder, and the other second source-drain electrode is separated from the first source-drain electrode located thereunder. One of the second source-drain electrodes in the second sub-unit region is in contact with the first source-drain electrode located thereunder, and the other second source-drain electrode is separated from the first source-drain electrode located thereunder.

15. The method of forming a semiconductor structure of claim 14, wherein, The second source-drain electrode away from the junction of the first sub-unit region and the second sub-unit region is in contact with the first source-drain electrode located thereunder.

16. The method of forming a semiconductor structure of claim 14, wherein, The step of forming the first source-drain electrode and the second source-drain electrode includes: forming a first dielectric layer covering the first channel layer and the second channel layer on one side of the first gate structure; forming a first source-drain electrode in the first channel layer on the other side of the first gate structure; forming a second source-drain electrode in the second channel layer on the other side of the first gate structure, and the first source-drain electrode is in contact with the second source-drain electrode; removing the first dielectric layer; forming a first source-drain electrode in the first channel layer in the region where the first dielectric layer is removed; forming a second dielectric layer covering the first source-drain electrode in the region where the first dielectric layer is removed, and the second dielectric layer exposes the second channel layer; forming a second source-drain electrode in the second channel layer in the region where the first dielectric layer is removed; removing the second dielectric layer.

17. The method of forming a semiconductor structure of claim 14, wherein, The process of forming the first source-drain electrode includes an epitaxial growth process; and the process of forming the second source-drain electrode includes an epitaxial growth process.

18. The method of forming a semiconductor structure of claim 15, wherein, After the pull-up transistor and the pull-down transistor are formed, before the gate plug is formed, the method further includes: forming a first source-drain plug on the top of the second source-drain electrode away from the junction of the first sub-unit region and the second sub-unit region, and the first source-drain plug is in electrical connection with the second source-drain electrode; forming a second source-drain plug on the end of the first source-drain electrode at the junction of the first sub-unit region and the second sub-unit region, and the second source-drain plug is in electrical connection with the first source-drain electrode, and the second source-drain plug is shared by the first sub-unit region and the second sub-unit region adjacent to each other; forming a third source-drain plug on the end of the second source-drain electrode at the junction of the first sub-unit region and the second sub-unit region, and the third source-drain plug is in electrical connection with the second source-drain electrode, and the third source-drain plug is shared by the first sub-unit region and the second sub-unit region adjacent to each other; In the process of forming the dielectric layer, the dielectric layer covers the first source-drain plug, the second source-drain plug, and the third source-drain plug.

19. The method of forming a semiconductor structure of claim 18, wherein, The step of forming the first source-drain plug, the second source-drain plug and the third source-drain plug comprises: forming a first auxiliary layer on top of the substrate, the first auxiliary layer covering sidewalls and top of the first source-drain and the second source-drain; forming a first opening in the first auxiliary layer adjacent to the junction of the first sub-cell region and the second sub-cell region, the first opening exposing end portions of the first source-drain and the second source-drain; forming a second source-drain plug in the first opening, the second source-drain plug covering the end portion of the first source-drain; forming a second auxiliary layer in the first opening, the second auxiliary layer covering top of the second source-drain plug, the second auxiliary layer exposing the end portion of the second source-drain; forming a third source-drain plug in the remaining space of the first opening; removing the first auxiliary layer and the second auxiliary layer.

20. The method of forming a semiconductor structure of claim 18, wherein, After forming the pass gate transistor, the method further comprises: forming a first via interconnect structure in the dielectric layer, the first via interconnect structure being located on top of the first source-drain plug and electrically connected to the first source-drain plug; forming a second via interconnect structure in the dielectric layer, the second via interconnect structure being located on top of the gate plug and away from the pass gate transistor, the second via interconnect structure being electrically connected to the gate plug; forming a first interconnect layer in the dielectric layer, the first interconnect layer connecting the first via interconnect structure of the first sub-cell region and the second via interconnect structure of the second sub-cell region; forming a second interconnect layer in the dielectric layer, the second interconnect layer connecting the second via interconnect structure of the first sub-cell region and the first via interconnect structure of the second sub-cell region.

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