Storage array and preparation method thereof, memory and electronic equipment

Abstract

The invention provides a memory array and a preparation method thereof, a memory and electronic equipment, and relates to the technical field of semiconductors. The memory array comprises a first layer structure, a second layer structure, a first conductive structure and a second conductive structure which are stacked, the first layer structure comprises a first transistor and a second transistor, and the second layer structure comprises a third transistor and a fourth transistor. The first conductive structure is located between the control electrode of the third transistor and the first electrode of the fourth transistor, and the control electrode of the third transistor and the first electrode of the fourth transistor are electrically connected with the first conductive structure. The second conductive structure is located between the first electrode of the third transistor and the control electrode of the fourth transistor. The first electrode of the third transistor and the control electrode of the fourth transistor are electrically connected with the second conductive structure. The orthographic projection of the first conductive structure on the reference surface is not overlapped with the orthographic projection of the second conductive structure on the reference surface. The memory array can be applied to a memory to realize reading and writing of data.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a storage array and a preparation method thereof, a memory and an electronic device. Background Art

[0002] With the development of storage technology, various types of memories, such as DRAM, SRAM and NAND flash memory, have achieved three-dimensional integration. Currently, how to reduce the area of ​​three-dimensional memory and improve its storage density has become a problem to be solved urgently in this field. Summary of the invention

[0003] The embodiments of the present application provide a storage array and a method for preparing the same, a storage device and an electronic device, aiming to reduce the area of ​​the storage device and improve its storage density.

[0004] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0005] In a first aspect, a memory array is provided, which includes a first layer structure and a second layer structure, a first conductive structure and a second conductive structure arranged in a stacked manner, the first layer structure includes a first transistor and a second transistor arranged adjacently, and the second layer structure includes a third transistor and a fourth transistor arranged adjacently. At least a portion of the first conductive structure is located between a control electrode of the third transistor and a first electrode of the fourth transistor, and the control electrode of the first transistor, the first electrode of the second transistor, the control electrode of the third transistor, and the first electrode of the fourth transistor are electrically connected to the first conductive structure, respectively. At least a portion of the second conductive structure is located between the first electrode of the third transistor and the control electrode of the fourth transistor, and the first electrode of the first transistor, the control electrode of the second transistor, the first electrode of the third transistor, and the control electrode of the fourth transistor are electrically connected to the second conductive structure, respectively. With the surface of the first layer structure away from the second layer structure as a reference plane, the orthographic projection of the first conductive structure on the reference plane does not overlap with the orthographic projection of the second conductive structure on the reference plane.

[0006] In the storage array provided in the above-mentioned embodiments of the present application, a first conductive structure and a second conductive structure are adopted, and the control electrode of the first transistor, the first electrode of the second transistor, the control electrode of the third transistor and the first electrode of the fourth transistor are electrically connected to the first conductive structure respectively, and the first electrode of the first transistor, the control electrode of the second transistor, the first electrode of the third transistor and the control electrode of the fourth transistor are electrically connected to the second conductive structure respectively, thereby realizing cross-coupling of the first transistor, the second transistor, the third transistor and the fourth transistor.

[0007] At least a portion of the first conductive structure (or the second conductive structure) is disposed between an electrode of the third transistor and an electrode of the fourth transistor. The first conductive structure (or the second conductive structure) serves as a "shared through hole" of the third transistor and the fourth transistor. One electrode of the third transistor and one electrode of the fourth transistor can be connected by using one shared through hole. The shared through hole is a transmission path for signals between the two transistors. Compared with using two through holes to connect one electrode of the third transistor and one electrode of the fourth transistor, the length of the transmission path is shortened and the resistance on the transmission path is reduced, which is beneficial to improving signal transmission efficiency.

[0008] Furthermore, the first conductive structure is located between the control electrode of the third transistor and the first electrode of the fourth transistor, the second conductive structure is located between the first electrode of the third transistor and the control electrode of the fourth transistor, and the orthographic projection of the first conductive structure on the reference plane does not overlap with the orthographic projection of the second conductive structure on the reference plane. The first conductive structure and the second conductive structure do not require winding or crossing wires, which is beneficial to reducing the area of ​​the storage array and improving the storage density of the memory using the storage array.

[0009] In some embodiments, the first transistor and the second transistor are arranged along the first direction, the first layer structure includes the first active layer and the second active layer, the first active layer includes the first electrode and the second electrode of the first transistor, and the second active layer includes the first electrode and the second electrode of the second transistor. The orthographic projection of the first conductive structure on the reference plane overlaps with the orthographic projection of the first active layer on the reference plane, and the two opposite boundaries of the first conductive structure along the second direction are located within the two opposite boundaries of the first active layer along the second direction. The orthographic projection of the second conductive structure on the reference plane overlaps with the orthographic projection of the second active layer on the reference plane, and the two opposite boundaries of the second conductive structure along the second direction are located within the two opposite boundaries of the second active layer along the second direction. Both the first direction and the second direction are parallel to the reference plane, and the first direction intersects with the second direction.

[0010] In the above embodiment, since the first conductive structure and the second conductive structure do not require winding or crossing wires, the boundary of the first conductive structure along the second direction will not exceed the boundary of the first active layer along the second direction, and the boundary of the second conductive structure along the second direction will not exceed the boundary of the second active layer along the second direction, which is beneficial to reducing the area of ​​the storage array.

[0011] In some embodiments, the third transistor and the fourth transistor are arranged along a first direction, and the first conductive structure and the second conductive structure are arranged along a second direction.

[0012] In some embodiments, the control electrode of the third transistor and the first electrode of the fourth transistor are directly in contact with the first conductive structure, respectively. The first electrode of the third transistor and the control electrode of the fourth transistor are directly in contact with the second conductive structure, respectively, which is conducive to improving signal transmission efficiency.

[0013] In some embodiments, the storage array further includes a first connection pattern and a second connection pattern, the first connection pattern is arranged between the first layer structure and the second layer structure, and the second connection pattern is arranged between the first layer structure and the second layer structure. The first conductive structure is electrically connected to the first connection pattern, and the control electrode of the first transistor and the first electrode of the second transistor are electrically connected to the first connection pattern respectively, so as to realize the connection between the control electrode of the first transistor and the first electrode of the second transistor and the first conductive structure. The second conductive structure is electrically connected to the second connection pattern, and the first electrode of the first transistor and the control electrode of the second transistor are electrically connected to the second connection pattern respectively, so as to realize the connection between the first electrode of the first transistor and the control electrode of the second transistor and the second conductive structure.

[0014] In some embodiments, the first conductive structure includes a first substructure and a second substructure connected to each other, and the second conductive structure includes a third substructure and a fourth substructure connected to each other. The first substructure is electrically connected to the control electrode and the first connection pattern of the third transistor, and the second substructure is electrically connected to the first electrode of the fourth transistor. The third substructure is electrically connected to the control electrode and the second connection pattern of the fourth transistor, and the fourth substructure is electrically connected to the first electrode of the third transistor.

[0015] Alternatively, the first substructure is electrically connected to the control electrode of the third transistor, the second substructure is electrically connected to the first electrode and the first connection pattern of the fourth transistor, the third substructure is electrically connected to the control electrode of the fourth transistor, and the fourth substructure is electrically connected to the first electrode and the second connection pattern of the third transistor.

[0016] In some embodiments, the memory array further includes a first transfer layer and a second transfer layer, the first transfer layer is arranged on a side of the first connection pattern close to the second layer structure, and the second transfer layer is arranged on a side of the second connection pattern close to the second layer structure. The first conductive structure is electrically connected to the first connection pattern through the first transfer layer, and the second conductive structure is electrically connected to the second connection pattern through the second transfer layer.

[0017] Through the above arrangement, the first transfer layer and the second transfer layer can inhibit the diffusion of metal elements in the first connection pattern and the second connection pattern, and avoid short circuit between the first connection pattern and the second connection pattern and the electrodes in the second layer structure.

[0018] Furthermore, during the process of preparing the first conductive structure and the second conductive structure, the first transfer layer and the second transfer layer can play a protective role, thereby preventing the first connection pattern and the second connection pattern from being damaged or corroded by etching.

[0019] In some embodiments, the boundary of the orthographic projection of the first transfer layer on the reference surface coincides with the boundary of the orthographic projection of the first conductive structure on the reference surface. The boundary of the orthographic projection of the second transfer layer on the reference surface coincides with the boundary of the orthographic projection of the second conductive structure on the reference surface. That is, the pattern of the transfer layer is the same as the pattern of the conductive structure, so that the same mask can be used to form the transfer layer and the conductive structure, and there is no need to add a new mask to form the transfer layer, thereby reducing the process cost.

[0020] Alternatively, the boundary of the orthographic projection of the first transfer layer on the reference surface coincides with the boundary of the orthographic projection of the first connection pattern on the reference surface. The boundary of the orthographic projection of the second transfer layer on the reference surface coincides with the boundary of the orthographic projection of the second connection pattern on the reference surface. That is, the pattern of the transfer layer is the same as the pattern of the connection pattern. In this way, the same mask can be used to form the transfer layer and the connection pattern, and there is no need to add a new mask to form the transfer layer, thereby reducing the process cost.

[0021] In some embodiments, the material of the first conductive structure includes at least one of copper, tungsten, titanium nitride, titanium, cobalt, nickel, ruthenium or tantalum, and the material of the second conductive structure includes at least one of copper, tungsten, titanium nitride, titanium, cobalt, nickel, ruthenium or tantalum.

[0022] In a second aspect, a method for preparing a memory array is provided, the method comprising: forming a first layer structure and a second layer structure arranged in a stacked manner, the first layer structure comprising a first transistor and a second transistor arranged adjacently, and the second layer structure comprising a third transistor and a fourth transistor arranged adjacently. Forming a first conductive structure and a second conductive structure, at least a portion of the first conductive structure is located between a control electrode of the third transistor and a first electrode of the fourth transistor, and the control electrode of the first transistor, the first electrode of the second transistor, the control electrode of the third transistor, and the first electrode of the fourth transistor are electrically connected to the first conductive structure respectively. At least a portion of the second conductive structure is located between the first electrode of the third transistor and the control electrode of the fourth transistor, and the first electrode of the first transistor, the control electrode of the second transistor, the first electrode of the third transistor, and the control electrode of the fourth transistor are electrically connected to the second conductive structure respectively. Taking the surface of the first layer structure away from the second layer structure as a reference plane, the orthographic projection of the first conductive structure on the reference plane does not overlap with the orthographic projection of the second conductive structure on the reference plane.

[0023] The preparation method provided by the above-mentioned embodiments of the present application first forms a first layer structure and a second layer structure stacked together, and then forms a first conductive structure and a second conductive structure. The first conductive structure (or the second conductive structure) serves as a "shared through hole" for the third transistor and the fourth transistor. One electrode of the third transistor and one electrode of the fourth transistor can be connected by one shared through hole. The shared through hole is a transmission path for signals between the two transistors. Compared with using two through holes to connect the third transistor to the fourth transistor, the length of the transmission path is shortened and the resistance on the transmission path is reduced, which is beneficial to improving the transmission efficiency of the signal.

[0024] Furthermore, the first conductive structure is located between the control electrode of the third transistor and the first electrode of the fourth transistor, the second conductive structure is located between the first electrode of the third transistor and the control electrode of the fourth transistor, and the orthographic projection of the first conductive structure on the reference plane does not overlap with the orthographic projection of the second conductive structure on the reference plane. The first conductive structure and the second conductive structure do not require winding or crossing wires, which is beneficial to reducing the area of ​​the storage array and improving the storage density of the memory using the storage array.

[0025] In some embodiments, after forming the first layer structure and before forming the second layer structure, the preparation method also includes: forming a first connection pattern and a second connection pattern on the first layer structure, the control electrode of the first transistor and the first electrode of the second transistor are electrically connected to the first connection pattern respectively, and the first electrode of the first transistor and the control electrode of the second transistor are electrically connected to the second connection pattern respectively.

[0026] In some embodiments, the first conductive structure includes a first substructure and a second substructure connected, and the second conductive structure includes a third substructure and a fourth substructure connected to form the first conductive structure and the second conductive structure, including: forming a dielectric layer, the dielectric layer covers the third transistor and the fourth transistor. Etching the dielectric layer to form a first via and a second via, the first via exposing the control electrode and the first connection pattern of the third transistor, and the second via exposing the control electrode and the second connection pattern of the fourth transistor. Forming the first substructure in the first via, and forming the third substructure in the second via. Etching the dielectric layer to form the third via and the fourth via, the third via exposing the first substructure and the first electrode of the fourth transistor, and the fourth via exposing the third substructure and the first electrode of the third transistor. Forming the second substructure in the third via, and forming the fourth substructure in the fourth via.

[0027] In the above embodiment, the first via hole and the second via hole are formed by etching the dielectric layer, the first via hole exposes the control electrode and the first connection pattern of the third transistor, and the second via hole exposes the control electrode and the second connection pattern of the fourth transistor. Therefore, it is necessary to adjust the etching process parameters so that the dielectric layer has a larger etching selectivity with the control electrode and the connection pattern of the transistor, so that the etching damage to the control electrode and the connection pattern of the transistor can be reduced during the etching of the dielectric layer.

[0028] Furthermore, since the first via does not expose the first electrode of the fourth transistor and the second via does not expose the first electrode of the third transistor M3, there is no need to consider the etching selectivity ratio between the first electrode and the second electrode of the transistor, and etching the dielectric layer will not cause etching damage to the first electrode and the second electrode of the transistor, which is beneficial to increasing the selection range of the electrode material of the transistor.

[0029] In some embodiments, the first conductive structure includes a first substructure and a second substructure connected, and the second conductive structure includes a third substructure and a fourth substructure connected to form the first conductive structure and the second conductive structure, including: forming a dielectric layer, the dielectric layer covers the third transistor and the fourth transistor. Etching the dielectric layer to form a first via and a second via, the first via exposing the first electrode and the first connection pattern of the fourth transistor, and the second via exposing the first electrode and the second connection pattern of the third transistor. Forming the second substructure in the first via, and forming the fourth substructure in the second via. Etching the dielectric layer to form a third via and a fourth via, the third via exposing the first substructure and the control electrode of the third transistor, and the fourth via exposing the third substructure and the control electrode of the fourth transistor. Forming the first substructure in the third via, and forming the third substructure in the fourth via.

[0030] In the above embodiment, the dielectric layer is first etched to form the first via hole and the second via hole, the first via hole exposes the first electrode and the first connection pattern of the fourth transistor, and the second via hole exposes the first electrode and the second connection pattern of the third transistor. Therefore, it is necessary to adjust the etching process parameters so that the dielectric layer has a larger etching selectivity with the first electrode and the second electrode and the connection pattern of the transistor, so that the etching damage to the first electrode and the second electrode and the connection pattern of the transistor can be reduced during the etching of the dielectric layer.

[0031] Furthermore, since the first via does not expose the control electrode of the third transistor and the second via does not expose the control electrode of the fourth transistor, there is no need to consider the etching selectivity ratio of the control electrode of the transistor, and etching the dielectric layer will not cause etching damage to the control electrode of the transistor, which is beneficial to increasing the selection range of the electrode material of the transistor.

[0032] In some embodiments, forming the first conductive structure and the second conductive structure includes: forming a dielectric layer, the dielectric layer covers the third transistor and the fourth transistor. Etching the dielectric layer to form a fifth via and a sixth via, the fifth via exposing the control electrode of the third transistor, the first electrode of the fourth transistor and the first connection pattern, and the sixth via exposing the first electrode of the third transistor, the control electrode of the fourth transistor and the second connection pattern. Forming the first conductive structure in the fifth via, and forming the second conductive structure in the sixth via.

[0033] In the above embodiment, the etching process parameters are adjusted to make the dielectric layer have a larger etching selectivity with the electrodes and connection patterns of the transistor. Thus, the etching damage to the electrodes and connection patterns of the transistor can be reduced during the etching of the dielectric layer.

[0034] The first connection pattern, the second connection pattern, the control electrode, the first electrode and the second electrode of the transistor can be made of materials with similar chemical properties, or the first connection pattern, the second connection pattern and the control electrode of the transistor can be made of materials with similar chemical properties, and the first electrode and the second electrode of the transistor can be made of materials with stable chemical properties. In this way, during the process of etching the dielectric layer, a wet cleaning process can be used to remove the dielectric material remaining on the connection pattern and the electrode of the transistor, and the liquid used for wet cleaning will not corrode the connection pattern and the electrode of the transistor.

[0035] In some embodiments, after forming the first connection pattern and the second connection pattern, the preparation method further includes: forming a first transfer layer and a second transfer layer, the first transfer layer is located on a side of the first connection pattern away from the first layer structure, and the second transfer layer is located on a side of the second connection pattern away from the first layer structure. After forming the first conductive structure and the second conductive structure, the first conductive structure is electrically connected to the first connection pattern through the first transfer layer, and the second conductive structure is electrically connected to the second connection pattern through the second transfer layer.

[0036] In the above embodiment, the first transfer layer and the second transfer layer can inhibit the diffusion of metal elements in the first connection pattern and the second connection pattern, and prevent the first connection pattern and the second connection pattern from short-circuiting with the electrodes in the second layer structure. In addition, during the preparation of the first conductive structure and the second conductive structure, the first transfer layer and the second transfer layer can play a protective role, and prevent the first connection pattern and the second connection pattern from being etched, damaged or corroded.

[0037] In some embodiments, the same mask is used to form the first connection pattern and the first transfer layer, and the same mask is used to form the second connection pattern and the second transfer layer, without adding a new mask, which can reduce process costs.

[0038] Alternatively, the same mask is used to form the first transfer layer and the fifth via hole. Also, the same mask is used to form the second transfer layer and the sixth via hole, without adding a new mask, which can reduce process costs.

[0039] In a third aspect, a memory is provided, which includes a controller and a storage array in any of the above embodiments, wherein the storage array is electrically connected to the controller.

[0040] In a fourth aspect, an electronic device is provided. The electronic device includes a processor and the memory in the above embodiment, and the memory is electrically connected to the processor.

[0041] It can be understood that the beneficial effects that can be achieved by the memory and electronic device provided in the above embodiments of the present application can refer to the beneficial effects of the storage array mentioned above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not intended to limit the actual size of the product involved in the embodiments of the present application, the actual process of the method, the actual timing of the signal, etc.

[0043] Figure 1 An architecture diagram of an electronic device provided in an embodiment of the present application;

[0044] Figure 2 An architectural diagram of a memory provided in an embodiment of the present application;

[0045] Figure 3 A circuit diagram of a storage unit provided in an embodiment of the present application;

[0046] Figure 4 A top view of a storage unit in a storage array provided in an embodiment of the present application;

[0047] Figure 5 for Figure 4 A cross-sectional view of the storage array along the section line AA';

[0048] Figure 6A to Figure 6E A diagram of the steps of preparing a storage array provided in an embodiment of the present application;

[0049] Figure 7 A cross-sectional view of another memory array along the section line AA' provided in an embodiment of the present application;

[0050] Figure 8A cross-sectional view of another memory array along the section line AA' provided in an embodiment of the present application;

[0051] Fig. 9 A cross-sectional view of another memory array along the section line AA' provided in an embodiment of the present application;

[0052] FIG. 10A to FIG. 10I A diagram of the steps of preparing another storage array provided in an embodiment of the present application;

[0053] Fig.11 A cross-sectional view of another memory array along the section line AA' provided in an embodiment of the present application;

[0054] FIG. 12A to FIG. 12I A diagram of the steps for preparing another storage array provided in an embodiment of the present application. DETAILED DESCRIPTION

[0055] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0056] In the description of the present application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to has a specific orientation, is constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0057] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics described may be included in any one or more embodiments or examples in any appropriate manner.

[0058] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0059] When describing some embodiments, the expression "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical or electrical contact with each other.

[0060] “At least one of A, B or C” includes the following combinations of A, B and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B and C.

[0061] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0062] Some embodiments of the present application provide an electronic device, which may be, for example, a mobile phone, a tablet computer, a personal digital assistant (PDA), a television, a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) terminal device, an augmented reality (AR) terminal device, a rechargeable small household appliance (e.g., a soymilk machine, a sweeping robot), a drone, a radar, an aerospace equipment, and a vehicle-mounted device, etc., and may also be a network device such as a base station. The embodiments of the present application do not impose any special restrictions on the specific form of the electronic device.

[0063] Figure 1 An architectural diagram of an electronic device provided in accordance with an embodiment of the present application.

[0064] See also Figure 1 The electronic device 1 includes: a storage device 11, a processor 12, an input device 13, an output device 14 and other components. Those skilled in the art can understand that Figure 1 The architecture of the electronic device 1 shown in the figure does not constitute a limitation on the electronic device 1, and the electronic device 1 may include, for example Figure 1 More or fewer components may be shown, or they may be combined as shown. Figure 1 Some of the components shown may be combined with Figure 1 The components shown are arranged differently.

[0065] The storage device 11 is used to store software programs and modules. The storage device 11 mainly includes a program storage area and a data storage area, wherein the program storage area can store and back up an operating system, an application required for at least one function (such as a sound playback function, an image playback function, etc.), etc.; the data storage area can store data created according to the use of the electronic device 1 (such as audio data, image data, phone book, etc.), etc. In addition, the storage device 11 includes an external memory 111, an internal memory 112, and a cache 113.

[0066] The external memory 111 may include, for example, a hard disk, a USB flash drive, a floppy disk, etc., the internal memory 112 may include, for example, a dynamic random access memory (DRAM), a ferroelectric random access memory (FeRAM), a NAND flash memory (NOT AND flash memory), etc., the cache 113 may include, for example, a first-level cache (L1 Cache), a second-level cache (L2Cache) and a last-level cache (LLC), the last-level cache (LLC), the second-level cache (L2Cache) and the first-level cache (L1 Cache) are electrically connected to the internal memory 112 in sequence, and the last-level cache may include, for example, a static random access memory (SRAM).

[0067] The processor 12 is the control center of the electronic device 1. It uses various interfaces and lines to connect various parts of the entire electronic device 1. By running or executing software programs and / or modules stored in the storage device 11, and calling data stored in the storage device 11, it executes various functions of the electronic device 1 and processes data, thereby monitoring the electronic device 1 as a whole. Optionally, the processor 12 may include one or more processing units. For example, the processor 12 may include an application processor (AP), a modem processor, a graphics processor (GPU), etc. Among them, different processing units may be independent devices or integrated into one or more processors. For example, the processor 12 may integrate an application processor and a modem processor, wherein the application processor mainly processes an operating system, a user interface, and an application program, etc., and the modem processor mainly processes wireless communications. It is understandable that the above-mentioned modem processor may not be integrated into the processor 12. The above-mentioned application processor may be, for example, a central processing unit (CPU).

[0068] Figure 1 Taking the processor 12 as a CPU as an example, the CPU may include an operator 121 and a controller 122. When the CPU wants to read a piece of data, it may first search from the cache 113 under the control of the controller 122. If the data is found, it may immediately read and send it to the CPU's operator 121 for processing; if the data is not found, it may search and read the data from the internal memory 112, and send the data to the CPU's operator 121 for processing. At the same time, the data block containing the data may be transferred to the cache 113 for temporary storage. After that, the CPU may directly read the data block from the cache 113 without calling the internal memory 112.

[0069] The input device 13 is used to receive input digital or character information, and to generate key signal input related to the user settings and function control of the electronic device. For example, the input device 13 may include a touch screen and other input devices. The touch screen, also known as a touch panel, can collect the user's touch operations on or near the touch screen (such as the user's operation on or near the touch screen using any suitable object or accessory such as a finger, stylus, etc.), and drive the corresponding connection device according to a pre-set program. The controller 122 in the above-mentioned processor 12 can also control the input device 13 to receive input signals or not receive input signals. In addition, the input digital or character information received by the input device 13, and the key signal input related to the user settings and function control of the electronic device can be stored in the internal memory 112.

[0070] The output device 14 is used to output the input of the input device 13 and the signal corresponding to the data stored in the internal memory 112. For example, the output device 14 outputs a sound signal or a video signal. The controller 122 in the processor 12 can also control the output device 14 to output a signal or not output a signal.

[0071] It can be seen that the operation of the electronic device 1 is inseparable from the memories in the storage device 11, and the capacity and performance of the memories become key factors restricting the performance of the processor 12. With the development of storage technology, memories such as the above-mentioned DRAM, FeRAM, NAND flash memory and SRAM can all realize an integrated three-dimensional (3D) architecture. At present, how to reduce the area of ​​3D memories and improve their storage density has become a problem to be solved in the field.

[0072] In order to solve the above problems, some embodiments of the present application provide a memory, which is described by taking SRAM as an example. Figure 2 An architectural diagram of the memory provided in accordance with an embodiment of the present application.

[0073] See also Figure 2 The memory 2 includes a storage array 21 and peripheral circuits. The peripheral circuits may include, for example, a row decoder 22, a column decoder 23, a memory controller 24, a read / write control circuit 25, and a sense amplifier (SA) 26.

[0074] The memory array 21 includes a plurality of memory cells 210 arranged in an array, and the plurality of memory cells 210 include a plurality of rows arranged along a first direction X, and a plurality of columns arranged along a second direction Y. The first direction X intersects with the second direction Y, for example, the two are perpendicular to each other. In the three-dimensional architecture of the memory 2, the peripheral circuit can be arranged below the memory array 21, and this structure can be referred to as "Periphery Under Cell" (PUC).

[0075] The memory controller 24 is electrically connected to the row decoder 22 , the column decoder 23 , the memory array 21 , the read / write control circuit 25 , and the sense amplifier 26 , respectively, and is configured to control each circuit.

[0076] The row decoder 22 is electrically connected to the memory array 21 , and is configured to select the memory cells 210 of the corresponding row according to the row address, so as to address the memory cells 210 of the corresponding row.

[0077] The column decoder 23 is electrically connected to the memory array 21. After the memory cells 210 of the corresponding row are selected, the column decoder 23 is configured to select the memory cells 210 of the corresponding column according to the column address, thereby selecting the memory cells 210 that need to be read or written.

[0078] The read / write control circuit 25 is electrically connected to the memory array 21 , and the read / write control circuit 25 is configured to control the selected memory cell 210 to perform a read operation or a write operation.

[0079] The sense amplifier 26 is electrically connected to the storage array 21 and is configured to read, amplify and output the data information stored in the selected storage cell 210 to implement a data read operation; or to input a data signal to the selected storage cell 210 to implement a data write operation.

[0080] Figure 3 A circuit diagram of a storage unit provided in an embodiment of the present application.

[0081] See also Figure 3 The memory cell 210 has a 6T (6-Transistor) structure, that is, the memory cell 210 includes six transistors, and the six transistors are respectively a first transistor M1 to a sixth transistor M6, wherein the control electrode of the first transistor M1 is connected to the node Q2, the first electrode of the second transistor M2 is connected to the first power line VDD, and the second electrode of the second transistor M2 is connected to the node Q1. The control electrode of the second transistor M2 is connected to the node Q1, the first electrode of the second transistor M2 is connected to the first power line VDD, and the second electrode of the second transistor M2 is connected to the node Q2. The control electrode of the third transistor M3 is connected to the node Q2, the first electrode of the third transistor M3 is connected to the second power line VSS, and the second electrode of the third transistor M3 is connected to the node Q1. The control electrode of the fourth transistor M4 is connected to the node Q1, the first electrode of the fourth transistor M4 is connected to the second power line VSS, and the second electrode of the fourth transistor M4 is connected to the node Q2. The control electrode of the fifth transistor M5 is connected to the word line WL, the first electrode of the fifth transistor M5 is connected to the first bit line BL, and the second electrode of the fifth transistor M5 is connected to the node Q1. A control electrode of the sixth transistor M6 is connected to the word line WL, a first electrode of the sixth transistor M6 is connected to the second bit line BLB, and a second electrode of the sixth transistor M6 is connected to the node Q2.

[0082] It can be understood that, under the control of the signal transmitted by the word line WL, the memory cell 210 can read and write data.

[0083] In the embodiment of the present application, the transistor may be a metal-oxide-semiconductor field effect transistor (MOSFET), and the transistor is divided into two types: an N-type transistor and a P-type transistor. The transistor includes a gate, a source, and a drain, the gate being the control electrode of the transistor, one of the source and the drain being the first electrode of the transistor, and the other being the second electrode of the transistor.

[0084] Furthermore, the N-type transistor is turned on under the control of a high-level signal at the control electrode, and the P-type transistor is turned on under the control of a low-level signal at the control electrode.

[0085] For example, Figure 3 In the embodiment, the first transistor M1 and the second transistor M2 are both P-type transistors, and the third transistor M3 to the sixth transistor M6 are all N-type transistors, but the embodiments of the present application are not limited thereto.

[0086] In addition, the storage unit 210 is not limited to a 6T structure, and may also be an 8T structure, which is not limited in the embodiments of the present application.

[0087] Figure 4 A top view of a storage unit in a storage array provided in an embodiment of the present application; Figure 5 for Figure 4 A cross-sectional view of the storage array along section line AA'.

[0088] See also Figure 4 and Figure 5 The memory array 21 includes a first layer structure 3 and a second layer structure 4 stacked together. The first layer structure 3 includes a first transistor M1 and a second transistor M2 arranged adjacent to each other. The first transistor M1 and the second transistor M2 may be arranged, for example, along a first direction X. The second layer structure 4 includes a third transistor M3 and a fourth transistor M4 arranged adjacent to each other. The third transistor M3 and the fourth transistor M4 may be arranged, for example, along the first direction X. Here, the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 are arranged adjacent to each other. Figure 3 The first transistor M1 to the fourth transistor M4 shown in FIG. 1 correspond to each other one by one.

[0089] Exemplarily, the manufacturing process of the memory array 21 includes a front end of line (FEOL) process and a back end of line (BEOL) process. The first layer structure 3 can be manufactured and formed in the front end process, and the second layer structure 4 can be manufactured and formed in the back end process.

[0090] Continue to see Figure 4 and Figure 5The memory array 21 further includes a first conductive structure 51 and a second conductive structure 52. At least a portion of the first conductive structure 51 is located between the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4. The control electrode of the first transistor M1, the first electrode of the second transistor M2, the control electrode of the third transistor M3, and the first electrode of the fourth transistor M4 are electrically connected to the first conductive structure 51. Furthermore, at least a portion of the second conductive structure 52 is located between the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4. The first electrode of the first transistor M1, the control electrode of the second transistor M2, the first electrode of the third transistor M3, and the control electrode of the fourth transistor M4 are electrically connected to the second conductive structure 52.

[0091] Exemplarily, the first conductive structure 51 and the second conductive structure 52 are arranged along the second direction Y, and the second direction Y intersects with the first direction X. For example, the second direction Y is perpendicular to the first direction X.

[0092] Exemplarily, the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4 are directly in contact with the first conductive structure 51, respectively, and the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4 are directly in contact with the second conductive structure 52, respectively. The control electrode of the third transistor M3 and the first electrode of the fourth transistor M4 can be connected by using one first conductive structure 51, and the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4 can be connected by using one second conductive structure 52. The connection between one electrode of the third transistor M3 and one electrode of the fourth transistor M4 shares the first conductive structure 51 or the second conductive structure 52, and the first conductive structure 51 and the second conductive structure 52 can be referred to as a "shared through hole".

[0093] Furthermore, compared to the related art in which two through holes are used to connect one electrode of the third transistor M3 with one electrode of the fourth transistor M4, in the above-mentioned embodiment of the present application, at least a portion of the first conductive structure 51 (or the second conductive structure 52) is disposed between one electrode of the third transistor M3 and one electrode of the fourth transistor M4, and one shared through hole is used to connect one electrode of the third transistor M3 with one electrode of the fourth transistor M4. The shared through hole serves as a transmission path for the signal between the electrode of the third transistor M3 and the electrode of the fourth transistor M4, and the length of the transmission path is shortened. The resistance on the transmission path only includes the resistance of the shared through hole itself and the contact resistance between the shared through hole and the electrode of the third transistor M3 and the electrode of the fourth transistor M4. The resistance on the transmission path is reduced, which is beneficial to improving the transmission efficiency of the signal.

[0094] In addition, the shared via provided in the embodiment of the present application can be applied not only to the memory array 21 of the memory 2, but also to the peripheral circuits of the memory 2 (such as the sense amplifier 26), as well as to inverters or other structures with transistor stacks.

[0095] Through the above configuration, the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4 are connected to the first conductive structure 51 , and the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4 are connected to the second conductive structure 52 .

[0096] For example, see Figure 4 and Figure 5 The memory array 21 further includes a first connection pattern 61, which is disposed between the first layer structure 3 and the second layer structure 4. The first conductive structure 51 is electrically connected to the first connection pattern 61, for example, the first conductive structure 51 penetrates the second layer structure 4 and is connected to the first connection pattern 61. The control electrode of the first transistor M1 and the first electrode of the second transistor M2 are electrically connected to the first connection pattern 61, for example, the control electrode of the first transistor M1 is connected to the first connection pattern 61 through a conductive pillar 7, and the first electrode of the second transistor M2 is connected to the first connection pattern 61 through another conductive pillar 7.

[0097] Through the above configuration, the control electrode of the first transistor M1 and the first electrode of the second transistor M2 are connected to the first conductive structure 51 .

[0098] For example, see Figure 4 and Figure 5 The memory array 21 further includes a second connection pattern 62, which is also disposed between the first layer structure 3 and the second layer structure 4. The second conductive structure 52 is electrically connected to the second connection pattern 62, for example, the second conductive structure 52 penetrates the second layer structure 4 and is connected to the second connection pattern 62. The first electrode of the first transistor M1 and the control electrode of the second transistor M2 are electrically connected to the second connection pattern 62, for example, the first electrode of the first transistor M1 is connected to the second connection pattern 62 through a conductive pillar 7, and the control electrode of the second transistor M2 is connected to the second connection pattern 62 through another conductive pillar 7.

[0099] Through the above configuration, the connection between the first electrode of the first transistor M1 and the control electrode of the second transistor M2 and the second conductive structure 52 is achieved.

[0100] Exemplarily, the material of the first conductive structure 51 includes at least one of copper, tungsten, titanium nitride, titanium, cobalt, nickel, ruthenium or tantalum, and the material of the second conductive structure 52 includes at least one of copper, tungsten, titanium nitride, titanium, cobalt, nickel, ruthenium or tantalum.

[0101] Continue to see Figure 4 and Figure 5 , the surface of the first layer structure 3 away from the second layer structure 4 is taken as the reference plane P, that is, the bottom surface of the first layer structure 3 is taken as the reference plane P, and the first direction X and the second direction Y are both parallel to the reference plane P. The orthographic projection of the first conductive structure 51 on the reference plane P does not overlap with the orthographic projection of the second conductive structure 52 on the reference plane P.

[0102] In the related art, a storage array uses a transistor cross-coupled connection structure, the connection structure has an interconnection winding design, and crossover wires are required between the connection structures, which increases the occupied area of ​​the device.

[0103] In the storage array 21 provided in the above-mentioned embodiment of the present application, the first conductive structure 51 and the second conductive structure 52 are adopted, and the control electrode of the first transistor M1, the first electrode of the second transistor M2, the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4 are electrically connected to the first conductive structure 51 respectively, and the first electrode of the first transistor M1, the control electrode of the second transistor M2, the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4 are electrically connected to the second conductive structure 52 respectively, thereby realizing cross-coupling of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4.

[0104] Furthermore, the first conductive structure 51 is located between the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4, the second conductive structure 52 is located between the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4, and the orthographic projection of the first conductive structure 51 on the reference plane P does not overlap with the orthographic projection of the second conductive structure 52 on the reference plane P, that is, the first conductive structure 51 and the second conductive structure 52 do not need to be wound or cross-wired, which is beneficial to reducing the area of ​​the memory array 21 and improving the storage density of the memory using the memory array 21.

[0105] In some embodiments, see Figure 4 and Figure 5 The first layer structure 3 includes a first active layer 31 and a second active layer 32, which may be arranged, for example, along a first direction X. The first active layer 31 includes a first electrode and a second electrode of a first transistor M1, and the second active layer 32 includes a first electrode and a second electrode of a second transistor M2.

[0106] Exemplarily, the first layer structure 3 may also include a substrate, a shallow trench isolation (STI) is formed on the substrate at a position corresponding to the first transistor M1, and then a dielectric material is filled in the shallow trench isolation, and the dielectric material is ion-doped to form a first active layer 31. The first active layer 31 is located on both sides of the control electrode of the first transistor M1, and can serve as the first electrode and the second electrode of the first transistor M1.

[0107] Furthermore, the substrate is ion-doped at a position corresponding to the second transistor M2 on the substrate to form a second active layer 32 . The second active layer 32 located on both sides of the control electrode of the second transistor M2 can serve as the first electrode and the second electrode of the second transistor M2 .

[0108] See also Figure 4 and Figure 5 The second layer structure 4 includes a third active layer 41 and a fourth active layer 42, which may be arranged, for example, along the first direction X. The third active layer 41 includes a first electrode and a second electrode of the third transistor M3, and the fourth active layer 42 includes a first electrode and a second electrode of the fourth transistor M4.

[0109] Exemplarily, the third active layer 41 located on both sides of the control electrode of the third transistor M3 can be used as the first electrode and the second electrode of the third transistor M3. The fourth active layer 42 located on both sides of the control electrode of the fourth transistor M4 can be used as the first electrode and the second electrode of the fourth transistor M4.

[0110] Continue to see Figure 4 and Figure 5 , the orthographic projection of the first conductive structure 51 on the reference plane P overlaps with the orthographic projection of the first active layer 31 on the reference plane P, and the orthographic projection of the first conductive structure 51 on the reference plane P does not overlap with the orthographic projection of the third active layer 41 on the reference plane P. The two relative boundaries of the first conductive structure 51 along the second direction Y are located within the two relative boundaries of the first active layer 31 along the second direction Y. In addition, the orthographic projection of the second conductive structure 52 on the reference plane P overlaps with the orthographic projection of the second active layer 32 on the reference plane P, and the orthographic projection of the second conductive structure 52 on the reference plane P does not overlap with the orthographic projection of the fourth active layer 42 on the reference plane P. The two relative boundaries of the second conductive structure 52 along the second direction Y are located within the two relative boundaries of the second active layer 32 along the second direction Y.

[0111] In the related art, the connection structure of the transistors used in the memory array has a boundary along the second direction Y that usually exceeds the boundary of the active layer in the first layer structure along the second direction Y, which increases the occupied area of ​​the device.

[0112] In the above-mentioned embodiment of the present application, since the first conductive structure 51 and the second conductive structure 52 do not need to be wound or crossed, the boundary of the first conductive structure 51 along the second direction Y will not exceed the boundary of the first active layer 31 along the second direction Y, and the boundary of the second conductive structure 52 along the second direction Y will not exceed the boundary of the second active layer 32 along the second direction Y, which is beneficial to reducing the area of ​​the storage array 21. For example, the area of ​​the storage array 21 provided in the embodiment of the present application can be reduced by at least 50%.

[0113] Exemplarily, the materials of the first active layer 31, the second active layer 32, the third active layer 41 and the fourth active layer 42 may include at least one of silicon-based materials, carbon-based materials, two-dimensional materials (transition metal sulfides, such as molybdenum disulfide), oxide semiconductor materials or Group III-V materials.

[0114] In some embodiments, see Figure 4 and Figure 5 The storage array 21 further includes a dielectric barrier layer 8, and the material of the dielectric barrier layer 8 may include, for example, doped silicon carbide (NDC). The dielectric barrier layer 8 is disposed between the first layer structure 3 and the second layer structure 4, and is located on the side of the first connection pattern 61 close to the second layer structure 4, and is located on the side of the second connection pattern 62 close to the second layer structure 4. The dielectric barrier layer 8 can inhibit the diffusion of metal elements in the first connection pattern 61 and the second connection pattern 62, and prevent the first connection pattern 61 and the second connection pattern 62 from short-circuiting with the electrodes in the second layer structure 4.

[0115] In some embodiments, see Figure 4 and Figure 5 The memory array 21 further includes a plurality of first power lines VDD, which are disposed between the first layer structure 3 and the second layer structure 4. For example, the plurality of first power lines VDD may be disposed in the same layer as the first connection pattern 61 and the second connection pattern 62. The second electrode of the first transistor M1 is electrically connected to a first power line VDD through the conductive pillar 7, and the second electrode of the second transistor M2 is electrically connected to a first power line VDD through the conductive pillar 7.

[0116] In the above embodiment, "same layer" refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0117] In some embodiments, see Figure 4 and Figure 5 The memory array 21 further includes a third conductive structure 53, a fourth conductive structure 54, and a plurality of second power lines VSS. For example, the third conductive structure 53 and the fourth conductive structure 54 may be disposed in the same layer as the first conductive structure 51 and the second conductive structure 52. The second electrode of the third transistor M3 is electrically connected to a second power line VSS through the third conductive structure 53, and the second electrode of the fourth transistor M4 is electrically connected to a second power line VSS through the fourth conductive structure 54.

[0118] In some embodiments, see Figure 4 and Figure 5 The second layer structure 4 also includes a fifth transistor M5, a sixth transistor M6, a word line WL, a first bit line BL and a second bit line BLB, the control electrode of the fifth transistor M5 is electrically connected to the word line WL, the first electrode of the fifth transistor M5 is connected to the first bit line BL, and the second electrode of the fifth transistor M5 is electrically connected to the first electrode of the third transistor M3.

[0119] It can be understood that the third active layer 41 further includes a first electrode and a second electrode of a fifth transistor M5 , and the second electrode of the fifth transistor M5 is integrally arranged with the first electrode of the third transistor M3 to achieve connection between the two.

[0120] See also Figure 4 and Figure 5 , a control electrode of the sixth transistor M6 is electrically connected to the word line WL, a first electrode of the sixth transistor M6 is connected to the second bit line BLB, and a second electrode of the sixth transistor M6 is electrically connected to a first electrode of the fourth transistor M4.

[0121] It can be understood that the fourth active layer 42 further includes a first electrode and a second electrode of a sixth transistor M6 , and the second electrode of the sixth transistor M6 is integrally arranged with the first electrode of the fourth transistor M4 to achieve connection between the two.

[0122] Some embodiments of the present application also provide a method for preparing a storage array. Figure 6A to Figure 6E A diagram of the steps for preparing a storage array provided in an embodiment of the present application.

[0123] The method for preparing the storage array includes the following steps S10 to S20:

[0124] S10: See Fig. 6A , forming a first layer structure 3 and a second layer structure 4 stacked together, the first layer structure 3 includes a first transistor M1 and a second transistor M2 adjacent to each other, and the second layer structure 4 includes a third transistor M3 and a fourth transistor M4 adjacent to each other.

[0125] Illustratively, after forming the first layer structure 3 and before forming the second layer structure 4, a first connection pattern 61 and a second connection pattern 62 are formed on the first layer structure 3, and the control electrode of the first transistor M1 and the first electrode of the second transistor M2 are electrically connected to the first connection pattern 61, respectively, and the first electrode of the first transistor M1 and the control electrode of the second transistor M2 are electrically connected to the second connection pattern 62, respectively.

[0126] Exemplarily, after forming the first connection patterns 61 and the second connection patterns 62 , a dielectric barrier layer 8 may be further formed over the first connection patterns 61 and the second connection patterns 62 .

[0127] S20: forming a first conductive structure 51 and a second conductive structure 52, wherein at least a portion of the first conductive structure 51 is located between the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4, and the control electrode of the first transistor M1, the first electrode of the second transistor M2, the control electrode of the third transistor M3, and the first electrode of the fourth transistor M4 are respectively electrically connected to the first conductive structure 51. At least a portion of the second conductive structure 52 is located between the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4, and the first electrode of the first transistor M1, the control electrode of the second transistor M2, the first electrode of the third transistor M3, and the control electrode of the fourth transistor M4 are respectively electrically connected to the second conductive structure 52.

[0128] Exemplarily, the above S20 may include the following S21 to S23:

[0129] S21: See Figure 6B , a dielectric layer 9 is formed, and the dielectric layer 9 covers the third transistor M3 and the fourth transistor M4.

[0130] S22: See Figure 6B and Figure 6C , the dielectric layer 9 is etched to form a via hole H1 , wherein the via hole H1 exposes the control electrode of the third transistor M3 , the first electrode of the fourth transistor M4 , and the first connection pattern 61 .

[0131] Furthermore, the dielectric layer 9 is etched to form a via hole H2 (not shown in the figure), and the via hole H2 exposes the first electrode of the third transistor M3 , the control electrode of the fourth transistor M4 , and the second connection pattern 62 .

[0132] For example, a first mask layer K1 and a second mask layer K2 may be formed on a side of the dielectric layer 9 away from the first layer structure 3, and then a photoresist (PR) layer K3 may be formed on a side of the second mask layer K2 away from the first layer structure 3, the photoresist layer K3 is exposed and developed, and the first mask layer K1 and the second mask layer K2 are etched using the photoresist layer K3 as a mask. Finally, the dielectric layer 9, the dielectric in the second layer structure 4, and the dielectric barrier layer 8 are etched using the first mask layer K1 and the second mask layer K2 as masks to form via holes H1 and H2.

[0133] For example, in the process of forming the via hole H1 and the via hole H2 , a via hole H3 (not shown in the figure) is also formed, and the via hole H3 exposes the second electrode of the third transistor M3 .

[0134] For example, see Figure 6B and Figure 6C In the process of forming the via hole H1 and the via hole H2 , a via hole H4 is also formed, and the via hole H4 exposes the second electrode of the fourth transistor M4 .

[0135] By adjusting the etching process parameters, the dielectric layer 9 and the electrodes (control electrode, first electrode and second electrode) of the transistor, the first connection pattern 61 and the second connection pattern 62 have a larger etching selectivity ratio. In this way, the etching damage to the electrodes of the transistor, the first connection pattern 61 and the second connection pattern 62 can be reduced during the etching of the dielectric layer 9.

[0136] In the case where the material of the first connection pattern 61 and the second connection pattern 62 includes tungsten, the material of the control electrode of the transistor can be selected from at least one of tungsten or titanium, the material of the first electrode and the second electrode of the transistor can be selected from at least one of tungsten, tungsten silicide, tungsten nitride, titanium nitride, molybdenum, nickel, platinum, palladium or ruthenium, and the first connection pattern 61, the second connection pattern 62, the control electrode, the first electrode and the second electrode of the transistor can be selected from materials with similar chemical properties; or, the first connection pattern 61, the second connection pattern 62 and the control electrode of the transistor are selected from materials with similar chemical properties, and the first electrode and the second electrode of the transistor are selected from materials with stable chemical properties.

[0137] In this way, during the process of etching the dielectric layer 9, a wet cleaning process can be used to remove the dielectric material remaining in the dielectric layer 9 on the first connection pattern 61, the second connection pattern 62 and the electrodes of the transistor, and the liquid used in the wet cleaning will not cause electrochemical corrosion (galvanic corrosion) to the first connection pattern 61, the second connection pattern 62 and the electrodes of the transistor.

[0138] S23: See Figure 6C to Figure 6E , a first conductive structure 51 is formed in the via hole H1.

[0139] Furthermore, a second conductive structure 52 is formed in the via hole H2.

[0140] For example, see Figure 6C and Fig.6D , forming an adhesive layer L covering the via holes H1 to H4, the material of the adhesive layer L may include titanium nitride, for example. Then, depositing a metal material so that the metal material fills the via holes H1 to H4.

[0141] See also Fig.6D and Fig. 6E , a chemical mechanical polishing (CMP) process is used to polish and remove excess metal material until the upper surface of the dielectric layer 9 is exposed, thereby obtaining a first conductive structure 51 located in the via hole H1, a second conductive structure 52 located in the via hole H2, a third conductive structure 53 located in the via hole H3, and a fourth conductive structure 54 located in the via hole H4.

[0142] Figure 7 A cross-sectional view of another memory array along section line AA' provided in an embodiment of the present application.

[0143] See also Figure 7 The memory array 21 further includes a first transfer layer V1, which is disposed on a side of the first connection pattern 61 close to the second layer structure 4. The first conductive structure 51 is electrically connected to the first connection pattern 61 through the first transfer layer V1.

[0144] For example, the first transfer layer V1 may be formed on the first connection pattern 61 after the first connection pattern 61 is formed and before the dielectric barrier layer 8 is formed.

[0145] Furthermore, the memory array 21 further includes a second transfer layer V2 (not shown), which is disposed on a side of the second connection pattern 62 close to the second layer structure 4. The second conductive structure 52 is electrically connected to the second connection pattern 62 through the second transfer layer V2.

[0146] For example, the second transfer layer V2 may be formed on the second connection pattern 62 after the second connection pattern 62 is formed and before the dielectric barrier layer 8 is formed.

[0147] Through the above-mentioned setting manner, when the material of the first connection pattern 61 and the second connection pattern 62 includes copper, the first transfer layer V1 and the second transfer layer V2 can suppress the diffusion of copper elements in the first connection pattern 61 and the second connection pattern 62, thereby avoiding a short circuit between the first connection pattern 61 and the second connection pattern 62 and the electrodes in the second layer structure 4.

[0148] Furthermore, in the process of etching the dielectric layer 9 to form the via holes H1 and H2, a wet cleaning process is used to remove the residual dielectric material. The first transfer layer V1 and the second transfer layer V2 can isolate the cleaning liquid to prevent the cleaning liquid from contacting the first connection pattern 61 and the second connection pattern 62 and causing corrosion.

[0149] In some embodiments, see Figure 7 , the boundary of the orthographic projection of the first transfer layer V1 on the reference plane P coincides with the boundary of the orthographic projection of the first conductive structure 51 on the reference plane P, that is, the pattern of the first transfer layer V1 is the same as the pattern of the first conductive structure 51. In this way, the same mask can be used to form the first transfer layer V1 and the first conductive structure 51, and there is no need to add a new mask to form the first transfer layer V1, thereby reducing the process cost.

[0150] Furthermore, the boundary of the orthographic projection of the second transfer layer V2 on the reference plane P coincides with the boundary of the orthographic projection of the second conductive structure 52 on the reference plane P, that is, the pattern of the second transfer layer V2 is the same as the pattern of the second conductive structure 52. In this way, the second transfer layer V2 and the second conductive structure 52 can be formed by using the same mask, and there is no need to add a new mask to form the second transfer layer V2, thereby reducing the process cost.

[0151] Figure 8 A cross-sectional view of another memory array along section line AA' provided in an embodiment of the present application.

[0152] See also Figure 8 , the boundary of the orthographic projection of the first transfer layer V1 on the reference plane P coincides with the boundary of the orthographic projection of the first connection pattern 61 on the reference plane P, that is, the pattern of the first transfer layer V1 is the same as the pattern of the first connection pattern 61. In this way, the same mask can be used to form the first transfer layer V1 and the first connection pattern 61, and there is no need to add a new mask to form the first transfer layer V1, thereby reducing the process cost.

[0153] Furthermore, the boundary of the orthographic projection of the second transfer layer V2 on the reference plane P coincides with the boundary of the orthographic projection of the second connection pattern 62 on the reference plane P, that is, the pattern of the second transfer layer V2 is the same as the pattern of the second connection pattern 62. In this way, the second transfer layer V2 and the second connection pattern 62 can be formed by using the same mask, and there is no need to add a new mask to form the second transfer layer V2, thereby reducing the process cost.

[0154] Fig. 9 A cross-sectional view of another memory array along section line AA′ is provided in an embodiment of the present application.

[0155] See also Fig. 9The first conductive structure 51 includes a first substructure 51a and a second substructure 51b connected to each other. The first substructure 51a is electrically connected to the control electrode of the third transistor M3 and the first connection pattern 61, and the second substructure 51b is electrically connected to the first electrode of the fourth transistor M4.

[0156] Furthermore, the second conductive structure 52 includes a third substructure 52a and a fourth substructure 52b (not shown) connected to each other. The third substructure 52a is electrically connected to the control electrode of the fourth transistor M4 and the second connection pattern 62, and the fourth substructure 52b is electrically connected to the first electrode of the third transistor M3.

[0157] Understandably, Fig. 9 The storage array 21 in the embodiment may also include a first switching layer V1 and a second switching layer V2 ( Fig. 9 (not shown in the figure), the pattern of the first switching layer V1 is the same as the pattern of the first connection pattern 61, and the pattern of the second switching layer V2 is the same as the pattern of the second connection pattern 62.

[0158] Alternatively, the first transfer layer V1 and the second transfer layer V2 each include two parts, the patterns of the two parts of the first transfer layer V1 are respectively the same as the patterns of the first substructure 51a and the second substructure 51b, and the patterns of the two parts of the second transfer layer V2 are respectively the same as the patterns of the third substructure 52a and the fourth substructure 52b.

[0159] The present application also provides Fig. 9 A method for preparing a storage array, FIG. 10A to FIG. 10I A diagram of the steps for preparing another storage array provided in an embodiment of the present application.

[0160] The storage array preparation method includes the following S30-S40:

[0161] S30: See Fig. 10A , forming a first layer structure 3 and a second layer structure 4 stacked together, the first layer structure 3 includes a first transistor M1 and a second transistor M2 adjacent to each other, and the second layer structure 4 includes a third transistor M3 and a fourth transistor M4 adjacent to each other.

[0162] Illustratively, after forming the first layer structure 3 and before forming the second layer structure 4, a first connection pattern 61 and a second connection pattern 62 are formed on the first layer structure 3, and the control electrode of the first transistor M1 and the first electrode of the second transistor M2 are electrically connected to the first connection pattern 61, respectively, and the first electrode of the first transistor M1 and the control electrode of the second transistor M2 are electrically connected to the second connection pattern 62, respectively.

[0163] Exemplarily, after forming the first connection patterns 61 and the second connection patterns 62 , a dielectric barrier layer 8 may be further formed over the first connection patterns 61 and the second connection patterns 62 .

[0164] S40: forming a first conductive structure 51 and a second conductive structure 52, wherein at least a portion of the first conductive structure 51 is located between the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4, and the control electrode of the first transistor M1, the first electrode of the second transistor M2, the control electrode of the third transistor M3, and the first electrode of the fourth transistor M4 are respectively electrically connected to the first conductive structure 51. At least a portion of the second conductive structure 52 is located between the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4, and the first electrode of the first transistor M1, the control electrode of the second transistor M2, the first electrode of the third transistor M3, and the control electrode of the fourth transistor M4 are respectively electrically connected to the second conductive structure 52.

[0165] Exemplarily, the above S40 may include the following S41 to S45:

[0166] S41: See Fig. 10B , a dielectric layer 9 is formed, and the dielectric layer 9 covers the third transistor M3 and the fourth transistor M4.

[0167] S42: See Fig. 10B and Fig. 10C , the dielectric layer 9 is etched to form a via hole H5 , wherein the via hole H5 exposes the control electrode of the third transistor M3 and the first connection pattern 61 .

[0168] Furthermore, the dielectric layer 9 is etched to form a via hole H6 (not shown in the figure), and the via hole H6 exposes the control electrode of the fourth transistor M4 and the second connection pattern 62 .

[0169] For example, in the process of forming the via holes H5 and H6 , a via hole H3 (not shown in the figure) is also formed, and the via hole H3 exposes the second electrode of the third transistor M3 .

[0170] For example, see Fig. 10B and Fig. 10C In the process of forming the via holes H5 and H6 , a via hole H4 is also formed, and the via hole H4 exposes the second electrode of the fourth transistor M4 .

[0171] By adjusting the etching process parameters, the dielectric layer 9 and the control electrode of the transistor, the first connection pattern 61 and the second connection pattern 62 have a larger etching selectivity ratio. In this way, the etching damage to the control electrode of the transistor, the first connection pattern 61 and the second connection pattern 62 can be reduced during the etching of the dielectric layer 9.

[0172] In the case where the material of the first connection pattern 61 and the second connection pattern 62 includes tungsten, the material of the control electrode of the transistor can be selected from at least one of tungsten or titanium, and the first connection pattern 61, the second connection pattern 62 and the control electrode of the transistor can be selected from materials with similar chemical properties. In this way, during the etching process of the dielectric layer 9, a wet cleaning process can be used to remove the dielectric material remaining in the dielectric layer 9 on the first connection pattern 61, the second connection pattern 62 and the control electrode of the transistor, and the liquid used for wet cleaning will not cause corrosion to the first connection pattern 61, the second connection pattern 62 and the control electrode of the transistor.

[0173] S43: See Figure 10C to Figure 10E , a first substructure 51 a is formed in the via hole H5 .

[0174] Furthermore, a third substructure 52 a is formed in the via hole H6 .

[0175] For example, see Fig. 10C and Fig. 10D , forming an adhesive layer L covering the via hole H5 and the via hole H6. Then, depositing a metal material so that the metal material fills the via hole H5 and the via hole H6.

[0176] See also Fig. 10D and Fig.10E A chemical mechanical polishing process is used to polish and remove excess metal material until the upper surface of the dielectric layer 9 is exposed, thereby obtaining a first substructure 51a located in the via hole H5 and a third substructure 52a located in the via hole H6.

[0177] S44: See Fig.10F and Figure 10G , the dielectric layer 9 is etched to form a via hole H7, wherein the via hole H7 exposes the first substructure 51a and the first electrode of the fourth transistor M4.

[0178] Furthermore, the dielectric layer 9 is etched to form a via hole H8 (not shown in the figure), and the via hole H8 exposes the third substructure 52a and the first electrode of the third transistor M3.

[0179] Exemplarily, by adjusting the etching process parameters, the dielectric layer 9 and the first and second electrodes of the transistor have a larger etching selectivity ratio, so that the etching damage to the first and second electrodes of the transistor can be reduced during the etching of the dielectric layer 9.

[0180] The via hole H7 may not expose the first connection pattern 61 , and the via hole H8 may not expose the second connection pattern 62 . Thus, during the process of etching the dielectric layer 9 , no etching damage is caused to the first connection pattern 61 and the second connection pattern 62 .

[0181] S45: See Figure 10G to Figure 10I , a second substructure 51b is formed in the via hole H7.

[0182] Furthermore, a fourth substructure 52 b is formed in the via hole H8 .

[0183] For example, see Figure 10G and Fig. 10H , forming an adhesive layer L covering the via hole H7 and the via hole H8. Then, depositing a metal material so that the metal material fills the via hole H7 and the via hole H8.

[0184] See also Fig. 10H and Fig.10I A chemical mechanical polishing process is used to polish and remove excess metal material until the upper surface of the dielectric layer 9 is exposed, thereby obtaining a second substructure 51b located in the via hole H7 and a fourth substructure 52b located in the via hole H8.

[0185] In the manufacturing method provided by the above-mentioned embodiment of the present application, the via hole H5 and the via hole H6 are first formed by etching the dielectric layer 9, wherein the via hole H5 exposes the control electrode and the first connection pattern 61 of the third transistor M3, and the via hole H6 exposes the control electrode and the second connection pattern 62 of the fourth transistor M4. Therefore, it is necessary to adjust the etching process parameters so that the dielectric layer 9 has a larger etching selectivity with the control electrode, the first connection pattern 61 and the second connection pattern 62 of the transistor, so that the etching damage to the control electrode, the first connection pattern 61 and the second connection pattern 62 of the transistor can be reduced during the etching of the dielectric layer 9.

[0186] Furthermore, since the via H5 does not expose the first electrode of the fourth transistor M4 and the via H6 does not expose the first electrode of the third transistor M3, there is no need to consider the etching selectivity ratio of the first electrode and the second electrode of the transistor, etching the dielectric layer 9 will not cause etching damage to the first electrode and the second electrode of the transistor, and wet cleaning will not cause corrosion to the first electrode and the second electrode of the transistor, thereby increasing the selection range of the electrode material of the transistor.

[0187] The chemical properties of the materials of the first electrode and the second electrode of the transistor may not be similar to the chemical properties of the materials of the first connection pattern 61, the second connection pattern 62 and the control electrode of the transistor. For example, the materials of the first connection pattern 61 and the second connection pattern 62 include tungsten, the material of the control electrode of the transistor can be selected from at least one of tungsten or titanium, and the materials of the first electrode and the second electrode of the transistor can be selected from at least one of titanium nitride, molybdenum, nickel, platinum, palladium or ruthenium.

[0188] Fig.11 A cross-sectional view of another memory array along section line AA′ is provided in an embodiment of the present application.

[0189] See also Fig.11The first conductive structure 51 includes a first substructure 51a and a second substructure 51b connected to each other. The first substructure 51a is electrically connected to the control electrode of the third transistor M3, and the second substructure 51b is electrically connected to the first electrode of the fourth transistor M4 and the first connection pattern 61.

[0190] Furthermore, the second conductive structure 52 includes a third substructure 52a and a fourth substructure 52b (not shown in the figure) connected to each other. The third substructure 52a is electrically connected to the control electrode of the fourth transistor M4, and the fourth substructure 52b is electrically connected to the first electrode of the third transistor M3 and the second connection pattern 62.

[0191] Understandably, Fig.11 The storage array 21 in the embodiment may also include a first switching layer V1 and a second switching layer V2 ( Fig.11 (not shown in the figure), the pattern of the first switching layer V1 is the same as the pattern of the first connection pattern 61, and the pattern of the second switching layer V2 is the same as the pattern of the second connection pattern 62.

[0192] Alternatively, the first transfer layer V1 and the second transfer layer V2 each include two parts, the patterns of the two parts of the first transfer layer V1 are respectively the same as the patterns of the first substructure 51a and the second substructure 51b, and the patterns of the two parts of the second transfer layer V2 are respectively the same as the patterns of the third substructure 52a and the fourth substructure 52b.

[0193] The present application also provides Fig.11 A method for preparing a storage array, FIG. 12A to FIG. 12I A diagram of the steps for preparing another storage array provided in an embodiment of the present application.

[0194] The method for preparing the storage array includes the following steps S50 to S60:

[0195] S50: See Fig. 12A , forming a first layer structure 3 and a second layer structure 4 stacked together, the first layer structure 3 includes a first transistor M1 and a second transistor M2 adjacent to each other, and the second layer structure 4 includes a third transistor M3 and a fourth transistor M4 adjacent to each other.

[0196] Illustratively, after forming the first layer structure 3 and before forming the second layer structure 4, a first connection pattern 61 and a second connection pattern 62 are formed on the first layer structure 3, and the control electrode of the first transistor M1 and the first electrode of the second transistor M2 are electrically connected to the first connection pattern 61, respectively, and the first electrode of the first transistor M1 and the control electrode of the second transistor M2 are electrically connected to the second connection pattern 62, respectively.

[0197] Exemplarily, after forming the first connection patterns 61 and the second connection patterns 62 , a dielectric barrier layer 8 may be further formed over the first connection patterns 61 and the second connection patterns 62 .

[0198] S60: forming a first conductive structure 51 and a second conductive structure 52, wherein at least a portion of the first conductive structure 51 is located between the control electrode of the third transistor M3 and the first electrode of the fourth transistor M4, and the control electrode of the first transistor M1, the first electrode of the second transistor M2, the control electrode of the third transistor M3, and the first electrode of the fourth transistor M4 are respectively electrically connected to the first conductive structure 51. At least a portion of the second conductive structure 52 is located between the first electrode of the third transistor M3 and the control electrode of the fourth transistor M4, and the first electrode of the first transistor M1, the control electrode of the second transistor M2, the first electrode of the third transistor M3, and the control electrode of the fourth transistor M4 are respectively electrically connected to the second conductive structure 52.

[0199] Exemplarily, the above S60 may include the following S61 to S65:

[0200] S61: See Fig. 12B , a dielectric layer 9 is formed, and the dielectric layer 9 covers the third transistor M3 and the fourth transistor M4.

[0201] S62: See Fig. 12B and Fig. 12C , the dielectric layer 9 is etched to form a via hole H9 , wherein the via hole H9 exposes the first electrode of the fourth transistor M4 and the first connection pattern 61 .

[0202] Furthermore, the dielectric layer 9 is etched to form a via hole H10 (not shown in the figure), and the via hole H10 exposes the first electrode of the third transistor M3 and the second connection pattern 62 .

[0203] For example, in the process of forming the via hole H9 and the via hole H10 , a via hole H3 (not shown in the figure) is also formed, and the via hole H3 exposes the second electrode of the third transistor M3 .

[0204] For example, see Fig. 12B and Fig. 12C In the process of forming the via holes H9 and H10 , a via hole H4 is also formed, and the via hole H4 exposes the second electrode of the fourth transistor M4 .

[0205] By adjusting the etching process parameters, the dielectric layer 9 and the first and second electrodes of the transistor, the first connection pattern 61 and the second connection pattern 62 have a larger etching selectivity ratio. In this way, the etching damage to the first and second electrodes of the transistor, the first connection pattern 61 and the second connection pattern 62 can be reduced during the etching of the dielectric layer 9.

[0206] When the material of the first connection pattern 61 and the second connection pattern 62 includes tungsten, the material of the first electrode and the second electrode of the transistor can be selected from at least one of tungsten, tungsten silicide, tungsten nitride, titanium nitride, molybdenum, nickel, platinum, palladium or ruthenium, and the first connection pattern 61, the second connection pattern 62, the first electrode and the second electrode of the transistor can be selected from materials with similar chemical properties, or the first electrode and the second electrode of the transistor can be selected from materials with stable chemical properties.

[0207] In this way, during the process of etching the dielectric layer 9, a wet cleaning process can be used to remove the dielectric material remaining in the dielectric layer 9 on the first connection pattern 61, the second connection pattern 62 and the first and second electrodes of the transistor, and the liquid used in the wet cleaning will not cause corrosion to the first connection pattern 61, the second connection pattern 62 and the first and second electrodes of the transistor.

[0208] S63: See Figure 12C to Figure 12E , a second substructure 51b is formed in the via hole H9.

[0209] Furthermore, a fourth substructure 52 b is formed in the via hole H10 .

[0210] For example, see Fig. 12C and Fig.12D , forming an adhesive layer L covering the via hole H9 and the via hole H10. Then, depositing a metal material so that the metal material fills the via hole H9 and the via hole H10.

[0211] See also Fig.12D and Fig.12E A chemical mechanical polishing process is used to polish and remove excess metal material until the upper surface of the dielectric layer 9 is exposed, thereby obtaining a second substructure 51b located in the via hole H9 and a fourth substructure 52b located in the via hole H10.

[0212] S64: See Fig.12F and Figure 12G , the dielectric layer 9 is etched to form a via hole H11 , wherein the via hole H11 exposes the second substructure 51 b and the control electrode of the third transistor M3 .

[0213] Furthermore, the dielectric layer 9 is etched to form a via hole H12 (not shown in the figure), and the via hole H12 exposes the fourth substructure 52 b and the control electrode of the fourth transistor M4 .

[0214] Exemplarily, by adjusting the etching process parameters, the dielectric layer 9 and the control electrode of the transistor have a larger etching selectivity ratio, so that the etching damage to the control electrode of the transistor can be reduced during the etching of the dielectric layer 9 .

[0215] The via hole H11 may not expose the first connection pattern 61 , and the via hole H12 may not expose the second connection pattern 62 . Thus, during the process of etching the dielectric layer 9 , no etching damage is caused to the first connection pattern 61 and the second connection pattern 62 .

[0216] S65: See Figure 12G to Figure 12I , a first substructure 51 a is formed in the via hole H11 .

[0217] Furthermore, a third substructure 52 a is formed in the via hole H12 .

[0218] For example, see Figure 12G and Fig.12H , forming an adhesive layer L covering the via hole H11 and the via hole H12. Then, depositing a metal material so that the metal material fills the via hole H11 and the via hole H12.

[0219] See also Fig.12H and Fig.12I A chemical mechanical polishing process is used to polish and remove excess metal material until the upper surface of the dielectric layer 9 is exposed, thereby obtaining a first substructure 51a located in the via hole H11 and a third substructure 52a located in the via hole H12.

[0220] In the manufacturing method provided by the above-mentioned embodiment of the present application, the via hole H9 and the via hole H10 are first formed by etching the dielectric layer 9, wherein the via hole H9 exposes the first electrode and the first connection pattern 61 of the fourth transistor M4, and the via hole H10 exposes the first electrode and the second connection pattern 62 of the third transistor M3. Therefore, it is necessary to adjust the etching process parameters so that the dielectric layer 9 has a larger etching selectivity with the first electrode and the second electrode of the transistor, the first connection pattern 61 and the second connection pattern 62, so that the etching damage to the first electrode and the second electrode of the transistor, the first connection pattern 61 and the second connection pattern 62 can be reduced during the etching of the dielectric layer 9.

[0221] Furthermore, since the via H9 does not expose the control electrode of the third transistor M3 and the via H10 does not expose the control electrode of the fourth transistor M4, there is no need to consider the etching selectivity ratio of the control electrode of the transistor, etching of the dielectric layer 9 will not cause etching damage to the control electrode of the transistor, and wet cleaning will not cause corrosion to the control electrode of the transistor, thereby increasing the selection range of the electrode material of the transistor.

[0222] The chemical properties of the material of the control electrode of the transistor may not be similar to the chemical properties of the materials of the first connection pattern 61, the second connection pattern 62 and the first electrode and the second electrode of the transistor. For example, the material of the first connection pattern 61 and the second connection pattern 62 includes tungsten, and the material of the first electrode and the second electrode of the transistor can be selected from at least one of tungsten, tungsten silicide, tungsten nitride, titanium nitride, molybdenum, nickel, platinum, palladium or ruthenium, and the material of the control electrode of the transistor can be selected from at least one of tungsten, aluminum or titanium.

[0223] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A storage array, characterized in that: include: A first layer structure and a second layer structure are stacked, wherein the first layer structure includes a first transistor and a second transistor that are adjacent to each other, and the second layer structure includes a third transistor and a fourth transistor that are adjacent to each other; a first conductive structure, at least a portion of which is located between a control electrode of the third transistor and a first electrode of the fourth transistor; the control electrode of the first transistor, the first electrode of the second transistor, the control electrode of the third transistor and the first electrode of the fourth transistor are electrically connected to the first conductive structure respectively; a second conductive structure, at least a portion of which is located between the first electrode of the third transistor and the control electrode of the fourth transistor; the first electrode of the first transistor, the control electrode of the second transistor, the first electrode of the third transistor and the control electrode of the fourth transistor are electrically connected to the second conductive structure respectively; Wherein, the surface of the first layer structure away from the second layer structure is a reference surface; The orthographic projection of the first conductive structure on the reference plane does not overlap with the orthographic projection of the second conductive structure on the reference plane.

2. The storage array according to claim 1, characterized in that: The first transistor and the second transistor are arranged along a first direction; the first layer structure includes a first active layer and a second active layer, the first active layer includes a first electrode and a second electrode of the first transistor, and the second active layer includes a first electrode and a second electrode of the second transistor; The orthographic projection of the first conductive structure on the reference plane overlaps with the orthographic projection of the first active layer on the reference plane; two opposite boundaries of the first conductive structure along the second direction are located within two opposite boundaries of the first active layer along the second direction; the orthographic projection of the second conductive structure on the reference plane overlaps with the orthographic projection of the second active layer on the reference plane; Two opposite boundaries of the second conductive structure along the second direction are located within two opposite boundaries of the second active layer along the second direction; The first direction and the second direction are both parallel to the reference plane, and the first direction intersects with the second direction.

3. The storage array according to claim 1 or 2, characterized in that: The third transistor and the fourth transistor are arranged along a first direction; The first conductive structure and the second conductive structure are arranged along a second direction, the first direction and the second direction are both parallel to the reference plane, and the first direction intersects with the second direction.

4. The storage array according to any one of claims 1 to 3, characterized in that: The control electrode of the third transistor and the first electrode of the fourth transistor are directly in contact with the first conductive structure respectively; The first electrode of the third transistor and the control electrode of the fourth transistor are directly in contact with the second conductive structure respectively.

5. The storage array according to claim 4, characterized in that: The memory array further includes a first connection pattern and a second connection pattern, wherein the first connection pattern is arranged between the first layer structure and the second layer structure, and the second connection pattern is arranged between the first layer structure and the second layer structure; The first conductive structure is electrically connected to the first connection pattern, and the control electrode of the first transistor and the first electrode of the second transistor are electrically connected to the first connection pattern respectively; The second conductive structure is electrically connected to the second connection pattern, and the first electrode of the first transistor and the control electrode of the second transistor are electrically connected to the second connection pattern respectively.

6. The storage array according to claim 5, characterized in that: The first conductive structure includes a first substructure and a second substructure connected to each other, and the second conductive structure includes a third substructure and a fourth substructure connected to each other; The first substructure is electrically connected to the control electrode of the third transistor and the first connection pattern, and the second substructure is electrically connected to the first electrode of the fourth transistor; the third substructure is electrically connected to the control electrode of the fourth transistor and the second connection pattern, and the fourth substructure is electrically connected to the first electrode of the third transistor; or, The first substructure is electrically connected to the control electrode of the third transistor, the second substructure is electrically connected to the first electrode of the fourth transistor and the first connection pattern; the third substructure is electrically connected to the control electrode of the fourth transistor, the fourth substructure is electrically connected to the first electrode of the third transistor and the second connection pattern.

7. The storage array according to any one of claims 1 to 6, characterized in that: The storage array further includes a first transfer layer and a second transfer layer, wherein the first transfer layer is arranged on a side of the first connection pattern close to the second layer structure, and the second transfer layer is arranged on a side of the second connection pattern close to the second layer structure; The first conductive structure is electrically connected to the first connection pattern through the first transfer layer; The second conductive structure is electrically connected to the second connection pattern through the second transfer layer.

8. The storage array according to claim 7, characterized in that: The boundary of the orthographic projection of the first switching layer on the reference surface coincides with the boundary of the orthographic projection of the first conductive structure on the reference surface; the boundary of the orthographic projection of the second switching layer on the reference surface coincides with the boundary of the orthographic projection of the second conductive structure on the reference surface; or, The boundary of the orthographic projection of the first transfer layer on the reference surface coincides with the boundary of the orthographic projection of the first connection pattern on the reference surface; the boundary of the orthographic projection of the second transfer layer on the reference surface coincides with the boundary of the orthographic projection of the second connection pattern on the reference surface.

9. The storage array according to any one of claims 1 to 8, characterized in that: The material of the first conductive structure includes at least one of copper, tungsten, titanium nitride, titanium, cobalt, nickel, ruthenium or tantalum; The material of the second conductive structure includes at least one of copper, tungsten, titanium nitride, titanium, cobalt, nickel, ruthenium or tantalum.

10. A method for preparing a storage array, characterized in that: include: forming a first layer structure and a second layer structure stacked together, wherein the first layer structure includes a first transistor and a second transistor disposed adjacent to each other, and the second layer structure includes a third transistor and a fourth transistor disposed adjacent to each other; forming a first conductive structure and a second conductive structure, wherein at least a portion of the first conductive structure is located between the control electrode of the third transistor and the first electrode of the fourth transistor, and the control electrode of the first transistor, the first electrode of the second transistor, the control electrode of the third transistor, and the first electrode of the fourth transistor are electrically connected to the first conductive structure respectively; At least a portion of the second conductive structure is located between the first electrode of the third transistor and the control electrode of the fourth transistor, and the first electrode of the first transistor, the control electrode of the second transistor, the first electrode of the third transistor and the control electrode of the fourth transistor are electrically connected to the second conductive structure respectively; Wherein, the surface of the first layer structure away from the second layer structure is a reference surface; The orthographic projection of the first conductive structure on the reference plane does not overlap with the orthographic projection of the second conductive structure on the reference plane.

11. The preparation method according to claim 10, characterized in that: After forming the first layer structure and before forming the second layer structure, the preparation method further includes: A first connection pattern and a second connection pattern are formed on the first layer structure, the control electrode of the first transistor and the first electrode of the second transistor are electrically connected to the first connection pattern respectively, and the first electrode of the first transistor and the control electrode of the second transistor are electrically connected to the second connection pattern respectively.

12. The preparation method according to claim 11, characterized in that: The first conductive structure includes a first substructure and a second substructure connected to each other, and the second conductive structure includes a third substructure and a fourth substructure connected to each other; Forming the first conductive structure and the second conductive structure includes: forming a dielectric layer, wherein the dielectric layer covers the third transistor and the fourth transistor; Etching the dielectric layer to form a first via hole and a second via hole; the first via hole exposes the control electrode of the third transistor and the first connection pattern, and the second via hole exposes the control electrode of the fourth transistor and the second connection pattern; forming the first substructure in the first via hole, and forming the third substructure in the second via hole; The dielectric layer is etched to form a third via hole and a fourth via hole; the third via hole exposes the first substructure and the first electrode of the fourth transistor, and the fourth via hole exposes the third substructure and the first electrode of the third transistor; The second substructure is formed in the third via hole, and the fourth substructure is formed in the fourth via hole.

13. The preparation method according to claim 11, characterized in that: The first conductive structure includes a first substructure and a second substructure connected to each other, and the second conductive structure includes a third substructure and a fourth substructure connected to each other; Forming the first conductive structure and the second conductive structure includes: forming a dielectric layer, wherein the dielectric layer covers the third transistor and the fourth transistor; Etching the dielectric layer to form a first via hole and a second via hole; the first via hole exposes the first electrode of the fourth transistor and the first connection pattern, and the second via hole exposes the first electrode of the third transistor and the second connection pattern; forming the second substructure in the first via hole, and forming the fourth substructure in the second via hole; Etching the dielectric layer to form a third via hole and a fourth via hole; the third via hole exposes the first substructure and the control electrode of the third transistor, and the fourth via hole exposes the third substructure and the control electrode of the fourth transistor; The first substructure is formed in the third via hole, and the third substructure is formed in the fourth via hole.

14. The preparation method according to claim 11, characterized in that: Forming the first conductive structure and the second conductive structure includes: forming a dielectric layer, wherein the dielectric layer covers the third transistor and the fourth transistor; Etching the dielectric layer to form a fifth via hole and a sixth via hole; the fifth via hole exposes the control electrode of the third transistor, the first electrode of the fourth transistor and the first connection pattern, and the sixth via hole exposes the first electrode of the third transistor, the control electrode of the fourth transistor and the second connection pattern; A first conductive structure is formed in the fifth via hole, and a second conductive structure is formed in the sixth via hole.

15. The preparation method according to claim 14, characterized in that: After forming the first connection pattern and the second connection pattern, the preparation method further includes: forming a first transfer layer and a second transfer layer, wherein the first transfer layer is located on a side of the first connection pattern away from the first layer structure, and the second transfer layer is located on a side of the second connection pattern away from the first layer structure; After the first conductive structure and the second conductive structure are formed, the first conductive structure is electrically connected to the first connection pattern through the first transfer layer, and the second conductive structure is electrically connected to the second connection pattern through the second transfer layer.

16. The preparation method according to claim 15, characterized in that: Using the same mask to form the first connection pattern and the first transfer layer; using the same mask to form the second connection pattern and the second transfer layer; or, Using the same mask to form the first transfer layer and the fifth via hole; The second transfer layer and the sixth via hole are formed by using the same mask.

17. A memory, characterized in that: include: The storage array according to any one of claims 1 to 9; A controller is electrically connected to the storage array.

18. An electronic device, characterized in that: include: processor; The memory of claim 17, electrically connected to the processor.

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