Three-dimensional memory, preparation method thereof, memory system and electronic equipment

Abstract

The invention provides a three-dimensional memory, a preparation method thereof, a storage system and electronic equipment, relates to the technical field of semiconductors, and aims to improve the storage capacity of the three-dimensional memory in unit area. The three-dimensional memory comprises a first stack structure, a second stack structure, a first communication structure, a second channel structure and a source layer. The first stack structure includes a plurality of first gate layers. The second stack structure includes a plurality of second gate layers. The first channel structure penetrates through the first stack structure. The second channel structure penetrates through the second stack structure. In the stacking direction of the first stacking structure, the source electrode layer is located between the first stacking structure and the second stacking structure, and the first channel structure and the second channel structure are electrically connected with the source electrode layer. The three-dimensional memory is applied to the electronic equipment so as to improve the memory space of the electronic equipment.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a three-dimensional memory and a preparation method thereof, a storage system, and an electronic device. Background Art

[0002] As the feature size of memory cells approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach an upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed a memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate. At present, how to further increase the storage capacity per unit area of ​​3D memory is a problem that needs to be solved. Summary of the invention

[0004] Embodiments of the present disclosure provide a three-dimensional memory and a manufacturing method thereof, a storage system, and an electronic device to increase the storage capacity per unit area of ​​the three-dimensional memory.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] On the one hand, a three-dimensional memory is provided. The three-dimensional memory includes a first stacking structure, a second stacking structure, a first channel structure, a second channel structure and a source layer. The first stacking structure includes a plurality of first gate layers. The second stacking structure includes a plurality of second gate layers. The first channel structure runs through the first stacking structure. The second channel structure runs through the second stacking structure. Along the stacking direction of the first stacking structure, the source layer is located between the first stacking structure and the second stacking structure; the first channel structure and the second channel structure are both connected to the source layer.

[0007] In the three-dimensional memory provided in the above embodiment of the present disclosure, the first stacking structure includes a plurality of first gate layers, the second stacking structure includes a plurality of second gate layers, the first gate layer and the first channel structure form a plurality of storage cells, and the second gate layer and the second channel structure also form a plurality of storage cells. In this way, the three-dimensional memory provided by the present disclosure has stacking structures (i.e., the first stacking structure and the second stacking structure) arranged on both sides of the source layer. Compared with the solution of only arranging the stacking structure on one side of the source layer, the number of storage cells per unit area of ​​the three-dimensional memory can be greater, so that the storage capacity per unit area of ​​the three-dimensional memory can be larger.

[0008] The first channel structure penetrates the first stacking structure, and the second channel structure penetrates the second stacking structure. Compared with the case where the first channel structure penetrates the first stacking structure and the second stacking structure, or the second channel structure penetrates the first stacking structure and the second stacking structure, the aspect ratio of the first channel structure can be smaller, and the aspect ratio of the second channel structure can also be smaller, so that the preparation difficulty of the first channel structure can be smaller, and the preparation difficulty of the second channel structure can also be smaller.

[0009] Compared with the solution of preparing a stacked structure on one side of the source layer, dividing the stacked structure into multiple stacked layers, and forming multiple channel structures in the multiple stacked layers of the stacked structure, the present disclosure does not need to align the first channel structure and the second channel structure, as long as the first channel structure and the second channel structure are both connected to the source layer. This effectively avoids the problems of damage to the storage function layer in the channel structure, leakage of the channel layer, or incomplete etching of the channel structure due to alignment failure or deviation.

[0010] In some embodiments, the three-dimensional memory further includes a first peripheral device layer, a first array interconnect layer, a second array interconnect layer and a first connection structure. The first peripheral device layer is located on a side of the first stacked structure away from the source layer. The first array interconnect layer is located between the first stacked structure and the first peripheral device layer. The first array interconnect layer includes a first bit line. The first peripheral device layer is connected to the first channel structure through the first bit line. The second array interconnect layer is located on a side of the second stacked structure away from the source layer. The second array interconnect layer includes a second bit line, and the second bit line is connected to the second channel structure. The first connection structure runs through the first stacked structure, the second stacked structure and the source layer, and is insulated from the multiple first gate layers, the multiple second gate layers and the source layer. Wherein, the first bit line is connected to the second bit line through the first connection structure.

[0011] In some embodiments, the first stacking structure and the second stacking structure each include a first storage block and a second storage block; the first channel structure and the second channel structure are located in the first storage block, and the first connection structure is located in the second storage block.

[0012] In some embodiments, the first stacking structure and the second stacking structure include a plurality of the first storage blocks and a plurality of the second storage blocks, and any two adjacent second storage blocks among the plurality of the second storage blocks are separated by at least one first storage block.

[0013] In some embodiments, the three-dimensional memory further includes a second peripheral device layer, a third peripheral device layer, a third array interconnect layer, and a fourth array interconnect layer.

[0014] The second peripheral device layer is located on a side of the first stacked structure away from the source layer. The third peripheral device layer is located on a side of the second stacked structure away from the source layer. The third array interconnect layer is located between the second peripheral device layer and the first stacked structure, the third array interconnect layer includes a third bit line, and the second peripheral device layer is connected to the first channel structure through the third bit line. The fourth array interconnect layer is located between the third peripheral device layer and the second stacked structure, the fourth array interconnect layer includes a fourth bit line, and the third peripheral device layer is connected to the second channel structure through the fourth bit line.

[0015] In some embodiments, the three-dimensional memory further includes an external connection structure and a third connection structure. The external connection structure runs through the second peripheral device layer. The third connection structure runs through the first stacked structure, the second stacked structure, and the source layer, and is insulated from the plurality of first gate layers, the plurality of second gate layers, and the source layer.

[0016] Among them, the third array interconnection layer also includes a first switching structure, the fourth array interconnection layer also includes a second switching structure, one end of the third connection structure is connected to the external connection structure through the first switching structure, and the other end is connected to the third peripheral device layer through the second switching structure.

[0017] In some embodiments, the first stacked structure and the second stacked structure each include a preset surface away from the source layer. The three-dimensional memory further includes a first gate contact and a second gate contact. The first gate contact extends from the preset surface of the first stacked structure to a corresponding first gate layer among the plurality of first gate layers, and is connected to the corresponding first gate layer. The second gate contact extends from the preset surface of the second stacked structure to a corresponding second gate layer among the plurality of second gate layers, and is connected to the corresponding second gate layer.

[0018] In some embodiments, when the three-dimensional memory includes a first peripheral device layer, a first array interconnect layer, and a second array interconnect layer, the first array interconnect layer also includes a first gate line and a second gate line, the first gate contact is connected to the first peripheral device layer through the first gate line; the second gate line is connected to the first peripheral device layer; the second array interconnect layer also includes a connecting line, and the connecting line is connected to the second gate contact.

[0019] The three-dimensional memory also includes a second connection structure, which runs through the first stacking structure, the second stacking structure and the source layer, and is insulated from the multiple first gate layers, the multiple second gate layers and the source layer; the second gate contact is connected to the second connection structure through the connecting line, and the second connection structure is connected to the first peripheral device layer through the second gate line.

[0020] In some embodiments, when the three-dimensional memory includes a second peripheral device layer, a third peripheral device layer, a third array interconnection layer and a fourth array interconnection layer, the third array interconnection layer further includes a third gate line, the fourth array interconnection layer further includes a fourth gate line, the first gate contact is connected to the second peripheral device layer through the third gate line, and the second gate contact is connected to the third peripheral device layer through the fourth gate line.

[0021] In some embodiments, the first connection structure, the second connection structure, and the third connection structure each include a first sub-section, a second sub-section, and a third sub-section. The first sub-section runs through the first stacked structure and is insulated from the plurality of first gate layers. The second sub-section runs through the second stacked structure and is insulated from the plurality of second gate layers. The third sub-section runs through the source layer and is insulated from the source layer. The first sub-section and the second sub-section are both connected to the third sub-section.

[0022] In some embodiments, in at least one of the first connecting structure, the second connecting structure, and the third connecting structure, a cross-section of the first sub-portion along a first set direction is the same as a cross-sectional shape of the first channel structure along the first set direction, and a cross-section of the second sub-portion along the first set direction is the same as a cross-sectional shape of the second channel structure along the first set direction; the first setting direction is parallel to the stacking direction of the first stacking structure.

[0023] In some embodiments, the three-dimensional memory includes a plurality of second gate contacts and a plurality of second connection structures correspondingly connected to the plurality of second gate contacts; the first stacking structure and the second stacking structure both include a first storage block and a second storage block. In the first storage block and / or the second storage block, the plurality of second gate contacts are arranged in two rows along the second setting direction, the plurality of second connection structures are arranged in two rows along the second setting direction, and the two rows of the second connection structures are located between the two rows of the second gate contacts; the second setting direction is parallel to the surface of the first stacking structure away from the source layer.

[0024] In some embodiments, an area of ​​an end surface of the second gate contact away from the source layer is greater than an area of ​​an end surface of the second sub-portion of the second connection structure away from the source layer.

[0025] In some embodiments, in at least one of the first connection structure, the second connection structure and the third connection structure, a cross-section of the first sub-portion along a first set direction is the same as a cross-sectional shape of a first gate contact of the three-dimensional memory along the first set direction, and a cross-section of the second sub-portion along the first set direction is the same as a cross-sectional shape of a second gate contact of the three-dimensional memory along the first set direction; the first set direction is parallel to the stacking direction of the first stacking structure.

[0026] In some embodiments, the three-dimensional memory includes a plurality of second gate contacts and a plurality of second connection structures correspondingly connected to the plurality of second gate contacts. The first stacking structure and the second stacking structure each include a first memory block and a second memory block.

[0027] In the first storage block and / or the second storage block, the multiple second gate contacts are arranged into two rows along a second set direction, some of the multiple second connection structures are arranged into at least one row along the second set direction, the at least one row of second connection structures is located between two rows of second gate contacts, and the remaining second connection structures of the multiple second connection structures are dispersed in the two rows of second gate contacts.

[0028] Alternatively, in the first storage block and / or the second storage block, the multiple second gate contacts and the multiple second connection structures are arranged in two rows along the second set direction, and in the same row, the second gate contacts and the second connection structures are alternately arranged; the second set direction is parallel to the surface of the first stacking structure away from the source layer.

[0029] In some embodiments, an area of ​​an end surface of the second gate contact away from the source layer is equal to an area of ​​an end surface of the second sub-portion of the second connection structure away from the source layer.

[0030] In some embodiments, in a direction parallel to the preset surface, a dimension of an end of the first gate contact away from the source layer is larger than a dimension of an end of the first gate contact close to the source layer, and a dimension of an end of the second gate contact away from the source layer is larger than a dimension of an end of the second gate contact close to the source layer.

[0031] In some embodiments, the first channel structure and the second channel structure each include at least one sub-channel structure; in a direction parallel to the preset surface, a size of an end of the sub-channel structure away from the source layer is larger than a size of an end of the sub-channel structure close to the source layer; the preset surface is a surface of the first channel structure away from the source layer.

[0032] In some embodiments, the first channel structure and the second channel structure each include at least one sub-channel structure; in a direction parallel to the preset surface, a size of an end of the sub-channel structure away from the source layer is smaller than a size of an end of the sub-channel structure close to the source layer; the preset surface is a surface of the first channel structure away from the source layer.

[0033] In some embodiments, the first channel structure includes a first channel layer, and the second channel structure includes a second channel layer; the first channel layer extends into the source layer, and the second channel layer extends into the source layer.

[0034] In some embodiments, the three-dimensional memory further includes a first source contact and a second source contact. The first source contact penetrates the first stacked structure and is connected to the source layer. The second source contact penetrates the second stacked structure and is connected to the source layer.

[0035] In a case where the three-dimensional memory includes a first peripheral device layer and a first array interconnect layer, the first source contact is connected to the first peripheral device layer through the first array interconnect layer.

[0036] When the three-dimensional memory includes a second peripheral device layer, a third peripheral device layer, a third array interconnect layer and a fourth array interconnect layer, the first source contact is connected to the second peripheral device layer through the third array interconnect layer, and the second source contact is connected to the third peripheral device layer through the fourth array interconnect layer.

[0037] On the other hand, a method for preparing a three-dimensional memory is provided. The preparation method includes forming a first stacking structure and a first channel structure on a first substrate. The first stacking structure includes a plurality of first gate layers, and the first channel structure penetrates the first stacking structure. The first substrate is removed. A first sublayer is formed on the first stacking structure, and the first sublayer is connected to the first channel structure. A second stacking structure and a second channel structure are formed on a second substrate; the second stacking structure includes a plurality of second gate layers, and the second channel structure penetrates the second stacking structure. The second substrate is removed. A second sublayer is formed on the second stacking structure, and the second sublayer is connected to the second channel structure. The first sublayer and the second sublayer are combined to form a source layer; along the stacking direction of the first stacking structure, the source layer is located between the first stacking structure and the second stacking structure.

[0038] In some embodiments, the fabrication method includes forming a first gate contact; and forming a second gate contact.

[0039] The first gate contact extends from a surface of the first stacking structure away from the first substrate to a corresponding first gate layer among the multiple first gate layers, and is connected to the corresponding first gate layer; or, the first gate contact extends from a surface of the first stacking structure used to contact the first substrate to a corresponding first gate layer among the multiple first gate layers, and is connected to the corresponding first gate layer.

[0040] The second gate contact extends from the surface of the second stacking structure away from the second substrate to the corresponding second gate layer among the multiple second gate layers, and is connected to the corresponding second gate layer; or, the second gate contact extends from the surface of the second stacking structure used for contacting the second substrate to the corresponding second gate layer among the multiple second gate layers, and is connected to the corresponding second gate layer.

[0041] In some embodiments, after forming the first gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method further includes forming a first array interconnect layer on the first stacked structure; the first array interconnect layer includes a first bit line, a first gate line, and a second gate line, the first bit line is connected to the first channel structure, and the first gate line is connected to the first gate contact. The first array interconnect layer is bonded to a first peripheral device layer. The first peripheral device layer is connected to the first bit line, the first gate line, and the second gate line.

[0042] After forming the second gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method also includes forming a second array interconnection layer on the second stacked structure, the second array interconnection layer including a second bit line and a connecting line, the second bit line is connected to the second channel structure and the first bit line, and the connecting line is in contact with the second gate and connected to the second gate line.

[0043] In some embodiments, the three-dimensional memory further includes a first connection structure and a second connection structure, and the first connection structure and the second connection structure each include a first sub-portion that runs through the first stacking structure and a second sub-portion that runs through the second stacking structure. The preparation method further includes forming a first sub-portion of the first connection structure and a first sub-portion of the second connection structure while forming the first gate contact; forming a second sub-portion of the first connection structure and a second sub-portion of the second connection structure while forming the second gate contact;

[0044] Alternatively, while forming the first channel structure, the first subsection of the first connection structure and the first subsection of the second connection structure are formed; while forming the second channel structure, the second subsection of the first connection structure and the second subsection of the second connection structure are formed.

[0045] Alternatively, a first subsection of the second connection structure is formed while the first gate contact is formed; a second subsection of the second connection structure is formed while the second gate contact is formed; a first subsection of the first connection structure is formed while the first channel structure is formed; and a second subsection of the first connection structure is formed while the second channel structure is formed.

[0046] In some embodiments, after forming the first gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method further includes forming a third array interconnect layer on the first stacked structure, the third array interconnect layer including a third bit line and a third gate line, the third bit line is connected to the first channel structure, and the third gate line is connected to the first gate contact. The third array interconnect layer is bonded to the second peripheral device layer; the third bit line and the third gate line are both connected to the second peripheral device layer.

[0047] After forming the second gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method further includes forming a fourth array interconnection layer on the second stacked structure, the fourth array interconnection layer including a fourth bit line and a fourth gate line, the fourth bit line is connected to the second channel structure, and the fourth gate line is connected to the second gate contact. The fourth array interconnection layer is bonded to a third peripheral device layer; the fourth bit line and the fourth gate line are both connected to the third peripheral device layer.

[0048] In some embodiments, the three-dimensional memory also includes a third connection structure, the third connection structure includes a first sub-portion extending through the first stacking structure, and a second sub-portion extending through the second stacking structure; the preparation method also includes forming the first sub-portion of the third connection structure while forming the first gate contact; and forming the second sub-portion of the third connection structure while forming the second gate contact.

[0049] Alternatively, the first sub-portion of the third connection structure is formed while the first channel structure is formed; and the second sub-portion of the third connection structure is formed while the second channel structure is formed.

[0050] On the other hand, a storage system is provided, comprising: a three-dimensional memory as described in any one of the above embodiments, and a controller coupled to the three-dimensional memory to control the three-dimensional memory to store data.

[0051] In another aspect, an electronic device is provided, comprising the storage system as described above.

[0052] It can be understood that the beneficial effects that can be achieved by the method for preparing the three-dimensional memory, the storage system, and the electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the three-dimensional memory described above, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0054] Figure 1 is a top view schematic diagram of a three-dimensional memory according to some embodiments;

[0055] Figure 2 is a bottom view schematic diagram of a three-dimensional memory according to some embodiments;

[0056] Figure 3 for Figure 1 A cross-sectional view of the three-dimensional memory along the section line AA' shown;

[0057] Figure 4 for Figure 3 An enlarged schematic diagram of the three-dimensional memory at MM is shown;

[0058] Figure 5 for Figure 1 Another cross-sectional view of the three-dimensional memory along the cross-sectional line AA' shown;

[0059] Figure 6 for Figure 5 An enlarged schematic diagram of the three-dimensional memory at the NN is shown;

[0060] Figure 7 is a schematic diagram of the structure of a storage unit string according to some embodiments;

[0061] Figure 8 for Figure 1 A cross-sectional view of the three-dimensional memory along the section line BB' shown;

[0062] Fig. 9 for Figure 1 Another cross-sectional view of the three-dimensional memory shown along the cross-sectional line BB';

[0063] Fig.10 is a schematic diagram of a structure of a three-dimensional memory according to some embodiments;

[0064] Fig.11 is another schematic diagram of the structure of a three-dimensional memory according to some embodiments;

[0065] Fig.12 is another bottom view schematic diagram of a three-dimensional memory according to some embodiments;

[0066] Fig.13 for Fig.12 Another cross-sectional view of the three-dimensional memory shown along the cross-sectional line CC';

[0067] Fig.14 for Fig.12 Another cross-sectional view of the three-dimensional memory along the cross-sectional line DD' shown;

[0068] Fig.15 is another structural schematic diagram of a three-dimensional memory according to some embodiments;

[0069] Fig.16 is a partial bottom view schematic diagram of a three-dimensional memory according to some embodiments;

[0070] Fig.17 is a schematic flow chart of a method for preparing a three-dimensional memory according to some embodiments;

[0071] Fig.18 for Fig.17 The structural state diagram of the three-dimensional memory corresponding to step S100 in the flowchart shown;

[0072] Fig.19 is another schematic flow chart of a method for preparing a three-dimensional memory according to some embodiments;

[0073] Fig. 20 for Fig.19 The structural state diagram of the three-dimensional memory corresponding to step S110 in the flowchart shown;

[0074] Fig.21 for Fig.19 The structural state diagram of the three-dimensional memory corresponding to step S120 in the flowchart shown;

[0075] Figure 22 to Figure 24 for Fig.17A structural state diagram of a three-dimensional memory corresponding to steps S200 to S400 in the flowchart shown;

[0076] Fig.25 is another schematic flow chart of a method for preparing a three-dimensional memory according to some embodiments;

[0077] Figure 26 to Figure 28 for Fig.17 A structural state diagram of a three-dimensional memory corresponding to steps S500 to S700 in the flowchart shown;

[0078] Figure 29 to Figure 39 The structural state diagram of the three-dimensional memory corresponding to step S810, step S820, step S830, step S812, step S813, step S910, step S920, step S930, step S940 and step S960 in the preparation method according to some embodiments is shown in sequence;

[0079] Fig.40 is a block diagram of a storage system according to some embodiments;

[0080] Fig.41 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0081] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0082] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0083] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0084] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0085] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0086] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0087] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0088] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0089] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0090] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of variation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0091] In the context of this disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “on” or “over” something, but also includes the meaning of “on” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0092] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0093] The present disclosure provides a three-dimensional memory 100. Figure 1 A schematic top view of a three-dimensional memory 100 provided by the present disclosure is shown in FIG. Figure 2 A bottom-view schematic diagram of the three-dimensional memory 100 provided by the present disclosure. Figure 3 for Figure 1 The schematic cross-sectional view of the three-dimensional memory at AA' is shown below. Figure 1 to Figure 3 The three-dimensional memory provided by the present disclosure is introduced in detail.

[0094] like Figure 1 to Figure 3 As shown, the three-dimensional memory 100 includes a first stacking structure 10, a second stacking structure 20, a first channel structure 30, a second channel structure 40 and a source layer SL. The first stacking structure 10 includes a plurality of first gate layers 11. The second stacking structure 20 includes a plurality of second gate layers 21. The first channel structure 30 runs through the first stacking structure 10. The second channel structure 40 runs through the second stacking structure 20. Along the stacking direction Z of the first stacking structure 10, the source layer SL is located between the first stacking structure 10 and the second stacking structure 20. The first channel structure 30 and the second channel structure 40 are both connected to the source layer SL.

[0095] Figure 4 for Figure 3 The enlarged schematic diagram of the three-dimensional memory 100 at MM is shown. Figure 4 As shown, in some examples, the first gate layer 11 and the second gate layer 21 may each include an interface layer 111, an adhesive layer 112 and a conductive layer 113. The interface layer 111 wraps the conductive layer 113, and the adhesive layer 112 is located between the interface layer 111 and the conductive layer 113.

[0096] Exemplarily, the interface layer 111 wraps the conductive layer 113 and is located between the conductive layer 113 and the first channel structure 30 to reduce the risk of charges in the first channel structure 30 flowing to the conductive layer 113. The interface layer 111 wraps the conductive layer 113 and is located between the conductive layer 113 and the second channel structure 40 to reduce the risk of charges in the second channel structure 40 flowing to the conductive layer 113. The dielectric constant value of the interface layer 111 may be greater than or equal to 7. Exemplarily, the material of the interface layer 111 includes at least one of aluminum oxide, hafnium oxide, and tantalum oxide.

[0097] The adhesive layer 112 is used to improve the adhesion between the interface layer 111 and the conductive layer 113. The material of the adhesive layer 112 may include at least one of titanium nitride, tantalum nitride and tungsten carbide.

[0098] The material of the conductive layer 113 may include a conductive material, and the conductive material is, for example, at least one of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

[0099] In order to insulate the plurality of first gate layers 11, as Figure 3 and Figure 4 As shown, the first stacked structure 10 may further include a plurality of first insulating layers 12, and the first insulating layer 12 is located between any two adjacent first gate layers 11. Similarly, in order to insulate the plurality of second gate layers 21, the second stacked structure 20 may further include a plurality of second insulating layers 22, and the second insulating layer 22 is located between any two adjacent second gate layers 21.

[0100] The materials of the first insulating layer 12 and the second insulating layer 22 may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (such as aluminum oxide, hafnium dioxide, etc.) and silicates thereof, and organic insulating materials. Exemplarily, the materials of the first insulating layer 12 and the second insulating layer 22 may be the same.

[0101] The present disclosure does not limit the number of first gate layers 11 and first insulating layers 12 in the first stacked structure 10, and can be designed according to actual needs. Similarly, the present disclosure does not limit the number of second gate layers 21 and second insulating layers 22 in the second stacked structure 20, and can be designed according to actual needs.

[0102] In some examples, the number of the first gate layer 11 and the first insulating layer 12 in the first stacked structure 10 may be equal to the number of the second gate layer 21 and the second insulating layer 22 in the second stacked structure 20. This is beneficial to balance the stress on both sides of the source layer SL and improve the structural stability of the three-dimensional memory 100.

[0103] It can be understood that “the stacking direction Z of the first stacking structure 10 ” is also the stacking direction of the second stacking structure 20 .

[0104] In some examples, such as Figure 4 As shown, the first channel structure 30 includes a first channel layer 31 and a first storage function layer 32. The second channel structure 40 includes a second channel layer 41 and a second storage function layer 42.

[0105] Exemplarily, the materials of the first channel layer 31 and the second channel layer 41 may include semiconductor materials, such as polysilicon or amorphous silicon.

[0106] Exemplarily, the first storage function layer 32 and the second storage function layer 42 include a blocking layer 321, a charge trapping layer 322, and a tunneling layer 323. The materials of the blocking layer 321, the charge trapping layer 322, and the tunneling layer 323 can be silicon oxide, silicon nitride, and silicon oxide, respectively, to form an "ONO" structure.

[0107] In some examples, such as Figure 4 As shown, the first channel structure 30 may further include a first filling layer 33 , and the second channel structure 40 may further include a second filling layer 43 .

[0108] The materials of the first filling layer 33 and the second filling layer 43 may be insulating materials, such as silicon oxide, etc. Exemplarily, the materials of the first filling layer 33 and the second filling layer 43 may be the same.

[0109] In some examples, such as Figure 3 As shown, the first channel structure 30 and the second channel structure 40 each include at least one sub-channel structure CH.

[0110] The above-mentioned “the first channel structure 30 and the second channel structure 40 each include at least one sub-channel structure CH” includes both the case where the first channel structure 30 and the second channel structure 40 include one sub-channel structure CH and the case where the first channel structure 30 and the second channel structure 40 include multiple sub-channel structures CH. Figure 3 In the figure, the first channel 30 and the second channel structure 40 both include two sub-channel structures CH.

[0111] When both the first channel structure 30 and the second channel structure 40 include a plurality of sub-channel structures CH, the plurality of sub-channel structures CH may be formed in steps, thereby reducing the difficulty of manufacturing the first channel structure 30 and the second channel structure 40 and improving the manufacturing efficiency of the three-dimensional memory 100 .

[0112] For example, Figure 3 As shown, in the direction X0 parallel to the surface of the first stacked structure 10 away from the source layer SL (ie, the preset surface S1), the size of one end of the sub-channel structure CH away from the source layer SL is larger than the size of one end of the sub-channel structure CH close to the source layer SL.

[0113] Or, if Figure 5 As shown, in the direction X0 parallel to the surface of the first stacked structure 10 away from the source layer SL (ie, the preset surface S1), the size of one end of the sub-channel structure CH away from the source layer SL is smaller than the size of one end of the sub-channel structure CH close to the source layer SL.

[0114] “Both the first channel structure 30 and the second channel structure 40 are connected to the source layer SL”, that is, the first channel layer 31 in the first channel structure 30 is connected to the source layer SL, and the second channel layer 41 in the second channel structure 40 is connected to the source layer SL.

[0115] In some examples, such as Figure 4 As shown, the first channel layer 31 extends into the source layer SL, and the second channel layer 41 extends into the source layer SL.

[0116] In other examples, such as Figure 5 and Figure 6 As shown, the first channel layer 31 and the second channel layer 41 are both in contact with the source layer.

[0117] In some other examples, one of the first channel layer 31 and the second channel layer 41 extends into the source layer SL, and the other abuts against the source layer SL. For example, the first channel layer 31 extends into the source layer SL, and the second channel layer 41 abuts against the source layer SL. For another example, the second channel layer 41 extends into the source layer SL, and the first channel layer 31 abuts against the source layer SL.

[0118] In some examples, the material of the source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V group compound semiconductor materials, II-VI group compound semiconductor materials, and other suitable semiconductor materials.

[0119] The first stack structure 10 and the second stack structure 20 may include array-arranged memory cell transistor strings (referred to herein as “memory cell strings”, such as NAND memory cell strings) 110. The source layer SL may be coupled to source terminals of the plurality of memory cell strings 110.

[0120] Specifically, see Figure 7 , the memory cell string 110 may include a plurality of transistors T, a transistor T (eg Figure 7 The transistors T1 to T6 in the embodiment can be set as a memory cell, and these transistors T are connected together to form a memory cell string. The transistor T (for example, each transistor T) can be formed by a first channel structure 30 and a first gate layer 11 surrounding the first channel structure 30, or can be formed by a second channel structure 40 and a second gate layer 21 surrounding the second channel structure 40. The first gate layer 11 and the second gate layer 21 are configured to control the conduction state of the transistor.

[0121] It should be noted that Figure 7 The number of transistors is only illustrative, and the memory cell string 110 of the three-dimensional memory 100 provided in the embodiment of the present disclosure may also include other numbers of transistors, such as 4, 16, 32, or 64.

[0122] Further, the gate layer closest to the source layer SL among the multiple first gate layers 11 and the multiple second gate layers 21 is constructed as a source selection gate SGS, and the source selection gate SGS is configured to control the conduction state of the transistor T6, thereby controlling the conduction state of the source channel in the memory cell string. The gate layer farthest from the source layer among the multiple gate layers is constructed as a drain selection gate SGD, and the drain selection gate SGD is configured to control the conduction state of the transistor T1, thereby controlling the conduction state of the drain channel in the memory cell string. The gate layer located in the middle of the multiple gate layers can be constructed as multiple word lines WL, for example, including word line WL0, word line WL1, word line WL2, and word line WL3. By writing different voltages on the word line WL, data writing, reading, and erasing of each memory cell (such as transistor T) in the memory cell string can be completed.

[0123] In the three-dimensional memory 100 provided by the present disclosure, the first stacking structure 10 includes a plurality of first gate layers 11, the second stacking structure 20 includes a plurality of second gate layers 21, the first gate layers 11 and the first channel structure 30 form a plurality of memory cells, and the second gate layers 21 and the second channel structure 40 also form a plurality of memory cells. In this way, the three-dimensional memory 100 provided by the present disclosure has stacking structures (i.e., the first stacking structure 10 and the second stacking structure 20) arranged on both sides of the source layer SL. Compared with the solution of only arranging the stacking structure on one side of the source layer SL, the number of memory cells per unit area of ​​the three-dimensional memory 100 can be greater, so that the storage capacity per unit area of ​​the three-dimensional memory 100 can be larger.

[0124] The first channel structure 30 penetrates the first stacking structure 10, and the second channel structure 40 penetrates the second stacking structure 20. Compared with the case where the first channel structure penetrates the first stacking structure 10 and the second stacking structure 20, or the second channel structure 40 penetrates the first stacking structure 10 and the second stacking structure 20, the aspect ratio of the first channel structure 30 can be smaller, and the aspect ratio of the second channel structure 40 can also be smaller, so that the preparation difficulty of the first channel structure 30 can be smaller, and the preparation difficulty of the second channel structure 40 can also be smaller.

[0125] Compared with the solution of preparing a stacked structure on one side of the source layer, dividing the stacked structure into multiple stacked layers, and forming multiple channel structures in the multiple stacked layers of the stacked structure, the present disclosure does not need to align the first channel structure 30 and the second channel structure 40, as long as the first channel structure 30 and the second channel structure 40 are both connected to the source layer SL. This effectively avoids the problems of damage to the storage function layer in the channel structure, leakage of the channel layer, or incomplete etching of the channel structure due to alignment failure or deviation.

[0126] In some embodiments, Figure 3 and Figure 5As shown, the three-dimensional memory 100 further includes a first peripheral device layer 50, a first array interconnection layer 60, a second array interconnection layer 70 and a first connection structure L1. The first peripheral device layer 50 is located on a side of the first stacked structure 10 away from the source layer SL. The first array interconnection layer 60 is located between the first stacked structure 10 and the first peripheral device layer 50. The first array interconnection layer 60 includes a first bit line BL1. The first peripheral device layer 50 is connected to the first channel structure 30 through the first bit line BL1. The second array interconnection layer 70 is located on a side of the second stacked structure 20 away from the source layer SL. The second array interconnection layer 70 includes a second bit line BL2, and the second bit line BL2 is connected to the second channel structure 40. The first connection structure L1 runs through the first stacked structure 10, the second stacked structure 20 and the source layer SL, and is insulated from the above-mentioned multiple first gate layers 11, the above-mentioned multiple second gate layers 21, and the source layer SL. Among them, the first bit line BL1 is connected to the second bit line BL2 through the first connection structure L1.

[0127] The first peripheral device layer 50 may include peripheral circuits configured to control and sense array devices. The peripheral circuits may be any suitable digital, analog, and / or mixed signal control and sensing circuits for supporting array device operations (or work), including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuits may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs) or storage circuits (e.g., static random access memories (SRAMs)).

[0128] The material of the first bit line BL1 and the second bit line BL2 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials.

[0129] It should be noted that Figure 1 The number of the first bit line BL1 is only an example. Figure 2 The number of the second bit lines BL2 is also only an example, and the number of the first bit lines BL1 and the number of the second bit lines BL2 in the present disclosure are not limited. The number of the first bit lines BL1 and the number of the second bit lines BL2 in the present disclosure are not limited and can be designed according to actual needs.

[0130] In some examples, the number of the first bit lines BL1 and the second bit lines BL2 may be the same. In some examples, the material of the first bit lines BL1 and the second bit lines BL2 may be the same.

[0131] In some examples, such as Figure 3 and Figure 5 As shown, the first array interconnection layer 60 may further include a first interlayer insulating layer 61 and a first contact 62. The first interlayer insulating layer 61 may be located between the first bit line BL1 and the first stacked structure 10 to insulate the first bit line BL1 from the first stacked structure 10. The first contact 62 penetrates the first interlayer insulating layer 61 to connect the first bit line BL1 and the first channel structure 30.

[0132] The second array interconnection layer 70 may further include a second interlayer insulating layer 71 and a second contact 72. The second interlayer insulating layer 71 may be located between the second bit line BL2 and the second stacked structure 20 to insulate the second bit line BL2 from the second stacked structure 20. The second contact 72 penetrates the second interlayer insulating layer 71 to connect the second bit line BL2 and the second channel structure 40.

[0133] The materials of the first interlayer insulating layer 61 and the second interlayer insulating layer 71 may be insulating materials, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0134] The material of the first contact 62 and the second contact 72 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials.

[0135] For example, the first interlayer insulating layer 61 and the second interlayer insulating layer 71 may be made of the same material, and the first contact 62 and the second contact 72 may be made of the same material.

[0136] The present disclosure does not limit the number and arrangement of the first connection structures L1 and can be designed according to actual needs.

[0137] The first connection structure L1 is insulated from the multiple first gate layers 11, the multiple second gate layers 21, and the source layer SL, and can also prevent the signal transmitted in the first connection structure L1 from entering the multiple first gate layers 11, the multiple second gate layers 21 and the source layer SL, thereby affecting the normal operation of the storage unit in the three-dimensional memory.

[0138] The manner in which the first connection structure L1 is insulated from the plurality of first gate layers 11 , the plurality of second gate layers 21 , and the source layer SL can be found in the following embodiments and will not be described in detail herein.

[0139] In the three-dimensional memory 100 provided by the present disclosure, the first peripheral device layer 50 is connected to the first channel structure 30 through the first bit line BL1 located in the first array interconnection layer 60, and the first peripheral device layer 50 is also connected to the second channel structure 40 through the first bit line BL1, the first connection structure L1 and the second bit line BL2. In this way, the memory cells in the first stacked structure 10 and the memory cells in the second stacked structure 20 can be controlled by the peripheral circuit in the first peripheral device layer 50. Therefore, it is helpful to simplify the structure of the three-dimensional memory 100 and reduce the preparation cost of the three-dimensional memory 100.

[0140] In some examples, such as Figure 1 and Figure 2 As shown, the first stack structure 10 and the second stack structure 20 each include a first memory block C1 and a second memory block C2. The first channel structure 30 and the second channel structure 40 are located in the first memory block C1, and the first connection structure L1 is located in the second memory block C2.

[0141] In some examples, such as Figure 1 As shown, the first stacking structure 10 and the second stacking structure 20 include a plurality of first storage blocks C1 and a plurality of second storage blocks C2, and any two adjacent second storage blocks C2 among the plurality of second storage blocks C2 are spaced apart by at least one first storage block C1. In the present disclosure, the plurality of second storage blocks C2 are spaced apart, thereby avoiding the problem of excessive stress caused by the concentration of the plurality of second storage blocks C2 and low stability of the three-dimensional memory structure.

[0142] “Any two adjacent second storage blocks C2 among a plurality of second storage blocks C2 are separated by at least one first storage block C1” includes both the case where any two adjacent second storage blocks C2 among a plurality of second storage blocks C2 are separated by one first storage block C1 and the case where any two adjacent second storage blocks C2 among a plurality of second storage blocks C2 are separated by a plurality of first storage blocks C1.

[0143] It can be understood that, when the first stacking structure 10 and the second stacking structure 20 include multiple first storage blocks C1 and multiple second storage blocks C2, the projection of the first storage block C1 in the first stacking structure 10 on the source layer SL overlaps with the projection of the first storage block C1 in the second stacking structure 20 on the source layer SL, and the projection of the second storage block C2 in the first stacking structure 10 on the source layer SL overlaps with the projection of the second storage block C2 in the second stacking structure 20 on the source layer SL.

[0144] In the present disclosure, there is no limitation on the size and quantity of the first storage block C1 and the second storage block C2, and they can be designed according to actual needs.

[0145] Figure 8 for Figure 1 A schematic cross-sectional view of the three-dimensional memory at BB' is shown. Fig. 9 for Figure 1 Another cross-sectional schematic diagram of the three-dimensional memory at BB' is shown. Figure 8 In the direction X0 parallel to the surface of the first stacked structure 10 away from the source layer SL (ie, the preset surface S1), the size of the end of the sub-channel structure CH away from the source layer SL is greater than the size of the end of the sub-channel structure CH close to the source layer SL. Fig. 9 In the direction X0 parallel to the surface of the first stacked structure 10 away from the source layer SL (ie, the preset surface S1), the size of one end of the sub-channel structure CH away from the source layer SL is smaller than the size of one end of the sub-channel structure CH close to the source layer SL.

[0146] like Figure 8 As shown, in some embodiments, the first stacked structure 10 and the second stacked structure 20 both include a predetermined surface S1 away from the source layer SL. The three-dimensional memory 100 further includes a first gate contact SCT1 and a second gate contact SCT2.

[0147] The first gate contact SCT1 penetrates from the predetermined surface S1 of the first stacked structure 10 to a corresponding first gate layer 11 among the plurality of first gate layers 11, and is connected to the corresponding first gate layer 11. The second gate contact SCT2 penetrates from the predetermined surface S1 of the second stacked structure 20 to a corresponding second gate layer 21 among the plurality of second gate layers 21, and is connected to the corresponding second gate layer 21.

[0148] The first gate layer 11 may be connected to a first gate contact SCT1, or may be connected to multiple first gate contacts SCT1 at the same time. Similarly, the second gate layer 21 may be connected to a second gate contact SCT2, or each second gate layer 21 may be connected to multiple second gate contacts SCT2 at the same time.

[0149] The present disclosure does not limit the number and size of the first gate contacts SCT1 and the second gate contacts SCT2 , and they can be designed according to actual needs.

[0150] In some examples, the material of the first gate contact SCT1 may be the same as that of the first gate layer 11 , and the material of the second gate contact SCT2 may be the same as that of the second gate layer 21 .

[0151] The three-dimensional memory 100 provided in the present disclosure can provide a control signal to the first gate layer 11 through the first gate contact SCT1, thereby controlling the conduction and disconnection of the memory cell connected to the first gate layer 11, and can also provide a control signal to the second gate layer 21 through the second gate contact SCT2, thereby controlling the conduction and disconnection of the memory cell connected to the second gate layer 21.

[0152] In some embodiments, Figure 1 As shown, the three-dimensional memory 100 may include a storage region D1 and a connection region D2, and the first gate contact SCT1 and the second gate contact SCT2 may both be located in the connection region D2. The first channel structure 30 and the second channel structure 40 may both be located in the storage region D1.

[0153] In some embodiments, in a direction parallel to the preset surface S1, a dimension of an end of the first gate contact SCT1 away from the source layer SL is greater than a dimension of an end of the first gate contact SCT1 close to the source layer SL, and a dimension of an end of the second gate contact SCT2 away from the source layer SL is greater than a dimension of an end of the second gate contact SCT2 close to the source layer SL.

[0154] In this way, the size of the end of the first gate contact SCT1 away from the source layer SL and the size of the end of the second gate contact SCT2 away from the source layer SL are both large, which is conducive to connecting the first gate contact SCT1 with other structures (such as the first gate line GL1 described below) and facilitating the connection of the second gate contact SCT2 with other structures (such as the connecting line 73 described below).

[0155] In some examples, such as Figure 8 and Fig. 9 As shown, in the case where the three-dimensional memory 100 includes a first peripheral device layer 50, a first array interconnection layer 60 and a second array interconnection layer 70, the first array interconnection layer 60 further includes a first gate line GL1 and a second gate line GL2, and the first gate contact SCT1 is connected to the first peripheral device layer 50 through the first gate line GL1. The second gate line GL2 is connected to the first peripheral device layer 50. The second array interconnection layer 70 further includes a connection line 73, and the connection line 73 is connected to the second gate contact SCT2.

[0156] Based on this, the three-dimensional memory 100 may further include a second connection structure L2, which runs through the first stacked structure 10, the second stacked structure 20 and the source layer SL, and is insulated from the plurality of first gate layers 11, the plurality of second gate layers 21 and the source layer SL. The second gate contact SCT2 is connected to the second connection structure L2 through a connection line 73, and the second connection structure L2 is connected to the first peripheral device layer 50 through a second gate line GL2.

[0157] In some examples, the material of the first gate line GL1 and the second gate line GL2 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials.

[0158] The second connection structure L2 is insulated from the multiple first gate layers 11, the multiple second gate layers 21, and the source layer SL, and can also prevent the signal transmitted in the second connection structure L2 from entering the multiple first gate layers 11, the multiple second gate layers 21 and the source layer SL, thereby affecting the normal operation of the storage unit in the three-dimensional memory.

[0159] The manner in which the second connection structure L2 is insulated from the plurality of first gate layers 11 , the plurality of second gate layers 21 , and the source layer SL can be found in the following embodiments, which will not be described in detail here.

[0160] In this way, the first peripheral device layer 50 can be connected to the first gate contact SCT1 through the first gate line GL1, and then transmit signals to the first gate layer 11 through the first gate contact SCT1. At the same time, the first peripheral device layer 50 can be connected to the second gate contact SCT2 through the second gate line GL2 and the second connection structure L2, and then transmit signals to the second gate layer 21 through the second gate contact SCT2.

[0161] For some examples, see Figure 1 , the first connection structure L1 may be located in the storage area D1. In this way, the distance between the first connection structure L1 and the first bit line BL1 and the second bit line BL2 may be relatively close, the power consumption of the conduction path formed by the first connection structure L1, the first bit line BL1 and the second bit line BL2 is relatively small, the connection structure between the first connection structure L1 and the first bit line BL1 is relatively simple, and the connection structure between the first connection structure L1 and the second bit line BL2 may also be relatively simple, which is conducive to simplifying the routing layout of the first array interconnection layer 60 and the second array interconnection layer 70, and further conducive to reducing the power consumption of the three-dimensional memory 100 and simplifying the structure of the three-dimensional memory 100.

[0162] For some examples, see Figure 2 , the second connection structure L2 may be located in the connection region D2. In this way, the second connection structure L2 and the second gate contact SCT2 are both located in the connection region D2, and the distance between the second gate contact SCT2 and the second connection structure L2 may be small, thereby facilitating the simplification of the connection structure between the second connection structure L2 and the second gate contact SCT2, and simplifying the structure of the three-dimensional memory 100.

[0163] Fig.10 A schematic diagram of the structure of the three-dimensional memory 100 provided by the present disclosure. Fig.11Another structural schematic diagram of the three-dimensional memory 100 provided by the present disclosure is shown.

[0164] in, Fig.10 In the direction X0 parallel to the surface of the first stacked structure 10 away from the source layer SL (ie, the preset surface S1), the size of the end of the sub-channel structure CH away from the source layer SL is greater than the size of the end of the sub-channel structure CH close to the source layer SL. Fig.11 In the direction X0 parallel to the surface of the first stacked structure 10 away from the source layer SL (ie, the preset surface S1), the size of one end of the sub-channel structure CH away from the source layer SL is smaller than the size of one end of the sub-channel structure CH close to the source layer SL.

[0165] like Fig.10 and Fig.11 As shown, in some embodiments, the three-dimensional memory 100 may further include a second peripheral device layer 81 , a third peripheral device layer 82 , a third array interconnect layer 91 and a fourth array interconnect layer 92 .

[0166] The second peripheral device layer 81 is located on a side of the first stacked structure 10 away from the source layer SL. The third peripheral device layer 82 is located on a side of the second stacked structure 20 away from the source layer SL. The third array interconnection layer 91 is located between the second peripheral device layer 81 and the first stacked structure 10, the third array interconnection layer 91 includes a third bit line BL3, and the second peripheral device layer 81 is connected to the first channel structure 30 through the third bit line BL3. The fourth array interconnection layer 92 is located between the third peripheral device layer 82 and the second stacked structure 20, the fourth array interconnection layer 92 includes a fourth bit line BL4, and the third peripheral device layer 82 is connected to the second channel structure 40 through the fourth bit line BL4.

[0167] The second peripheral device layer 81 and the third peripheral device layer 82 may each include a peripheral circuit, and the peripheral circuit is configured to control and sense the array device.

[0168] The material of the third bit line BL3 and the fourth bit line BL4 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials. Exemplarily, the material of the third bit line BL3 and the fourth bit line BL4 may be the same.

[0169] In the present disclosure, the number of the third bit lines BL3 and the number of the fourth bit lines BL4 are not limited and can be designed according to actual needs. In some examples, the number of the third bit lines BL3 can be the same as the number of the fourth bit lines BL4.

[0170] In some examples, the third array interconnect layer 91 may further include a third interlayer insulating layer 911 and a third contact 912. The third interlayer insulating layer 911 may be located between the third bit line BL3 and the first stacked structure 10 to insulate the third bit line BL3 from the first stacked structure 10. The third contact 912 penetrates the third interlayer insulating layer 911 to connect the third bit line BL3 and the first channel structure 30.

[0171] The fourth array interconnection layer 92 may further include a fourth interlayer insulating layer 921 and a fourth contact 922. The fourth interlayer insulating layer 921 may be located between the fourth bit line BL4 and the second stacked structure 20 to insulate the fourth bit line BL4 from the second stacked structure 20. The fourth contact 922 penetrates the fourth interlayer insulating layer 921 to connect the fourth bit line BL4 and the second channel structure 40.

[0172] The materials of the third interlayer insulating layer 911 and the fourth interlayer insulating layer 921 may be insulating materials, such as a combination of one or more of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0173] The material of the third contact 912 and the fourth contact 922 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials.

[0174] For example, the third interlayer insulating layer 911 and the fourth interlayer insulating layer 921 may be made of the same material, and the third contact 912 and the fourth contact 922 may be made of the same material.

[0175] In the three-dimensional memory 100 provided by the present disclosure, a second peripheral device layer 81 and a third array interconnection layer 91 are arranged on a side of the first stacked structure 10 away from the source layer SL. The third array interconnection layer 91 includes a third bit line BL3, which connects the second peripheral device layer 81 with the first channel structure 30, so that the second peripheral device layer 81 can control the storage unit in the first stacked structure 10. A third peripheral device layer 82 and a fourth array interconnection layer 92 are arranged on a side of the second stacked structure 20 away from the source layer SL. The fourth array interconnection layer 92 includes a fourth bit line BL4, which connects the third peripheral device layer 82 with the second channel structure 40, so that the third peripheral device layer 82 can control the storage unit in the second stacked structure 20. In this way, the storage unit in the first stacked structure 10 and the storage unit in the second stacked structure 20 are controlled by the peripheral circuit in the second peripheral device layer 81 and the peripheral circuit in the third peripheral device layer 82, respectively, which is conducive to simplifying the complexity of the peripheral circuit and simplifying the structure of the second peripheral device layer 81 and the third peripheral device layer 82.

[0176] In some examples, such as Fig.10 and Fig.11 As shown, the three-dimensional memory 100 may also include an external connection structure 93 and a third connection structure L3. The external connection structure 93 runs through the second peripheral device layer 81. The third connection structure L3 runs through the first stacked structure 10, the second stacked structure 20 and the source layer SL, and is insulated from the above-mentioned multiple first gate layers 11, the above-mentioned multiple second gate layers 21 and the source layer SL. Among them, the third array interconnection layer 91 also includes a first transfer structure 913, and the fourth array interconnection layer 92 also includes a second transfer structure 923. One end of the third connection structure L3 is connected to the external connection structure 93 through the first transfer structure 913, and the other end is connected to the third peripheral device layer 82 through the second transfer structure 923.

[0177] The present disclosure does not limit the specific structures of the first adapter structure 913 and the second adapter structure 923, and they can be designed according to actual needs.

[0178] Exemplarily, the first transfer structure 913 may include a first conductive line 9131 and a fifth contact 9132 . The second transfer structure 923 may include a second conductive line 9231 and a sixth contact 9232 .

[0179] The first conductive line 9131 may be disposed in the same layer as the third bit line BL3 , the second conductive line 9231 may be disposed in the same layer as the fourth bit line BL4 , the fifth contact 9132 may penetrate the third interlayer insulating layer 911 , and the sixth contact 9232 may penetrate the fourth interlayer insulating layer 921 .

[0180] The first conductive line 9131 and the third bit line BL3 may be made of the same material, the second conductive line 9231 and the fourth bit line BL4 may be made of the same material, the fifth contact 9132 and the third contact 912 may be made of the same material, and the sixth contact 9232 and the fourth contact 922 may be made of the same material.

[0181] In some examples, the third connection structure L3 may be located in a storage area.

[0182] The third connection structure L3 is insulated from the multiple first gate layers 11, the multiple second gate layers 21, and the source layer SL, and can also prevent the signal transmitted in the third connection structure L3 from entering the multiple first gate layers 11, the multiple second gate layers 21 and the source layer SL, thereby affecting the normal operation of the storage unit in the three-dimensional memory.

[0183] The manner in which the third connection structure L3 is insulated from the plurality of first gate layers 11 , the plurality of second gate layers 21 , and the source layer SL can be found in the following embodiments, which will not be described in detail here.

[0184] In the three-dimensional memory 100 provided in the present disclosure, the signal in the third peripheral device layer 82 is transmitted to the side where the second peripheral device layer 81 is located through the third connection structure L3 and the external connection structure 93, so that when the three-dimensional memory 100 is connected to the controller, the signal of the controller can be transmitted to the third peripheral device layer 82 through the third connection structure L3 and the external connection structure 93, thereby controlling the third peripheral device layer 82 to control the storage unit in the second stacking structure 20.

[0185] For some examples, see Fig.10 In the case where the three-dimensional memory 100 includes a second peripheral device layer 81, a third peripheral device layer 82, a third array interconnection layer 91 and a fourth array interconnection layer 92, the third array interconnection layer 91 further includes a third gate line GL3, the fourth array interconnection layer 92 further includes a fourth gate line GL4, the first gate contact SCT1 is connected to the second peripheral device layer 81 through the third gate line GL3, and the second gate contact SCT2 is connected to the third peripheral device layer 82 through the fourth gate line GL4.

[0186] In this way, the second peripheral device layer 81 can be connected to the first gate contact SCT1 through the third gate line GL3, and then transmit signals to the first gate layer 11 through the first gate contact SCT1. At the same time, the third peripheral device layer 82 can be connected to the second gate contact SCT2 through the fourth gate line GL4, and then transmit signals to the second gate layer 21 through the second gate contact SCT2.

[0187] In some examples, the third gate line GL3 and the fourth gate line GL4 may be made of a conductive material, such as tungsten, cobalt, copper, aluminum, and a combination of one or more metal silicides, or other suitable materials.

[0188] In some embodiments, see Figure 3 , Figure 8 and Fig.10 , the first connection structure L1, the second connection structure L2 and the third connection structure L3 may each include a first sub-portion L01, a second sub-portion L02 and a third sub-portion L03. The first sub-portion L01 runs through the first stacked structure 10 and is insulated from the plurality of first gate layers 11. The second sub-portion L02 runs through the second stacked structure 20 and is insulated from the plurality of second gate layers 21. The third sub-portion L03 runs through the source layer SL and is insulated from the source layer SL. The first sub-portion L01 and the second sub-portion L02 are both connected to the third sub-portion L03.

[0189] For example, see Figure 3 , Figure 8 and Fig.10The three-dimensional memory 100 may further include a first insulating dielectric layer M1, a second insulating dielectric layer M2, and a third insulating dielectric layer M3. The first insulating dielectric layer M1 is at least located between the first sub-portion L01 and the plurality of first gate layers 11, the second insulating dielectric layer M2 is at least located between the second sub-portion L02 and the plurality of second gate layers 21, and the third insulating dielectric layer M3 is located between the third sub-portion L03 and the source layer SL.

[0190] The first insulating dielectric layer M1 is used to insulate the first sub-section L01 from the multiple first gate layers 11, the second insulating dielectric layer M2 is used to insulate the second sub-section L02 from the multiple second gate layers 21, and the third insulating dielectric layer M3 is used to insulate the third sub-section L03 from the source layer SL.

[0191] It can be understood that "the first insulating dielectric layer M1 is at least located between the first sub-section L01 and the above-mentioned multiple first gate layers 11", that is, the first insulating dielectric layer M1 can be located only between the first sub-section L01 and the above-mentioned multiple first gate layers 11, or the first insulating dielectric layer M1 can also be located between the first sub-section L01 and the above-mentioned multiple first gate layers 11, and between the first sub-section L01 and the first insulating layer 12 (in this case, the first insulating dielectric layer M1 can surround the side of the first sub-section L01).

[0192] Similarly, "the second insulating dielectric layer M2 is at least located between the second sub-section L02 and the above-mentioned multiple second gate layers 21", that is, the second insulating dielectric layer M2 can be located only between the second sub-section L02 and the above-mentioned multiple second gate layers 21, or the second insulating dielectric layer M2 can also be located between the second sub-section L02 and the above-mentioned multiple second gate layers 21, and between the second sub-section L02 and the second insulating layer 22 (in this case, the second insulating dielectric layer M2 can surround the side of the second sub-section L02).

[0193] In some examples, the first insulating dielectric layer M1, the second insulating dielectric layer M2, and the third insulating dielectric layer M3 may include at least one of silicon oxide, silicon nitride, doped silicon oxide, organic silicate glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials.

[0194] In some examples, the materials of the first insulating dielectric layer M1 , the second insulating dielectric layer M2 , and the third insulating dielectric layer M3 may be the same.

[0195] In some other examples, the material of the first insulating dielectric layer M1 may be the same as the material of the first insulating layer 12 , and the material of the second insulating dielectric layer M2 may be the same as the material of the second insulating layer 22 .

[0196] In some examples, the materials of the first sub-portion L01 , the second sub-portion L02 , and the third sub-portion L03 may include a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide.

[0197] In the present disclosure, the first sub-unit L01 penetrates the first stacking structure 10, the second sub-unit L02 penetrates the second stacking structure 20, and the first sub-unit L01 and the second sub-unit L02 are both connected to the third sub-unit L03. In this way, the first sub-unit L01 and the second sub-unit L02 can be prepared separately, the depth of the first sub-unit L01 and the second sub-unit L02 can be smaller, and the aspect ratio of the first sub-unit L01 and the second sub-unit L02 can be smaller, which is conducive to reducing the difficulty of preparing the first sub-unit L01 and the second sub-unit L02 and improving the preparation efficiency of the three-dimensional memory 100.

[0198] Fig.12 A bottom view of another three-dimensional memory 100 provided by the present disclosure is shown. Fig.13 for Fig.12 The cross-sectional schematic diagram of the three-dimensional memory shown is at CC'. Fig.14 for Fig.12 The cross-sectional schematic diagram of the three-dimensional memory shown is at DD'. Fig.15 A schematic diagram of the structure of another three-dimensional memory provided by the present disclosure.

[0199] like Figure 12 to Figure 15 As shown, in some embodiments, in at least one of the first connection structure L1, the second connection structure L2, and the third connection structure L3, the cross section of the first sub-portion L01 along the first setting direction Z0 is the same as the cross section of the first channel structure 30 along the first setting direction Z0, and the cross section of the second sub-portion L02 along the first setting direction Z0 is the same as the cross section of the second channel structure 40 along the first setting direction Z0. The first setting direction Z0 is parallel to the stacking direction Z of the first stacked structure 10.

[0200] In some examples, such as Fig.13 As shown, the cross-section of the first sub-portion L01 of the first connection structure L1 along the first setting direction Z0 is the same as the cross-section shape of the first channel structure 30 along the first setting direction Z0, and the cross-section of the second sub-portion L02 of the first connection structure L1 along the first setting direction Z0 is the same as the cross-section shape of the second channel structure 40 along the first setting direction Z0.

[0201] In this way, the first sub-portion L01 of the first connection structure L1 can be prepared simultaneously with the first channel structure 30 , and the second sub-portion L02 of the first connection structure L1 can be prepared simultaneously with the second channel structure 40 , which is beneficial to simplify the preparation process of the three-dimensional memory 100 and improve the preparation efficiency of the three-dimensional memory 100 .

[0202] When the first connection structure L1 and the first channel structure 30 and the second channel structure 40 are all located in the storage area D1, the first sub-portion L01 of the first connection structure L1 is the same as the cross-sectional shape of the first channel structure 30 along the first set direction Z0, and the first sub-portion L01 and the first channel structure 30 occupy the same volume in the first stacking structure 10. The second sub-portion L02 of the first connection structure L1 is the same as the cross-sectional shape of the second channel structure 40 along the first set direction Z0, and the second sub-portion L02 and the second channel structure 40 occupy the same volume in the second stacking structure 20, which is also beneficial to balancing the forces in the storage area D1 of the first stacking structure 10 and the storage area D1 of the second stacking structure 20, thereby improving the structural stability of the three-dimensional memory 100.

[0203] In other examples, such as Fig.14 As shown, the cross section of the first sub-portion L01 of the second connection structure L2 along the first setting direction Z0 is the same as the cross section of the first channel structure 30 along the first setting direction Z0, and the cross section of the second sub-portion L02 of the second connection structure L2 along the first setting direction Z0 is the same as the cross section of the second channel structure 40 along the first setting direction Z0. In this way, the first sub-portion L01 of the second connection structure L2 can be prepared simultaneously with the first channel structure 30, and the second sub-portion L02 of the second connection structure L2 can be prepared simultaneously with the second channel structure 40, which is conducive to simplifying the preparation process of the three-dimensional memory 100 and improving the preparation efficiency of the three-dimensional memory 100.

[0204] In some other examples, such as Fig.15 As shown, the cross section of the first sub-portion L01 of the third connection structure L3 along the first setting direction Z0 is the same as the cross section of the first channel structure 30 along the first setting direction Z0, and the cross section of the second sub-portion L02 of the third connection structure L3 along the first setting direction Z0 is the same as the cross section of the second channel structure 40 along the first setting direction Z0. In this way, the first sub-portion L01 of the third connection structure L3 can be prepared simultaneously with the first channel structure 30, and the second sub-portion L02 of the third connection structure L3 can be prepared simultaneously with the second channel structure 40, which is conducive to simplifying the preparation process of the three-dimensional memory 100 and improving the preparation efficiency of the three-dimensional memory 100.

[0205] For some further examples, see Fig.13 and Fig.14 In the first connection structure L1 and the second connection structure L2, the cross-section of the first sub-portion L01 along the first setting direction Z0 is also the same as the cross-sectional shape of the first channel structure 30 along the first setting direction Z0, and the cross-section of the second sub-portion L02 along the first setting direction Z0 is the same as the cross-sectional shape of the second channel structure 40 along the first setting direction Z0.

[0206] At this time, the first sub-portion L01 of the first connection structure L1 and the first sub-portion L01 of the second connection structure L2 can be prepared simultaneously with the first channel structure 30. The second sub-portion L02 of the first connection structure L1 and the second sub-portion L02 of the second connection structure L2 can be prepared simultaneously with the second channel structure 40, which is conducive to further simplifying the preparation process of the three-dimensional memory 100 and improving the preparation efficiency of the three-dimensional memory 100.

[0207] In some examples, such as Fig.12 As shown, the three-dimensional memory 100 includes a plurality of second gate contacts SCT2 and a plurality of second connection structures L2 correspondingly connected to the plurality of second gate contacts SCT2. The first stacked structure 10 and the second stacked structure 20 both include a first memory block C1 and a second memory block C2.

[0208] In the first storage block C1 and / or the second storage block C2, a plurality of second gate contacts SCT2 are arranged in two rows along a second setting direction X, a plurality of second connection structures L2 are arranged in two rows along the second setting direction X, and the two rows of second connection structures L2 are located between the two rows of second gate contacts SCT2. The second setting direction X is parallel to the surface of the first stacked structure 10 away from the source layer SL.

[0209] It can be understood that the arrangement of the second gate contact SCT2 and the second connection structure L2 in the embodiment of the present application is not limited thereto.

[0210] In some examples, such as Fig.12 As shown, the area of ​​the end surface of the second gate contact SCT2 away from the source layer SL is greater than the area of ​​the end surface of the second sub-portion L02 of the second connection structure L2 away from the source layer SL. In this way, the area of ​​the end surface of the second sub-portion L02 of the second connection structure L2 away from the source layer SL can be smaller, which is beneficial to reduce the occupied area of ​​the second connection structure L2, thereby facilitating the reduction of the size of the three-dimensional memory 100.

[0211] In the embodiment of the present application, there is no restriction on the specific values ​​of the area of ​​the end surface of the second gate contact SCT2 away from the source layer SL and the area of ​​the end surface of the second sub-portion L02 of the second connection structure L2 away from the source layer SL, and they can be designed according to actual needs.

[0212] In some embodiments, see Figure 3 , Figure 8 and Fig.10In at least one of the first connection structure L1, the second connection structure L2, and the third connection structure L3, the cross section of the first sub-portion L01 along the first setting direction Z0 is the same as the cross section of the first gate contact SCT1 of the three-dimensional memory 100 along the first setting direction Z0, and the cross section of the second sub-portion L02 along the first setting direction Z0 is the same as the cross section of the second gate contact SCT2 of the three-dimensional memory 100 along the first setting direction Z0. The first setting direction Z0 is parallel to the stacking direction Z of the first stacked structure 10.

[0213] In some examples, such as Figure 3 and Figure 8 As shown, the cross section of the first sub-portion L01 of the first connection structure L1 along the first setting direction Z0 is the same as the cross section of the first gate contact SCT1 along the first setting direction Z0, and the cross section of the second sub-portion L02 of the first connection structure L1 along the first setting direction Z0 is the same as the cross section of the second gate contact SCT2 along the first setting direction Z0. At this time, the first sub-portion L01 of the first connection structure L1 can be prepared simultaneously with the first gate contact SCT1, and the second sub-portion L02 of the first connection structure L1 can be prepared simultaneously with the second gate contact SCT2, which is conducive to simplifying the preparation process of the three-dimensional memory 100 and improving the preparation efficiency of the three-dimensional memory 100.

[0214] In other examples, such as Figure 8 As shown, the cross section of the first sub-portion L01 of the second connection structure L2 along the first setting direction Z0 is the same as the cross section of the first gate contact SCT1 along the first setting direction Z0, and the cross section of the second sub-portion L02 of the second connection structure L2 along the first setting direction Z0 is the same as the cross section of the second gate contact SCT2 along the first setting direction Z0. At this time, the first sub-portion L01 of the second connection structure L2 can be prepared at the same time as the first gate contact SCT1, and the second sub-portion L02 of the second connection structure L2 can be prepared at the same time as the second gate contact SCT2, which is conducive to simplifying the preparation process of the three-dimensional memory 100 and improving the preparation efficiency of the three-dimensional memory 100.

[0215] When the second connection structure L2 and the first gate contact SCT1 and the second gate contact SCT2 are all located in the connection area D2, the first sub-portion L01 of the second connection structure L2 and the first gate contact SCT1 have the same cross-sectional shape along the first set direction Z0, the first sub-portion L01 of the second connection structure L2 and the first gate contact SCT1 occupy the same volume in the first stacking structure, the second sub-portion L02 of the second connection structure L2 and the second gate contact SCT2 have the same cross-sectional shape along the first set direction Z0, and the second sub-portion L02 of the second connection structure L2 and the second gate contact SCT2 occupy the same volume in the second stacking structure 20, which is beneficial to balancing the forces on the storage area D1 of the first stacking structure 10 and the storage area D1 of the second stacking structure 20, thereby improving the structural stability of the three-dimensional memory 100.

[0216] In some other examples, such as Fig.10 As shown, the cross section of the first sub-portion L01 of the third connection structure L3 along the first setting direction Z0 is the same as the cross section of the first gate contact SCT1 along the first setting direction Z0, and the cross section of the second sub-portion L02 of the third connection structure L3 along the first setting direction Z0 is the same as the cross section of the second gate contact SCT2 along the first setting direction Z0. At this time, the first sub-portion L01 of the third connection structure L3 can be prepared at the same time as the first gate contact SCT1, and the second sub-portion L02 of the third connection structure L3 can be prepared at the same time as the second gate contact SCT2, which is conducive to simplifying the preparation process of the three-dimensional memory 100 and improving the preparation efficiency of the three-dimensional memory 100.

[0217] In some other examples, such as Figure 3 and Figure 8 As shown, in the first connection structure L1 and the second connection structure L2, the cross section of the first sub-portion L01 along the first setting direction Z0 is the same as the cross section of the first gate contact SCT1 along the first setting direction Z0, and the cross section of the second sub-portion L02 along the first setting direction Z0 is the same as the cross section of the second gate contact SCT2 along the first setting direction Z0. At this time, the first sub-portion L01 of the first connection structure L1 and the second connection structure L2 can be prepared simultaneously with the first gate contact SCT1, and the second sub-portion L02 of the first connection structure L1 and the second connection structure L2 can be prepared simultaneously with the second gate contact SCT2, which is conducive to further simplifying the preparation process of the three-dimensional memory 100 and improving the preparation efficiency of the three-dimensional memory 100.

[0218] In some embodiments, Figure 2 As shown, the three-dimensional memory 100 includes a plurality of second gate contacts SCT2 and a plurality of second connection structures L2 correspondingly connected to the plurality of second gate contacts SCT2. The first stacked structure 10 and the second stacked structure 20 both include a first memory block C1 and a second memory block C2.

[0219] In the first storage block C1 and / or the second storage block C2, a plurality of second gate contacts SCT2 and a plurality of second connection structures L2 are arranged in two rows along a second setting direction X, and in the same row, the second gate contacts SCT2 and the second connection structures L2 are alternately arranged. The second setting direction X is parallel to the surface of the first stacked structure 10 away from the source layer SL.

[0220] In other embodiments, Fig.16 As shown, in the first storage block C1 and / or the second storage block C2, a plurality of second gate contacts SCT2 are arranged in two rows along the second setting direction X, a portion of the second connection structures L2 in the plurality of second connection structures L2 are arranged in at least one row along the second setting direction X, at least one row of second connection structures L2 is located between the two rows of second gate contacts SCT2, and the remaining second connection structures L2 in the plurality of second connection structures L2 are dispersed in the two rows of second gate contacts SCT2. The second setting direction X is parallel to the surface of the first stacked structure 10 away from the source layer SL. Wherein, Fig.16 In the figure, a part of the second connection structures L2 in the plurality of second connection structures L2 is arranged in a row along the second setting direction X as an example for illustration.

[0221] It can be understood that the arrangement of the second gate contact SCT2 and the second connection structure L2 in the present disclosure is not limited thereto.

[0222] In some examples, such as Fig.16 As shown, the area of ​​the end surface of the second gate contact SCT2 away from the source layer SL is equal to the area of ​​the end surface of the second sub-portion L02 of the second connection structure L2 away from the source layer SL. In this way, the area of ​​the end surface of the second sub-portion L02 away from the source layer SL can be larger, which is conducive to improving the connection yield between the second connection structure L2 and the connection line 73.

[0223] It can be understood that “the area of ​​the end face of the second gate contact SCT2 away from the source layer SL is equal to the area of ​​the end face of the second sub-portion L02 of the second connection structure L2 away from the source layer SL” not only includes the situation that the area of ​​the end face of the second gate contact SCT2 away from the source layer SL is completely equal to the area of ​​the end face of the second sub-portion L02 of the second connection structure L2 away from the source layer SL, but also includes the situation that the area of ​​the end face of the second gate contact SCT2 away from the source layer SL is approximately equal to the area of ​​the end face of the second sub-portion L02 of the second connection structure L2 away from the source layer SL.

[0224] Here, "approximately equal" means that there may be a difference between the area of ​​the end surface of the second gate contact SCT2 away from the source layer SL and the area of ​​the end surface of the second sub-portion L02 of the second connection structure L2 away from the source layer SL, and the difference is within an acceptable deviation range. The acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0225] In some embodiments, see Fig.15 The three-dimensional memory 100 may further include a first source contact 94 and a second source contact 95. The first source contact 94 penetrates the first stacked structure 10 and is connected to the source layer SL. The second source contact 95 penetrates the second stacked structure 20 and is connected to the source layer SL.

[0226] When the three-dimensional memory 100 includes the first peripheral device layer 50 and the first array interconnect layer 60 , the first source contact 94 is connected to the first peripheral device layer 50 through the first array interconnect layer 60 .

[0227] When the three-dimensional memory 100 includes a second peripheral device layer 81, a third peripheral device layer 82, a third array interconnect layer 91 and a fourth array interconnect layer 92, the first source contact 94 is connected to the second peripheral device layer 81 through the third array interconnect layer 91, and the second source contact 95 is connected to the third peripheral device layer 82 through the fourth array interconnect layer 92.

[0228] In the case where the three-dimensional memory 100 provided by the present disclosure includes the first peripheral device 50 and the first array interconnection layer 60, the first peripheral device 50 can provide a voltage to the source layer SL through the first array interconnection layer 60 and the first source contact 94. In the case where the three-dimensional memory 100 provided by the present disclosure includes the second peripheral device layer 81, the third peripheral device layer 82, the third array interconnection layer 91 and the fourth array interconnection layer 92, the second peripheral device layer 81 can provide a voltage to the source layer SL through the third array interconnection layer 91 and the first source contact 94, and the third peripheral device layer 82 can provide a voltage to the source layer SL through the fourth array interconnection layer 92 and the second source contact 95.

[0229] The present disclosure also provides a method for preparing the three-dimensional memory 100 . Fig.17 A flow chart of the preparation method provided by the present disclosure, such as Fig.17 As shown, the preparation method includes steps S100 to S700.

[0230] S100, such as Fig.18As shown, a first stacked structure 10 and a first channel structure 30 are formed on a first substrate 01. The first stacked structure 10 includes a plurality of first gate layers 11, and the first channel structure 30 runs through the first stacked structure 10. The first substrate 01 is used to support the first stacked structure 10.

[0231] Exemplarily, the material of the first substrate 01 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0232] Exemplarily, the first stacked structure 10 may further include a plurality of first insulating layers 12, and the first insulating layer 12 is located between any two adjacent first gate layers 11. The structure and material of the first gate layer 11 and the first insulating layer 12 are not described in detail in this disclosure, and reference may be made to the above embodiments.

[0233] In some examples, such as Fig.19 As shown, step S100 may include steps S110 to S130.

[0234] S110, such as Fig. 20 As shown, multiple first sacrificial layers 101 and multiple first insulating layers 12 are alternately stacked and formed on a first substrate 01 .

[0235] The first sacrificial layer 101 and the first insulating layer 12 are made of different materials, so that the first insulating layer 12 and the first sacrificial layer 101 have different etching selectivities for the same etchant.

[0236] Exemplarily, the material of the first sacrificial layer 101 may include at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, but the present disclosure is not limited thereto.

[0237] Exemplarily, the first sacrificial layer 101 and the first insulating layer 12 may be formed by any thin film deposition process of CVD, PVD, and ALD.

[0238] S120, such as Fig.21 As shown, a first channel structure 30 penetrating the first stacked structure 10 is formed.

[0239] For example, a channel hole penetrating the first stacked structure 10 may be formed by a dry / wet etching process, and then the first channel structure 30 may be formed in the channel hole.

[0240] S130, see Fig.18 , the first sacrificial layer 101 is replaced by the first gate layer 11 .

[0241] Illustratively, the first sacrificial layer 101 may be removed by a dry etching process or a wet etching process to form a cavity, and then the first gate layer 11 may be formed in the cavity.

[0242] S200, such as Fig. 22 As shown, the first substrate 01 is removed.

[0243] For example, a chemical mechanical planarization process and an etching process may be used to remove the first substrate 01 .

[0244] S300, such as Fig.23 As shown, a first sub-layer N1 is formed on the first stacked structure 10 , and the first sub-layer N1 is connected to the first channel structure 30 .

[0245] Exemplarily, the material of the first sub-layer N1 may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0246] S400, such as Fig.24 As shown, a second stacked structure 20 and a second channel structure 40 are formed on a second substrate 02. The second stacked structure 20 includes a plurality of second gate layers 21, and the second channel structure 40 runs through the second stacked structure 20. The second substrate 02 is used to support the second stacked structure 20.

[0247] Exemplarily, the material of the second substrate 02 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0248] Exemplarily, the second stacked structure 20 may further include a plurality of second insulating layers 22, and the second insulating layer 22 is located between any two adjacent second gate layers 21. The structure and material of the second gate layer 21 and the second insulating layer 22 are not described in detail in this disclosure, and reference may be made to the above embodiments.

[0249] In some examples, such as Fig.25 As shown, step S400 may include steps S410 to S430.

[0250] S410, see Fig. 20 , multiple layers of second sacrificial layers 102 and multiple layers of second insulating layers 22 that are alternately stacked are formed on the second substrate 02 .

[0251] The second sacrificial layer 102 and the second insulating layer 22 are made of different materials, so that the second insulating layer 22 and the second sacrificial layer 102 have different etching selectivities for the same etchant.

[0252] Exemplarily, the material of the second sacrificial layer 102 may include at least one of silicon, silicon oxide, silicon carbide, and silicon nitride, but the present disclosure is not limited thereto.

[0253] For example, the second sacrificial layer 102 and the second insulating layer 22 may be formed by any thin film deposition process of CVD, PVD, and ALD.

[0254] S420, see Fig.21 , forming a second channel structure 40 penetrating the second stacked structure 20 .

[0255] For example, a channel hole penetrating the second stacked structure 20 may be formed by a dry / wet etching process, and then the second channel structure 40 may be formed in the channel hole.

[0256] S430, see Fig.24 , the second sacrificial layer 102 is replaced by the second gate layer 21 .

[0257] For example, the second sacrificial layer 102 may be removed by a dry etching process or a wet etching process to form a cavity, and then the second gate layer 21 may be formed in the cavity.

[0258] S500, such as Fig.26 As shown, the second substrate 02 is removed.

[0259] For example, the second substrate 02 may be removed by using a chemical mechanical planarization process and an etching process.

[0260] S600, such as Fig. 27 As shown, a second sub-layer N2 is formed on the second stacked structure 20 , and the second sub-layer N2 is connected to the second channel structure 40 .

[0261] Exemplarily, the material of the second sub-layer N2 may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials.

[0262] S700, such as Fig.28 As shown, the first sub-layer N1 and the second sub-layer N2 are combined to form a source layer SL. Along the stacking direction Z of the first stacking structure 10 , the source layer SL is located between the first stacking structure 10 and the second stacking structure 20 .

[0263] In the preparation method provided by the above embodiment of the present disclosure, a first stacking structure 10 and a first channel structure 30 penetrating the first stacking structure 10 are formed on a first substrate 01, and a second stacking structure 20 and a second channel structure 40 penetrating the second stacking structure 20 are formed on a second substrate 02. On the one hand, the number of stacking layers of the first gate layer 11 in the first stacking structure 10 and the second gate layer 21 in the second stacking structure 20 can be large, the total number of stacking layers of the first gate layer 11 and the second gate layer 21 in the prepared three-dimensional memory 100 is large, and the number of storage units in the three-dimensional memory 100 can be more, which is conducive to improving the storage capacity per unit area of ​​the three-dimensional memory 100.

[0264] On the other hand, compared with the solution in which the first stacking structure and the second stacking structure are directly formed on the same side of the source layer SL, and the first channel structure or the second channel structure penetrates the first stacking structure and the second stacking structure, the aspect ratio of the first channel structure 30 and the second channel structure 40 in the embodiment of the present application can be smaller, and the difficulty of preparing the first channel structure 30 and the second channel structure 40 can be smaller, which is beneficial to improving the preparation efficiency of the three-dimensional memory 100 and reducing the preparation cost of the three-dimensional memory 100.

[0265] In the three-dimensional memory 100 prepared by the embodiment of the present application, the first channel structure 30 and the second channel structure 40 only need to be connected to the source layer, and there is no need to align the first channel structure 30 and the second channel structure 40, thereby effectively reducing the difficulty of preparing the three-dimensional memory 100 and avoiding the problems of damage to the storage functional layer in the channel structure, leakage of the channel layer or incomplete etching of the channel structure caused by the failure or deviation of alignment of different channel structures in different stacking structures.

[0266] In some embodiments, see Fig.18 , Fig.24 , Fig.29 and Fig.30 The preparation method also includes step S810 and step S820.

[0267] S810 , forming a first gate contact SCT1 .

[0268] For some examples, see Fig.18 The first gate contact SCT1 may be formed before removing the first substrate 01. At this time, the first gate contact SCT1 penetrates from the surface of the first stacked structure 10 away from the first substrate 01 to the corresponding first gate layer 11 among the plurality of first gate layers 11 and is connected to the corresponding first gate layer 11.

[0269] For other examples, see Fig.29 , the first gate contact SCT1 may be formed after removing the first substrate 01 .

[0270] At this time, the first gate contact SCT1 penetrates from the surface S2 of the first stacked structure 10 for contacting the first substrate 01 to the corresponding first gate layer 11 among the plurality of first gate layers 11 , and is connected to the corresponding first gate layer 11 .

[0271] S820 , forming a second gate contact SCT2 .

[0272] For some examples, see Fig.24 The second gate contact SCT2 may be formed before removing the second substrate 02. At this time, the second gate contact SCT2 penetrates from the surface of the second stacked structure 20 away from the second substrate 02 to the corresponding second gate layer 21 among the plurality of second gate layers 21 and is connected to the corresponding second gate layer 21.

[0273] For other examples, see Fig.30 , the second gate contact SCT2 can be formed after removing the second substrate 02. At this time, the second gate contact SCT2 penetrates from the surface S3 of the second stacked structure 20 for contacting the second substrate 02 to the corresponding second gate layer 21 among the plurality of second gate layers 21, and is connected to the corresponding second gate layer 21.

[0274] In some embodiments, see Fig. 22 and Fig.31 After forming the first gate contact SCT1 and before combining the first sub-layer N1 and the second sub-layer N2 to form the source layer SL, the preparation method further includes step S830 and step S840.

[0275] S830, such as Fig.31 As shown, a first array interconnection layer 60 is formed on the first stacked structure 10. The first array interconnection layer 60 includes a first bit line BL1, a first gate line GL1 and a second gate line GL2. The first bit line BL1 is connected to the first channel structure 30, and the first gate line GL1 is connected to the first gate contact SCT1.

[0276] S840, such as Fig. 22 As shown, the first array interconnection layer 60 is bonded to the first peripheral device layer 50. The first peripheral device layer 50 is connected to the first bit line BL1, the first gate line GL1 and the second gate line GL2.

[0277] See also Fig.26 After forming the second gate contact SCT2 and before combining the first sub-layer N1 and the second sub-layer N2 to form the source layer SL, the preparation method further includes step S850.

[0278] S850, such as Fig.26As shown, a second array interconnection layer 70 is formed on the second stacked structure 20, and the second array interconnection layer 70 includes a second bit line BL2 and a connecting line 73. The second bit line BL2 is connected to the second channel structure 40 and the first bit line (not shown), and the connecting line 73 is connected to the second gate contact SCT2 and the second gate line (not shown).

[0279] In the three-dimensional memory 100 prepared by the preparation method provided by the present disclosure, the first peripheral device layer 50 can be connected to the first channel structure 30 through the first bit line BL1 located in the first array interconnection layer 60, and connected to the first gate contact SCT1 through the first gate line GL1 located in the first array interconnection layer 60. The first peripheral device layer 50 is also connected to the second channel structure 40 through the first bit line BL1 and the second bit line BL2, and connected to the second gate contact SCT2 through the second gate line GL2 and the connection line 73.

[0280] In this way, the memory cells in the first stacked structure 10 and the memory cells in the second stacked structure 20 can be controlled by the peripheral circuit in the first peripheral device layer 50. This is helpful to simplify the structure of the three-dimensional memory 100 and reduce the manufacturing cost of the three-dimensional memory 100.

[0281] In some embodiments, the three-dimensional memory 100 further includes a first connection structure L1 and a second connection structure L2, each of which includes a first sub-portion L01 penetrating the first stacking structure 10 and a second sub-portion L02 penetrating the second stacking structure 20. The preparation method further includes one of step S811, step S812, and step S813.

[0282] S811, see Fig. 22 and Fig.24 When the first gate contact SCT1 is formed, the first sub-portion L01 of the first connection structure L1 and the first sub-portion L01 of the second connection structure L2 are formed. When the second gate contact SCT2 is formed, the second sub-portion L02 of the first connection structure L1 and the second sub-portion L02 of the second connection structure L2 are formed.

[0283] S812, such as Fig.32 As shown, the first sub-portion L01 of the first connection structure L1 and the first sub-portion L01 of the second connection structure L2 are formed while the first channel structure 30 is formed. The second sub-portion L02 of the first connection structure L1 and the second sub-portion L02 of the second connection structure L2 are formed while the second channel structure 40 is formed.

[0284] S813, such as Fig.33 and Fig.34As shown, while forming the first gate contact SCT1, the first sub-portion L01 of the second connection structure L2 is formed. While forming the second gate contact SCT2, the second sub-portion L02 of the second connection structure L2 is formed. While forming the first channel structure 30, the first sub-portion L01 of the first connection structure L1 is formed. While forming the second channel structure 40, the second sub-portion L02 of the first connection structure L1 is formed.

[0285] In the present disclosure, the first sub-portion L01 is insulated from the first gate layer 11, and the second sub-portion L02 is insulated from the second gate layer 21. Therefore, a first insulating dielectric layer may be formed in the process of forming the first sub-portion L01 of the first connection structure L1 and the second connection structure L2, and a second insulating dielectric layer may be formed in the process of forming the second sub-portion L02 of the first connection structure L1 and the second connection structure L2.

[0286] In some embodiments, Fig.35 and Fig.36 As shown, after forming the first gate contact SCT1 and before combining the first sub-layer N1 and the second sub-layer N2 to form the source layer SL, the preparation method further includes step S910 and step S920.

[0287] S910, such as Fig.35 As shown, a third array interconnection layer 91 is formed on the first stacked structure 10 , and the third array interconnection layer 91 includes a third bit line BL3 and a third gate line GL3 . The third bit line BL3 is connected to the first channel structure 30 , and the third gate line GL3 is connected to the first gate contact SCT1 .

[0288] S920, such as Fig.36 As shown, the third array interconnection layer 91 is bonded to the second peripheral device layer 81. The third bit line BL3 and the third gate line GL3 are both connected to the second peripheral device layer 81.

[0289] After forming the second gate contact SCT2 and before combining the first sub-layer N1 and the second sub-layer N2 to form the source layer SL, the preparation method further includes steps S930 and S940.

[0290] S930, such as Fig.37 As shown, a fourth array interconnection layer 92 is formed on the second stacked structure 20 , and the fourth array interconnection layer 92 includes a fourth bit line BL4 and a fourth gate line GL4 . The fourth bit line BL4 is connected to the second channel structure 40 , and the fourth gate line GL4 is connected to the second gate contact SCT2 .

[0291] S940, such as Fig.38As shown, the fourth array interconnection layer 92 is bonded to the third peripheral device layer 82. The fourth bit line BL4 and the fourth gate line GL4 are both connected to the third peripheral device layer 82.

[0292] In some embodiments, the three-dimensional memory 100 further includes a third connection structure L3, the third connection structure L3 includes a first sub-portion L01 penetrating the first stacking structure 10, and a second sub-portion L02 penetrating the second stacking structure 20. Based on this, refer to Fig.35 , Fig.37 and Fig.39 The preparation method further includes step S950 or step S960.

[0293] S950, see Fig.35 and Fig.37 , while forming the first gate contact SCT1, the first sub-portion L01 of the third connection structure L3 is formed. While forming the second gate contact SCT2, the second sub-portion L02 of the third connection structure L3 is formed.

[0294] S960, see Fig.39 , while forming the first channel structure 30 , the first sub-portion L01 of the third connection structure L3 is formed. While forming the second channel structure 40 , the second sub-portion L02 of the third connection structure L3 is formed.

[0295] In the present disclosure, the first sub-portion L01 of the third connection structure L3 is insulated from the first gate layer 11, and the second sub-portion L02 of the third connection structure L3 is insulated from the second gate layer 21. Therefore, a first insulating dielectric layer may be formed in the process of forming the first sub-portion L01 of the third connection structure L3, and a second insulating dielectric layer may be formed in the process of forming the second sub-portion L02 of the third connection structure L3.

[0296] In some embodiments, see Fig.23 , after step S300, the preparation process may further include step S310.

[0297] S310, forming a first connection member N11. The first connection member N11 penetrates the first sub-layer N1 and is insulated from the first sub-layer N1.

[0298] Exemplarily, the material of the first connection member N11 may include a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide.

[0299] The first connection member N11 may be connected to the first connection structure L1 , the second connection structure L2 , and the first sub-portion L01 of the third connection structure L3 .

[0300] Exemplarily, an insulating layer may be disposed between the first connector N11 and the first sub-layer N1 to insulate the first connector N11 from the first sub-layer N1.

[0301] Based on this, the process of forming the first connecting component N11 can be, for example: first, the first sub-layer N1 is etched to form a first opening, and the first opening exposes a portion of the surface of the first sub-part L01; then, an insulating layer is formed in the first opening; then, the insulating layer is etched to form a second opening, and the second opening exposes a portion of the surface of the first sub-part L01; finally, the first connecting component N11 is formed in the second opening, and the remaining part of the insulating layer insulates the first sub-layer N1 from the first connecting component N11.

[0302] In some embodiments, see Fig. 27 , after step S600, the preparation method may further include step S610.

[0303] S610: Form a second connection member N21. The second connection member N21 penetrates the second sub-layer N2 and is insulated from the second sub-layer N2.

[0304] Exemplarily, the material of the first connection member N11 may include a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide.

[0305] The second connection member N21 may be connected to the first connection structure L1 , the second connection structure L2 , and the second sub-portion L02 of the third connection structure L3 .

[0306] Illustratively, an insulating layer may be disposed between the second connector N21 and the second sub-layer N2 to insulate the second connector N21 from the second sub-layer N2.

[0307] Among them, the process of forming the second connecting component N21 can be, for example: first, the second sub-layer N2 is etched to form a third opening, and the third opening exposes a portion of the surface of the second sub-part L02; then, an insulating layer is formed in the third opening; then, the insulating layer is etched to form a fourth opening, and the fourth opening exposes a portion of the surface of the second sub-part L02; finally, the second connecting component N21 is formed in the fourth opening, and the remaining part of the insulating layer insulates the second sub-layer N2 from the second connecting component N21.

[0308] The first connection member N11 and the second connection member N21 are combined with the first sub-layer N1 and the second sub-layer N2 to form the first connection structure L1, the second connection structure L2 and the third sub-portion L03 of the third connection structure L3.

[0309] like Fig.28As shown, after the first connector N11 is combined with the second connector N21, the remaining portion of the insulating layer in the first opening and the remaining portion of the insulating layer in the third opening can form a third insulating dielectric layer M3, which insulates the third sub-portion L03 from the source layer SL.

[0310] In some examples, the material of the first connector N11 and the material of the second connector N21 may be the same.

[0311] Fig.40 is a block diagram of a storage system according to some embodiments. Fig.41 is a block diagram of a storage system according to some other embodiments.

[0312] See also Fig.40 and Fig.41 Some embodiments of the present disclosure further provide a storage system 200. The storage system 200 includes a controller 210 and the three-dimensional memory 100 of some embodiments above. The controller 210 is coupled to the three-dimensional memory 100 to control the three-dimensional memory 100 to store data.

[0313] The storage system 200 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 200 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0314] In some embodiments, see Fig.40 , the storage system 200 includes a controller 210 and a three-dimensional memory 100, and the storage system 200 can be integrated into a memory card.

[0315] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0316] In other embodiments, see Fig.41 The storage system 200 includes a controller 210 and a plurality of three-dimensional memories 100, and the storage system 200 is integrated into a solid state drive (SSD).

[0317] In the storage system 200, in some embodiments, the controller 210 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0318] In other embodiments, the controller 210 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0319] In some embodiments, the controller 210 may be configured to manage data stored in the three-dimensional memory 100 and communicate with an external device (e.g., a host). In some embodiments, the controller 210 may also be configured to control operations of the three-dimensional memory 100, such as read, erase, and program operations. In some embodiments, the controller 210 may also be configured to manage various functions regarding data stored or to be stored in the three-dimensional memory 100, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 210 is also configured to process error correction codes regarding data read from or written to the three-dimensional memory 100.

[0320] Of course, the controller 210 may also perform any other suitable functions, such as formatting the three-dimensional memory 100; for example, the controller 210 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0321] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0322] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0323] The electronic device may include the storage system 200 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0324] It can be understood that the technical effects that can be achieved by the electronic device provided by the above embodiments of the present disclosure are the same as the technical effects that can be achieved by the three-dimensional memory provided by the above embodiments of the present disclosure, and will not be repeated here.

[0325] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A three-dimensional memory, characterized in that: include: A first stacked structure comprising a plurality of first gate layers; A second stacked structure comprising a plurality of second gate layers; A first channel structure, penetrating the first stacking structure; A second channel structure, penetrating the second stack structure; A source layer is located between the first stacking structure and the second stacking structure along the stacking direction of the first stacking structure; and the first channel structure and the second channel structure are both connected to the source layer.

2. The three-dimensional memory according to claim 1, characterized in that: Also includes: A first peripheral device layer, located on a side of the first stacked structure away from the source layer; A first array interconnect layer, located between the first stacked structure and the first peripheral device layer; The first array interconnect layer includes a first bit line; the first peripheral device layer is connected to the first channel structure through the first bit line; A second array interconnection layer is located on a side of the second stacked structure away from the source layer; the second array interconnection layer comprises a second bit line, and the second bit line is connected to the second channel structure; a first connection structure, which penetrates the first stacking structure, the second stacking structure and the source layer, and is insulated from the plurality of first gate layers, the plurality of second gate layers and the source layer; The first bit line and the second bit line are connected via the first connection structure.

3. The three-dimensional memory according to claim 2, characterized in that: The first stacking structure and the second stacking structure each include a first storage block and a second storage block; the first channel structure and the second channel structure are located in the first storage block, and the first connection structure is located in the second storage block.

4. The three-dimensional memory according to claim 3, characterized in that: The first stacking structure and the second stacking structure include a plurality of the first storage blocks and a plurality of the second storage blocks, and any two adjacent second storage blocks among the plurality of the second storage blocks are separated by at least one first storage block.

5. The three-dimensional memory according to claim 1, characterized in that: Also includes: A second peripheral device layer is located on a side of the first stack structure away from the source layer; A third peripheral device layer is located on a side of the second stack structure away from the source layer; a third array interconnect layer, located between the second peripheral device layer and the first stacked structure, the third array interconnect layer comprising a third bit line, and the second peripheral device layer and the first channel structure are connected through the third bit line; A fourth array interconnection layer is located between the third peripheral device layer and the second stacked structure. The fourth array interconnection layer includes a fourth bit line. The third peripheral device layer and the second channel structure are connected through the fourth bit line.

6. The three-dimensional memory according to claim 5, characterized in that: Also includes: An external connection structure, which passes through the second peripheral device layer; a third connection structure, which penetrates the first stacking structure, the second stacking structure and the source layer, and is insulated from the plurality of first gate layers, the plurality of second gate layers and the source layer; Among them, the third array interconnection layer also includes a first switching structure, the fourth array interconnection layer also includes a second switching structure, one end of the third connection structure is connected to the external connection structure through the first switching structure, and the other end is connected to the third peripheral device layer through the second switching structure.

7. The three-dimensional memory according to any one of claims 1 to 6, characterized in that: The first stacked structure and the second stacked structure both include a predetermined surface away from the source layer; The three-dimensional memory further comprises: A first gate contact, extending from a predetermined surface of the first stacked structure to a corresponding first gate layer among the plurality of first gate layers, and connected to the corresponding first gate layer; The second gate contact extends from a predetermined surface of the second stack structure to a corresponding second gate layer among the plurality of second gate layers and is connected to the corresponding second gate layer.

8. The three-dimensional memory according to claim 7, characterized in that: In the case where the three-dimensional memory includes a first peripheral device layer, a first array interconnect layer and a second array interconnect layer, the first array interconnect layer further includes a first gate line and a second gate line, the first gate contact is connected to the first peripheral device layer through the first gate line; the second gate line is connected to the first peripheral device layer; The second array interconnection layer further comprises a connection line, and the connection line is contact-connected with the second gate; The three-dimensional memory further comprises: A second connection structure, wherein the second connection structure passes through the first stacking structure, the second stacking structure and the source layer, and is insulated from the multiple first gate layers, the multiple second gate layers and the source layer; the second gate contact is connected to the second connection structure through the connecting line, and the second connection structure is connected to the first peripheral device layer through the second gate line.

9. The three-dimensional memory according to claim 7, characterized in that: In the case where the three-dimensional memory includes a second peripheral device layer, a third peripheral device layer, a third array interconnect layer and a fourth array interconnect layer, The third array interconnection layer further includes a third gate line, the fourth array interconnection layer further includes a fourth gate line, the first gate contact is connected to the second peripheral device layer through the third gate line, and the second gate contact is connected to the third peripheral device layer through the fourth gate line.

10. The three-dimensional memory according to any one of claims 2 to 4, 6 and 8, characterized in that: The first connection structure, the second connection structure and the third connection structure each include: A first sub-portion, which passes through the first stacked structure and is insulated from the plurality of first gate layers; A second sub-portion, which passes through the second stacked structure and is insulated from the plurality of second gate layers; The third sub-section penetrates the source layer and is insulated from the source layer; the first sub-section and the second sub-section are both connected to the third sub-section.

11. The three-dimensional memory according to claim 10, characterized in that: In at least one of the first connecting structure, the second connecting structure and the third connecting structure, the cross-section of the first sub-portion along a first set direction is the same as the cross-section shape of the first channel structure along the first set direction, and the cross-section of the second sub-portion along the first set direction is the same as the cross-section shape of the second channel structure along the first set direction; the first setting direction is parallel to the stacking direction of the first stacking structure.

12. The three-dimensional memory according to claim 11, characterized in that: The three-dimensional memory includes a plurality of second gate contacts and a plurality of second connection structures correspondingly connected to the plurality of second gate contacts; the first stacking structure and the second stacking structure both include a first storage block and a second storage block; In the first storage block and / or the second storage block, the multiple second gate contacts are arranged in two rows along the second set direction, the multiple second connection structures are arranged in two rows along the second set direction, and the two rows of second connection structures are located between the two rows of second gate contacts; the second set direction is parallel to the surface of the first stacking structure away from the source layer.

13. The three-dimensional memory according to claim 11 or 12, characterized in that: An area of ​​an end surface of the second gate contact away from the source layer is larger than an area of ​​an end surface of the second sub-portion of the second connection structure away from the source layer.

14. The three-dimensional memory according to claim 10, characterized in that: In at least one of the first connection structure, the second connection structure and the third connection structure, the cross-section of the first sub-portion along the first set direction is the same as the cross-section shape of the first gate contact of the three-dimensional memory along the first set direction, and the cross-section of the second sub-portion along the first set direction is the same as the cross-section shape of the second gate contact of the three-dimensional memory along the first set direction; the first set direction is parallel to the stacking direction of the first stacking structure.

15. The three-dimensional memory according to claim 14, characterized in that: The three-dimensional memory includes a plurality of second gate contacts and a plurality of second connection structures correspondingly connected to the plurality of second gate contacts; the first stacking structure and the second stacking structure both include a first storage block and a second storage block; In the first storage block and / or the second storage block, the plurality of second gate contacts are arranged in two rows along a second set direction, some of the plurality of second connection structures are arranged in at least one row along the second set direction, the at least one row of second connection structures is located between the two rows of second gate contacts, and the remaining second connection structures of the plurality of second connection structures are dispersed in the two rows of second gate contacts; or, In the first storage block and / or the second storage block, the multiple second gate contacts and the multiple second connection structures are arranged in two rows along the second set direction, and in the same row, the second gate contacts and the second connection structures are alternately arranged; the second set direction is parallel to the surface of the first stacking structure away from the source layer.

16. The three-dimensional memory according to claim 14 or 15, characterized in that: An area of ​​an end surface of the second gate contact away from the source layer is equal to an area of ​​an end surface of the second sub-portion of the second connection structure away from the source layer.

17. The three-dimensional memory according to claim 7, characterized in that: In a direction parallel to the preset surface, a dimension of an end of the first gate contact away from the source layer is larger than a dimension of an end of the first gate contact close to the source layer, and a dimension of an end of the second gate contact away from the source layer is larger than a dimension of an end of the second gate contact close to the source layer.

18. The three-dimensional memory according to any one of claims 1 to 6, characterized in that: The first channel structure and the second channel structure each include at least one sub-channel structure; in a direction parallel to a preset surface, a size of an end of the sub-channel structure away from the source layer is larger than a size of an end of the sub-channel structure close to the source layer; The preset surface is a surface of the first channel structure away from the source layer.

19. The three-dimensional memory according to any one of claims 1 to 6, characterized in that: The first channel structure and the second channel structure each include at least one sub-channel structure; in a direction parallel to a preset surface, a size of an end of the sub-channel structure away from the source layer is smaller than a size of an end of the sub-channel structure close to the source layer; The preset surface is a surface of the first channel structure away from the source layer.

20. The three-dimensional memory according to any one of claims 1 to 6, characterized in that: The first channel structure includes a first channel layer, and the second channel structure includes a second channel layer; The first channel layer extends into the source layer, and the second channel layer extends into the source layer.

21. The three-dimensional memory according to any one of claims 1 to 6, characterized in that: Also includes: A first source contact, penetrating the first stacked structure and connected to the source layer; A second source contact, penetrating the second stacked structure and connected to the source layer; In the case where the three-dimensional memory includes a first peripheral device layer and a first array interconnect layer, the first source contact is connected to the first peripheral device layer through the first array interconnect layer; When the three-dimensional memory includes a second peripheral device layer, a third peripheral device layer, a third array interconnect layer and a fourth array interconnect layer, the first source contact is connected to the second peripheral device layer through the third array interconnect layer, and the second source contact is connected to the third peripheral device layer through the fourth array interconnect layer.

22. A method for preparing a three-dimensional memory, characterized in that: include: forming a first stack structure and a first channel structure on a first substrate; The first stacked structure includes a plurality of first gate layers, and the first channel structure runs through the first stacked structure; removing the first substrate; forming a first sublayer on the first stacked structure, wherein the first sublayer is connected to the first channel structure; forming a second stack structure and a second channel structure on a second substrate; The second stacked structure includes a plurality of second gate layers, and the second channel structure runs through the second stacked structure; removing the second substrate; forming a second sublayer on the second stacked structure, wherein the second sublayer is connected to the second channel structure; combining the first sub-layer and the second sub-layer to form a source layer; Along the stacking direction of the first stacking structure, the source layer is located between the first stacking structure and the second stacking structure.

23. The preparation method according to claim 22, characterized in that: Also includes: forming a first gate contact; The first gate contact extends from a surface of the first stacked structure away from the first substrate to a corresponding first gate layer among the plurality of first gate layers, and is connected to the corresponding first gate layer; or, the first gate contact extends from a surface of the first stacked structure for contacting the first substrate to a corresponding first gate layer among the plurality of first gate layers, and is connected to the corresponding first gate layer; A second gate contact is formed; the second gate contact extends from a surface of the second stacking structure away from the second substrate to a corresponding second gate layer among the multiple second gate layers, and is connected to the corresponding second gate layer; or, the second gate contact extends from a surface of the second stacking structure for contacting the second substrate to a corresponding second gate layer among the multiple second gate layers, and is connected to the corresponding second gate layer.

24. The preparation method according to claim 23, characterized in that: After forming the first gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method further includes: A first array interconnection layer is formed on the first stacked structure; the first array interconnection layer comprises a first bit line, a first gate line and a second gate line, the first bit line is connected to the first channel structure, and the first gate line is contact-connected to the first gate; Bonding the first array interconnect layer to the first peripheral device layer; connecting the first peripheral device layer to the first bit line, the first gate line and the second gate line; After forming the second gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method further includes: A second array interconnection layer is formed on the second stacked structure, the second array interconnection layer includes a second bit line and a connection line, the second bit line is connected to the second channel structure and the first bit line, the connection line is in contact with the second gate and connected to the second gate line.

25. The preparation method according to claim 24, characterized in that: The three-dimensional memory further includes a first connection structure and a second connection structure, wherein the first connection structure and the second connection structure each include a first sub-portion penetrating the first stacking structure and a second sub-portion penetrating the second stacking structure; The preparation method further comprises: while forming the first gate contact, forming a first sub-portion of the first connection structure and a first sub-portion of the second connection structure; while forming the second gate contact, forming a second sub-portion of the first connection structure and a second sub-portion of the second connection structure; or, While forming the first channel structure, forming a first sub-portion of the first connection structure and a first sub-portion of the second connection structure; while forming the second channel structure, forming a second sub-portion of the first connection structure and a second sub-portion of the second connection structure; or, While forming the first gate contact, a first subsection of the second connection structure is formed; while forming the second gate contact, a second subsection of the second connection structure is formed; while forming the first channel structure, a first subsection of the first connection structure is formed; while forming the second channel structure, a second subsection of the first connection structure is formed.

26. The preparation method according to claim 23, characterized in that: After forming the first gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method further includes: forming a third array interconnection layer on the first stacked structure, the third array interconnection layer comprising a third bit line and a third gate line, the third bit line is connected to the first channel structure, and the third gate line is contact-connected to the first gate; Bonding the third array interconnect layer to the second peripheral device layer; the third bit line and the third gate line are both connected to the second peripheral device layer; After forming the second gate contact and before combining the first sublayer and the second sublayer to form a source layer, the preparation method further includes: forming a fourth array interconnection layer on the second stacked structure, the fourth array interconnection layer comprising a fourth bit line and a fourth gate line, the fourth bit line being connected to the second channel structure, and the fourth gate line being contact-connected to the second gate; The fourth array interconnection layer is bonded to the third peripheral device layer; the fourth bit line and the fourth gate line are both connected to the third peripheral device layer.

27. The preparation method according to claim 26, characterized in that: The three-dimensional memory further includes a third connection structure, wherein the third connection structure includes a first sub-section penetrating the first stacking structure and a second sub-section penetrating the second stacking structure; and the preparation method further includes: forming a first sub-portion of the third connection structure while forming the first gate contact; forming a second sub-portion of the third connection structure while forming the second gate contact; or, The first sub-portion of the third connection structure is formed while the first channel structure is formed; and the second sub-portion of the third connection structure is formed while the second channel structure is formed.

28. A storage system, characterized in that: include: A three-dimensional memory, wherein the three-dimensional memory is the three-dimensional memory according to any one of claims 1 to 21; The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

29. An electronic device, characterized in that: Comprising the storage system of claim 28.

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