Semiconductor device

Abstract

A semiconductor device may include: a substrate; data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction crossing each other and parallel to a top surface of the substrate; first cell conductive lines extending in a first direction on the data storage pattern and spaced apart from each other in a second direction; cell via contacts spaced apart from each other in the first direction and disposed between the pair of first cell conductive lines; dummy data storage patterns spaced apart from each other in a first direction between the pair of first cell conductive lines and disposed between the cell via contacts; and upper conductive lines on and electrically connected to the cell via contacts, respectively.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a magnetic tunnel junction and / or a method of manufacturing the semiconductor device. Background Art

[0002] As electronic products tend to be high speed and / or low power consumption, semiconductor memory devices included in electronic products may increasingly require high speed and low operating voltage. Magnetic memory devices have been developed as semiconductor memory devices. Since magnetic memory devices can operate at high speed and can have non-volatile characteristics, they have attracted considerable attention as next generation semiconductor memory devices.

[0003] Typically, a magnetic memory device may include a magnetic tunnel junction (MTJ). A magnetic tunnel junction may include two magnetic structures and a dielectric layer interposed between them. The resistance of a magnetic tunnel junction may vary according to the magnetization directions of the two magnetic structures. For example, a magnetic tunnel junction may have a high resistance when the magnetization directions of the two magnetic structures are antiparallel, and a magnetic tunnel junction may have a low resistance when the magnetization directions of the two magnetic structures are parallel. A magnetic memory device may write and read data using the resistance difference between the high resistance and the low resistance of a magnetic tunnel junction. With the remarkable progress of the electronics industry, the demand for high integration and / or low power consumption of magnetic memory devices is increasing. Therefore, many studies have been conducted. Summary of the invention

[0004] Some embodiments of the inventive concepts provide semiconductor devices optimized for high integration.

[0005] Some embodiments of the inventive concept provide a semiconductor device having improved difficulty in a manufacturing process and a method of manufacturing the same.

[0006] Some embodiments of the inventive concept provide a semiconductor device having improved electrical characteristics and a method of manufacturing the same.

[0007] According to some embodiments of the inventive concept, a semiconductor device may include: a substrate; a plurality of data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate; a plurality of first unit conductive lines extending in the first direction on the data storage patterns and spaced apart from each other in the second direction, each of the plurality of first unit conductive lines being connected to data storage patterns of a corresponding column spaced apart from each other in the first direction among the plurality of data storage patterns; a plurality of unit via contacts spaced apart from each other in the first direction and arranged between a pair of first unit conductive lines among the plurality of first unit conductive lines; a plurality of dummy data storage patterns spaced apart from each other in the first direction and arranged between the pair of first unit conductive lines among the plurality of first unit conductive lines, the plurality of dummy data storage patterns being inserted between the plurality of unit via contacts; and a plurality of upper conductive lines on the plurality of unit via contacts and electrically connected to the plurality of unit via contacts, respectively.

[0008] According to some embodiments of the inventive concept, a semiconductor device may include: a substrate; a plurality of data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate; a plurality of first unit conductive lines extending in the first direction and spaced apart from each other in the second direction on the data storage patterns, each of the plurality of first unit conductive lines being connected to a corresponding column of data storage patterns spaced apart from each other in the first direction among the plurality of data storage patterns; a plurality of unit path contacts spaced apart from each other in the first direction and arranged between a pair of first unit conductive lines among the plurality of first unit conductive lines, the plurality of unit path contacts being aligned with the corresponding column of data storage patterns in the second direction, respectively; and a plurality of dummy data storage patterns spaced apart from each other in the first direction and arranged between the pair of first unit conductive lines among the plurality of first unit conductive lines, the plurality of dummy data storage patterns being arranged between the plurality of unit path contacts. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A circuit diagram showing a unit memory cell of a semiconductor device according to some embodiments of the inventive concept is shown.

[0010] Figure 2 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown.

[0011] Figure 3 Shown along Figure 2 A cross-sectional view taken along line AA′ of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0012] Figure 4Shown along Figure 2 A cross-sectional view taken along line BB′ of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0013] Figure 5 Shown along Figure 2 A cross-sectional view taken along line CC' of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0014] Fig. 6A and Figure 6B A cross-sectional view showing an example of a magnetic tunnel junction pattern according to some embodiments of the inventive concept is illustrated.

[0015] Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A Shown along Figure 2 A cross-sectional view taken along line AA′ of FIG. 1 shows a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0016] Figure 7B , Figure 8B , Fig. 9B and Fig. 10B Shown along Figure 2 A cross-sectional view taken along line CC' of FIG. 1 shows a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0017] Fig.11A Shown along Figure 2 A cross-sectional view taken along line AA′ of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0018] Fig. 11B Shown along Figure 2 A cross-sectional view taken along line CC' of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0019] Fig.12 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown.

[0020] Fig.13 Shown along Fig.12 A cross-sectional view taken along line DD' of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0021] Fig.14 Shown along Fig.12 A cross-sectional view taken along line EE' of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0022] Fig.15 Shown along Fig.12A cross-sectional view taken along line FF' of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept.

[0023] Fig.16A , Fig.17A , Fig.18A and Fig.19A Shown along Fig.12 A cross-sectional view taken along line DD′ of FIG. 1 shows a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0024] Fig. 16B , Fig. 17B , Fig.18B and Fig.19B Shown along Fig.12 A cross-sectional view taken along line EE' of FIG. 1 shows a method of manufacturing a semiconductor device according to some embodiments of the inventive concept.

[0025] Fig. 20 Shown along Fig.12 A cross-sectional view taken along line FF' of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0026] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the relevant numerical value includes a manufacturing or operating tolerance (e.g., ±10%) around the numerical value. In addition, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but that the latitude of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified as "about" or "substantially", it will be understood that these numerical values ​​and shapes should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the numerical value or shape. When a range is specified, the range includes all values ​​therebetween, such as increments of 0.1%.

[0027] Some embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0028] Figure 1 A circuit diagram showing a unit memory cell of a semiconductor device according to some embodiments of the inventive concept is shown. Figure 1 , the unit memory cell MC may include a memory element ME and a selection element SE. The memory element ME and the selection element SE may be electrically connected in series with each other. The memory element ME may be connected between the bit line BL and the selection element SE. The selection element SE may be connected between the memory element ME and the source line SL and may be controlled by the word line WL. The selection element SE may include, for example, a bipolar transistor or a metal oxide semiconductor (MOS) field effect transistor.

[0029] The storage element ME may include a magnetic tunnel junction pattern MTJ, which includes magnetic patterns MP1 and MP2 and a tunnel barrier pattern TBP between the magnetic patterns MP1 and MP2 spaced apart from each other. One of the magnetic patterns MP1 and MP2 may be a reference magnetic pattern having a fixed magnetization direction regardless of an external magnetic field under a normal use environment. The other of the magnetic patterns MP1 and MP2 may be a free magnetic pattern whose magnetization direction changes between two stable magnetization directions due to an external magnetic field. The magnetic tunnel junction pattern MTJ may have a much greater resistance value when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are antiparallel to each other than when the magnetization directions of the reference magnetic pattern and the free magnetic pattern are parallel to each other. For example, the resistance of the magnetic tunnel junction pattern MTJ may be controlled by changing the magnetization direction of the free magnetic pattern. The storage element ME may utilize a resistance difference depending on the magnetization direction of the reference magnetic pattern and the free magnetic pattern, and this mechanism may enable the unit memory cell MC to store data therein.

[0030] Figure 2 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown. Figure 3 Shown along Figure 2 A cross-sectional view taken along line AA'. Figure 4 Shown along Figure 2 A cross-sectional view taken along line BB'. Figure 5 Shown along Figure 2 A cross-sectional view taken along line CC'. Fig. 6A and Figure 6B A cross-sectional view showing an example of a magnetic tunnel junction pattern according to some embodiments of the inventive concept is illustrated.

[0031] Reference Figures 2 to 5 , a substrate 100 may be provided, and the substrate 100 may include a cell region CR and a peripheral region PR. The substrate 100 may be a semiconductor substrate including silicon (Si), silicon on insulator (SOI), silicon germanium (SiGe), germanium (Ge), or gallium arsenic (GaAs). The cell region CR may be a portion of the substrate 100 including Figure 1 The peripheral region PR may be a region of the substrate 100 including a peripheral circuit for driving the memory cells MC, and the peripheral region PR may be another region of the substrate 100 including a peripheral circuit for driving the memory cells MC.

[0032] Wiring structures 102 and 104 may be disposed on a substrate 100. Wiring structures 102 and 104 may be disposed on a cell region CR and a peripheral region PR of the substrate 100. Wiring structures 102 and 104 may include wiring lines 102 spaced vertically from the substrate 100 and wiring contacts 104 connected to the wiring lines 102. The wiring lines 102 may be spaced apart from the top surface 100U of the substrate 100 in a direction perpendicular to the top surface 100U of the substrate 100. The wiring contacts 104 may be disposed between the substrate 100 and the wiring lines 102. Each wiring line 102 may be electrically connected to the substrate 100 through a corresponding one of the wiring contacts 104. The wiring lines 102 and the wiring contacts 104 may include a metal (e.g., copper).

[0033] Select components (see Figure 1 The SE of the substrate 100 can be arranged at the cell region CR of the substrate 100, and the peripheral transistor constituting the peripheral circuit can be arranged at the peripheral region PR of the substrate 100. The selection element and the peripheral transistor can be, for example, a field effect transistor. Each wiring line 102 can be electrically connected to a terminal (for example, a source terminal, a drain terminal, or a gate terminal) of a corresponding one of the selection element or the peripheral transistor through a corresponding one of the wiring contacts 104.

[0034] The wiring dielectric layer 110 may be disposed on the substrate 100 to cover the wiring structures 102 and 104. The wiring dielectric layer 110 may be disposed on the cell region CR of the substrate 100 and may extend to the peripheral region PR of the substrate 100. The wiring dielectric layer 110 may expose the top surface of the uppermost wiring line of the wiring lines 102. For example, the wiring dielectric layer 110 may have a top surface that is substantially coplanar with the top surface of the uppermost wiring line 102. The wiring dielectric layer 110 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0035] The first lower dielectric layer 120 may be disposed on the wiring dielectric layer 110 and may cover the exposed top surface of the uppermost wiring line 102. The first lower dielectric layer 120 may be disposed on the wiring dielectric layer 110 on the cell region CR and may extend onto the wiring dielectric layer 110 on the peripheral region PR. The first lower dielectric layer 120 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0036] The second lower dielectric layer 130 may be disposed on the first lower dielectric layer 120. The second lower dielectric layer 130 may be disposed on the first lower dielectric layer 120 on the cell region CR and may extend onto the first lower dielectric layer 120 on the peripheral region PR. On the cell region CR and the peripheral region PR, the first lower dielectric layer 120 may be interposed between the wiring dielectric layer 110 and the second lower dielectric layer 130. The second lower dielectric layer 130 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. The first lower dielectric layer 120 and the second lower dielectric layer 130 may be referred to as lower dielectric layers.

[0037] The data storage patterns DS may be disposed on the second lower dielectric layer 130 on the cell region CR. The data storage patterns DS may be spaced apart from each other in a first direction D1 and a second direction D2 that intersect each other and are parallel to the top surface 100U of the substrate 100, and may be arranged along the first direction D1 at a first pitch P. The first pitch P may be defined as representing a distance between centers of a pair of data storage patterns DS that are adjacent to each other in the first direction D1.

[0038] The second lower dielectric layer 130 on the cell region CR may have a top surface 130RU recessed toward the substrate 100 between the data storage patterns DS. The second lower dielectric layer 130 on the peripheral region PR may have a top surface 130U located at a height (or level) lower than the height (or level) of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. In this specification, the term "height" may refer to a distance measured from the top surface 100U of the substrate 100 in a third direction D3 perpendicular to the top surface 100U of the substrate 100.

[0039] The lower electrode contacts 140 may be disposed in the second lower dielectric layer 130 on the cell region CR and may be spaced apart from each other in the first direction D1 and the second direction D2. The lower electrode contacts 140 may be disposed under corresponding ones of the data storage patterns DS and electrically connected to corresponding ones of the data storage patterns DS. Each lower electrode contact 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR and may be connected to a corresponding one of the topmost wiring lines 102. Each corresponding data storage pattern DS may be electrically connected to one terminal (e.g., a drain terminal) of a corresponding selection element through a corresponding lower electrode contact 140 and a corresponding topmost wiring line 102.

[0040] The lower electrode contact 140 may have a top surface 140U located at a height higher than that of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. The lower electrode contact 140 may include at least one selected from a doped semiconductor material (e.g., doped silicon), a metal (e.g., one or more of tungsten, titanium, and tantalum), a metal-semiconductor compound (e.g., metal silicide), and a conductive metal nitride (e.g., one or more of titanium nitride, tantalum nitride, and tungsten nitride).

[0041] Each data storage pattern DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the second lower dielectric layer 130 in the third direction D3. The magnetic tunnel junction pattern MTJ may be disposed between the bottom electrode BE and the top electrode TE. The lower electrode contact 140 may be connected to the bottom electrode BE of the data storage pattern DS accordingly. The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP. The bottom electrode BE may include, for example, a conductive metal nitride (e.g., titanium nitride or tantalum nitride). The top electrode TE may include at least one selected from a metal (e.g., Ta, W, Ru, or Ir) and a conductive metal nitride (e.g., TiN).

[0042] The data storage patterns DS may include first columns of data storage patterns DS spaced apart from each other in the first direction D1 and second columns of data storage patterns DS spaced apart from each other in the first direction D1. The second columns of data storage patterns DS may be spaced apart from the first columns of data storage patterns DS in the second direction D2.

[0043] The dummy data storage pattern DS_d may be disposed between the data storage pattern DS of the first column and the data storage pattern DS of the second column, and may be spaced apart from each other in the first direction D1. The dummy data storage pattern DS_d may be spaced apart from the data storage pattern DS of the first column in the second direction D2, and the data storage pattern DS of the second column may be spaced apart from the dummy data storage pattern DS_d in the second direction D2. The dummy data storage pattern DS_d may be offset from the data storage pattern DS of the first column and the data storage pattern DS of the second column in the first direction D1. The dummy data storage pattern DS_d may not be electrically connected to the lower electrode contact 140. The dummy data storage pattern DS_d may be configured substantially identically to the data storage pattern DS. Each dummy data storage pattern DS_d may include a bottom electrode BE, a top electrode TE, and a magnetic tunnel junction pattern MTJ between the bottom electrode BE and the top electrode TE.

[0044] Reference Fig. 6A and Figure 6B The first magnetic pattern MP1 may be a reference layer having a magnetization direction MD1 fixed in one direction, and the second magnetic pattern MP2 may be a free layer having a magnetization direction MD2 that can be changed to be parallel or antiparallel to the magnetization direction MD1 of the first magnetic pattern MP1. Fig. 6A and Figure 6B An example in which the second magnetic pattern MP2 is a free layer is shown, but the inventive concept is not limited thereto. Fig. 6A and Figure 6B Different from what is shown, the first magnetic pattern MP1 may be a free layer, and the second magnetic pattern MP2 may be a reference layer.

[0045] Reference Fig. 6A , for example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 may be perpendicular to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include at least one selected from an intrinsic perpendicular magnetic material and an extrinsic perpendicular magnetic material. The intrinsic perpendicular magnetic material may include a material having a perpendicular magnetization property even in the absence of external factors. The intrinsic perpendicular magnetic material may include a material selected from a perpendicular magnetic material (e.g., CoFeTb, CoFeGd, CoFeDy), a material having L1 0 At least one selected from a perpendicular magnetic material with a structure, a CoPt with a hexagonal close-packed (HCP) lattice structure, and a perpendicular magnetization structure. 0 The vertical magnetic material of the structure can include L1 0 Structure of FePt, L1 0 Structure of FePd, L1 0 CoPd and L1 of the structure0 The perpendicular magnetic structure may include magnetic layers and non-magnetic layers that are alternately and repeatedly stacked.

[0046] For example, the vertical magnetic structure may include at least one selected from (Co / Pt)n, (CoFe / Pt)n, (CoFe / Pd)n, (Co / Pd)n, (Co / Ni)n, (CoNi / Pt)n, (CoCr / Pt)n, and (CoCr / Pd)n (where n is the number of stacked layers). The non-intrinsic vertical magnetic material may include a material having an intrinsic horizontal magnetization characteristic or a vertical magnetization characteristic caused by an external factor. For example, the non-intrinsic vertical magnetic material may have a vertical magnetization characteristic due to magnetic anisotropy caused by the junction between the tunnel barrier pattern TBP and the first magnetic pattern MP1 (or the second magnetic pattern MP2). The non-intrinsic vertical magnetic material may include, for example, CoFeB.

[0047] Reference Figure 6B For another example, the magnetization direction MD1 of the first magnetic pattern MP1 and the magnetization direction MD2 of the second magnetic pattern MP2 may be parallel to the interface between the tunnel barrier pattern TBP and the second magnetic pattern MP2. In this case, each of the first magnetic pattern MP1 and the second magnetic pattern MP2 may include a ferromagnetic material. The first magnetic pattern MP1 may also include an antiferromagnetic material for fixing the magnetization direction of the ferromagnetic material in the first magnetic pattern MP1.

[0048] Each of the first and second magnetic patterns MP1 and MP2 may include a Heusler alloy including Co. The tunnel barrier pattern TBP may include at least one selected from a magnesium (Mg) oxide layer, a titanium (Ti) oxide layer, an aluminum (Al) oxide layer, a magnesium-zinc (MgZn) oxide layer, and a magnesium-boron (MgB) oxide layer.

[0049] Return to reference Figures 2 to 5 , a capping dielectric layer 150 may be disposed on the second lower dielectric layer 130 on the cell region CR. The capping dielectric layer 150 may conformally cover the side surface of each data storage pattern DS and the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR. When viewed in a plan view, the capping dielectric layer 150 may surround the side surface of each data storage pattern DS. The capping dielectric layer 150 may conformally cover the side surface of the bottom electrode BE, the side surface of the magnetic tunnel junction pattern MTJ, and the side surface of the top electrode TE. When viewed in a plan view, the capping dielectric layer 150 may surround the side surface of the bottom electrode BE, the side surface of the magnetic tunnel junction pattern MTJ, and the side surface of the top electrode TE. The capping dielectric layer 150 may include a nitride (e.g., silicon nitride).

[0050] The unit dielectric layer 160 may be disposed on the second lower dielectric layer 130 on the unit region CR and may cover the data storage pattern DS. The unit dielectric layer 160 may fill the space between the data storage patterns DS. The cover dielectric layer 150 may be interposed between the unit dielectric layer 160 and the side surface of each data storage pattern DS, and may extend between the unit dielectric layer 160 and the recessed top surface 130RU of the second lower dielectric layer 130 on the unit region CR. The unit dielectric layer 160 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. For example, the unit dielectric layer 160 may include tetraethyl orthosilicate (TEOS) oxide.

[0051] The upper dielectric layer 170 may be disposed on the cell dielectric layer 160 on the cell region CR. The upper dielectric layer 170 may include a material different from that of the cell dielectric layer 160. The upper dielectric layer 170 may include silicon nitride (eg, SiCN).

[0052] The peripheral dielectric layer 180 may be disposed on the second lower dielectric layer 130 on the peripheral region PR. The top surface 130U of the second lower dielectric layer 130 on the peripheral region PR may be located at a height lower than the height of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR, and the peripheral dielectric layer 180 may be in contact with the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR. The peripheral dielectric layer 180 may be in contact with the side surface 160S of the cell dielectric layer 160 and the side surface 170S of the upper dielectric layer 170. The top surface 180U of the peripheral dielectric layer 180 may be located at the same height as the top surface 170U of the upper dielectric layer 170. The top surface 180U of the peripheral dielectric layer 180 may be coplanar with the top surface 170U of the upper dielectric layer 170.

[0053] The peripheral dielectric layer 180 may include a material different from that of the unit dielectric layer 160. The peripheral dielectric layer 180 may include a dielectric material having a dielectric constant (k) less than that of the unit dielectric layer 160. The peripheral dielectric layer 180 may include a material different from that of the upper dielectric layer 170, and may include a dielectric material having a dielectric constant (k) less than that of the upper dielectric layer 170. The peripheral dielectric layer 180 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. For example, the peripheral dielectric layer 180 may include a dielectric material, such as porous SiOC, whose dielectric constant (k) is equal to or less than 2.5 or 2.0.

[0054] The first unit conductive lines 192 may be disposed on the unit region CR. The first unit conductive lines 192 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. Each first unit conductive line 192 may have a linear shape extending in the first direction D1. Each first unit conductive line 192 may be electrically connected to a corresponding data storage pattern DS spaced apart from each other in the first direction D1 among the data storage patterns DS. The data storage patterns DS spaced apart from each other in the second direction D2 among the data storage patterns DS may be electrically connected to the corresponding first unit conductive lines 192.

[0055] Each first unit conductive line 192 may pass through the upper portion of the upper dielectric layer 170 and the unit dielectric layer 160 to be connected with the corresponding data storage pattern DS spaced apart from each other in the first direction D1. Each first unit conductive line 192 may have a bottom surface 192L in contact with the corresponding data storage pattern DS spaced apart from each other in the first direction D1 or with the top surface TE of each of the corresponding data storage patterns DS spaced apart from each other in the first direction D1. The first unit conductive line 192 may include a conductive material such as a metal (e.g., copper).

[0056] The cell via contacts 200 may be disposed between the first cell conductive lines 192 on the cell region CR. The cell via contacts 200 may be spaced apart from each other in the first direction D1 between the first cell conductive lines 192. The cell via contacts 200 may be aligned in the second direction D2 with data storage patterns DS arranged in the second direction D2 among the data storage patterns DS.

[0057] The dummy data storage pattern DS_d may be interposed between the cell via contacts 200. The cell via contacts 200 and the dummy data storage pattern DS_d may be alternately disposed along the first direction D1 between the first cell conductive lines 192. The cell via contacts 200 and the dummy data storage pattern DS_d may be spaced apart from each other along the first direction D1 by a second pitch P'. The second pitch P' may be defined as representing the distance between the center of the cell via contact 200 and the center of the dummy data storage pattern DS_d immediately adjacent in the first direction D1. The second pitch P' may be smaller than the first pitch P, for example, approximately half of the first pitch P.

[0058] According to the inventive concept, the dummy data storage pattern DS_d can be formed between the cell via contacts 200 and adjacent to the cell via contacts 200 in the first direction D1. Therefore, a bridge failure of connecting the cell via contacts 200 to each other can be limited and / or prevented. As a result, the semiconductor device can improve electrical characteristics.

[0059] Furthermore, since the dummy data storage pattern DS_d is disposed between the cell via contacts 200, there is no need to additionally form the dummy data storage pattern DS_d on a region adjacent to the cell via contact 200. Therefore, integration of the data storage pattern DS disposed on the cell region CR may be increased, and as a result, integration of the semiconductor device may be easy.

[0060] Each cell via contact 200 may include a first vertical portion 200V extending in the third direction D3 between the data storage patterns DS and a second vertical portion 200V′ extending in the third direction D3 below the first vertical portion 200V. The second vertical portion 200V′ may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR and may be connected to a corresponding one of the uppermost wiring lines 102. Each cell via contact 200 may be electrically connected to a corresponding selection element (see Figure 1 The cell via contact 200 may include a terminal (eg, a gate terminal) of the SE of the cell. The cell via contact 200 may include the same material as that of the first cell conductive line 192. The cell via contact 200 may include a conductive material such as a metal (eg, copper).

[0061] The first vertical portion 200V may have a top surface 200U located at the same height as the top surface 192U of the first unit conductive line 192 and the top surface 170U of the upper dielectric layer 170. The top surface 200U of the first vertical portion 200V may be coplanar with the top surface 192U of the first unit conductive line 192 and the top surface 170U of the upper dielectric layer 170. The top surface 200U of the first vertical portion 200V may be referred to as a top surface of each unit via contact 200.

[0062] According to some embodiments, a cell dielectric pattern 182 may be disposed on the cell region CR. The cell dielectric pattern 182 may penetrate the cell dielectric layer 160 and the cover dielectric layer 150 and may extend into the second lower dielectric layer 130. The cell dielectric pattern 182 may include the same material as that of the peripheral dielectric layer 180. The cell dielectric pattern 182 may include a dielectric material having a dielectric constant (k) less than that of the cell dielectric layer 160. The cell dielectric pattern 182 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride. For example, the cell dielectric pattern 182 may include a dielectric material having a dielectric constant (k) equal to or less than 2.5 or 2.0, such as porous SiOC.

[0063] Each cell via contact 200 may penetrate the upper dielectric layer 170, the cell dielectric layer 160, the cell dielectric pattern 182, the second lower dielectric layer 130, and the first lower dielectric layer 120. A first vertical portion 200V of each cell via contact 200 may penetrate the upper dielectric layer 170, and may penetrate an upper portion of the cell dielectric layer 160 and an upper portion of the cell dielectric pattern 182. A second vertical portion 200V′ of each cell via contact 200 may be disposed in the cell dielectric pattern 182. The second vertical portion 200V′ of each cell via contact 200 may penetrate a lower portion of the cell dielectric pattern 182, the second lower dielectric layer 130, and the first lower dielectric layer 120, and may be connected to a corresponding uppermost wiring line 102.

[0064] The peripheral conductive line 210 may be disposed in the peripheral dielectric layer 180 and on the second lower dielectric layer 130 on the peripheral region PR. The peripheral dielectric layer 180 may cover the peripheral conductive line 210. The peripheral conductive line 210 may have a top surface 210U that is not covered by the peripheral dielectric layer 180 and is exposed. The top surface 210U of the peripheral conductive line 210 may be coplanar with the top surface 180U of the peripheral dielectric layer 180. The top surface 210U of the peripheral conductive line 210 may be located at the same height as the top surface 180U of the peripheral dielectric layer 180. The top surface 210U of the peripheral conductive line 210 may be located at the same height as the top surface 180U of the peripheral dielectric layer 180. The top surface 210U of the peripheral conductive line 210 may be located at the same height as the top surface 192U of the first unit conductive line 192, the top surface 200U of the unit via contact 200, and the top surface 170U of the upper dielectric layer 170. A top surface 210U of the peripheral conductive line 210 may be coplanar with a top surface 192U of the first unit conductive line 192 , a top surface 200U of the unit via contact 200 , and a top surface 170U of the upper dielectric layer 170 .

[0065] The peripheral conductive contact 220 may be disposed below the peripheral conductive line 210 on the peripheral region PR. The peripheral conductive contact 220 may be electrically connected to the peripheral conductive line 210. Each peripheral conductive contact 220 and its corresponding one peripheral conductive line 210 may contact each other without an interface. Each peripheral conductive contact 220 and its corresponding peripheral conductive line 210 may be connected to form a single integral piece. Each peripheral conductive contact 220 may penetrate the lower portion of the peripheral dielectric layer 180. Each peripheral conductive contact 220 may penetrate the second lower dielectric layer 130 and the first lower dielectric layer 120 on the peripheral region PR, and may be electrically connected to a corresponding one of the topmost wiring lines 102. Each peripheral conductive line 210 may be electrically connected to one terminal (e.g., source terminal, drain terminal, or gate terminal) of the corresponding peripheral transistor through the corresponding peripheral conductive contact 220 and the corresponding topmost wiring line 102.

[0066] The peripheral conductive line 210 and the peripheral conductive contact 220 may include a conductive material such as a metal (eg, copper). The first cell conductive line 192, the cell via contact 200, the peripheral conductive line 210, and the peripheral conductive contact 220 may include the same material.

[0067] The first interlayer dielectric layer 230 may be disposed on the cell region CR and the peripheral region PR, and may cover the top surface 170U of the upper dielectric layer 170, the top surface 192U of the first cell conductive line 192, the top surface 200U of the cell via contact 200, the top surface 180U of the peripheral dielectric layer 180, and the top surface 210U of the peripheral conductive line 210. The first interlayer dielectric layer 230 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0068] The second cell conductive line 196 may be disposed in the first interlayer dielectric layer 230 on the cell region CR. The second cell conductive lines 196 may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. The second cell conductive line 196 may vertically overlap the first cell conductive line 192 (e.g., in the third direction D3), respectively. The first conductive contact 194 may be disposed in the first interlayer dielectric layer 230 on the cell region CR and may be located between the first cell conductive line 192 and the second cell conductive line 196. The first cell conductive line 192 may be electrically connected to the corresponding second cell conductive line 196 through the corresponding first conductive contact 194. The bit line 190 (see Figure 1 The first unit conductive line 192, the corresponding first conductive contact 194, and the corresponding second unit conductive line 196 may be composed of a first unit conductive line 192, a corresponding first conductive contact 194, and a corresponding second unit conductive line 196. The first conductive contact 194 and the second unit conductive line 196 may include a conductive material such as a metal (eg, copper).

[0069] The second interlayer dielectric layer 240 may be disposed on the cell region CR and the peripheral region PR and may cover a top surface of the second cell conductive line 196. The second interlayer dielectric layer 240 may include, for example, one or more of silicon oxide, silicon nitride, and silicon oxynitride.

[0070] The upper conductive line 260 may be disposed on the second interlayer dielectric layer 240 on the cell region CR. The upper conductive line 260 may extend in the second direction D2 and may be spaced apart from each other in the first direction D1. The upper conductive line 260 may extend across the first cell conductive line 192 and the second cell conductive line 196 and may be located at a height higher than that of the first cell conductive line 192 and the second cell conductive line 196. The second conductive contacts 250 may be correspondingly disposed on the cell via contacts 200 and may be spaced apart from each other in the first direction D1. The second conductive contacts 250 may be correspondingly connected to the upper conductive lines 260. Each upper conductive line 260 may be electrically connected to a corresponding cell via contact 200 through a corresponding second conductive contact 250. Each upper conductive line 260 may be used as Figure 1 The upper conductive line 260 and the second conductive contact 250 may include a conductive material such as metal (eg, copper).

[0071] In addition, the cell via contact 200 may electrically connect the upper conductive line 260 to the wiring line 102 in the wiring structures 102 and 104. The upper conductive line 260 may have a larger line width (or thickness or size) than the line width of the wiring line 102 in the wiring structures 102 and 104, and thus may have a relatively small resistance. Each upper conductive line 260 may be used as Figure 1 The word line WL can therefore be reduced Figure 1 Therefore, a semiconductor device with improved electrical characteristics can be provided.

[0072] 7A to 10B A cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments of the inventive concept is shown. Specifically, Fig. 7A , Fig. 8A , Fig.9A and Fig. 10A Shown along Figure 2 A cross-sectional view taken along line AA′ of FIG. 1 shows a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Figure 7B , Figure 8B , Fig. 9B and Fig. 10B Shown along Figure 2 A cross-sectional view taken along line CC' of FIG. 1 shows a method for manufacturing a semiconductor device according to some embodiments of the inventive concept. For the sake of brevity of description, it will be omitted to avoid reference to Figures 2 to 5 , Fig. 6A and Figure 6B Repeated description of the semiconductor device discussed.

[0073] Reference Figure 2 , Fig. 7A and Figure 7B, a substrate 100 may be provided, the substrate 100 including a cell region CR and a peripheral region PR. Selecting elements (see Figure 1 The selection element and the peripheral transistor may be formed at the substrate 100, and the wiring structures 102 and 104 may be formed on the selection element and the peripheral transistor. The wiring structures 102 and 104 may include wiring lines 102 spaced apart vertically (e.g., in the third direction D3) from the substrate 100, and may also include wiring contacts 104 connected to the wiring lines 102. Each wiring line 102 may be electrically connected to one terminal (e.g., source terminal, drain terminal, or gate terminal) of a corresponding one of the selection element or the peripheral transistor through a corresponding one of the wiring contacts 104.

[0074] The wiring dielectric layer 110 may be formed on the substrate 100, and may cover the wiring structures 102 and 104. The wiring dielectric layer 110 may expose a top surface of an uppermost wiring line among the wiring lines 102.

[0075] The first lower dielectric layer 120 may be formed on the wiring dielectric layer 110 and may cover the exposed top surface of the uppermost wiring line 102. The first lower dielectric layer 120 may be formed on the wiring dielectric layer 110 on the cell region CR and may extend onto the wiring dielectric layer 110 on the peripheral region PR.

[0076] The second lower dielectric layer 130 may be formed on the first lower dielectric layer 120. The second lower dielectric layer 130 may be formed on the first lower dielectric layer 120 on the cell region CR, and may extend onto the first lower dielectric layer 120 on the peripheral region PR.

[0077] The lower electrode contacts 140 may be formed in the second lower dielectric layer 130 on the cell region CR. Each of the lower electrode contacts 140 may penetrate the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR and may be electrically connected to one of the uppermost wiring lines 102. The formation of the lower electrode contacts 140 may, for example, include: forming a lower contact hole penetrating the first lower dielectric layer 120 and the second lower dielectric layer 130 on the cell region CR; forming a lower contact layer filling the lower contact hole on the second lower dielectric layer 130; and planarizing the lower contact layer until the top surface of the second lower dielectric layer 130 is exposed. In the planarization process, the lower electrode contacts 140 may be locally formed in the corresponding lower contact holes.

[0078] The data storage patterns DS may be formed on the second lower dielectric layer 130 on the cell region CR. The lower electrode contacts 140 may be disposed under and electrically connected to corresponding ones of the data storage patterns DS. The dummy data storage patterns DS_d not connected to the lower electrode contacts 140 may be formed by the same or substantially the same method as that for forming the data storage patterns DS.

[0079] Each data storage pattern DS may include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the second lower dielectric layer 130. The magnetic tunnel junction pattern MTJ may include a first magnetic pattern MP1, a second magnetic pattern MP2, and a tunnel barrier pattern TBP between the first magnetic pattern MP1 and the second magnetic pattern MP2. The first magnetic pattern MP1 may be disposed between the bottom electrode BE and the tunnel barrier pattern TBP, and the second magnetic pattern MP2 may be disposed between the top electrode TE and the tunnel barrier pattern TBP. The formation of the data storage pattern DS may, for example, include: sequentially forming a bottom electrode layer and a magnetic tunnel junction layer on the second lower dielectric layer 130; forming a conductive mask pattern on the magnetic tunnel junction layer; and sequentially etching the magnetic tunnel junction layer and the bottom electrode layer using the conductive mask pattern as an etching mask.

[0080] The magnetic tunnel junction layer may include a first magnetic layer, a tunnel barrier layer, and a second magnetic layer stacked sequentially on the bottom electrode layer. The magnetic tunnel junction layer and the bottom electrode layer may be formed by, for example, a sputtering process, a chemical vapor deposition process, or an atomic layer deposition process. The mask layer may be patterned to form a conductive mask pattern for forming a data storage pattern DS. The mask layer may include a top electrode layer and a hard mask layer stacked sequentially. The hard mask layer may be formed by, for example, one or more of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

[0081] The magnetic tunnel junction layer and the bottom electrode layer may be etched to form a magnetic tunnel junction pattern MTJ and a bottom electrode BE, respectively. The etching of the magnetic tunnel junction layer may include etching the second magnetic layer, the tunnel barrier layer, and the first magnetic layer in sequence using the conductive mask pattern as an etching mask. The second magnetic layer, the tunnel barrier layer, and the first magnetic layer may be etched to form a second magnetic pattern MP2, a tunnel barrier pattern TBP, and a first magnetic pattern MP1. After the magnetic tunnel junction layer and the bottom electrode layer are etched, the conductive mask pattern may remain on the magnetic tunnel junction pattern MTJ, and the remaining portion of the conductive mask pattern may be defined as a top electrode TE.

[0082] An ion beam etching process using an ion beam may be used to perform an etching process for etching the magnetic tunnel junction layer and the bottom electrode layer. The ion beam may include inert ions. The etching process may form a recess in the upper portion of the second lower dielectric layer 130 between the data storage patterns DS. Therefore, the second lower dielectric layer 130 on the cell region CR may have a recessed top surface 130RU (which is recessed toward the substrate 100). The recessed top surface 130RU of the second lower dielectric layer 130 may be located at a height lower than the height of the top surface 140U of the lower electrode contact 140. In addition, the etching process may recess the upper portion of the second lower dielectric layer 130 on the peripheral region PR.

[0083] The second lower dielectric layer 130 on the peripheral region PR may have a top surface 130U located at a height (or level) lower than that of the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR.

[0084] The conductive mask pattern may define a region where the data storage pattern DS and the dummy data storage pattern DS_d are to be formed, and may be uniformly disposed on the cell region CR.

[0085] The layout difference between the region where the cell via contact 200 described later is to be formed and the surrounding region (e.g., the difference in pattern density of the conductive mask pattern) can be reduced. Therefore, the region where the cell via contact 200 is to be formed can be restricted and / or prevented from being over-etched in the etching process of the magnetic tunnel junction layer and the bottom electrode layer. Therefore, the difficulty of etching the magnetic tunnel junction layer and the bottom electrode layer can be reduced.

[0086] The cover dielectric layer 150 may be formed on the second lower dielectric layer 130 on the cell region CR and may conformally cover the top surface and side surfaces of each of the data storage pattern DS and the dummy data storage pattern DS_d. The cover dielectric layer 150 may conformally cover the recessed top surface 130RU of the second lower dielectric layer 130 on the cell region CR and may extend onto the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR.

[0087] Reference Figure 2 , Fig. 8A and Figure 8B, the cell dielectric layer 160 may be formed on the cover dielectric layer 150. Since the cell dielectric layer 160 covers the cover dielectric layer 150 on the cell region CR, the cell dielectric layer 160 may cover the data storage pattern DS and the dummy data storage pattern DS_d and may fill the space between the data storage patterns DS. The cell dielectric layer 160 may extend onto the cover dielectric layer 150 on the peripheral region PR. The cell dielectric layer 160 may be formed by using, for example, high density plasma chemical vapor deposition (HDP CVD).

[0088] The upper dielectric layer 170 may be formed on the cell dielectric layer 160. The upper dielectric layer 170 may be formed on the cell dielectric layer 160 on the cell region CR, and may extend onto the cell dielectric layer 160 on the peripheral region PR.

[0089] The peripheral opening OP_P may be formed on the peripheral region PR and may expose the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR. The formation of the peripheral opening OP_P may include removing the upper dielectric layer 170, the unit dielectric layer 160, and the covering dielectric layer 150 from the peripheral region PR. For example, the formation of the peripheral opening OP_P may include forming a unit mask pattern on the upper dielectric layer 170 on the unit region CR and etching the upper dielectric layer 170, the unit dielectric layer 160, and the covering dielectric layer 150 from the peripheral region PR using the unit mask pattern as an etching mask. The unit mask pattern may be, for example, a photoresist pattern. In the etching process, the upper dielectric layer 170, the unit dielectric layer 160, and the covering dielectric layer 150 on the peripheral region PR may be removed to expose the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR.

[0090] According to some embodiments, the cell opening OP_C may be formed on the cell region CR. The cell opening OP_C may pass through the upper dielectric layer 170, the cell dielectric layer 160, and the cover dielectric layer 150 between the data storage patterns DS spaced apart from each other in the second direction D2, and may extend into the second lower dielectric layer 130. The formation of the cell opening OP_C may, for example, include forming a cell mask pattern on the upper dielectric layer 170 on the cell region CR and etching the upper dielectric layer 170, the cell dielectric layer 160, the cover dielectric layer 150, and a portion of the second lower dielectric layer 130 between the data storage patterns DS using the cell mask pattern as an etching mask. According to some embodiments, the cell mask pattern may include an opening defining an area where the cell opening OP_C is to be formed. Thereafter, the cell mask pattern may be removed. The cell mask pattern may be removed by performing, for example, one or more of an ashing process and a stripping process.

[0091] Reference Figure 2 , Fig.9A and Fig. 9B , a peripheral dielectric layer 180 may be formed to fill the peripheral opening OP_P. The peripheral dielectric layer 180 may contact the top surface 130U of the second lower dielectric layer 130 on the peripheral region PR. The peripheral dielectric layer 180 may contact the side surface 160S of the cell dielectric layer 160 on the cell region CR and the side surface 170S of the upper dielectric layer 170 on the cell region CR.

[0092] According to some embodiments, a cell dielectric pattern 182 may be formed to fill the cell opening OP_C. The peripheral dielectric layer 180 and the cell dielectric pattern 182 may include a dielectric material whose dielectric constant is less than that of the cell dielectric layer 160 and the upper dielectric layer 170. The peripheral dielectric layer 180 and the cell dielectric pattern 182 may include the same material. The formation of the peripheral dielectric layer 180 and the cell dielectric pattern 182 may, for example, include forming a dielectric layer filling the peripheral opening OP_P and the cell opening OP_C and planarizing the dielectric layer until the top surface of the upper dielectric layer 170 is exposed. The dielectric layer may be formed by using, for example, chemical vapor deposition. The planarization process may be performed by using, for example, at least one selected from an etch-back process and a chemical mechanical polishing process.

[0093] Reference Figure 2 , Fig. 10A and Fig. 10B , the first unit trenches 192T may be formed on the cell region CR. The first unit trenches 192T may extend in the first direction D1 and may be spaced apart from each other in the second direction D2. The first unit trenches 192T may each have a linear shape extending in the first direction D1, and may expose corresponding data storage patterns DS spaced apart from each other in the first direction D1 among the data storage patterns DS. Each first unit trench 192T may penetrate the upper portion of the upper dielectric layer 170 and the unit dielectric layer 160. The bottom surface 192TL of the first unit trench 192T may correspondingly expose the top electrode TE of the corresponding data storage pattern DS.

[0094] The cell via holes 200H may be formed between the first cell trenches 192T on the cell region CR, and may be spaced apart from each other in the first direction D1 between the first cell trenches 192T. The cell via holes 200H may be spaced apart from the first cell trenches 192T horizontally (e.g., in the second direction D2). In addition, the cell via holes 200H may be aligned with the data storage patterns DS spaced apart from each other in the second direction D2 in the second direction D2, and may be formed between the dummy data storage patterns DS_d spaced apart from each other in the first direction D1. The cell via holes 200H and the dummy data storage patterns DS_d may be alternately disposed along the first direction D1.

[0095] Each unit via hole 200H may include a first vertical hole 200VH and a second vertical hole 200VH', the second vertical hole 200VH' extending from the first vertical hole 200VH along the third direction D3 and between the data storage patterns DS. According to some embodiments, the first vertical hole 200VH of each unit via contact 200 may penetrate the upper dielectric layer 170, the upper portion of the unit dielectric layer 160, and the upper portion of the unit dielectric pattern 182. According to some embodiments, the second vertical hole 200VH' may be disposed in the unit dielectric pattern 182. The second vertical hole 200VH' may penetrate the unit dielectric pattern 182, the second lower dielectric layer 130, and the first lower dielectric layer 120, and may expose the top surface of a corresponding one of the uppermost wiring lines 102.

[0096] The peripheral trench 210T may be formed in the peripheral dielectric layer 180 on the peripheral region PR. Each peripheral trench 210T may penetrate an upper portion of the peripheral dielectric layer 180 on the peripheral region PR. The peripheral hole 220H may extend from the bottom surface of the peripheral trench 210T toward the substrate 100 along the third direction D3. Each peripheral hole 220H may penetrate a lower portion of the peripheral dielectric layer 180 on the peripheral region PR, the second lower dielectric layer 130, and the first lower dielectric layer 120, thereby exposing a top surface of a corresponding one of the uppermost wiring lines 102.

[0097] The first etching process may form the first unit trench 192T, the first vertical hole 200VH, and the peripheral trench 210T. The first etching process may, for example, include forming a first mask pattern defining an area on which the first unit trench 192T, the first vertical hole 200VH, and the peripheral trench 210T are formed, and etching the upper dielectric layer 170, the unit dielectric layer 160, the unit dielectric pattern 182, and the peripheral dielectric layer 180 using the first mask pattern as an etching mask. The first unit trench 192T, the first vertical hole 200VH, and the peripheral trench 210T may be simultaneously formed in the first etching process.

[0098] The second etching process may form the peripheral hole 220H and the second vertical hole 200VH' of each unit via hole 200H. The second etching process may, for example, include forming a second mask pattern that defines an area on which the peripheral hole 220H and the second vertical hole 200VH' of each unit via hole 200H are formed, and etching the unit dielectric pattern 182, the peripheral dielectric layer 180, the second lower dielectric layer 130, and the first lower dielectric layer 120 using the second mask pattern as an etching mask. The peripheral hole 220H and the second vertical hole 200VH' of each unit via hole 200H may be simultaneously formed in the second etching process.

[0099] Return to reference Figures 2 to 5 The first cell conductive line 192 may be formed in the first cell trench 192T, and the cell via contact 200 may be formed in the cell via hole 200H. The peripheral conductive line 210 may be formed in the peripheral trench 210T, and the peripheral conductive contact 220 may be formed in the peripheral hole 220H.

[0100] The formation of the first cell conductive line 192, the cell via contact 200, the peripheral conductive line 210, and the peripheral conductive contact 220 may, for example, include forming a first conductive layer filling the cell via hole 200H, the peripheral trench 210T, and the peripheral hole 220H on the upper dielectric layer 170 and the peripheral dielectric layer 180, and planarizing the first conductive layer until the top surface 170U of the upper dielectric layer 170 and the top surface 180U of the peripheral dielectric layer 180 are exposed. The planarization process may allow the first cell conductive line 192 to have a top surface 192U located at the same height as the top surface 170U of the upper dielectric layer 170, the top surface 200U of the cell via contact 200, the top surface 180U of the peripheral dielectric layer 180, and the top surface 210U of the peripheral conductive line 210.

[0101] The first interlayer dielectric layer 230 may be formed on the cell region CR and the peripheral region PR and may cover a top surface 170U of the upper dielectric layer 170, a top surface 192U of the first cell conductive line 192, a top surface 200U of the cell via contact 200, a top surface 180U of the peripheral dielectric layer 180, and a top surface 210U of the peripheral conductive line 210.

[0102] The second unit conductive line 196 and the first conductive contact 194 may be formed in the first interlayer dielectric layer 230. The formation of the second unit conductive line 196 and the first conductive contact 194 may, for example, include: forming a second unit trench penetrating an upper portion of the first interlayer dielectric layer 230; forming a first hole penetrating a lower portion of the first interlayer dielectric layer 230 from a bottom surface of the second unit trench; forming a second conductive layer filling the second unit trench and the first hole on the first interlayer dielectric layer 230; and planarizing the second conductive layer until the top surface of the first interlayer dielectric layer 230 is exposed.

[0103] The second interlayer dielectric layer 240 may be formed on the cell region CR and the peripheral region PR, and may cover the top surface of the second cell conductive line 196. The upper conductive line 260 may be formed on the second interlayer dielectric layer 240 on the cell region CR, and the second conductive contact 250 may be formed in the second interlayer dielectric layer 240. The second conductive contact 250 may penetrate the first interlayer dielectric layer 230 and the second interlayer dielectric layer 240 to be connected to the corresponding cell via contact 200. The upper conductive line 260 and the second conductive contact 250 may be formed by, for example, the same or substantially the same method as that used to form the second cell conductive line 196 and the first conductive contact 194.

[0104] The cell via contact 200 may be used as Figure 1 The upper conductive line 260 of the word line WL is electrically connected to the wiring line 102 in the wiring structures 102 and 104. The upper conductive line 260 may have a resistance smaller than that of the wiring line 102 in the wiring structures 102 and 104, thereby reducing the Figure 1 The resistance of the word line WL of the memory cell MC.

[0105] Embodiments of the inventive concepts may provide a semiconductor device having improved electrical performance and / or a method of manufacturing the same.

[0106] Fig.11A Shown along Figure 2 A cross-sectional view taken along line AA′ of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept. Fig. 11B Shown along Figure 2 The cross-sectional view taken along the line CC' of FIG. 1 shows a semiconductor device according to some embodiments of the inventive concept. The following semiconductor device is similar to the semiconductor device of FIG. 1 . Figures 2 to 5 , Fig. 6A and Figure 6B The semiconductor devices discussed here are mainly different from each other, so for the sake of brevity of description, the main differences between the semiconductor devices will be described below. Figure 2 , Fig.11A and Fig. 11B According to some embodiments, reference to Figure 3The cell dielectric pattern 182 discussed. In this case, each cell via contact 200 may penetrate the upper dielectric layer 170, the cell dielectric layer 160, the cover dielectric layer 150, the second lower dielectric layer 130, and the first lower dielectric layer 120. The first vertical portion 200V of each cell via contact 200 may penetrate the upper portion of the upper dielectric layer 170 and the cell dielectric layer 160. The second vertical portion 200V' of each cell via contact 200 may extend toward the substrate 100. The second vertical portion 200V' may penetrate the lower portion of the cell dielectric layer 160, the cover dielectric layer 150, the second lower dielectric layer 130, and the first lower dielectric layer 120, and may be connected to a corresponding one of the uppermost wiring lines 102. In addition to the above, the semiconductor device according to the present embodiment is different from the reference Figure 5 , Fig. 6A and Figure 6B The semiconductor devices discussed are essentially the same.

[0107] Fig.12 A plan view showing a semiconductor device according to some embodiments of the inventive concept is shown. Fig.13 Shown along Fig.12 A cross-sectional view taken along line D-D'. Fig.14 Shown along Fig.12 A cross-sectional view taken along line EE'. Fig.15 Shown along Fig.12 The following semiconductor device is similar to the reference Figures 2 to 5 , Fig. 6A and Figure 6B The semiconductor devices discussed are described below, so for the sake of brevity of description, the main differences between the semiconductor devices will be described below.

[0108] Reference Figures 12 to 15 According to some embodiments, the data storage pattern DS may include a first column of data storage patterns DS spaced apart from each other in a first direction D1 and a second column of data storage patterns DS spaced apart from each other in the first direction D1. The second column of data storage patterns DS may be spaced apart from the first column of data storage patterns DS in a second direction D2.

[0109] The dummy data storage pattern DS_d may be disposed between the data storage pattern DS of the first column and the data storage pattern DS of the second column, and may be spaced apart from each other in the first direction D1. The dummy data storage pattern DS_d may be spaced apart from the data storage pattern DS of the first column in the second direction D2, and the data storage pattern DS of the second column may be spaced apart from the dummy data storage pattern DS_d in the second direction D2. The dummy data storage pattern DS_d may be aligned with the data storage pattern DS of the first column and the data storage pattern DS of the second column in the second direction D2.

[0110] The cell via contact 200 may be disposed between the first cell conductive lines 192 on the cell region CR. The cell via contact 200 may be disposed between the data storage pattern DS of the first column and the data storage pattern DS of the second column, and may be spaced apart from each other in the first direction D1. The cell via contact 200 may be spaced apart from the data storage pattern DS of the first column in the second direction D2, and the data storage pattern DS of the second column may be spaced apart from the cell via contact 200 in the second direction D2. The cell via contact 200 may be arranged to be offset from the data storage pattern DS of the first column and the data storage pattern DS of the second column in the first direction D1.

[0111] The dummy data storage pattern DS_d and the cell via contact 200 may be spaced apart from each other by a second pitch P' along the first direction D1. The second pitch P' may be smaller than the first pitch P, for example, approximately half of the first pitch P. In addition to the above, the semiconductor device according to the present embodiment is similar to the reference Figure 5 , Fig. 6A and Figure 6B The semiconductor devices discussed are essentially the same.

[0112] Fig.16A , Fig.17A , Fig.18A and Fig.19A Shown along Fig.12 A cross-sectional view taken along line DD′ of FIG. 1 shows a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. Fig. 16B , Fig. 17B , Fig.18B and Fig.19B Shown along Fig.12 The cross-sectional view taken along the line EE' of FIG. 1 shows a method of manufacturing a semiconductor device according to some embodiments of the inventive concept. The semiconductor device below is similar to the semiconductor device of FIG. 1 . Figures 2 to 5 , Fig. 6A , Figure 6B , Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B The semiconductor devices discussed are described below, so for the sake of brevity of description, the main differences between the semiconductor devices will be described below.

[0113] Reference Fig.12 , Fig.16A and Fig. 16B, the data storage pattern DS and the dummy data storage pattern DS_d may each include a bottom electrode BE, a magnetic tunnel junction pattern MTJ, and a top electrode TE sequentially stacked on the second lower dielectric layer 130. The formation of the dummy data storage pattern DS_d may, for example, include: sequentially forming a bottom electrode layer and a magnetic tunnel junction layer on the second lower dielectric layer 130; forming a conductive mask pattern on the magnetic tunnel junction layer; and sequentially etching the magnetic tunnel junction layer and the bottom electrode layer using the conductive mask pattern as an etching mask.

[0114] The data storage patterns DS may include first columns of data storage patterns DS spaced apart in the first direction D1 and second columns of data storage patterns DS spaced apart in the first direction D1. The second columns of data storage patterns DS may be spaced apart from the first columns of data storage patterns DS in the second direction D2.

[0115] The dummy data storage patterns DS_d may be disposed between the data storage patterns DS of the first column and the data storage patterns DS of the second column and may be spaced apart from each other in the first direction D1. Each dummy data storage pattern DS_d may be formed to be aligned in the second direction D2 with the data storage patterns DS arranged in the second direction D2 among the data storage patterns DS.

[0116] Reference Fig.12 , Fig.17A and Fig. 17B According to some embodiments, the cell opening OP_C may be formed on the cell region CR. The cell opening OP_C may be formed to be offset in the first direction D1 from the data storage patterns DS arranged in the first direction D1. The cell opening OP_C may expose the second lower dielectric layer 130 between the data storage patterns DS_d spaced apart from each other in the first direction D1, may penetrate the upper dielectric layer 170, the cell dielectric layer 160, and the cover dielectric layer 150, and may extend into the second lower dielectric layer 130.

[0117] Reference Fig.12 , Fig.18A and Fig.18B According to some embodiments, a cell dielectric pattern 182 may be formed to fill the cell opening OP_C. Fig.12 , Fig.19A and Fig.19B , a cell via hole 200H may be formed between the first cell trenches 192T on the cell region CR. The cell via holes 200H may be spaced apart from each other in the first direction D1 between the first cell trenches 192T, and may be spaced apart horizontally (e.g., in the second direction D2) from the first cell trenches 192T. The cell via holes 200H may be formed to be offset in the first direction D1 from the data storage patterns DS arranged in the first direction D1.

[0118] Return to reference Figures 12 to 15 , an upper conductive line 260 may be formed on the second interlayer dielectric layer 240 on the cell region CR, and a second conductive contact 250 may be formed in the second interlayer dielectric layer 240. The second conductive contact 250 may penetrate the first interlayer dielectric layer 230 and the second interlayer dielectric layer 240 to be connected to the corresponding cell via contact 200. The upper conductive line 260 and the second conductive contact 250 may be formed by, for example, the same or substantially the same method as the method for forming the second cell conductive line 196 and the first conductive contact 194. Except for the above, the method of manufacturing a semiconductor device according to the present embodiment is the same as that of the reference embodiment. Fig. 7A , Fig. 8A , Fig.9A , Fig. 10A , Figure 7B , Figure 8B , Fig. 9B and Fig. 10B The approach discussed is essentially the same.

[0119] Fig. 20 Shown along Fig.12 The cross-sectional view taken along the line F-F' shows a semiconductor device according to some embodiments of the inventive concept. Fig.12 The differences in semiconductor devices discussed. Fig.12 and Fig. 20 According to some embodiments, it can be omitted Fig.14 and Fig.15 The cell dielectric pattern 182 shown. In this case, each cell via contact 200 may penetrate the upper dielectric layer 170, the cell dielectric layer 160, the cover dielectric layer 150, the second lower dielectric layer 130, and the first lower dielectric layer 120. The first vertical portion 200V of each cell via contact 200 may penetrate the upper portion of the upper dielectric layer 170 and the cell dielectric layer 160. The second vertical portion 200V' of each cell via contact 200 may extend toward the substrate 100. The second vertical portion 200V' may penetrate the lower portion of the cell dielectric layer 160, the cover dielectric layer 150, the second lower dielectric layer 130, and the first lower dielectric layer 120, and may be connected to a corresponding one of the uppermost wiring lines 102. In addition to the above, the semiconductor device according to the present embodiment is different from the reference Figures 12 to 15 The semiconductor devices discussed are essentially the same.

[0120] According to an embodiment of the inventive concept, a semiconductor device may include cell via contacts spaced apart from each other in a first direction between first cell conductive lines, and may further include dummy data storage patterns spaced apart from each other in the first direction between the first cell conductive lines and interposed between the cell via contacts.

[0121] Since the dummy data storage pattern is disposed between the cell via contacts, it may not be necessary to form an additional dummy data storage pattern on a region adjacent to the cell via contacts. Therefore, integration of the data storage pattern may be increased, and as a result, integration of the semiconductor device may be easy.

[0122] In addition, in the etching process for forming the data storage pattern and the dummy data storage pattern, the conductive mask pattern can be uniformly arranged on the cell area. Therefore, the area where the cell path contact is formed can be limited and / or prevented from being over-etched. Therefore, the semiconductor device can improve the manufacturing difficulty.

[0123] In addition, the upper conductive line having a relatively small resistance can be connected to the selection element at the substrate through the cell via contact and can be used as a word line. Therefore, the resistance of the word line included in the memory cell can be reduced.

[0124] While example embodiments of the inventive concepts have been particularly shown and described, it will be understood by those skilled in the art that changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0125] This application claims the priority of Korean Patent Application No. 10-2023-0106748 filed in the Korean Intellectual Property Office on August 16, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: substrate; a plurality of data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate; a plurality of first unit conductive lines extending in the first direction on the data storage patterns and spaced apart from each other in the second direction, each of the plurality of first unit conductive lines being connected to data storage patterns of a corresponding column spaced apart from each other in the first direction among the plurality of data storage patterns; a plurality of unit via contacts spaced apart from each other in the first direction and disposed between a pair of first unit conductive lines among the plurality of first unit conductive lines; a plurality of dummy data storage patterns spaced apart from each other in the first direction and disposed between the pair of first unit conductive lines among the plurality of first unit conductive lines, the plurality of dummy data storage patterns being interposed between the plurality of unit via contacts; as well as A plurality of upper conductive lines are on the plurality of cell via contacts and are electrically connected to the plurality of cell via contacts, respectively. 2 . The semiconductor device according to claim 1 , wherein the plurality of cell via contacts and the plurality of dummy data storage patterns are alternately disposed along the first direction between the pair of first cell conductive lines among the plurality of first cell conductive lines.

3. The semiconductor device according to claim 1, further comprising: A plurality of first conductive contacts are respectively on the plurality of unit via contacts, wherein Each of the plurality of upper conductive lines is electrically connected to a corresponding one of the plurality of cell via contacts through a corresponding one of the plurality of first conductive contacts.

4. The semiconductor device according to claim 1, wherein Top surfaces of the plurality of unit via contacts are at the same height as top surfaces of the plurality of first unit conductive lines. 5 . The semiconductor device according to claim 1 , wherein a material of the plurality of unit via contacts is the same as a material of the plurality of first unit conductive lines. 6 . The semiconductor device according to claim 1 , wherein the plurality of dummy data storage patterns are offset from the data storage patterns of the corresponding columns in the first direction. 7 . The semiconductor device according to claim 6 , wherein the plurality of cell via contacts are aligned in the second direction with data storage patterns of corresponding rows arranged in the second direction among the plurality of data storage patterns. 8 . The semiconductor device according to claim 1 , wherein the plurality of cell via contacts are offset from the data storage patterns of the corresponding columns in the first direction. 9 . The semiconductor device of claim 8 , wherein each of the plurality of dummy data storage patterns is aligned in the second direction with a corresponding row of data storage patterns arranged in the second direction among the plurality of data storage patterns.

10. The semiconductor device according to claim 9, wherein The data storage patterns of the respective columns are spaced apart from each other at a first pitch along the first direction, The plurality of cell via contacts and the plurality of dummy data storage patterns are spaced apart from each other at a second pitch along the first direction, and The second pitch is smaller than the first pitch. The semiconductor device according to claim 10 , wherein the second pitch is half of the first pitch.

12. The semiconductor device according to claim 1, further comprising: a wiring structure between the substrate and the plurality of data storage patterns; and A plurality of lower electrode contacts are provided between the wiring structure and the plurality of data storage patterns, wherein The plurality of lower electrode contacts are respectively connected to corresponding data storage patterns among the plurality of data storage patterns, The plurality of lower electrode contacts are respectively connected to corresponding uppermost conductive lines among the uppermost conductive lines of the wiring structure, and The plurality of unit vias are contact-connected to other corresponding uppermost conductive lines among the uppermost conductive lines of the wiring structure.

13. The semiconductor device according to claim 12, further comprising: a wiring dielectric layer on the substrate and covering the wiring structure; a first lower dielectric layer on the wiring dielectric layer; as well as a second lower dielectric layer on the first lower dielectric layer and covering the plurality of lower electrode contacts, wherein The plurality of data storage patterns are on the second lower dielectric layer, The plurality of lower electrode contacts penetrate the second lower dielectric layer and the first lower dielectric layer to be connected to the corresponding uppermost conductive lines of the wiring structure, the second lower dielectric layer has a top surface recessed between the plurality of data storage patterns, and A lowest point of a top surface of the recess of the second lower dielectric layer has a height lower than a height of top surfaces of the plurality of lower electrode contacts.

14. The semiconductor device according to claim 13, wherein The substrate includes a cell region and a peripheral region, The plurality of lower electrode contacts, the plurality of data storage patterns, the plurality of first cell conductive lines, the plurality of dummy data storage patterns and the plurality of upper conductive lines are on the cell region, The wiring dielectric layer, the first lower dielectric layer, and the second lower dielectric layer cover the cell region and the peripheral region, and A top surface of the second lower dielectric layer on the peripheral region is lower than the lowest point of the top surface of the recess of the second lower interlayer dielectric layer.

15. The semiconductor device according to claim 13, further comprising: a unit dielectric layer on the lower dielectric layer, wherein the unit dielectric layer covers the plurality of data storage patterns and the plurality of dummy data storage patterns, and The plurality of cell via contacts penetrate the cell dielectric layer and are connected to the other respective uppermost conductive lines of the wiring structure.

16. The semiconductor device according to claim 1, further comprising: a plurality of second unit conductive lines extending in the first direction on the plurality of first unit conductive lines and spaced apart from each other in the second direction; and A plurality of first conductive contacts are respectively provided between the plurality of first unit conductive lines and the plurality of second unit conductive lines, wherein The plurality of second unit conductive lines are respectively electrically connected to the plurality of first unit conductive lines through the plurality of first conductive contacts. 17 . The semiconductor device according to claim 16 , wherein heights of the plurality of upper conductive lines are higher than heights of the plurality of second unit conductive lines.

18. A semiconductor device comprising: substrate; a plurality of data storage patterns on the substrate and spaced apart from each other in a first direction and a second direction, the first direction and the second direction intersecting each other and being parallel to a top surface of the substrate; a plurality of first unit conductive lines extending in the first direction on the data storage patterns and spaced apart from each other in the second direction, each of the plurality of first unit conductive lines being connected to data storage patterns of a corresponding column spaced apart from each other in the first direction among the plurality of data storage patterns; a plurality of cell via contacts spaced apart from each other in the first direction and disposed between a pair of first cell conductive lines among the plurality of first cell conductive lines, the plurality of cell via contacts being aligned with the data storage patterns of the corresponding columns in the second direction, respectively; as well as A plurality of dummy data storage patterns are spaced apart from each other in the first direction and disposed between the pair of first unit conductive lines among the plurality of first unit conductive lines, the plurality of dummy data storage patterns being disposed between the plurality of unit via contacts.

19. The semiconductor device according to claim 18, further comprising: a plurality of first conductive contacts, respectively on the plurality of unit via contacts; and a plurality of upper conductive lines, on and respectively connected to the plurality of first conductive contacts, The plurality of upper conductive lines are electrically connected to the plurality of cell via contacts through the plurality of first conductive contacts, respectively. 20 . The semiconductor device of claim 18 , wherein the plurality of dummy data storage patterns are offset from the data storage patterns of the corresponding columns in the first direction.

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