Display device and manufacturing method of active element substrate

Abstract

The invention discloses a display device and a manufacturing method of an active component substrate. The display device comprises a substrate, a first correction mark, an insulating layer, a semiconductor layer, a gate dielectric layer, a gate, an interlayer dielectric layer, a source and a drain. The substrate is provided with a display area and a peripheral area surrounding the display area. The peripheral area comprises a correction mark area, and the display area comprises an active component area. The first correction mark is located on the correction mark area. The insulating layer is located on the substrate and extends from the active component area to the correction mark area. The insulating layer has a correction opening overlapping the first correction mark. The semiconductor layer is located on the active element region. The insulating layer at least partially overlaps the semiconductor layer. The gate dielectric layer is located on the semiconductor layer and the correction opening.

Description

Technical Field

[0001] The invention relates to a display device and a manufacturing method of an active component substrate. Background Art

[0002] In many display devices, thin film transistors are used to process signals, and these thin film transistors may be arranged in a driving circuit or in a pixel structure. Generally speaking, electrode material layers and semiconductor material layers are deposited by thin film deposition technology, and these electrode material layers and semiconductor material layers are subjected to a patterning process to obtain electrodes and semiconductor layers in thin film transistors. Generally speaking, a photoresist pattern is used as a mask for patterning. However, in the process of making a photoresist pattern, the formed photoresist pattern may deviate from the expected position due to alignment problems, thereby affecting the yield of the thin film transistor. Summary of the invention

[0003] At least one embodiment of the present invention provides a method for manufacturing an active component substrate, comprising the following steps. An alignment mark and a first correction mark are formed on the alignment mark area and the correction mark area of ​​the substrate, respectively. An insulating layer is formed to extend from the active component area of ​​the substrate to the correction mark area. A semiconductor layer is formed on the active component area. A first photoresist pattern is formed on the semiconductor layer and the insulating layer according to the alignment mark. A first ion implantation process is performed on the semiconductor layer using the first photoresist pattern as a mask to form a first doped region in the semiconductor layer. The insulating layer is etched using the first photoresist pattern as a mask to form a correction opening in the insulating layer that overlaps the first correction mark. The first photoresist pattern is removed. A gate dielectric layer is formed on the semiconductor layer and the correction opening. A gate, an interlayer dielectric layer, a source, and a drain are formed on the gate dielectric layer.

[0004] At least one embodiment of the present invention provides a method for manufacturing an active device substrate, comprising the following steps. An alignment mark and a first correction mark are formed on the alignment mark area and the correction mark area of ​​the substrate, respectively. A buffer layer is formed to extend from the active device area of ​​the substrate to the correction mark area. A semiconductor layer is formed on the buffer layer and on the active device area. An insulating layer is formed on the semiconductor layer and extends from the active device area of ​​the substrate to the correction mark area. A first photoresist pattern is formed on the insulating layer according to the alignment mark. A first ion implantation process is performed on the semiconductor layer using the first photoresist pattern as a mask to form a first doped region in the semiconductor layer. The insulating layer is etched using the first photoresist pattern as a mask to form a correction opening in the insulating layer that overlaps the first correction mark. The first photoresist pattern is removed. A gate dielectric layer is formed on the semiconductor layer, the insulating layer, and the correction opening. A gate, an interlayer dielectric layer, a source, and a drain are formed on the gate dielectric layer.

[0005] At least one embodiment of the present invention provides a display device, which includes a substrate, a first correction mark, an insulating layer, a semiconductor layer, a gate dielectric layer, a gate, an interlayer dielectric layer, a source and a drain. The substrate has a display area and a peripheral area surrounding the display area. The peripheral area includes a correction mark area, and the display area includes an active device area. The first correction mark is located above the correction mark area. The insulating layer is located on the substrate and extends from the active device area to the correction mark area. The insulating layer has a correction opening overlapping the first correction mark. The semiconductor layer is located above the active device area. The insulating layer at least partially overlaps the semiconductor layer. The gate dielectric layer is located on the semiconductor layer and the correction opening. The gate, the interlayer dielectric layer, the source and the drain are located on the gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 is a schematic top view of a display device according to an embodiment of the present invention;

[0007] Figure 2 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0008] FIG. 3A to FIG. 3O Is manufacturing Figure 2 A schematic cross-sectional view of each stage of the display device;

[0009] Figure 4 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0010] Figure 5 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0011] Figure 6 is a cross-sectional schematic diagram of a display device according to an embodiment of the present invention;

[0012] FIG. 7A to FIG. 7P Is manufacturing Figure 6 A cross-sectional schematic diagram of various stages of the display device.

[0013] Explanation of symbols

[0014] 10,20,30,40: Display device

[0015] 100:Substrate

[0016] 112: First calibration mark

[0017] 113: Alignment mark

[0018] 114: Light shielding layer

[0019] 116: first capacitor electrode

[0020] 120A, 120B: Insulation layer

[0021] 120A-1: First floor

[0022] 120A-2: Second floor

[0023] 122: Correction opening

[0024] 123: Alignment opening

[0025] 124: Groove

[0026] 132: Semiconductor layer

[0027] 132a: first doping region

[0028] 132a-1: Part I

[0029] 132a-2: Part 2

[0030] 132b: second doping region

[0031] 132c: lightly doped region

[0032] 132d: Channel area

[0033] 134: second capacitor electrode

[0034] 140: Gate dielectric layer

[0035] 150: conductive material layer

[0036] 152: Second calibration mark

[0037] 154: Gate

[0038] 156: third capacitor electrode

[0039] 160: Interlayer dielectric layer

[0040] 172: Source

[0041] 174: Drain

[0042] 180: Display unit

[0043] AA: Display area

[0044] BL: Buffer layer

[0045] C: Capacitor

[0046] CR: Capacitor region

[0047] H1,H2: Open

[0048] IP1: The first ion implantation process

[0049] IP2: Second ion implantation process

[0050] IP3: The third ion implantation process

[0051] MR: Correction Marker Region

[0052] NR: Registration mark area

[0053] PA: Peripheral area

[0054] PR1: First photoresist pattern

[0055] PR2A~PR2C: Second photoresist pattern

[0056] TFT: Thin Film Transistor

[0057] TR: Active component area DETAILED DESCRIPTION

[0058] Figure 1 is a top view schematic diagram of a display device according to an embodiment of the present invention. Figure 1 The substrate 100 of the display device has a display area AA and a peripheral area PA surrounding the display area AA. The shape of the display area AA can be adjusted according to needs, such as a rectangle, a circle, an ellipse or other suitable shapes.

[0059] An array of pixel structures is disposed on the display area AA, each pixel structure including an active element (e.g., a thin film transistor), a passive element (e.g., a capacitor), and other suitable elements. In some embodiments, the pixel structure also includes a display unit, such as a micro light emitting diode, an organic photodiode, a liquid crystal medium, an electrophoretic medium, or other suitable elements.

[0060] Various circuit structures are provided on the peripheral area PA, and these circuit structures are, for example, used to provide signals to the pixel structures on the display area AA. In the present embodiment, the peripheral area PA includes a correction mark area MR and an alignment mark area NR. The correction mark area MR is provided with marks for detecting / correcting the exposure manufacturing process in the process of manufacturing the display device. The alignment mark area NR is provided with marks for alignment in the process of manufacturing the display device. The correction mark area MR and the alignment mark area NR can be located at any position in the peripheral area PA. In the present embodiment, the correction mark area MR is located at the four corners of the peripheral area PA, and the alignment mark area NR is located at the edge of the peripheral area PA, but the present invention is not limited thereto. In other embodiments, the correction mark area MR and the alignment mark area NR can also be set at other positions.

[0061] Figure 2is a cross-sectional schematic diagram of a display device 10 (also referred to as an active device substrate) according to an embodiment of the present invention. Figure 2 Shows Figure 1 The display area AA and the peripheral area PA are shown in Figure 2. Figure 2 The display device 10 includes a substrate 100, a first correction mark 112, an alignment mark 113, a light shielding layer 114, a first capacitor electrode 116, an insulating layer 120A, a semiconductor layer 132, a second capacitor electrode 134, a gate dielectric layer 140, a second correction mark 152, a gate 154, a third capacitor electrode 156, an interlayer dielectric layer 160, a source 172, a drain 174 and a display unit 180.

[0062] The substrate 100 has a display area AA and a peripheral area PA surrounding the display area AA (see Figure 1 ). The peripheral area PA includes an alignment mark area NR and a calibration mark area MR, and the display area AA includes an active device area TR and a capacitor area CR. The thin film transistor TFT and the capacitor C are respectively located on the active device area TR and the capacitor area CR. The alignment mark 113 is located on the alignment mark area NR. The first calibration mark 112 and the second calibration mark 152 are located on the calibration mark area MR.

[0063] The thin film transistor TFT includes a light shielding layer 114 , a semiconductor layer 132 , a gate electrode 154 , a source electrode 172 , and a drain electrode 174 . The capacitor C includes a first capacitor electrode 116 , a second capacitor electrode 134 , and a third capacitor electrode 156 .

[0064] The light shielding layer 114 and the first capacitor electrode 116 are located on the substrate 100. In this embodiment, the light shielding layer 114 and the first capacitor electrode 116 are separated from each other, but the present invention is not limited thereto. In other embodiments, the light shielding layer 114 and the first capacitor electrode 116 are connected.

[0065] The first calibration mark 112 and the alignment mark 113 are located on the substrate 100. In this embodiment, the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 are separated from each other.

[0066] The insulating layer 120A is located on the substrate 100 and extends from the active device region TR and the capacitor region CR to the alignment mark region NR and the calibration mark region MR. The insulating layer 120A surrounds the light shielding layer 114, the first capacitor electrode 116, the first calibration mark 112, and the alignment mark 113. In the present embodiment, the insulating layer 120A has a calibration opening 122 and an alignment opening 123, and the calibration opening 122 is located on the calibration mark region MR and overlaps the first calibration mark 112. The alignment opening 123 is located on the alignment mark region NR and does not overlap the alignment mark 113. In some embodiments, the width of the calibration opening 122 is greater than the width of the first calibration mark 112, but the present invention is not limited thereto.

[0067] In this embodiment, the insulating layer 120A covers the top surface of the first calibration mark 112, the top surface of the alignment mark 113, the top surface of the light shielding layer 114, and the top surface of the first capacitor electrode 116. In other words, the first calibration mark 112, the alignment mark 113, the light shielding layer 114, and the first capacitor electrode 116 are located between the insulating layer 120A and the substrate 100. In other embodiments, the calibration opening 122 extends to the top surface of the first calibration mark 112, so that the insulating layer 120A does not cover the top surface of the first calibration mark 112.

[0068] The semiconductor layer 132 and the second capacitor electrode 134 are respectively located on the active device region TR and the capacitor region CR. The insulating layer 120A at least partially overlaps the semiconductor layer 132. In the present embodiment, the insulating layer 120A overlaps the semiconductor layer 132 and the second capacitor electrode 134, and the insulating layer 120A is located between the semiconductor layer 132 and the substrate 100 and between the second capacitor electrode 134 and the substrate 100. In some embodiments, the insulating layer 120A has a groove 124 that overlaps the sidewall of the semiconductor layer 132. In some embodiments, one of the sidewalls of the semiconductor layer 132 overlaps the groove 124, while the other sidewall does not overlap the groove 124. In addition, in some embodiments, the sidewall of the second capacitor electrode 134 also overlaps the groove 124.

[0069] The semiconductor layer 132 includes a first doped region 132a, a second doped region 132b, a lightly doped region 132c, and a channel region 132d. The lightly doped region 132c and the channel region 132d are located between the first doped region 132a and the second doped region 132b. The lightly doped region 132c is located between the channel region 132d and the second doped region 132b, and the channel region 132d is located between the first doped region 132a and the lightly doped region 132c. In the semiconductor layer 132, the channel region 132d has a lower doping concentration (or is undoped) and has the highest resistivity. The first doped region 132a and the second doped region 132b have a higher doping concentration (also referred to as a heavily doped region) and have the lowest resistivity. The doping concentration of the lightly doped region 132c is lower than the doping concentration of the first doped region 132a and the second doped region 132b, and the resistivity of the lightly doped region 132c is higher than the resistivity of the first doped region 132a and the second doped region 132b. In addition, in some embodiments, the doping concentration of the first doping region 132 a is equal to or different from the doping concentration of the second doping region 132 b .

[0070] The second capacitor electrode 134 overlaps the first capacitor electrode 116, and a portion of the insulating layer 120A is located between the second capacitor electrode 134 and the first capacitor electrode 116. The doping concentration of the second capacitor electrode 134 is substantially the same as the doping concentration of the first doping region 132a, and both have similar resistivities.

[0071] The gate dielectric layer 140 is disposed on the semiconductor layer 132 , the second capacitor electrode 134 and the insulating layer 120A. In this embodiment, the gate dielectric layer 140 is disposed on the correction opening 122 , the alignment opening 123 and the groove 124 of the insulating layer 120A and fills the correction opening 122 , the alignment opening 123 and the groove 124 .

[0072] The second calibration mark 152 , the gate 154 , and the third capacitor electrode 156 are located on the gate dielectric layer 140 .

[0073] The second alignment mark 152 overlaps the alignment opening 122 and the first alignment mark 112 . In some embodiments, a portion of the gate dielectric layer 140 and a portion of the insulating layer 120A are located between the first alignment mark 112 and the second alignment mark 152 .

[0074] The gate 154 overlaps the channel region 132d and a portion of the first doped region 132a of the semiconductor layer 132. For example, the first doped region 132a has a second portion 132a-2 close to the channel region 132d and a first portion 132a-1 away from the channel region 132d, wherein the gate 154 overlaps the second portion 132a-2 and does not overlap the first portion 132a-1. A portion of the gate dielectric layer 140 is located between the gate 154 and the semiconductor layer 132.

[0075] The third capacitor electrode 156 overlaps the second capacitor electrode 134 and the first capacitor electrode 116 . A portion of the gate dielectric layer 140 is located between the second capacitor electrode 134 and the third capacitor electrode 156 .

[0076] The interlayer dielectric layer 160 is located on the gate 154, the third capacitor electrode 156 and the gate dielectric layer 140, and covers the gate 154 and the third capacitor electrode 156. In this embodiment, the interlayer dielectric layer 160 also covers the second calibration mark 152, but the present invention is not limited thereto. In other embodiments, the interlayer dielectric layer 160 does not cover the second calibration mark 152.

[0077] The source 172 and the drain 174 are located on the gate dielectric layer 140. In the present embodiment, the source 172 and the drain 174 are located on the interlayer dielectric layer 160 and are connected to the semiconductor layer 132 through vias in the interlayer dielectric layer 160 and the gate dielectric layer 140. One of the source 172 and the drain 174 is connected to the first doped region 132a, and the other is connected to the second doped region 132b. For example, the drain 174 is connected to the first doped region 132a, and the source 172 is connected to the second doped region 132b. In other embodiments, the source 172 is connected to the first doped region 132a, and the drain 174 is connected to the second doped region 132b.

[0078] The display unit 180 is electrically connected or electrically coupled to the active device TFT. For example, the display unit 180 is electrically connected or electrically coupled to one of the source 172 and the drain 174. In some embodiments, the display unit 180 is, for example, a micro light emitting diode, an organic light emitting diode, a liquid crystal medium, an electrophoretic display medium, or other suitable elements. In some embodiments, other conductive structures may be included between the display unit 180 and the active device TFT, but the present invention is not limited thereto.

[0079] FIG. 3A to FIG. 3O Is manufacturing Figure 2 Schematic cross-sectional view of each stage of the display device 10. Please refer to Figure 3A , a first calibration mark 112 , an alignment mark 113 , a light shielding layer 114 and a first capacitor electrode 116 are formed on the substrate 100 .

[0080] In some embodiments, the substrate 100 is, for example, a rigid substrate, and its material may be glass, quartz, an organic polymer, or an opaque / reflective material (e.g., a conductive material, a metal, a wafer, a ceramic, or other applicable materials) or other applicable materials. However, the present invention is not limited thereto, and in other embodiments, the substrate 100 may also be a flexible substrate or a stretchable substrate. For example, the materials of the flexible substrate and the stretchable substrate include polyimide (PI), polydimethylsiloxane (PDMS), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyester (PES), polymethylmethacrylate (PMMA), polycarbonate (PC), polyurethane PU, or other suitable materials.

[0081] The first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 have the same material. In some embodiments, the materials of the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 include metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, the above alloys, the above metal oxides, the above metal nitrides or the above combinations or other conductive materials. In some embodiments, the method of forming the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 includes: first, forming a conductive material layer on the substrate 100. Then, patterning the above conductive material layer to form the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116. In some embodiments, the method of forming the conductive material layer includes sputtering, electroplating, chemical plating, physical vapor deposition, chemical vapor deposition or other suitable manufacturing processes.

[0082] exist Figure 3A In the embodiment of the present invention, the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 directly contact the substrate 100, but the present invention is not limited thereto. In other embodiments, a buffer layer is first formed on the substrate 100, and then the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 are formed on the buffer layer.

[0083] Please refer to Figure 3B, an insulating layer 120A is formed on the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116. The insulating layer 120A extends from the active device region TR and the capacitor region CR of the substrate 100 to the alignment mark region NR and the calibration mark region MR.

[0084] In some embodiments, the material of the insulating layer 120A includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations thereof. In some embodiments, the method of forming the insulating layer 120A includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable manufacturing processes. In some embodiments, the thickness of the insulating layer 120A is 500 angstroms to 10,000 angstroms.

[0085] A semiconductor layer 132 and a second capacitor electrode 134 are formed on the insulating layer 120A. The semiconductor layer 132 and the second capacitor electrode 134 have the same material. In some embodiments, the semiconductor layer 132 and the second capacitor electrode 134 are each a single layer or a multilayer structure, which includes amorphous silicon, polycrystalline silicon, microcrystalline silicon, single crystal silicon, oxide semiconductor materials (e.g., indium zinc oxide, indium gallium zinc oxide or other suitable materials, or a combination of the above materials) or other suitable materials or a combination of the above materials. In some embodiments, the method of forming the semiconductor layer 132 and the second capacitor electrode 134 includes: first, forming a semiconductor material layer on the insulating layer 120A. Then, patterning the aforementioned semiconductor material layer to form the semiconductor layer 132 and the second capacitor electrode 134.

[0086] Please refer to Figure 3C , a first photoresist pattern PR1 is formed on the semiconductor layer 132 and the insulating layer 120A according to the alignment mark 113. Specifically, a whole layer of photoresist material layer is first formed on the semiconductor layer 132, the second capacitor electrode 134 and the insulating layer 120A. Then, an exposure process is performed on the photoresist material layer using a photomask. In the aforementioned exposure process, the machine and / or photomask used in the exposure process is aligned through the alignment mark 113. For example, the alignment mark 113 is irradiated with light, and the position of the alignment mark 113 is confirmed by the penetration and / or reflection of the light, thereby determining the exposure position of the photoresist material layer. After the exposure process, a development process is performed to remove unnecessary portions of the photoresist material layer and leave the first photoresist pattern PR1.

[0087] In the present embodiment, the first photoresist pattern PR1 has an opening H1 and an opening H2, wherein the opening H1 is located on the calibration mark region MR and overlaps the first calibration mark 112. The opening H2 is located on the alignment mark region NR. In addition, the first photoresist pattern PR1 covers a portion of the semiconductor layer 132 and exposes another portion of the semiconductor layer 132 and the second capacitor electrode 134.

[0088] In the present embodiment, the positions of the opening H1 of the first photoresist pattern PR1 and the first calibration mark 112 are measured to confirm whether the exposure process is accurately executed. For example, the first photoresist pattern PR1 and the first calibration mark 112 are irradiated with light, and the relative positions of the first photoresist pattern PR1 and the first calibration mark 112 are confirmed by the penetration and / or reflection of the light, thereby obtaining the process offset parameter of the exposure process of the first photoresist pattern PR1. If the exposure process of the first photoresist pattern PR1 produces an excessive offset, the first photoresist pattern PR1 can be removed, and the exposure process can be corrected using the previously obtained process offset parameter. A photoresist material layer is re-formed on the semiconductor layer 132, the second capacitor electrode 134 and the insulating layer 120A, and then the photoresist material layer is exposed using the corrected exposure process. In this way, the yield of the manufacturing process can be improved.

[0089] Please refer to Figure 3D , a first ion implantation process IP1 is performed on the semiconductor layer 132 using the first photoresist pattern PR1 as a mask to form a first doped region 132a in the semiconductor layer 132. In this embodiment, the first ion implantation process IP1 also dopes the second capacitor electrode 134.

[0090] In some embodiments, the first doped region 132a of the semiconductor layer 132 and the second capacitor electrode 134 include a P-type silicon semiconductor, and the dopant selected by the first ion implantation process IP1 is aluminum (Al), boron (B), gallium (Ga) or other suitable materials. In some embodiments, the first doped region 132a of the semiconductor layer 132 and the second capacitor electrode 134 include an N-type silicon semiconductor, and the dopant selected by the first ion implantation process IP1 is antimony (Sb), arsenic (As), phosphorus (P) or other suitable materials. In some embodiments, the first ion implantation process IP1 can be called a heavily doped process, and the first doped region 132a can be called a P+ region or an N+ region.

[0091] Please refer to Figure 3EAfter performing the first ion implantation process IP1, the insulating layer 120A is etched using the first photoresist pattern PR1 as a mask to form an alignment opening 123 and a correction opening 122 in the insulating layer 120A. In some embodiments, the aforementioned etching also forms a groove 124 in the insulating layer 120A around the semiconductor layer 132 and / or the second capacitor electrode 134. In some embodiments, the aforementioned etching process includes a wet etching process or other suitable processes. For example, the insulating layer 120A is etched using hydrofluoric acid.

[0092] In some embodiments, the sidewall of the groove 124 may shrink inwardly from the sidewall of the semiconductor layer 132 and / or the second capacitor electrode 134 due to undercut. Similarly, the sidewalls of the alignment opening 123 and the correction opening 122 may also shrink inwardly from the sidewall of the first photoresist pattern PR1.

[0093] In some embodiments, the depths of the alignment opening 123 , the correction opening 122 , and the groove 124 are 500 angstroms to 3000 angstroms.

[0094] Please refer to Figure 3F , remove the first photoresist pattern PR1. For example, remove the first photoresist pattern PR1 by an ashing process, a stripping process or other suitable processes.

[0095] Please refer to Figure 3G , forming a gate dielectric layer 140 on the insulating layer 120A, the semiconductor layer 132, the second capacitor electrode 134, the alignment opening 123, the correction opening 122 and the groove 124. In some embodiments, the gate dielectric layer 140 has a single-layer or multi-layer structure, and its material includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating material, other suitable materials or combinations of the above materials. In some embodiments, the method of forming the gate dielectric layer 140 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable manufacturing processes. In some embodiments, the thickness of the gate dielectric layer 140 is 500 angstroms to 1500 angstroms.

[0096] The gate dielectric layer 140 is filled in the alignment opening 123, the correction opening 122, and the groove 124. In some embodiments, since the sidewall of the groove 124 is retracted from the sidewall of the semiconductor layer 132 and the second capacitor electrode 134, a portion of the gate dielectric layer 140 may be located between the semiconductor layer 132 and the insulating layer 120A and between the second capacitor electrode 134 and the insulating layer 120A in the normal direction of the top surface of the substrate 100. In this embodiment, a portion of the insulating layer 120A covers the first correction mark 112 and the alignment mark 113, and separates the first correction mark 112 and the alignment mark 113 from the gate dielectric layer 140, but the present invention is not limited thereto. In other embodiments, the correction opening 122 exposes the top surface of the first correction mark 112, and the gate dielectric layer 140 fills the correction opening 122 and contacts the top surface of the first correction mark 112. In this case, the gate dielectric layer 140 contacts the first correction mark 112, but is separated from the alignment mark 113.

[0097] Please refer to Figure 3H , forming a conductive material layer 150 on the gate dielectric layer 140. In some embodiments, the conductive material layer 150 has a single-layer or multi-layer structure, and its material includes metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, etc., the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. In some embodiments, the method of forming the conductive material layer 150 includes sputtering, electroplating, chemical plating, physical vapor deposition, chemical vapor deposition or other suitable manufacturing processes.

[0098] Please refer to Fig. 3I , a second photoresist pattern PR2A~PR2C is formed on the conductive material layer 150 according to the alignment opening 123. Specifically, a whole layer of photoresist material layer is first formed on the conductive material layer 150. Then, an exposure process is performed on the photoresist material layer using a photomask. In the aforementioned exposure process, the machine and / or photomask used in the exposure process is aligned through the alignment opening 123. For example, the alignment opening 123 is irradiated with light, and the position of the alignment opening 123 is confirmed by the penetration and / or reflection of the light, thereby determining the exposure position of the photoresist material layer. After the exposure process, a development process is performed to remove unnecessary portions of the photoresist material layer, leaving behind the second photoresist patterns PR2A~PR2C.

[0099] In the present embodiment, the second photoresist pattern PR2A overlaps the correction opening 122, and the positions of the second photoresist pattern PR2A and the correction opening 122 are measured to confirm whether the exposure process is accurately executed. For example, the second photoresist pattern PR2A and the correction opening 122 are irradiated with light, and the relative position of the second photoresist pattern PR2A and the correction opening 122 is confirmed by the penetration and / or reflection of the light, and then the process shift parameters of the exposure process of the second photoresist patterns PR2A~PR2C are obtained. If the exposure process of the second photoresist patterns PR2A~PR2C produces an excessively large shift, the second photoresist patterns PR2A~PR2C can be removed, and the exposure process can be corrected using the previously obtained process shift parameters. A photoresist material layer is re-formed on the conductive material layer 150, and the photoresist material layer is exposed using the corrected exposure process. In this way, the yield of the manufacturing process can be improved.

[0100] Please refer to Figure 3J , the conductive material layer 150 is etched using the second photoresist patterns PR2A-PR2C as a mask to form a second calibration mark 152, a gate 154, and a third capacitor electrode 156. The second calibration mark 152 overlaps the first calibration mark 112 and the calibration opening 122. The gate 154 overlaps the semiconductor layer 132, wherein the gate 154 partially overlaps the first doped region 132a. The third capacitor electrode 156 overlaps the first capacitor electrode 116 and the second capacitor electrode 134.

[0101] The photolithography process of the second photoresist patterns PR2A-PR2C of this embodiment can be calibrated according to the calibration opening 122 without using the first calibration mark 112 for calibration, thereby avoiding the problem of misalignment caused by the superposition of the process variations of the two photolithography processes. For example, the position of the first photoresist pattern PR1 (see Figure 3E ) can be calibrated according to the first calibration mark 112, and the manufacturing process variation of the first photoresist pattern PR1 is 0 micrometers to 0.25 micrometers, and the manufacturing process variation is the square of half of the maximum offset of the critical dimension (Critical dimension) of the photolithography manufacturing process plus the opening H1 of the first photoresist pattern PR1 (please refer to Figure 3C) and the geometric center of the first calibration mark 112, wherein the maximum critical dimension offset is -0.6 microns to 0.6 microns, and the maximum geometric center offset is -0.4 microns to 0.4 microns. If the second photoresist patterns PR2A-PR2C are also calibrated according to the first calibration mark 112, the manufacturing process variation of forming the second photoresist patterns PR2A-PR2C will be accumulated with the manufacturing process variation of forming the first photoresist pattern PR1, resulting in the relative position between the gate 154 and the first doped region 132a being more easily offset.

[0102] In the present embodiment, the position of the second photoresist patterns PR2A-PR2C can be corrected according to the correction opening 122, and the manufacturing process variation of the second photoresist patterns PR2A-PR2C is 0 micrometers to 0.25 micrometers, and the manufacturing process variation is the square of one-half of the maximum offset of the critical dimension plus the square of the maximum offset between the geometric center of the second photoresist pattern PR2A and the geometric center of the correction opening 122, wherein the maximum offset of the critical dimension is -0.6 micrometers to 0.6 micrometers, and the maximum offset is -0.4 micrometers to 0.4 micrometers. Therefore, the relative position between the gate 154 and the first doped region 132a is only affected by the manufacturing process variation when forming the second photoresist patterns PR2A-PR2C, and is not affected by the manufacturing process variation when forming the first photoresist pattern PR1.

[0103] Please refer to Figure 3K , a second ion implantation process IP2 is performed on the semiconductor layer 132 using the gate 154 as a mask to form a second doped region 132b in the semiconductor layer 132. The first doped region 132a is separated from the second doped region 132b.

[0104] In some embodiments, the second doping region 132b of the semiconductor layer 132 includes a P-type silicon semiconductor, and the dopant selected by the second ion implantation process IP2 is aluminum (Al), boron (B), gallium (Ga) or other suitable materials. In some embodiments, the second doping region 132b of the semiconductor layer 132 includes an N-type silicon semiconductor, and the dopant selected by the first ion implantation process IP1 is antimony (Sb), arsenic (As), phosphorus (P) or other suitable materials. In some embodiments, the second ion implantation process IP2 can be called a heavily doped process, and the second doping region 132b can be called a P+ region or an N+ region. The first doping region 132a and the second doping region 132b include the same dopant.

[0105] In some embodiments, since part of the first doped region 132a is also doped by the second ion implantation process IP2, the first doped region 132a may include the first doped region 132a that has been doped by the first ion implantation process IP1 (see Figure 3D ) plus the first portion 132a-1 of the second ion implantation process IP2 and the second portion 132a-2 that has only been subjected to the first ion implantation process IP1. In some embodiments, the doping concentration of the first portion 132a-1 is greater than or equal to the doping concentration of the second portion 132a-2.

[0106] Please refer to Figure 3L , an etch-back process is performed on the second calibration mark 152, the gate 154, and the third capacitor electrode 156 to reduce the widths of the second calibration mark 152, the gate 154, and the third capacitor electrode 156. After the etch-back process, a portion of the undoped region of the semiconductor layer 132 between the first doping region 132a and the second doping region 132b does not overlap the gate 154 after the width is reduced.

[0107] In some embodiments, the width and thickness of the second photoresist patterns PR2A-PR2C are also reduced during the etch-back process.

[0108] Please refer to Figure 3M , a third ion implantation process IP3 is performed on the semiconductor layer 132 using the gate 154 as a mask to form a lightly doped region 132c in the semiconductor layer 132. The lightly doped region 132c is located between the second doped region 132b and the channel region 132d of the semiconductor layer 132. In some embodiments, the first portion 132a-1, a portion of the second portion 132a-2, and the second doped region 132b are also subjected to the third ion implantation process IP3, while the channel region 132d overlapping the gate 154 and another portion of the second portion 132a-2 are not subjected to the third ion implantation process IP3.

[0109] In some embodiments, the third ion implantation process IP3 is performed after the second photoresist patterns PR2A-PR2C are removed, but the present invention is not limited thereto. In other embodiments, the second photoresist patterns PR2A-PR2C are removed after the third ion implantation process IP3 is performed. In some embodiments, the second photoresist patterns PR2A-PR2C are removed by an ashing process, a stripping process, or other suitable processes.

[0110] Please refer to Figure 3N, an interlayer dielectric layer 160 is formed on the gate electrode 154 and the third capacitor electrode 156. In this embodiment, the interlayer dielectric layer 160 also covers the second calibration mark 152, but the present invention is not limited thereto. In other embodiments, the second calibration mark 152 is not covered by the interlayer dielectric layer 160.

[0111] In some embodiments, the material of the interlayer dielectric layer 160 includes silicon oxide, silicon nitride, silicon oxynitride, organic insulating material, other suitable materials or a combination of the above materials. In some embodiments, the method of forming the interlayer dielectric layer 160 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable manufacturing processes. In some embodiments, a plurality of through holes passing through the interlayer dielectric layer 160 and the gate dielectric layer 140 are formed by an etching manufacturing process. These through holes expose the first doped region 132a and the second doped region 132b of the semiconductor layer 132.

[0112] Please refer to Fig.3O , a source 172 and a drain 174 are formed on the interlayer dielectric layer 160. One of the source 172 and the drain 174 is connected to the first doped region 132a, and the other is connected to the second doped region 132b.

[0113] Finally, please return Figure 2 , forming the display unit 180 on the active device TFT and electrically connecting or electrically coupling to the active device TFT.

[0114] Figure 4 is a cross-sectional schematic diagram of a display device 20 according to an embodiment of the present invention. It must be noted here that Figure 4 The implementation examples are used Figures 2 to 3O The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0115] Figure 4 The display device 20 and Figure 2 The display device 10 is different from the display device 20 in that: in the display device 20, the gate dielectric layer 140 contacts the top surface of the first alignment mark 112 through the alignment opening 122. The insulating layer 120A surrounds the first alignment mark 112 and does not cover the top surface of the first alignment mark 112.

[0116] Figure 5 is a cross-sectional schematic diagram of a display device 30 according to an embodiment of the present invention. It must be noted here that Figure 5 The implementation examples are used Figure 4The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0117] Figure 5 The display device 30 and Figure 4 The difference between the display device 20 and the display device 30 is that: in the display device 30, the insulating layer 120A includes a multi-layer structure. For example, the insulating layer 120A includes a first layer 120A-1 and a second layer 120A-2, wherein the first layer 120A-1 is located between the second layer 120A-2 and the substrate 100. In some embodiments, the correction opening 122 and the alignment opening 123 pass through the entire second layer 120A-2 and extend into the first layer 120A-1, but the present invention is not limited thereto. In other embodiments, the correction opening 122 and the alignment opening 123 do not extend into the first layer 120A-1.

[0118] The first layer 120A-1 and the second layer 120A-2 include different materials. In some embodiments, the materials of the first layer 120A-1 and the second layer 120A-2 include silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations thereof.

[0119] Figure 6 is a cross-sectional schematic diagram of a display device 40 according to an embodiment of the present invention. It must be noted here that Figure 6 The implementation examples are used Figures 2 to 3O The component numbers and partial contents of the embodiments are the same, wherein the same or similar numbers are used to represent the same or similar components, and the description of the same technical contents is omitted. The description of the omitted parts can be referred to the aforementioned embodiments, and will not be repeated here.

[0120] Figure 6 The display device 40 and Figure 2 The display device 10 is different in that: in the display device 40 , the insulating layer 120B including the correction opening 122 and the alignment opening 123 is disposed above the semiconductor layer 132 , and the semiconductor layer 132 further includes a buffer layer BL below the semiconductor layer 132 . The insulating layer 120B is located between the semiconductor layer 132 and the gate dielectric layer 140 .

[0121] In some embodiments, the correction opening 122 and the alignment opening 123 do not extend into the buffer layer BL, but the present invention is not limited thereto. In other embodiments, the correction opening 122 and the alignment opening 123 extend into the buffer layer BL.

[0122] FIG. 7A to FIG. 7P Is manufacturing Figure 6Schematic cross-sectional view of various stages of the display device 40. Please refer to Fig. 7A , a first calibration mark 112 , an alignment mark 113 , a light shielding layer 114 and a first capacitor electrode 116 are formed on the substrate 100 .

[0123] exist Fig. 7A In the embodiment of the present invention, the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 directly contact the substrate 100, but the present invention is not limited thereto. In other embodiments, other buffer layers are first formed on the substrate 100, and then the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116 are formed on the other buffer layers.

[0124] Please refer to Figure 7B , a buffer layer BL is formed on the first calibration mark 112, the alignment mark 113, the light shielding layer 114 and the first capacitor electrode 116. The buffer layer BL extends from the active device region TR and the capacitor region CR of the substrate 100 to the alignment mark region NR and the calibration mark region MR.

[0125] In some embodiments, the material of the buffer layer BL includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations thereof. In some embodiments, the method of forming the buffer layer BL includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable manufacturing processes.

[0126] A semiconductor layer 132 and a second capacitor electrode 134 are formed on the buffer layer BL.

[0127] Please refer to Figure 7C , an insulating layer 120B is formed on the semiconductor layer 132 and the second capacitor electrode 134. The insulating layer 120B extends from the active device region TR and the capacitor region CR of the substrate 100 to the alignment mark region NR and the calibration mark region MR.

[0128] In some embodiments, the material of the insulating layer 120B includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations thereof. In some embodiments, the method of forming the insulating layer 120B includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable manufacturing processes. In some embodiments, the thickness of the insulating layer 120B is 400 angstroms to 1500 angstroms.

[0129] Please refer to Fig.7D, a first photoresist pattern PR1 is formed on the insulating layer 120B according to the alignment mark 113. Specifically, a whole layer of photoresist material layer is first formed on the insulating layer 120B. Then, the photoresist material layer is exposed using a photomask. In the aforementioned exposure process, the machine and / or photomask used in the exposure process is aligned by the alignment mark 113.

[0130] In this embodiment, the first photoresist pattern PR1 has an opening H1 overlapping the first calibration mark 112 . In addition, the first photoresist pattern PR1 overlaps a portion of the semiconductor layer 132 , and does not overlap another portion of the semiconductor layer 132 and the second capacitor electrode 134 .

[0131] In the present embodiment, the positions of the opening H1 of the first photoresist pattern PR1 and the first calibration mark 112 are measured to confirm whether the exposure process is accurately executed. For example, the first photoresist pattern PR1 and the first calibration mark 112 are irradiated with light, and the relative positions of the first photoresist pattern PR1 and the first calibration mark 112 are confirmed by the penetration and / or reflection of the light, thereby obtaining the process offset parameter of the exposure process of the first photoresist pattern PR1. If the exposure process of the first photoresist pattern PR1 produces an excessive offset, the first photoresist pattern PR1 can be removed, and the exposure process can be corrected using the previously obtained process offset parameter. A photoresist material layer is re-formed on the insulating layer 120B, and the photoresist material layer is exposed using the corrected exposure process. In this way, the yield of the manufacturing process can be improved.

[0132] Please refer to Fig. 7E , a first ion implantation process IP1 is performed on the semiconductor layer 132 using the first photoresist pattern PR1 as a mask to form a first doped region 132a in the semiconductor layer 132. In this embodiment, the first ion implantation process IP1 also dopes the second capacitor electrode 134.

[0133] Please refer to Figure 7F After performing the first ion implantation process IP1, the insulating layer 120B is etched using the first photoresist pattern PR1 as a mask to form an alignment opening 123 and a correction opening 122 in the insulating layer 120B, and to expose the first doped region 132a and the first capacitor electrode 134. In some embodiments, the etching process includes a dry etching process, a wet etching process or other suitable processes. For example, the insulating layer 120B is etched using hydrofluoric acid or fluoroform (CHF3).

[0134] In this embodiment, since the insulating layer 120B covers the semiconductor layer 132 and the second capacitor electrode 134 before the etching process, damage to the semiconductor layer 132 and the second capacitor electrode 134 caused by the etching process can be reduced.

[0135] In addition, in the present embodiment, the alignment opening 123 and the correction opening 122 do not extend into the buffer layer BL, but the present invention is not limited thereto. In some embodiments, the etching process allows the alignment opening 123 and the correction opening 122 to extend into the buffer layer BL, and forms a groove deep into the buffer layer BL around the semiconductor layer 132 and the second capacitor electrode 134.

[0136] Please refer to Figure 7G , remove the first photoresist pattern PR1. For example, remove the first photoresist pattern PR1 by an ashing process, a stripping process or other suitable processes.

[0137] Please refer to Figure 7H , forming a gate dielectric layer 140 on the insulating layer 120B, the semiconductor layer 132, the second capacitor electrode 134, the alignment opening 123 and the correction opening 122. In some embodiments, the gate dielectric layer 140 has a single-layer or multi-layer structure, and its material includes silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, hafnium oxide, aluminum oxide, organic insulating materials, other suitable materials or combinations of the above materials. In some embodiments, the method of forming the gate dielectric layer 140 includes physical vapor deposition, chemical vapor deposition, atomic layer deposition, coating or other suitable manufacturing processes. In some embodiments, the thickness of the gate dielectric layer 140 is 200 angstroms to 1500 angstroms. For example, the gate dielectric layer 140 includes 0 angstroms to 1500 angstroms of silicon oxide and 0 angstroms to 1500 angstroms of silicon nitride.

[0138] The gate dielectric layer 140 fills the alignment opening 123 and the correction opening 122 and contacts the buffer layer BL.

[0139] Please refer to Fig.7I , forming a conductive material layer 150 on the gate dielectric layer 140. In some embodiments, the conductive material layer 150 has a single-layer or multi-layer structure, and its material includes metals such as chromium, gold, silver, copper, tin, lead, hafnium, tungsten, molybdenum, neodymium, titanium, tantalum, aluminum, zinc, nickel, etc., the above alloys, the above metal oxides, the above metal nitrides, or the above combinations or other conductive materials. In some embodiments, the method of forming the conductive material layer 150 includes sputtering, electroplating, chemical plating, physical vapor deposition, chemical vapor deposition or other suitable manufacturing processes.

[0140] Please refer to Figure 7J, second photoresist patterns PR2A-PR2C are formed on the conductive material layer 150 according to the alignment opening 123. Specifically, a whole layer of photoresist material layer is first formed on the conductive material layer 150. Then, an exposure process is performed on the photoresist material layer using a photomask. In the aforementioned exposure process, the machine and / or photomask used in the exposure process is aligned through the alignment opening 123.

[0141] In the present embodiment, the second photoresist pattern PR2A overlaps the correction opening 122, and the positions of the second photoresist pattern PR2A and the correction opening 122 are measured to confirm whether the exposure process is accurately executed. For example, the second photoresist pattern PR2A and the correction opening 122 are irradiated with light, and the relative position of the second photoresist pattern PR2A and the correction opening 122 is confirmed by the penetration and / or reflection of the light, and then the process shift parameters of the exposure process of the second photoresist patterns PR2A~PR2C are obtained. If the exposure process of the second photoresist patterns PR2A~PR2C produces an excessively large shift, the second photoresist patterns PR2A~PR2C can be removed, and the exposure process can be corrected using the previously obtained process shift parameters. A photoresist material layer is re-formed on the conductive material layer 150, and the photoresist material layer is exposed using the corrected exposure process. In this way, the yield of the manufacturing process can be improved.

[0142] Please refer to Figure 7K , the conductive material layer 150 is etched using the second photoresist patterns PR2A-PR2C as a mask to form a second calibration mark 152, a gate 154, and a third capacitor electrode 156. The second calibration mark 152 overlaps the first calibration mark 112 and the calibration opening 122. The gate 154 overlaps the semiconductor layer 132, wherein the gate 154 partially overlaps the first doped region 132a. The third capacitor electrode 156 overlaps the first capacitor electrode 116 and the second capacitor electrode 134.

[0143] The positions of the second photoresist patterns PR2A-PR2C of this embodiment can be calibrated according to the calibration opening 122 instead of the first calibration mark 112, thereby avoiding the problem of excessive process variation caused by the superposition of two photolithography process errors.

[0144] Please refer to Figure 7L , a second ion implantation process IP2 is performed on the semiconductor layer 132 using the gate 154 as a mask to form a second doped region 132b in the semiconductor layer 132. The first doped region 132a is separated from the second doped region 132b.

[0145] In some embodiments, since part of the first doped region 132a is also doped by the second ion implantation process IP2, the first doped region 132a may include the first doped region 132a that has been doped by the first ion implantation process IP1 (see Fig. 7E ) plus the first portion 132a-1 subjected to the second ion implantation process IP2 and the second portion 132a-2 subjected only to the first ion implantation process IP1.

[0146] Please refer to Figure 7M , an etch-back process is performed on the second calibration mark 152, the gate 154, and the third capacitor electrode 156 to reduce the widths of the second calibration mark 152, the gate 154, and the third capacitor electrode 156. After the etch-back process, a portion of the undoped region of the semiconductor layer 132 between the first doping region 132a and the second doping region 132b does not overlap the gate 154 after the width is reduced.

[0147] In some embodiments, the width and thickness of the second photoresist patterns PR2A-PR2C are also reduced during the etch-back process.

[0148] Please refer to Figure 7N , a third ion implantation process IP3 is performed on the semiconductor layer 132 using the gate 154 as a mask to form a lightly doped region 132c in the semiconductor layer 132. The lightly doped region 132c is located between the second doped region 132b and the channel region 132d of the semiconductor layer 132. In some embodiments, the first portion 132a-1, a portion of the second portion 132a-2, and the second doped region 132b are also subjected to the third ion implantation process IP3, while the channel region 132d overlapping the gate 154 and another portion of the second portion 132a-2 are not subjected to the third ion implantation process IP3.

[0149] In the present embodiment, the gate dielectric layer 140 contacts the top surface of the first doped region 132 a , and the insulating layer 120B contacts the top surfaces of the second doped region 132 b , the lightly doped region 132 c , and the channel region 132 d .

[0150] In some embodiments, the third ion implantation process IP3 is performed after the second photoresist patterns PR2A-PR2C are removed, but the present invention is not limited thereto. In other embodiments, the second photoresist patterns PR2A-PR2C are removed after the third ion implantation process IP3 is performed. In some embodiments, the second photoresist patterns PR2A-PR2C are removed by an ashing process, a stripping process, or other suitable processes.

[0151] Please refer to Fig.7O, an interlayer dielectric layer 160 is formed on the gate electrode 154 and the third capacitor electrode 156. In this embodiment, the interlayer dielectric layer 160 also covers the second calibration mark 152, but the present invention is not limited thereto. In other embodiments, the second calibration mark 152 is not covered by the interlayer dielectric layer 160.

[0152] Please refer to Figure 7P , a source 172 and a drain 174 are formed on the interlayer dielectric layer 160. One of the source 172 and the drain 174 is connected to the first doped region 132a, and the other is connected to the second doped region 132b. One of the source 172 and the drain 174 contacts the insulating layer 120B, and the other is separated from the insulating layer 120B.

[0153] Finally, please return Figure 6 , forming the display unit 180 on the active device TFT and electrically connecting or electrically coupling to the active device TFT.

[0154] In summary, the present invention can avoid the problem of the gate 154 and the first doped region 132 a being offset due to excessive manufacturing process variation by correcting the arrangement of the opening 122 .

Claims

1. A method for manufacturing an active component substrate, comprising: Forming an alignment mark and a first calibration mark on an alignment mark area and a calibration mark area of ​​the substrate respectively; forming an insulating layer extending from the active device region of the substrate to the calibration mark region; forming a semiconductor layer on the active device region; Forming a first photoresist pattern on the semiconductor layer and the insulating layer according to the alignment mark; Performing a first ion implantation process on the semiconductor layer using the first photoresist pattern as a mask to form a first doped region in the semiconductor layer; etching the insulating layer using the first photoresist pattern as a mask to form a calibration opening in the insulating layer that overlaps the first calibration mark; removing the first photoresist pattern; forming a gate dielectric layer on the semiconductor layer and the correction opening; as well as A gate, an interlayer dielectric layer, a source and a drain are formed on the gate dielectric layer.

2. The manufacturing method as claimed in claim 1, wherein the method of forming the gate, the interlayer dielectric layer, the source and the drain on the gate dielectric layer comprises: forming a conductive material layer on the gate dielectric layer; Etching the insulating layer using the first photoresist pattern as a mask to form an alignment opening in the insulating layer; Forming a second photoresist pattern on the conductive material layer according to the alignment opening; Using the second photoresist pattern as a mask, etching the conductive material layer to form the gate, wherein the gate overlaps the semiconductor layer; Performing a second ion implantation process on the semiconductor layer using the gate as a mask to form a second doped region in the semiconductor layer, wherein the first doped region is separated from the second doped region; Performing an etch-back process on the gate to reduce the width of the gate; After the etching back process, a third ion implantation process is performed on the semiconductor layer using the gate as a mask to form a lightly doped region in the semiconductor layer, wherein the lightly doped region is located between the second doped region and the channel region of the semiconductor layer; forming the interlayer dielectric layer on the gate; as well as The source and the drain are formed on the interlayer dielectric layer, wherein one of the source and the drain is connected to the first doped region, and the other of the source and the drain is connected to the second doped region.

3. The manufacturing method according to claim 2, further comprising: irradiating the first photoresist pattern and the first calibration mark with light to confirm the positions of the first photoresist pattern and the first calibration mark; as well as The second photoresist pattern and the calibration opening are irradiated with light to confirm the positions of the second photoresist pattern and the calibration opening.

4. A method for manufacturing an active component substrate, comprising: Forming an alignment mark and a first calibration mark on an alignment mark area and a calibration mark area of ​​the substrate respectively; forming a buffer layer extending from the active device region of the substrate to the calibration mark region; forming a semiconductor layer on the buffer layer and the active device region; forming an insulating layer on the semiconductor layer and extending from the active device region of the substrate to the calibration mark region; Forming a first photoresist pattern on the insulating layer according to the alignment mark; Performing a first ion implantation process on the semiconductor layer using the first photoresist pattern as a mask to form a first doped region in the semiconductor layer; etching the insulating layer using the first photoresist pattern as a mask to form a calibration opening in the insulating layer that overlaps the first calibration mark; removing the first photoresist pattern; forming a gate dielectric layer on the semiconductor layer, the insulating layer and the correction opening; as well as A gate, an interlayer dielectric layer, a source and a drain are formed on the gate dielectric layer.

5. The manufacturing method as claimed in claim 4, wherein the insulating layer is etched using the first photoresist pattern as a mask to expose the first doped region, and the gate dielectric layer contacts the first doped region, wherein the method of forming the gate, the interlayer dielectric layer, the source and the drain on the gate dielectric layer comprises: forming a conductive material layer on the gate dielectric layer; Etching the insulating layer using the first photoresist pattern as a mask to form an alignment opening in the insulating layer; Forming a second photoresist pattern on the conductive material layer according to the alignment opening; Using the second photoresist pattern as a mask, etching the conductive material layer to form the gate, wherein the gate partially overlaps the semiconductor layer; Performing a second ion implantation process on the semiconductor layer using the gate as a mask to form a second doped region in the semiconductor layer, wherein the first doped region is separated from the second doped region; Performing an etch-back process on the gate to reduce the width of the gate; After the etching back process, a third ion implantation process is performed on the semiconductor layer using the gate as a mask to form a lightly doped region in the semiconductor layer, wherein the lightly doped region is located between the second doped region and the channel region of the semiconductor layer; forming the interlayer dielectric layer on the gate; as well as The source and the drain are formed on the interlayer dielectric layer, wherein one of the source and the drain is connected to the first doped region, and the other of the source and the drain is connected to the second doped region.

6. The manufacturing method according to claim 5, further comprising: irradiating the first photoresist pattern and the first calibration mark with light to confirm the positions of the first photoresist pattern and the first calibration mark; as well as The second photoresist pattern and the calibration opening are irradiated with light to confirm the positions of the second photoresist pattern and the calibration opening.

7. A display device, comprising: A substrate having a display area and a peripheral area surrounding the display area, wherein the peripheral area includes a calibration mark area, and the display area includes an active component area; a first calibration mark, located on the calibration mark area; An insulating layer is located on the substrate and extends from the active device region to the calibration mark region, wherein the insulating layer has a calibration opening overlapping the first calibration mark; A semiconductor layer is located above the active device region, and the insulating layer at least partially overlaps the semiconductor layer; A gate dielectric layer is located on the semiconductor layer and the correction opening; The gate, the interlayer dielectric layer, the source and the drain are located on the gate dielectric layer. 8 . The display device as claimed in claim 7 , wherein the insulating layer surrounds the first alignment mark, and the gate dielectric layer contacts a top surface of the first alignment mark through the alignment opening. 9 . The display device as claimed in claim 7 , wherein the insulating layer is located between the semiconductor layer and the substrate, and the insulating layer has a groove overlapping a sidewall of the semiconductor layer.

10. A display device as described in claim 7, wherein the insulating layer is located between the semiconductor layer and the gate dielectric layer, wherein the semiconductor layer further includes a second doped region, a lightly doped region and a channel region, wherein the lightly doped region is located between the channel region and the second doped region, and the channel region is located between the first doped region and the lightly doped region, wherein the resistivity of the lightly doped region is higher than the resistivity of the first doped region and the second doped region, and wherein the gate dielectric layer contacts the top surface of the first doped region, and the insulating layer contacts the top surface of the second doped region, the top surface of the lightly doped region and the top surface of the channel region. 11 . The display device as claimed in claim 7 , wherein the insulating layer is located between the semiconductor layer and the gate dielectric layer, wherein one of the source and the drain contacts the insulating layer, and the other of the source and the drain is separated from the insulating layer.

12. The display device according to claim 7, further comprising: A first capacitor electrode, located on the substrate and comprising the same material as the first calibration mark; A second capacitor electrode overlaps the first capacitor electrode and comprises the same material as the semiconductor layer; as well as The third capacitor electrode overlaps the second capacitor electrode, and a portion of the gate dielectric layer is located between the second capacitor electrode and the third capacitor electrode.

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