Novel CIS chip packaging structure and method
By forming a high refractive film layer on the lower surface of the glass in the CIS chip packaging structure, the problem of reducing the effective light amount caused by light refraction is solved, and a more efficient optical signal conversion capability is achieved.
Patent Information
- Application Number
- CN202411404265.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-10
- Publication Date
- 2025-02-21
AI Technical Summary
When light is not vertically incident, the existing CIS chip packaging structure causes the effective light to decrease, affecting the chip's signal conversion capability.
A high refractive film layer is formed on the lower surface of the bonded glass, with a refractive index greater than that of the glass. The refractive angle is smaller when the light passes through the refractive film layer, and more light is gathered to the photosensitive area of the CIS chip.
By increasing the amount of light that reaches the photosensitive area of the CIS chip, the ability of the CIS chip to convert the optical signal into an electrical signal is significantly enhanced.
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Figure CN119497436A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor chip packaging, and in particular to a novel CIS chip packaging structure and method. Background Art
[0002] CIS (CMOS Image Sensor) uses the photoelectric conversion function of photoelectric devices to convert the light image on the photosensitive surface into an electrical signal that is proportional to the light image. Compared with photosensitive elements such as photodiodes and phototransistors, which are "point" light sources, image sensors are functional devices that divide the light image on the light-receiving surface into many small units and convert them into usable electrical signals. Image sensors are divided into photoconductive camera tubes and solid-state image sensors. Compared with photoconductive camera tubes, solid-state image sensors have the characteristics of small size, light weight, high integration, high resolution, low power consumption, long life, and low price. Therefore, they have been widely used in various industries.
[0003] The Chinese utility model patent with publication number CN207052606U discloses a packaging structure for a CIS chip, which bonds a CIS wafer to a glass containing a cavity, and then forms a line redistribution on the back of the Si through TSV (Through Silicon Via) technology, and then cuts it into a single package. For a CIS chip prepared using this packaging technology, when light reaches the glass surface with non-vertical incidence (i.e., with a certain incident angle), the light will be refracted when passing through the glass, and the effective amount of light that finally reaches the photosensitive area of the CIS chip will be reduced, thereby affecting the ability of the CIS chip to convert optical signals into electrical signals, that is, the signal conversion ability of the CIS chip will be weakened. How to effectively enhance the ability of the CIS chip to convert optical signals into electrical signals is gradually becoming a hot topic in the research of CIS chip packaging technology. Summary of the invention
[0004] In order to solve the above technical problems, the purpose of the present invention is to provide a new CIS chip packaging structure and method. The packaging structure and method form a high refractive film layer (with a refractive index greater than that of glass) on the lower surface of the bonding glass, and the light passes through the film to present a convergent projection effect, which will generate more light to converge to the photosensitive area of the CIS chip, and by increasing the amount of light reaching the photosensitive area of the CIS chip, the ability of the CIS chip to convert optical signals into electrical signals is enhanced.
[0005] In order to achieve the above technical purpose and the above technical effect, a novel CIS chip packaging method comprises the following steps:
[0006] S1, forming a refractive film layer on the glass;
[0007] S2, forming a cofferdam structure and pasting an adhesive layer on the glass;
[0008] S3, bonding the CIS chip to the glass;
[0009] S4, thinning the back side of the CIS chip and forming a through-hole structure;
[0010] S5, forming a conductive structure and a first metal redistribution layer on the back side of the CIS chip;
[0011] S6, forming a first insulating layer on the first metal redistribution layer;
[0012] S7, forming a second metal redistribution layer on the first insulating layer;
[0013] S8, completing the ball planting process on the second metal redistribution.
[0014] The material of the metal redistribution layer in steps S5 and S7 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel, and tin. In this embodiment, the material of the insulating layer metal redistribution layer is copper. The material of the insulating layer in step S6 is epoxy resin, silicon oxide insulating material or other insulating material; in this embodiment, the insulating layer material is photosensitive epoxy resin.
[0015] Furthermore, by forming a high-refractive film layer on the lower surface of the bonding glass, the amount of light reaching the photosensitive area of the CIS chip is increased, thereby enhancing the ability of the CIS chip to convert optical signals into electrical signals.
[0016] According to another aspect of the present invention, a novel CIS chip packaging structure is provided, comprising:
[0017] A refractive film layer formed on the glass, the refractive film layer comprising glass and a refractive film layer disposed on the glass;
[0018] A cofferdam structure is formed on the refractive film layer structure, and an adhesive layer is printed on the cofferdam structure;
[0019] The adhesive layer of the cofferdam structure is bonded to the CIS chip through a bonding process, with the back of the CIS chip facing outward, and the conductive structure of the CIS chip and the photosensitive area of the CIS chip facing inward; the back of the CIS chip is thinned, and a conductive through-hole structure is formed at the back of the CIS chip corresponding to the position of the conductive structure;
[0020] A conductive structure is formed at the conductive through-hole structure, and a first metal redistribution layer is formed;
[0021] forming a first insulating layer on the first metal redistribution layer, and forming a conductive through-hole structure on the first insulating layer;
[0022] forming a second metal redistribution layer on the conductive via structure;
[0023] Conductive structure balls are arranged on the second metal redistribution layer.
[0024] Beneficial effects of the invention: The present application discloses a novel CIS chip packaging structure and method. The packaging structure and method form a high-refractive film layer (with a refractive index greater than that of glass) on the lower surface of the bonding glass. When the light passes through the glass and reaches the high-refractive film layer, because the refractive index of the high-refractive film layer is greater than that of the glass, the refraction angle of the light in the high-refractive film layer is smaller. The high-refractive film layer gathers the light scattered to the side of the photosensitive area of the CIS chip to the front of the photosensitive area of the CIS chip as much as possible. The light passes through the CIS chip and presents a convergent projection effect, which will generate more light to converge to the photosensitive area of the CIS chip. By increasing the amount of light reaching the photosensitive area of the CIS chip, the ability of the CIS chip to convert optical signals into electrical signals can be effectively enhanced. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Figure 1 The present invention forms a refractive film layer structure on the glass.
[0026] Figure 2 For Figure 1 The structure shown has a cofferdam structure formed on it and a structure with an adhesive layer printed on it.
[0027] Figure 3 For Figure 2 The structure shown is a structure in which the CIS chip is bonded together through a bonding process.
[0028] Figure 4 For Figure 3 In the structure shown, the back side of the CIS chip is thinned and a conductive through-hole structure is formed at a position on the back side of the CIS chip corresponding to the position of the conductive structure.
[0029] Figure 5 For Figure 4 The conductive via structure shown in the structure forms a conductive structure and a first metal redistribution layer structure.
[0030] Figure 6 For Figure 5 A first insulating layer is formed on the structure and a conductive via structure is formed on the first insulating layer.
[0031] Figure 7 For Figure 6 A second metal redistribution layer is formed on the structure shown.
[0032] Figure 8 For Figure 7 The structure shown has completed the ball implantation process.
[0033] Fig. 9 It is the structure of each layer in the CIS chip packaging structure. DETAILED DESCRIPTION
[0034] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.
[0035] (1) Forming a refractive film layer on the glass to obtain Figure 1 The structure is shown. 10 is glass, 11 is a refractive film layer, 201 is the lower surface of the glass, 202 is the upper surface of the glass, and 203 is the upper surface of the refractive film layer. It is necessary to ensure that the refractive index of the refractive film layer is greater than the refractive index of the glass. There are two main sizes of the refractive film layer, such as Figure 1 As shown in (a) / 1(b): ① The refractive film layer presents a patterned design, and its size matches the size of the photosensitive area of the CIS chip, such as Figure 1 As shown in (a) in the figure; ② The refractive film layer covers the entire surface of the glass, as shown in Figure 1 As shown in (b) in .
[0036] (2) Figure 1 A cofferdam structure is formed on the structure shown in FIG. 1 , and an adhesive layer is printed on the cofferdam structure to obtain a Figure 2 The structure shown in FIG. 12 is a cofferdam structure and 13 is an adhesive layer. There are three main relative position relationships between the refractive film layer and the cofferdam structure and the adhesive layer, such as Figure 2 As shown in (a) / 2(b) / 2(c): ① The refractive film layer presents a patterned design, and its size matches the size enclosed by the cofferdam structure, such as Figure 2 As shown in (a); ② The refractive film layer presents a patterned design, and its size is smaller than the size enclosed by the cofferdam structure, such as Figure 2 (b) in FIG. 3; ③ The refractive film layer covers the entire surface of the glass, and the cofferdam structure and the adhesive layer are formed on the refractive film layer, such as Figure 2 As shown in (c) in this embodiment. Figure 2 The description is based on the structure shown in (a) in FIG.
[0037] (3) Figure 2 The structure shown in (a) is bonded together with the CIS chip through a bonding process to obtain Figure 3 The structure shown in FIG. 14 is a CIS chip, 15 is an Al Pad conductive structure of the CIS chip, 16 is a photosensitive area of the CIS chip, and 204 is the back of the CIS chip.
[0038] (4) Figure 3 In the structure shown in FIG. 1 , the back side of the CIS chip is thinned, and a conductive through-hole structure is formed at the back side of the CIS chip corresponding to the position of the conductive structure, so as to obtain Figure 4 The structure shown in FIG. 205 is a conductive through-hole structure formed on the back side of the CIS chip.
[0039] (5) Figure 4A conductive structure is formed at the conductive via structure shown in the structure, and a first metal redistribution layer is formed to obtain Figure 5 The structure shown in FIG. 17 is the first metal redistribution layer.
[0040] (6) In Figure 5 A first insulating layer is formed on the structure shown in FIG. 1 , and a conductive through-hole structure is formed on the first insulating layer to obtain a structure as shown in FIG. Figure 6 The structure shown in FIG. 18 is a first insulating layer, 206 is an upper surface of the first insulating layer, and 207 is a conductive through-hole structure formed on the first insulating layer.
[0041] (7) In Figure 6 A second metal redistribution layer (ie, pad) is formed on the structure shown in FIG. Figure 7 The structure shown in FIG. 19 is a second metal redistribution layer.
[0042] (8) Figure 7 The ball implantation process is completed on the structure shown in the figure, and the Figure 8 The structure shown in FIG. 20 is a conductive structure ball (solder ball).
[0043] like Fig. 9 As shown in the structure, the layers in the CIS chip packaging structure prepared in this embodiment are specifically as follows: 10-glass, 11-refractive film layer, 12-cofferdam structure, 13-adhesive layer on the cofferdam structure, 14-CIS chip, 15-CIS chip conductive structure (i.e. AlPad), 16-CIS chip photosensitive area, 17-first metal redistribution layer, 18-first insulating layer, 19-second metal redistribution layer (soldering pad), 20-conductive structure ball (tin ball).
[0044] The present packaging structure and method forms a high-refractive film layer (with a refractive index greater than that of glass) on the lower surface of the bonded glass. When light passes through the glass and reaches the high-refractive film layer, the refraction angle of the light in the high-refractive film layer is smaller because the refractive index of the high-refractive film layer is greater than the refractive index of air. The high-refractive film layer gathers the light scattered to the side of the photosensitive area of the CIS chip to the front of the photosensitive area of the CIS chip as much as possible, and the light presents a convergent projection effect, which will generate more light to converge on the photosensitive area of the CIS chip. By increasing the amount of light reaching the photosensitive area of the CIS chip, the ability of the CIS chip to convert optical signals into electrical signals can be effectively enhanced.
[0045] It is worth noting that: in the description of the present invention, the meaning of "multiple" is two or more than two, unless otherwise clearly and specifically defined. In the present invention, unless otherwise clearly stipulated and defined, the terms "install", "connect", "connect", "fix" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; the circuits described in the present invention are all commonly used circuits in the art, and other related components are all existing commonly used components. For ordinary technicians in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.
[0046] It is obvious to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential features of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-restrictive, and the scope of the present invention is defined by the appended claims rather than the above description, and it is intended that all changes that fall within the meaning and scope of the elements of the claims be included in the present invention. Any reference numeral in a claim should not be regarded as limiting the claim to which it relates.
Claims
1. A novel CIS chip packaging method, characterized in that: The steps include: S1, forming a refractive film layer on the glass; S2, forming a cofferdam structure and pasting an adhesive layer on the glass; S3, bonding the CIS chip to the glass; S4, thinning the back side of the CIS chip and forming a through-hole structure; S5, forming a conductive structure and a first metal redistribution layer on the back side of the CIS chip; S6, forming a first insulating layer on the first metal redistribution layer; S7, forming a second metal redistribution layer on the first insulating layer; S8, completing the ball planting process on the second metal redistribution.
2. The novel CIS chip packaging method according to claim 1, characterized in that: The material of the metal redistribution layer in steps S5 and S7 is one or a combination of two or more of aluminum, copper, gold, platinum, nickel and tin.
3. The novel CIS chip packaging method according to claim 1, characterized in that: The material of the insulating layer metal redistribution layer is copper.
4. The novel CIS chip packaging method according to claim 1 is characterized in that: The material of the insulating layer in step S6 is epoxy resin, silicon oxide insulating material or other insulating materials.
5. The novel CIS chip packaging method according to claim 1, characterized in that: In step S3, a high-refractive film layer is formed on the lower surface of the bonding glass to increase the amount of light reaching the photosensitive area of the CIS chip, thereby enhancing the ability of the CIS chip to convert optical signals into electrical signals.
6. The novel CIS chip packaging structure obtained by the method according to claim 1 is characterized in that: include: A refractive film layer formed on the glass, the refractive film layer comprising glass and a refractive film layer disposed on the glass; A cofferdam structure is formed on the refractive film layer structure, and an adhesive layer is printed on the cofferdam structure; The adhesive layer of the cofferdam structure is bonded to the CIS chip through a bonding process, with the back of the CIS chip facing outward, and the conductive structure of the CIS chip and the photosensitive area of the CIS chip facing inward; the back of the CIS chip is thinned, and a conductive through-hole structure is formed at the back of the CIS chip corresponding to the position of the conductive structure; A conductive structure is formed at the conductive through-hole structure, and a first metal redistribution layer is formed; forming a first insulating layer on the first metal redistribution layer, and forming a conductive through-hole structure on the first insulating layer; forming a second metal redistribution layer on the conductive via structure; Conductive structure balls are arranged on the second metal redistribution layer.
7. The packaging structure according to claim 6, characterized in that: The second metal redistribution layer is a pad, and the conductive structure ball is a solder ball.
Citation Information
Patent Citations
Packaging structure of CIS chip
CN207052606U
Cited By
Low-stress packaging method and product thereof
CN120603358A