Low-contact-resistance organic thin film transistor and preparation method thereof
By using eutectic indium gallium alloy and platinum electrode in organic thin film transistors, combined with hafnium-based ferroelectric oxide insulating layer, the problem of high contact resistance in traditional processes is solved, and lower contact resistance and higher tunneling is achieved possibility.
Patent Information
- Application Number
- CN202411648317.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-19
- Publication Date
- 2025-02-21
AI Technical Summary
In the prior art, bombardment of high-energy metal ions in the organic semiconductor thin film leads to an increase in defect state, and the wave function hybrid coupling between the organic semiconductor and traditional copper or gold metal is weak, resulting in a higher contact resistance of the organic thin film transistor.
Add eutectic indium gallium alloy as the adhesive between the source and drain voltages, and replace the traditional copper metal electrode with platinum, and select hafnium-based ferroelectric oxide as the gate insulating layer to form a new organic thin film transistor structure.
It effectively reduces the contact resistance of organic thin film transistors, reduces damage to organic semiconductor thin films, and increases the possibility of tunneling.
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Figure CN119497486A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of organic semiconductors, and in particular to a low contact resistance organic thin film transistor and a preparation method thereof. Background Art
[0002] Organic electronics has developed rapidly in recent decades and has gradually become an emerging discipline. Due to the characteristics of low production cost, good mechanical flexibility, and diverse chemical synthesis methods, organic semiconductor materials have been widely used in the fields of field effect transistors, solar cells, flexible displays, radio frequency tags, and electronic paper, and have shown great potential in new electronic industries such as biochips and wearable electronic devices. As an emerging research hotspot for microelectronic semiconductors after silicon-based semiconductors, compared with inorganic semiconductors, organic semiconductors generally have lower performance due to factors such as film defects, many grain boundaries, and poor contact interfaces. More importantly, their contact resistance is two orders of magnitude higher than that of inorganic semiconductors (such as oxides, two-dimensional materials, etc.), which seriously restricts the development and application of organic semiconductors.
[0003] As people's quality of life improves, the requirements for device performance and stability in organic electronics are becoming increasingly higher, requiring a purer and more intrinsic organic material platform to conduct a deeper study of the physical properties and mechanisms of materials and devices, that is, research on transistor structure and preparation technology. The key to the realization of high-performance organic transistors is the ohmic contact between metal and organic semiconductors, which is particularly important in high-performance organic circuits. In the field of inorganic semiconductors, ohmic contact is usually achieved by various methods such as heteroepitaxial growth and doping, so that the channel material and the contact electrode are chemically bonded, so that its contact resistance approaches the quantum limit; since organic semiconductors are difficult to dope, they need to rely on carrier injection for conductivity, which requires the development of a new ohmic contact technology to prepare transistors.
[0004] The existing technology for preparing transistors mostly adopts the traditional metal deposition process. Since high-energy metal ions are required to bombard the semiconductor film (mainly appearing in the source and drain metals), the organic semiconductor will produce a higher defect state, resulting in a high contact resistance. In addition, some organic molecules have longer alkyl chains, which leads to weak wave function hybridization coupling between organic semiconductors and traditional copper metal or gold metal as electrode metals, and low tunneling possibility, which further leads to high contact resistance of organic thin film transistors. These problems lead to the general problem of high contact resistance of organic transistor devices prepared by traditional processes, which has become a key bottleneck restricting the development of organic semiconductor devices.
[0005] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention
[0006] In response to the problems in the related art, the present invention proposes a low contact resistance organic thin film transistor and a preparation method thereof, which has the advantages of effectively reducing the contact resistance of the organic thin film transistor by adding a eutectic indium gallium alloy as a binder between the source and drain voltages, replacing the traditional copper metal electrode with platinum, and selecting a hafnium-based ferroelectric oxide as the gate insulating layer, thereby solving the problem in the prior art that high-energy metal ions are required to bombard the semiconductor film, which will cause the organic semiconductor to produce a higher defect state, and the wave function hybridization coupling between the organic semiconductor and the traditional copper metal or gold metal as the electrode metal is weak, and the tunneling possibility is low, resulting in a higher contact resistance of the organic thin film transistor.
[0007] To this end, the specific technical solution adopted by the present invention is as follows: According to one aspect of the present invention, there is provided a low contact resistance organic thin film transistor, which includes a silicon-hafnium-based ferroelectric substrate, an organic semiconductor thin film is arranged on the top of the silicon-hafnium-based ferroelectric substrate, a first eutectic indium gallium alloy is arranged on one side of the top of the organic semiconductor film, a second eutectic indium gallium alloy is arranged on the other side of the top of the organic semiconductor film, and a top electrode structure is arranged on the tops of the first eutectic indium gallium alloy and the second eutectic indium gallium alloy.
[0008] Furthermore, the silicon-hafnium-based ferroelectric substrate includes a second P-type silicon substrate, and a hafnium-based ferroelectric gate insulating layer is disposed on the top of the second P-type silicon substrate.
[0009] Furthermore, the hafnium-based ferroelectric gate insulating layer includes a hafnium zirconium oxide film disposed on the top of the second P-type silicon substrate, and the organic semiconductor film includes a C 10 -DNTT organic film.
[0010] Furthermore, the top electrode structure includes a platinum source metal electrode disposed on the top of the first eutectic Indium Gallium alloy, and the structure of the first eutectic Indium Gallium alloy is the same as that of the second eutectic Indium Gallium alloy.
[0011] Furthermore, the top electrode structure also includes a platinum drain metal electrode disposed on the top of the second eutectic InGa alloy, and the structure of the platinum source metal electrode is the same as that of the platinum drain metal electrode.
[0012] Furthermore, the platinum source metal electrode includes a first P-type silicon substrate, a plurality of pre-patterned platinum electrodes are arranged on the top of the first P-type silicon substrate, and the first P-type silicon substrate is connected to the first eutectic InGa alloy through the pre-patterned platinum electrodes.
[0013] According to another aspect of the present invention, a method for preparing a low contact resistance organic thin film transistor is also provided, and the method for preparing a low contact resistance organic thin film transistor comprises: S1, generating a pattern on the surface of a first P-type silicon substrate using an electron beam exposure technique, and depositing platinum on the surface of the first P-type silicon substrate using an electron beam evaporation technique to obtain a plurality of pre-patterned platinum electrodes; S2, preheating the atomic layer deposition chamber based on a preset time, placing a second P-type silicon substrate into the preheated atomic layer deposition chamber and evacuating the chamber, and purging the second P-type silicon substrate by alternating hafnium source pulses, zirconium source pulses and water source pulses in a cycle until a hafnium-based ferroelectric gate insulating layer of a predetermined thickness is generated; S3. Using a solution preparation process according to a specific solvent and organic molecules, a C10-DNTT solution of a predetermined concentration is obtained, and based on a hafnium-based ferroelectric gate insulating layer, a C10-DNTT solution is grown using a solution shearing method. 10 -DNTT organic film; S4. Use dropper technology in C 10 -A first eutectic Indium Gallium alloy and a second eutectic Indium Gallium alloy are deposited on the surface of the DNTT organic film, and a pre-patterned platinum electrode is transferred to the surface of the first eutectic Indium Gallium alloy and the second eutectic Indium Gallium alloy by a probe-assisted transfer method to form a top electrode structure.
[0014] Further, preheating the atomic layer deposition chamber based on a preset time, placing the second P-type silicon substrate into the preheated atomic layer deposition chamber and evacuating the chamber, and purging the second P-type silicon substrate by alternating hafnium source pulses, zirconium source pulses, and water source pulse cycles until a hafnium-based ferroelectric gate insulating layer of a predetermined thickness is generated includes: S21, based on the preset outer chamber temperature and the preset inner chamber temperature, preheating the atomic layer deposition chamber for a preset time, and placing a second P-type silicon substrate; S22, evacuating the atomic layer deposition chamber after placing the second P-type silicon substrate, setting the purge time of the hafnium source pulse, the zirconium source pulse and the water source pulse, using the hafnium source pulse, the zirconium source pulse and the water source pulse to alternately purge the second P-type silicon substrate, and purge the inert gas to the surface of the second P-type silicon substrate at alternating intervals; S23, repeating step S22 until a predetermined number of cycles is reached to obtain a hafnium-based ferroelectric gate insulating layer with a predetermined thickness.
[0015] Furthermore, according to the specific solvent and organic molecules, a solution preparation process is used to obtain a C10-DNTT solution of a predetermined concentration, and based on the hafnium-based ferroelectric gate insulating layer, a solution shearing method is used to grow C 10 -DNTT organic films include: S31, based on tetralin solvent, prepare C of predetermined concentration 10 -DNTT solution, and heat it in a water bath to obtain a fully dissolved organic molecule solution; S32, setting the scraper inclination angle and spacing parameters, and injecting a fully dissolved organic molecule solution between the hafnium-based ferroelectric gate insulating layer and the scraper; S33, based on the preset temperature and the scraper movement rate, through the solution shear deposition process, generate C 10 -DNTT organic film.
[0016] Furthermore, using the dropper technique in C 10 -Depositing a first eutectic InGa alloy and a second eutectic InGa alloy on the surface of the DNTT organic film, and transferring a pre-patterned platinum electrode to the surface of the first eutectic InGa alloy and the second eutectic InGa alloy by a probe-assisted transfer method, forming a top electrode structure including: S41, based on C 10 -DNTT organic thin film, using a dropper drop process to deposit an alloy contact layer to obtain a first eutectic InGa alloy and a second eutectic InGa alloy; S42, using a probe-assisted transfer method, transferring a plurality of pre-patterned platinum electrodes to the surface of the first eutectic indium gallium alloy to form a platinum source metal electrode; S43. Transferring a number of pre-patterned platinum electrodes to the surface of the second eutectic indium gallium alloy through a probe-assisted transfer method to form a platinum drain metal electrode, thereby obtaining a top electrode structure of the transistor.
[0017] The beneficial effects of the present invention are: (1) The present invention provides a silicon-hafnium-based ferroelectric substrate, a C 10 -DNTT, eutectic indium gallium alloy and platinum together constitute a new type of organic thin film transistor, which solves the problem in the existing technology that high-energy metal ions are needed to bombard the semiconductor film, which will cause the organic semiconductor to produce a higher defect state, and the wave function hybrid coupling between the organic semiconductor and the traditional copper metal or gold metal as the electrode metal is weak, and the tunneling possibility is low, resulting in a higher contact resistance of the organic thin film transistor.
[0018] (2) The preparation method of the present invention can reduce the damage to the organic semiconductor film caused by the traditional process, and at the same time, the hafnium-based ferroelectric oxide is used as the oxidative insulating layer and platinum is used as the metal electrode, thereby improving the organic semiconductor C 10 -DNTT and the platinum electrode, thereby further reducing the contact resistance of the organic thin film transistor. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0020] Figure 1 is a schematic structural diagram of a low contact resistance organic thin film transistor according to an embodiment of the present invention; Figure 2 is a schematic structural diagram of a low contact resistance organic thin film transistor obtained in step S1 of a method for preparing a low contact resistance organic thin film transistor according to an embodiment of the present invention; Figure 3 is a schematic structural diagram of a low contact resistance organic thin film transistor obtained in step S2 of a method for preparing a low contact resistance organic thin film transistor according to an embodiment of the present invention; Figure 4 is a schematic structural diagram of a low contact resistance organic thin film transistor obtained in step S3 of a method for preparing a low contact resistance organic thin film transistor according to an embodiment of the present invention; Figure 5 is a schematic diagram of a solution shearing method in a method for preparing an organic thin film transistor with low contact resistance according to an embodiment of the present invention; Figure 6 It is C 10 -Molecular structure of DNTT; Figure 7 It is a schematic diagram of a process of manufacturing an organic thin film transistor with low contact resistance according to an embodiment of the present invention.
[0021] In the figure: 101, first P-type silicon substrate; 102, pre-patterned platinum electrode; 201, second P-type silicon substrate; 202, hafnium-based ferroelectric gate insulating layer; 301, C 10 -DNTT organic film; 401, first eutectic Indium Gallium alloy; 402, second eutectic Indium Gallium alloy; 403, platinum source metal electrode; 404, platinum drain metal electrode. DETAILED DESCRIPTION
[0022] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments and can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in the field should be able to understand other possible implementations and advantages of the present invention. The components in the figures are not drawn to scale, and similar component symbols are generally used to represent similar components.
[0023] According to an embodiment of the present invention, a low contact resistance organic thin film transistor and a method for preparing the same are provided.
[0024] The present invention is further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, according to one embodiment of the present invention, a low contact resistance organic thin film transistor is provided, which includes a silicon-hafnium-based ferroelectric substrate, an organic semiconductor film is arranged on the top of the silicon-hafnium-based ferroelectric substrate, a first eutectic indium gallium alloy 401 is arranged on one side of the top of the organic semiconductor film, a second eutectic indium gallium alloy 402 is arranged on the other side of the top of the organic semiconductor film, and a top electrode structure is arranged on the top of the first eutectic indium gallium alloy 401 and the second eutectic indium gallium alloy 402.
[0025] In one embodiment, the silicon-hafnium-based ferroelectric substrate includes a second P-type silicon substrate 201 , and a hafnium-based ferroelectric gate insulating layer 202 is disposed on the top of the second P-type silicon substrate 201 .
[0026] In one embodiment, the hafnium-based ferroelectric gate insulating layer 202 includes a hafnium zirconium oxide film disposed on the top of the second P-type silicon substrate 201, and the organic semiconductor film includes a C 10 -DNTT organic film 301.
[0027] In one embodiment, the top electrode structure includes a platinum source metal electrode 403 disposed on the top of the first eutectic InGa alloy 401 , and the first eutectic InGa alloy 401 and the second eutectic InGa alloy 402 have the same structure.
[0028] In one embodiment, the top electrode structure further includes a platinum drain metal electrode 404 disposed on the top of the second eutectic InGa alloy 402 , and the platinum source metal electrode 403 has the same structure as the platinum drain metal electrode 404 .
[0029] In one embodiment, the platinum source metal electrode 403 includes a first P-type silicon substrate 101 , a plurality of pre-patterned platinum electrodes 102 are disposed on the top of the first P-type silicon substrate 101 , and the first P-type silicon substrate 101 is connected to the first eutectic InGa alloy 401 through the pre-patterned platinum electrodes 102 .
[0030] like Figure 7 According to another embodiment of the present invention, a method for preparing a low contact resistance organic thin film transistor is provided, the method comprising: S1, using electron beam exposure technology to generate a pattern on the surface of the first P-type silicon substrate 101, and using electron beam evaporation technology to deposit platinum on the surface of the first P-type silicon substrate 101 to obtain a plurality of pre-patterned platinum electrodes 102; Specifically, Figure 2 As shown, a first P-type silicon substrate 101 is provided, and a plurality of pre-patterned platinum electrodes 102 are prepared by electron beam exposure and electron beam evaporation technology.
[0031] S2, preheating the atomic layer deposition chamber based on a preset time, placing the second P-type silicon substrate 201 into the preheated atomic layer deposition chamber and evacuating the chamber, and purging the second P-type silicon substrate 201 by alternating hafnium source pulses, zirconium source pulses and water source pulses in a cycle until a hafnium-based ferroelectric gate insulating layer 202 of a predetermined thickness is generated; S3, using a solution preparation process to obtain a C10-DNTT solution of a predetermined concentration according to a specific solvent and an organic molecule, and growing C10-DNTT based on the hafnium-based ferroelectric gate insulating layer 202 by a solution shearing method. 10 -DNTT organic film 301; S4. Use dropper technology in C 10 A first eutectic InGa alloy 401 and a second eutectic InGa alloy 402 are deposited on the surface of the -DNTT organic film 301, and a pre-patterned Pt electrode 102 is transferred to the surface of the first eutectic InGa alloy 401 and the second eutectic InGa alloy 402 by a probe-assisted transfer method to form a top electrode structure.
[0032] Specifically, the present invention provides a novel low contact resistance organic thin film transistor (OTFT) structure and a preparation method thereof, wherein the organic semiconductor is selected from C 10 -DNTT (eg Figure 6 As shown, compared with the organic thin film transistor under the traditional process, the present invention uses eutectic indium gallium alloy to bond between the organic semiconductor and the metal source and drain. The eutectic indium gallium alloy is a liquid metal with a melting point close to or lower than room temperature, and this alloy has very high thermal conductivity and electrical conductivity, avoiding the damage of the organic film caused by the direct bombardment of the semiconductor film by metal high-energy ions in the traditional metal precipitation process. At the same time, the gate insulating layer is selected to use hafnium-based ferroelectric oxide (Hf is used in this embodiment) 0.5 Zr 0.5 O2) hafnium-based ferroelectric thin films were prepared by atomic layer deposition. The source and drain metals were selected to be platinum electrodes pre-patterned on a silicon substrate. Then, eutectic indium gallium alloy was applied on its surface and gently pressed onto the organic film to avoid damage to the organic film. Due to the high conductivity of the eutectic indium gallium alloy, no special removal operation was required after transfer. Also, when platinum formed electrical contact with the organic semiconductor, C 10 The alkyl chain of -DNTT acts as a tunneling barrier, and the hole-type carriers of platinum are 10 -DNTT tunneling is more likely, further reducing the contact resistance of the organic thin film transistor.
[0033] In one embodiment, the atomic layer deposition chamber is preheated based on a preset time, the second P-type silicon substrate 201 is placed in the preheated atomic layer deposition chamber and evacuated, and the second P-type silicon substrate 201 is purged by alternating hafnium source pulses, zirconium source pulses, and water source pulse cycles until a hafnium-based ferroelectric gate insulating layer 202 of a predetermined thickness is generated, including: S21, based on the preset outer chamber temperature and the preset inner chamber temperature, preheating the atomic layer deposition chamber for a preset time, and placing the second P-type silicon substrate 201; S22, evacuating the atomic layer deposition chamber after placing the second P-type silicon substrate 201, setting the purge time of the hafnium source pulse, the zirconium source pulse and the water source pulse, using the hafnium source pulse, the zirconium source pulse and the water source pulse to alternately purge the second P-type silicon substrate 201, and purge the inert gas to the surface of the second P-type silicon substrate 201 at alternating intervals; S23, repeating step S22 until a predetermined number of cycles is reached, thereby obtaining a hafnium-based ferroelectric gate insulating layer 202 with a predetermined thickness.
[0034] Specifically, Figure 3 As shown, another second P-type silicon substrate 201 is provided. First, the atomic layer deposition chamber (ALD chamber) is preheated for 1 hour, the outer chamber temperature is set to 200 degrees Celsius, and the inner chamber temperature is set to 150 degrees Celsius. The cleaned and dried second P-type silicon substrate 201 is placed in the preheated ALD chamber and evacuated. Then, the hafnium source pulse purge time of each cycle is set to 150ms, the zirconium source pulse purge time is set to 150ms, and the water source pulse purge time is set to 300ms. The hafnium source and zirconium source pulses are purged simultaneously, and the inert gas N2 is purged between the two and the water source pulses. The inert gas purge time is set to 30s, and finally a hafnium-based ferroelectric HZO (Hf) film with a thickness of 30nm is grown. 0.5 Zr 0.5 O2) The membrane required 165 cycles of purge.
[0035] Specifically, Figure 3 As shown, a hafnium-based ferroelectric HZO (Hf) with a height of 30 nm is grown on the second P-type silicon substrate 201 by atomic layer deposition. 0.5 Zr 0.5 O2) thin film to obtain a hafnium-based ferroelectric gate insulating layer 202, and the hafnium-based ferroelectric gate insulating layer 202 and the second P-type silicon substrate 201 form a silicon-hafnium-based ferroelectric (Si-HZO) substrate.
[0036] In one embodiment, according to a specific solvent and an organic molecule, a solution configuration process is used to obtain a C10-DNTT solution of a predetermined concentration, and based on the hafnium-based ferroelectric gate insulating layer 202, a solution shearing method is used to grow C 10 -DNTT organic film 301 includes: S31, based on tetralin solvent, prepare C of predetermined concentration 10 -DNTT solution, and heat it in a water bath to obtain a fully dissolved organic molecule solution; S32, setting the scraper inclination angle and spacing parameters, and injecting a fully dissolved organic molecule solution between the hafnium-based ferroelectric gate insulating layer 202 and the scraper; S33, based on the preset temperature and the scraper movement rate, through the solution shear deposition process, generate C 10 -DNTT organic film 301.
[0037] It should be noted that C 10 -DNTT is a common organic compound in the field of organic semiconductors. It has good charge transfer performance and high quantum efficiency, high carrier mobility and stability. It is often used to prepare organic light-emitting diodes and high-performance field-effect transistors. This is an existing technology in the field of organic semiconductors and will not be elaborated here.
[0038] Specifically, Figure 4 As shown, C was grown by solution shearing 10 -DNTT organic film 301, first prepare the solution required for growth, the solvent is 1,2,3,4-tetrahydronaphthalene (naphthalene) and the solute concentration is 0.25mg / ml C 10 -DNTT solution, after preparation, is heated in a water bath to ensure that the organic molecules in the solution are fully dissolved, and the solution is injected into the intersection of the silicon-hafnium-based ferroelectric substrate obtained in step S2 and the upper scraper, the temperature is set to 70 degrees Celsius, the upper scraper inclination angle is 14°, the upper and lower scraper distance is 100um, and the upper scraper moving speed is 3um / s. Figure 3 As shown, a layer of C is grown on the Si-HZO substrate obtained in step S2 by a solution shearing method. 10 -DNTT organic film 301.
[0039] Specifically, the solution shearing process is as follows Figure 5As shown in the figure, Shearing direction is the solution shearing direction; Shearing plate is the shearing plate (the upper scraper in this embodiment); Semiconductor solution is the organic semiconductor solution; Propagating crystalline film is the organic semiconductor film; PST-treated SIO2 / Si (stationary) is silicon dioxide or silicon substrate (referring to oxide film layer or Si substrate); Heated bottom substrate is the heating plate (the lower scraper in this embodiment); in the above embodiment, the temperature range of the solution shearing method is set to 65-75 degrees Celsius, the scraper inclination angle is set to 12°-15°, the speed is set to 3um / s-5um / s, and the distance between the upper and lower scrapers is set to 80-120um.
[0040] In one embodiment, the dropper technique is used to 10 - A first eutectic Indium Gallium alloy 401 and a second eutectic Indium Gallium alloy 402 are deposited on the surface of the DNTT organic film 301, and a pre-patterned platinum electrode 102 is transferred to the surface of the first eutectic Indium Gallium alloy 401 and the second eutectic Indium Gallium alloy 402 by a probe-assisted transfer method to form a top electrode structure including: S41, based on C 10 -DNTT organic film 301, using a dropper dripping process to deposit an alloy contact layer to obtain a first eutectic Indium Gallium alloy 401 and a second eutectic Indium Gallium alloy 402; S42, using a probe-assisted transfer method, transferring a plurality of pre-patterned platinum electrodes 102 to the surface of the first eutectic InGa alloy 401 to form a platinum source metal electrode 403; S43. Transferring a plurality of pre-patterned platinum electrodes 102 to the surface of the second eutectic indium gallium alloy 402 by a probe-assisted transfer method to form a platinum drain metal electrode 404, thereby obtaining a top electrode structure of the transistor.
[0041] It should be noted that the probe-assisted transfer method is a micro-nano structure transfer technology that can utilize the van der Waals force or electrostatic force interaction between the probe tip and the pre-patterned platinum electrode to obtain the electrode structure to be transferred and achieve precise three-dimensional position control. In this scheme, the probe-assisted transfer method is used to utilize moderate interaction forces to obtain a transfer process that is almost damageless to the underlying organic film, thereby achieving controllable transfer of the platinum electrode from the source substrate to the surface of the eutectic indium gallium alloy. This is a prior art and will not be elaborated on here.
[0042] Specifically, Figure 1 As shown, the first eutectic InGa alloy 401 and the second eutectic InGa alloy 402 are dropped onto the C 10-DNTT organic film 301, and then the platinum electrode 102 pre-patterned in step S1 is transferred to C by probe-assisted transfer method. 10 -DNTT organic film 301 on the surface of the first eutectic InGa alloy 401, the second eutectic InGa alloy 402, this method is effective in C 10 The -DNTT organic film 301 is hardly damaged while forming a platinum source metal electrode 403 and a platinum drain metal electrode 404, thereby completing the preparation of a top electrode type low contact resistance organic thin film transistor (OTFT).
[0043] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims
1. A low contact resistance organic thin film transistor, characterized in that: The low contact resistance organic thin film transistor includes a silicon-hafnium-based ferroelectric substrate, an organic semiconductor film is arranged on the top of the silicon-hafnium-based ferroelectric substrate, a first eutectic indium gallium alloy is arranged on one side of the top of the organic semiconductor film, a second eutectic indium gallium alloy is arranged on the other side of the top of the organic semiconductor film, and a top electrode structure is arranged on the tops of the first eutectic indium gallium alloy and the second eutectic indium gallium alloy.
2. The low contact resistance organic thin film transistor according to claim 1, characterized in that: The silicon-hafnium-based ferroelectric substrate comprises a second P-type silicon substrate, and a hafnium-based ferroelectric gate insulating layer is arranged on the top of the second P-type silicon substrate.
3. The low contact resistance organic thin film transistor according to claim 2, characterized in that: The hafnium-based ferroelectric gate insulating layer includes a hafnium zirconium oxide film disposed on the top of the second P-type silicon substrate, and the organic semiconductor film includes a C 10 -DNTT organic film.
4. The low contact resistance organic thin film transistor according to claim 1, characterized in that: The top electrode structure includes a platinum source metal electrode disposed on the top of the first eutectic Indium Gallium alloy, and the first eutectic Indium Gallium alloy has the same structure as the second eutectic Indium Gallium alloy.
5. The low contact resistance organic thin film transistor according to claim 4, characterized in that: The top electrode structure also includes a platinum drain metal electrode disposed on the top of the second eutectic InGa alloy, and the platinum source metal electrode has the same structure as the platinum drain metal electrode.
6. The low contact resistance organic thin film transistor according to claim 5, characterized in that: The platinum source metal electrode includes a first P-type silicon substrate, a plurality of pre-patterned platinum electrodes are arranged on the top of the first P-type silicon substrate, and the first P-type silicon substrate is connected to the first eutectic indium gallium alloy through the pre-patterned platinum electrodes.
7. A method for preparing a low contact resistance organic thin film transistor, for preparing the low contact resistance organic thin film transistor according to any one of claims 1 to 6, characterized in that: The low contact resistance organic thin film transistor preparation method comprises: S1, generating a pattern on the surface of a first P-type silicon substrate using an electron beam exposure technique, and depositing platinum on the surface of the first P-type silicon substrate using an electron beam evaporation technique to obtain a plurality of pre-patterned platinum electrodes; S2, preheating the atomic layer deposition chamber based on a preset time, placing a second P-type silicon substrate into the preheated atomic layer deposition chamber and evacuating the chamber, and purging the second P-type silicon substrate by alternating hafnium source pulses, zirconium source pulses and water source pulses in a cycle until a hafnium-based ferroelectric gate insulating layer of a predetermined thickness is generated; S3. Using a solution preparation process according to a specific solvent and organic molecules, a C10-DNTT solution of a predetermined concentration is obtained, and based on a hafnium-based ferroelectric gate insulating layer, a C10-DNTT solution is grown using a solution shearing method. 10 -DNTT organic film; S4. Use dropper technology in C 10 -A first eutectic Indium Gallium alloy and a second eutectic Indium Gallium alloy are deposited on the surface of the DNTT organic film, and a pre-patterned platinum electrode is transferred to the surface of the first eutectic Indium Gallium alloy and the second eutectic Indium Gallium alloy by a probe-assisted transfer method to form a top electrode structure.
8. The method for preparing a low contact resistance organic thin film transistor according to claim 7, characterized in that: The method of preheating the atomic layer deposition chamber based on a preset time, placing the second P-type silicon substrate in the preheated atomic layer deposition chamber and evacuating the chamber, and purging the second P-type silicon substrate by alternating hafnium source pulses, zirconium source pulses, and water source pulse cycles until a hafnium-based ferroelectric gate insulating layer of a predetermined thickness is generated comprises: S21, based on the preset outer chamber temperature and the preset inner chamber temperature, preheating the atomic layer deposition chamber for a preset time, and placing a second P-type silicon substrate; S22, evacuating the atomic layer deposition chamber after placing the second P-type silicon substrate, setting the purge time of the hafnium source pulse, the zirconium source pulse and the water source pulse, using the hafnium source pulse, the zirconium source pulse and the water source pulse to alternately purge the second P-type silicon substrate, and purge the inert gas to the surface of the second P-type silicon substrate at alternating intervals; S23, repeating step S22 until a predetermined number of cycles is reached to obtain a hafnium-based ferroelectric gate insulating layer with a predetermined thickness.
9. The method for preparing a low contact resistance organic thin film transistor according to claim 7, characterized in that: The method uses a solution configuration process to obtain a C10-DNTT solution of a predetermined concentration according to a specific solvent and an organic molecule, and uses a solution shearing method to grow C10-DNTT based on a hafnium-based ferroelectric gate insulating layer. 10 -DNTT organic films include: S31, based on tetralin solvent, prepare C of predetermined concentration 10 -DNTT solution, and heat it in a water bath to obtain a fully dissolved organic molecule solution; S32, setting the scraper inclination angle and spacing parameters, and injecting a fully dissolved organic molecule solution between the hafnium-based ferroelectric gate insulating layer and the scraper; S33, based on the preset temperature and the scraper movement rate, through the solution shear deposition process, generate C 10 -DNTT organic film.
10. The method for preparing a low contact resistance organic thin film transistor according to claim 7, characterized in that: The use of dropper technology in C 10 -Depositing a first eutectic Indium Gallium alloy and a second eutectic Indium Gallium alloy on the surface of the DNTT organic film, and transferring a pre-patterned platinum electrode to the surface of the first eutectic Indium Gallium alloy and the second eutectic Indium Gallium alloy by a probe-assisted transfer method, forming a top electrode structure including: S41, based on C 10 -DNTT organic thin film, using a dropper drop process to deposit an alloy contact layer to obtain a first eutectic InGa alloy and a second eutectic InGa alloy; S42, using a probe-assisted transfer method, transferring a plurality of pre-patterned platinum electrodes to the surface of the first eutectic indium gallium alloy to form a platinum source metal electrode; S43. Transferring a number of pre-patterned platinum electrodes to the surface of the second eutectic indium gallium alloy through a probe-assisted transfer method to form a platinum drain metal electrode, thereby obtaining a top electrode structure of the transistor.