Display device

Abstract

A display device is provided. The display device includes a plurality of unit pixel regions, a first thin film transistor in a unit pixel region among the plurality of unit pixel regions and including a first active layer on the substrate, a second thin film transistor in the unit pixel region and including a second active layer at a layer different from a layer of the first active layer, a plurality of conductive layers in the unit pixel area and including a plurality of wirings and conductive patterns electrically connected to the first and second thin film transistors, a valley portion surrounding the unit pixel area and penetrating at least some of the plurality of insulating layers overlapping the first and second thin film transistors; and a stacked structure in the valley portion and including one or more patterns stacked at the same layer as the plurality of conductive layers and the plurality of insulating layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0108273 filed in the Korean Intellectual Property Office on August 18, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device. Background Art

[0004] With the progress of the information society, more and more demands have been put forward for display devices that display images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices and / or smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device and an organic light emitting display device. Among the flat panel display devices, in the light emitting display device, since each of the pixels of the display panel includes a light emitting element that can emit light by itself, an image can be displayed without a backlight unit for providing light to the display panel.

[0005] The display device may include pixels emitting predetermined light, and may further include scan lines, data lines, and power lines for driving the pixels, a scan driver outputting scan signals to the scan lines, and a display driver outputting data voltages to the data lines.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the present disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] One or more embodiments of the present disclosure may relate to a display device capable of preventing or substantially preventing damage to a circuit element due to an impact applied from the outside.

[0008] However, the aspects and features of the present disclosure are not limited to the aspects and features described above. Through the following description, the above and other aspects and features of the present disclosure will become more apparent to those skilled in the art.

[0009] According to one or more embodiments of the present disclosure, a display device includes a first semiconductor layer including a first active layer on a substrate, a first insulating layer on the first active layer, a first conductive layer on the first insulating layer and including a first gate electrode overlapping the first active layer and including a first capacitor electrode, a second insulating layer on the first conductive layer, a second conductive layer on the second insulating layer and including a second capacitor electrode overlapping the first capacitor electrode, a third insulating layer on the second conductive layer, a second semiconductor layer including a second active layer on the third insulating layer, a fourth insulating layer on the second active layer, a third conductive layer on the fourth insulating layer and including a second gate electrode overlapping the second active layer, a fifth insulating layer on the third conductive layer, a valley portion penetrating at least some of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, a stacked structure of one or more of a plurality of insulating patterns included in the valley portion at the same layers as the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer, respectively, a sixth insulating layer on the fifth insulating layer and including at least a portion in the valley portion, and a light emitting element on the sixth insulating layer.

[0010] In an embodiment, the display device may further include a barrier layer between the first active layer and the substrate, a lower metal layer between the barrier layer and the first active layer, and a buffer layer between the lower metal layer and the first active layer. The valley portion may penetrate the buffer layer, and the stacked structure may be directly positioned on the barrier layer.

[0011] In an embodiment, a height of the stack structure measured from the barrier layer may be greater than a height of the second active layer measured from the barrier layer.

[0012] In embodiments, the stack structure may include one or more of a plurality of metal patterns respectively positioned at the same layers as the lower metal layer, the first conductive layer, the second conductive layer, and the third conductive layer.

[0013] In embodiments, the stack structure may include one or more of a plurality of semiconductor patterns respectively positioned at the same layers as the first semiconductor layer and the second semiconductor layer.

[0014] In an embodiment, the height of the stacked structure may be greater than the depth of the valley portion.

[0015] In an embodiment, the height of the stacked structure may be smaller than the depth of the valley portion.

[0016] In an embodiment, the stacked structure may include a first metal pattern at the same layer as that of the lower metal layer, a first insulating pattern at the same layer as that of the buffer layer, a first semiconductor pattern at the same layer as that of the first semiconductor layer, a second insulating pattern at the same layer as that of the first insulating layer, a second metal pattern at the same layer as that of the first conductive layer, a third insulating pattern at the same layer as that of the second insulating layer, a third metal pattern at the same layer as that of the second conductive layer, a fourth insulating pattern at the same layer as that of the third insulating layer, a second semiconductor pattern at the same layer as that of the second semiconductor layer, a fifth insulating pattern at the same layer as that of the fourth insulating layer, a fourth metal pattern at the same layer as that of the third conductive layer, and a sixth insulating pattern at the same layer as that of the fifth insulating layer.

[0017] In an embodiment, a first metal pattern, a first insulation pattern, a first semiconductor pattern, a second insulation pattern, a second metal pattern, a third insulation pattern, a third metal pattern, a fourth insulation pattern, a second semiconductor pattern, a fifth insulation pattern, a fourth metal pattern and a sixth insulation pattern may be sequentially stacked in a stack structure.

[0018] In an embodiment, a sixth insulating layer may surround the stack structure.

[0019] In an embodiment, in the valley portion, the depth of the portion that does not overlap with the first to third conductive layers, the first semiconductor layer, and the second semiconductor layer may be greater than the depth of the portion that overlaps with any one of the first to third conductive layers, the first semiconductor layer, and the second semiconductor layer.

[0020] In an embodiment, the first active layer may include silicon, and the second active layer may include an oxide semiconductor.

[0021] In an embodiment, the second conductive layer may further include a back gate electrode overlapping the second active layer.

[0022] In an embodiment, the display device may further include a fourth conductive layer between the fifth insulating layer and the sixth insulating layer, the fourth conductive layer including a first connection electrode connected to the first active layer and a bridge electrode connected to the second active layer.

[0023] According to one or more embodiments of the present disclosure, a display device includes a plurality of unit pixel areas, a first thin film transistor in a unit pixel area among the plurality of unit pixel areas and including a first active layer on a substrate, a second thin film transistor in the unit pixel area and including a second active layer at a layer different from that of the first active layer, a plurality of conductive layers in the unit pixel area and including a plurality of wirings and a plurality of conductive patterns electrically connected to the first thin film transistor and the second thin film transistor, a valley portion surrounding the unit pixel area and penetrating at least some of the plurality of insulating layers overlapping the first thin film transistor and the second thin film transistor, and a plurality of stacked structures in the valley portion and including one or more patterns stacked at the same layer as a layer among the plurality of conductive layers and the plurality of insulating layers.

[0024] In an embodiment, the plurality of unit pixel regions may be positioned along a first direction and a second direction crossing the first direction, and the valley portion may include portions extending in the first direction and the second direction.

[0025] In an embodiment, a stack structure among the plurality of stack structures may be positioned in a region where a portion of the valley portion extending in the first direction and a portion of the valley portion extending in the second direction cross each other.

[0026] In embodiments, a stack structure among the plurality of stack structures may include one or more of a first semiconductor pattern at the same layer as the first active layer and a second semiconductor pattern at the same layer as the second active layer.

[0027] In embodiments, a stack structure among the plurality of stack structures may include one or more of a plurality of metal patterns respectively at the same layers as the plurality of conductive layers and a plurality of insulating patterns respectively at the same layers as the plurality of insulating layers.

[0028] In an embodiment, a stack structure among the plurality of stack structures may not overlap a conductive pattern and a wiring electrically connected to any one of the first thin film transistor and the second thin film transistor.

[0029] According to one or more embodiments of the present disclosure, a display device may include a valley portion surrounding an area where a pixel circuit is arranged, and a stacked structure arranged in the valley portion and stacked with a pattern arranged at the same layer as (e.g., in or above) a layer in a plurality of conductive layers and insulating layers. The display device can absorb an impact applied from the outside through the valley portion and the stacked structure, and can prevent or substantially prevent circuit elements of the display device from being damaged.

[0030] According to one or more embodiments of the present disclosure, when the display device has flexible characteristics, the valley portion may prevent or substantially prevent cracks that may be formed in a plurality of insulating layers disposed on a substrate when the substrate is folded.

[0031] However, the aspects and features of the present disclosure are not limited to the aspects and features described above, and additional aspects and features will be set forth in part in the detailed description that follows with reference to the accompanying drawings and in part may be apparent therefrom, or may be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above and other aspects and features of the present disclosure will be more clearly understood through the following detailed description of illustrative, non-limiting embodiments with reference to the accompanying drawings, in which:

[0033] Figure 1 is a perspective view of a display device according to an embodiment;

[0034] Figure 2 It is shown Figure 1 A plan view of a display device;

[0035] Figure 3 is along Figure 2 A cross-sectional view taken along line AA';

[0036] Figure 4 is a plan view showing a display panel according to an embodiment;

[0037] Figure 5 is a pixel circuit diagram of a sub-pixel according to an embodiment;

[0038] Figure 6 is a pixel circuit diagram of a sub-pixel according to an embodiment;

[0039] Figure 7 is a plan view showing the arrangement of a plurality of pixel circuits arranged in a display area of ​​a display device according to an embodiment;

[0040] Figure 8 It is shown that the arrangement Figure 7 A plan view of a pixel circuit in a unit pixel area;

[0041] Fig. 9 is along Figure 8 A sectional view taken along line IX-IX';

[0042] Fig.10 is a cross-sectional view showing a second thin film transistor, a valley portion, and a stacked structure of a display device according to an embodiment;

[0043] Fig.11 is a cross-sectional view showing a pixel circuit of a display device according to another embodiment;

[0044] Fig.12 It is shown Fig.11A cross-sectional view of a second thin film transistor, a valley portion, and a stacked structure of a display device;

[0045] Fig.13 is a cross-sectional view showing a pixel circuit of a display device according to another embodiment;

[0046] Fig.14 It is shown Fig.13 A cross-sectional view of a second thin film transistor, a valley portion, and a stacked structure of a display device;

[0047] Fig.15 is a plan view showing the arrangement of pixel circuits and stack structures arranged in a display area of ​​a display device according to an embodiment; and

[0048] Fig.16 is a plan view showing the arrangement of a plurality of pixel circuits and a plurality of stack structures arranged in a display area of ​​a display device according to an embodiment. DETAILED DESCRIPTION

[0049] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which similar reference numerals always refer to similar elements. However, the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects and features of the present disclosure to those skilled in the art. Accordingly, processes, elements and techniques that are unnecessary for a complete understanding of the aspects and features of the present disclosure by those of ordinary skill in the art may not be described. Unless otherwise noted, similar reference numerals represent similar elements throughout the drawings and written descriptions, and therefore their redundant descriptions may not be repeated.

[0050] When a certain embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described successively may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0051] In the accompanying drawings, for clarity, the relative size, thickness and ratio of elements, layers and zones can be exaggerated and / or simplified. Spatial relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and similar words, can be used in this article for the convenience of explanation to describe the relationship between an element or feature as shown in the figure and another element or feature (other elements or features). It will be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to also include different orientations of the device in use or operation. For example, if the device in the figure is flipped, the element described as "below", "beneath" or "under" of other elements or features will be subsequently oriented to other elements or features "above". Therefore, the exemplary terms "below" and "under" can include both the orientation of the top and the bottom. The device can be oriented in other ways (for example, rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0052] In the figure, the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the directions corresponding to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0053] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, first component, first region, first layer or first part discussed below can be referred to as the second element, second component, second region, second layer or second part without departing from the spirit and scope of the present disclosure.

[0054] It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or directly coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected to" another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, and / or can be indirectly electrically connected with one or more intervening layers, regions, or elements therebetween. Furthermore, it will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0055] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include plural forms. It will also be understood that when the terms "comprise", "comprising", "include", "including", "has", "have" and "having" are used in this specification, the existence of the stated features, integers, steps, operations, elements and / or parts is described, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or their clusters is not excluded. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the statement "A and / or B" means A, B, or A and B. When a statement such as "at least one" is after a column of elements, the entire column of elements is modified, and the individual elements in the column are not modified. For example, the expressions "at least one of a, b, or c," "at least one of a, b, and c," and "at least one selected from the cluster consisting of a, b, and c" indicate only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0056] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation and not as terms of degree, and are intended to take into account the inherent deviations of measurements or calculations that one of ordinary skill in the art would recognize. In addition, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0057] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense.

[0058] Figure 1 is a perspective view of a display device according to an embodiment.

[0059] Reference Figure 1 The display device 10 is a device for displaying moving images or still images. The display device 10 can be used as a display screen of various suitable devices such as televisions, laptop computers, monitors, billboards, and Internet of Things (IOT) devices, and various suitable portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra mobile PCs (UMPCs).

[0060] The display device 10 may be a light-emitting display device, such as an organic light-emitting display including an organic light-emitting diode, a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, or a micro light-emitting display using a micro or nano light-emitting diode (LED). For convenience, the display device 10 will be described in more detail below with an embodiment of an organic light-emitting display device, but the present disclosure is not limited thereto, and the type of the display device 10 is not limited thereto.

[0061] In an embodiment, the display device 10 may be formed to be flat or substantially flat. For example, the display device 10 may be formed flat or substantially flat on a plane defined by the first direction DR1 and the second direction DR2, and may have a suitable thickness or height (e.g., a predetermined thickness or height) in the third direction DR3. In another embodiment, the display device 10 may include a curved surface in at least a portion including an edge region and / or a similar region. In addition, the display device 10 may be formed to be flexible so that it can be bent, curved, folded, or curled.

[0062] In some embodiments, with respect to the image display surface of the display device 10, for example, the first direction DR1 may be a vertical direction, a column direction, or a perpendicular direction, and the second direction DR2 may be a direction crossing or intersecting the first direction DR1, such as a width direction, a row direction, or a horizontal direction. The third direction DR3 may be a thickness direction or a height direction of the display device 10.

[0063] The display device 10 may include a display panel 100 , a driver 200 , and a circuit board 300 .

[0064] The display panel 100 may include a main area MA including a display area DA displaying an image, and a sub area SBA positioned on one side of the main area MA.

[0065] The main area MA may include a display area DA and a non-display area NA surrounding the display area DA (e.g., around the periphery of the display area DA). The display area DA may be located at the center of the main area MA and may occupy most of the area in the main area MA. The non-display area NA may be located at an edge of the main area MA and may contact the sub-area SBA.

[0066] The display area DA may be a region where pixels (eg, Figure 4 In an embodiment, the display area DA may also be provided with a sensing pattern (e.g., a touch electrode) for detecting a touch input and similar events, and the display area DA may include a sensing area for detecting a touch input through the sensing pattern.

[0067] In an embodiment, the display area DA may include long sides extending in the first direction DR1 and short sides extending in the second direction DR2, and may be formed as a plane having an approximately rectangular shape. Corner portions where the long sides and short sides of the display area DA meet each other may be rounded or at right angles. However, the present disclosure is not limited thereto, and the shape of the display area DA may be variously modified as needed or desired. For example, the display area DA may be formed in a polygonal shape other than a quadrilateral shape, a circular shape, an elliptical shape, or the like.

[0068] The non-display area NA may be positioned just around the display area DA (e.g., positioned adjacent to the display area DA). The non-display area NA may surround the display area DA (e.g., around the periphery of the display area DA). An embedded circuit may be arranged in the non-display area NA. For example, an embedded circuit including a scan driving circuit or the like may be arranged in the non-display area NA positioned on one side (e.g., the left side or the right side) or both sides (e.g., opposite sides) of the display area DA.

[0069] The sub-area SBA may be positioned on one side of the main area MA. For example, the sub-area SBA may be an area protruding from one side of the main area MA in the first direction DR1. For example, the sub-area SBA may protrude from the lower end of the main area MA in the first direction DR1. In an embodiment, the sub-area SBA may have a width narrower than that of the main area MA. For example, with respect to the second direction DR2, the sub-area SBA may have a width narrower than that of the main area MA.

[0070] Wiring and pads may be arranged in the sub-area SBA. For example, wiring and pads connected to pixels and / or embedded circuits positioned in the main area MA and the driver 200 and / or circuit board 300 positioned in the sub-area SBA may be arranged in the sub-area SBA. As used herein, the term "connection" may include electrical connection and / or physical connection.

[0071] In an embodiment, the driver 200 (eg, a display driving circuit) may be mounted in the sub-area SBA. The circuit board 300 may be disposed on a portion of the sub-area SBA.

[0072] The driver 200 may include a data driving circuit to drive the pixel. In an embodiment, the driver 200 may be formed as an integrated circuit chip (IC) and may be arranged in the sub-area SBA. In another embodiment, the driver 200 may be arranged on the circuit board 300 on the sub-area SBA, or may be arranged on another circuit board connected to the display panel 100 through the circuit board 300.

[0073] The circuit board 300 may be arranged on a portion of the sub-area SBA. For example, the circuit board 300 may be bonded to a pad positioned on a portion (e.g., a lower edge) of the sub-area SBA, and may supply and / or transmit a power voltage and a driving signal for driving the display panel 100 to the display panel 100. For example, the circuit board 300 may supply input image data (e.g., digital image data), a driving signal including a timing signal, and a driving voltage to the display panel 100. The circuit board 300 may be a flexible film (such as a flexible printed circuit board (FPCB)), a rigid printed circuit board (PCB), or a chip on film (COF), but the present disclosure is not limited thereto.

[0074] Figure 2 It is shown Figure 1A plan view of a display device. Figure 3 is along Figure 2 A cross-sectional view taken along line AA'.

[0075] Figure 1 The display device 10 is shown not bent but unfolded, and Figure 2 and Figure 3 The display device 10 is shown bent in the sub-area SBA. Figure 1 A sub-area SBA is shown extending side by side with the main area MA, and Figure 2 and Figure 3 A portion of the sub-area SBA is shown in a bent state.

[0076] Reference Figure 2 and Figure 3 , the display panel 100 may include a substrate 110 including a main area MA and a sub-area SBA. The display panel 100 may also include a circuit layer 120, a light emitting element layer 190, and an encapsulation layer 140 sequentially arranged on the substrate 110. The circuit layer 120 may also be positioned in the main area MA and the sub-area SBA on the substrate 110. The light emitting element layer 190 and the encapsulation layer 140 may be positioned on portions of the substrate 110 and the circuit layer 120. For example, the light emitting element layer 190 and the encapsulation layer 140 may be positioned in the main area MA.

[0077] In an embodiment, the display device 10 may further include additional elements disposed on the display panel 100. For example, the display device 10 may further include at least one of a sensor layer (e.g., a touch sensor layer), a polarizing layer, a color filter layer, and a protective layer (e.g., a window) disposed on the encapsulation layer 140. Each of the sensor layer, the polarizing layer, the color filter layer, and the protective layer may be manufactured integrally with the display panel 100, or may be manufactured separately from the display panel 100 and attached to the display panel 100 by an adhesive layer or the like.

[0078] The substrate 110 may include an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide or another insulating material. The substrate 110 may be a flexible substrate that can be deformed (such as being able to be bent, folded, or curled). As another example, the substrate 110 may include an insulating material such as glass.

[0079] The circuit layer 120 may include pixel circuits and wiring. For example, the circuit layer 120 may include circuit elements (e.g., pixel transistors and capacitors) constituting pixel circuits for each pixel and wiring connected to the pixels. In an embodiment, the circuit layer 120 may also include circuit elements constituting embedded circuits (such as scan drive circuits) and wiring connected to the embedded circuits.

[0080] The light emitting element layer 190 may include a light emitting element arranged in an emission region of a pixel. For example, each of the pixels may include at least one light emitting element and a pixel circuit connected to the light emitting element. Each of the pixels may be positioned in a pixel region including an emission region in which a light emitting element is arranged and a pixel circuit region in which a pixel circuit is arranged. The emission region and the pixel circuit region of the corresponding pixel may overlap each other, but the present disclosure is not limited thereto.

[0081] For convenience, the circuit layer 120 and the light emitting element layer 190 are described separately below, but the present disclosure is not limited thereto. For example, the circuit layer 120 and the light emitting element layer 190 may be integrated together.

[0082] The encapsulation layer 140 may cover the light emitting element layer 190, and may extend to the non-display area NA to contact the circuit layer 120. In an embodiment, the encapsulation layer 140 may have a multilayer structure including at least two inorganic encapsulation films (also referred to herein as inorganic encapsulation layers) overlapping each other and at least one organic encapsulation film (also referred to herein as organic encapsulation layer) interposed between the inorganic encapsulation films.

[0083] In an embodiment, the display panel 100 may be bent in the bending area BA. The bending area BA may be part of the sub area SBA and may be spaced apart from the main area MA.

[0084] The substrate 110 and the circuit layer 120 may be bent in the bending area BA corresponding to a partial section of the sub-area SBA. Accordingly, a bezel area that may be recognized as the non-display area NA by a user may be reduced or minimized.

[0085] Figure 4 is a plan view showing a display panel according to an embodiment. Figure 4 The display panel 100 is shown in an unbent and unfolded state.

[0086] Reference Figure 4 , the display panel 100 may include a main area MA and a sub-area SBA. The main area MA may include a display area DA and a non-display area NA. The sub-area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA.

[0087] The display area DA may be an area where a plurality of pixels PX are arranged. The pixels PX and wirings (or some of the wirings) connected to the pixels PX may be arranged in the display area DA.

[0088] The pixel PX may be provided on the circuit layer 120 (eg, referring to Figure 3 ) and the light emitting element layer 190 (for example, see Figure 3As an example, each pixel PX may include a circuit element disposed at (eg, in or on) the circuit layer 120 and a light emitting element (eg, in or on) the light emitting element layer 190. Figure 5 or Figure 6 A pixel circuit (e.g., a light emitting element EL) Figure 5 or Figure 6 Pixel circuit PCA).

[0089] The pixel PX may include at least two color sub-pixels SPX that emit light of different colors from each other. For example, the pixel PX may include a first color sub-pixel SPX1 for emitting light of a first color (e.g., red light), a second color sub-pixel SPX2 for emitting light of a second color (e.g., green light), and a third color sub-pixel SPX3 for emitting light of a third color (e.g., blue light).

[0090] At least one first color sub-pixel SPX1, at least one second color sub-pixel SPX2, and at least one third color sub-pixel SPX3 adjacent to each other may constitute a unit pixel PX (may be referred to herein as pixel PX for short). For example, one first color sub-pixel SPX1, two second color sub-pixels SPX2, and one third color sub-pixel SPX3 adjacent to each other may constitute a unit pixel PX. Each unit pixel PX may emit light of various suitable colors, including white light, by mixing the colors of light emitted from the sub-pixels SPX1, SPX2, and SPX3 constituting the unit pixel PX. In an embodiment, the first color sub-pixel SPX1 and the third color sub-pixel SPX3 may be alternately arranged in the first direction DR1 and / or the second direction DR2, and the second color sub-pixel SPX2 may be continuously and / or sequentially arranged in the first direction DR1. The types, shapes, and / or arrangement structures of the sub-pixels SPX1, SPX2, and SPX3 may be variously modified as needed or desired. In addition, the types, quantities, ratios, and / or arrangement structures of the sub-pixels SPX1 , SPX2 , and SPX3 constituting each unit pixel PX may also be variously modified as needed or desired.

[0091] The encapsulation layer 140 (eg, see Figure 3 ) may be disposed on the pixel PX. For example, the encapsulation layer 140 may be provided to cover the pixel PX at least in the display area DA, and a portion of the encapsulation layer 140 may extend into the non-display area NA.

[0092] The wiring may be provided in the circuit layer 120 and may be positioned in the display area DA and the non-display area NA. In addition, the wiring may also be positioned in the sub-area SBA. For example, the wiring may extend from the sub-area SBA through the non-display area NA to the display area DA.

[0093] The non-display area NA may be positioned around the display area DA (eg, positioned adjacent to the display area DA). For example, the non-display area NA may be an edge area of ​​the main area MA positioned outside the display area DA.

[0094] The non-display area NA may include a dam area DAMA spaced apart from the display area DA, a first non-display area NA1 between the display area DA and the dam area DAMA, and a second non-display area NA2 outside the dam area DAMA. The dam area DAMA may be an area where a dam is arranged around the display area DA (e.g., around the periphery of the display area DA). The second non-display area NA2 may include an inorganic encapsulation area IEA (also referred to as a "joining area") where the inorganic encapsulation layers of the encapsulation layer 140 are joined to each other.

[0095] The sub-area SBA may include a bank area BNKA, a driving circuit mounting area ICA, and a pad area PA sequentially arranged on one side of the main area MA. Wiring (or part of the wiring), bank, and pad PD may be arranged in the sub-area SBA. At least some of the wirings may extend into the main area MA and be connected to the pixel PX.

[0096] The bank area BNKA may be an area where a bank including at least one organic layer is arranged. In an embodiment, the bank area BNKA may include a bending area BA. For example, the bank area BNKA may include a bending area BA spaced apart from the main area MA and a first edge area BEA1 and a second edge area BEA2 positioned on both sides (e.g., opposite sides) of the bending area BA in the first direction DR1. The bank may be provided in the bending area BA and in a peripheral area of ​​the bending area BA (e.g., the first edge area BEA1 and the second edge area BEA2 of the bank area BNKA) to cover a wiring passing through the bending area BA. The display panel 100 may be bent in the bending area BA so that a portion of the sub-area SBA may be positioned behind (e.g., below) the main area MA.

[0097] The driving circuit mounting area ICA may be an area where the driver 200 is arranged. Pads for connecting at least some of the wirings to the driver 200 may be arranged in the driving circuit mounting area ICA. For example, in the driving circuit mounting area ICA, input pads for connecting the driver 200 to specific pads (e.g., data input pads) of the pad area PA and output pads for connecting the driver 200 to the pixels PX may be arranged.

[0098] In some embodiments, the driver 200 may not be disposed on the display panel 100. In this case, the display panel 100 may not include the driving circuit mounting area ICA, and wirings may be disposed (eg, only wirings) in an area between the bank area BNKA and the pad area PA.

[0099] The pad area PA may be a region where a display panel 100 and / or a driver 200 is connected to a circuit board 300 (eg, referring to FIG. 1 ). Figure 3 ) and the like. The circuit board 300 may be arranged or bonded on the pad area PA.

[0100] A plurality of pads PD including power pads and signal pads connected to the pixels PX, the driver 200, and / or the embedded circuit may be arranged in the pad area PA. A power voltage for driving the pixels PX, the driver 200, and / or the embedded circuit, etc. may be supplied to the power pads. A driving signal and / or image data for driving the pixels PX, the driver 200, and / or the embedded circuit, etc. may be supplied to the signal pads. The type, position, arrangement order, and / or number of the pads PD may be variously modified as needed or desired.

[0101] Figure 5 is a pixel circuit diagram of a sub-pixel according to an embodiment. Figure 6 is a pixel circuit diagram of a sub-pixel according to an embodiment.

[0102] Figure 5 and Figure 6 Various embodiments related to the pixel circuit PCA and the wiring connected to the pixel circuit PCA are shown. The configuration of the pixel circuit PCA and the kind and number of wiring connected to the pixel circuit PCA may be variously modified as needed or desired.

[0103] Figure 5 1 shows an embodiment in which the pixel circuit (eg, each pixel circuit) PCA includes a first transistor T1 to a seventh transistor T7. In the embodiment, the pixel circuit (eg, each pixel circuit) PCA includes a first transistor T1 to a seventh transistor T7. Figure 5 The scan lines SL of the sub-pixel SPX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fourth scan line SL4. Figure 5 The power line PL of the sub-pixel SPX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL, and a second initialization power line VAIL. Figure 5 The sub-pixel SPX may also be connected to an emission control line ECL.

[0104] Figure 6 1 shows an embodiment in which the pixel circuit (eg, each pixel circuit) PCA includes a first transistor T1 to an eighth transistor T8. In the embodiment, the pixel circuit (eg, each pixel circuit) PCA includes a first transistor T1 to an eighth transistor T8. Figure 6 The scan lines SL of the sub-pixel SPX may include a first scan line SL1, a second scan line SL2, a third scan line SL3, and a fifth scan line SL5. Figure 6The power lines PL of the sub-pixel SPX may include a first pixel power line VDL, a second pixel power line VSL, a first initialization power line VIL, a second initialization power line VAIL, and a bias power line VOBL. Figure 6 The sub-pixel SPX may also be connected to an emission control line ECL.

[0105] Reference Figure 5 , the sub-pixel SPX may include a light emitting unit (eg, light emitting device) EMU including at least one light emitting element EL and a pixel circuit PCA (also referred to as a “pixel driver”) connected to the light emitting unit EMU.

[0106] The light emitting element EL may be connected between the pixel circuit PCA and the second pixel power line VSL to which the second pixel power voltage ELVSS is applied. In an embodiment, the second pixel power voltage ELVSS may be a low potential pixel driving voltage. Figure 4 ) can emit light in response to the driving current supplied from the pixel circuit PCA.

[0107] The light emitting element EL may be an organic light emitting diode, but the present disclosure is not limited thereto. For example, the light emitting element EL may be an inorganic light emitting element, a quantum dot light emitting element, or another light emitting element.

[0108] The pixel circuit PCA can control the light emission timing and brightness of the light emitting element EL by controlling the driving current supplied to the light emitting element EL. The pixel circuit PCA may include at least one pixel transistor T and a capacitor Cst. In an embodiment, the pixel circuit PCA may include a plurality of pixel transistors T including a first transistor T1 to a seventh transistor T7.

[0109] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode electrically connected to the first pixel power line VDL through a fifth transistor T5, and a second electrode electrically connected to the light emitting unit EMU through a sixth transistor T6. One of the first electrode and the second electrode may be a source electrode, and the other may be a drain electrode. The first transistor T1 may control a source-drain current (hereinafter referred to as a "driving current") flowing between the first electrode and the second electrode according to a voltage applied to the gate electrode (e.g., a voltage of the first node N1 corresponding to a voltage of a data signal). For example, the first transistor T1 may be a driving transistor of the sub-pixel SPX.

[0110] The second transistor T2 may include a gate electrode connected to the first scan line SL1, a first electrode connected to the data line DL, and a second electrode connected to the first electrode of the first transistor T1. The second transistor T2 may be turned on by a first scan signal supplied to the first scan line SL1 to electrically connect the first electrode of the first transistor T1 to the data line DL. When the second transistor T2 is turned on, a voltage of a data signal supplied to the data line DL may be applied to the first electrode of the first transistor T1.

[0111] The third transistor T3 may include a gate electrode connected to the second scan line SL2, a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the gate electrode (or the first node N1) of the first transistor T1. The third transistor T3 may be turned on by the second scan signal supplied to the second scan line SL2 to electrically connect the gate electrode of the first transistor T1 to the second electrode. When the third transistor T3 is turned on, the first transistor T1 may be driven as a diode, or in other words, the first transistor T1 may be diode-connected by the third transistor T3.

[0112] The fourth transistor T4 may include a gate electrode connected to the third scan line SL3, a first electrode connected to the gate electrode of the first transistor T1, and a second electrode connected to the first initialization power line VIL. The fourth transistor T4 may be turned on by the third scan signal supplied to the third scan line SL3 to electrically connect the gate electrode of the first transistor T1 to the first initialization power line VIL. When the fourth transistor T4 is turned on, a first initialization voltage VINT (e.g., a gate initialization voltage) of the first initialization power line VIL may be applied to the gate electrode of the first transistor T1.

[0113] The fifth transistor T5 may include a gate electrode connected to the emission control line ECL, a first electrode connected to the first pixel power line VDL, and a second electrode connected to the first electrode of the first transistor T1. The fifth transistor T5 may be turned on by the emission control signal supplied to the emission control line ECL, and thus may electrically connect the first electrode of the first transistor T1 to the first pixel power line VDL to which the first pixel power voltage ELVDD is applied. When the fifth transistor T5 is turned on, the first pixel power voltage ELVDD may be applied to the first electrode of the first transistor T1. In an embodiment, the first pixel power voltage ELVDD may be a high potential pixel driving voltage.

[0114] The sixth transistor T6 may include a gate electrode connected to an emission control line ECL, a first electrode connected to a second electrode of the first transistor T1, and a second electrode connected to the light emitting element EL. The sixth transistor T6 may be turned on by an emission control signal supplied to the emission control line ECL to electrically connect the first transistor T1 to the light emitting element EL. When all of the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current having a magnitude corresponding to a voltage of the gate electrode of the first transistor T1 may flow through the light emitting element EL.

[0115] The seventh transistor T7 may include a gate electrode connected to the fourth scan line SL4, a first electrode connected to the anode electrode of the light emitting element EL, and a second electrode connected to the second initialization power line VAIL. The seventh transistor T7 may be turned on by the fourth scan signal supplied to the fourth scan line SL4 to electrically connect the anode electrode of the light emitting element EL to the second initialization power line VAIL. The fourth scan signal may be the same signal as the first scan signal or a different signal. When the seventh transistor T7 is turned on, a second initialization voltage VAINT (e.g., an anode initialization voltage) of the second initialization power line VAIL may be applied to the anode electrode of the light emitting element EL.

[0116] The capacitor Cst may be connected between the gate electrode of the first transistor T1 and the first pixel power line VDL. The capacitor Cst may be charged with a voltage corresponding to a voltage of a data signal applied to the gate electrode of the first transistor T1.

[0117] The active layer (e.g., semiconductor pattern including the channel region) of each of the plurality of pixel transistors T (e.g., the first transistor T1 to the seventh transistor T7) may include one semiconductor material among polycrystalline silicon, amorphous silicon, and an oxide semiconductor. In an embodiment, some of the plurality of pixel transistors T and others of the plurality of pixel transistors T may be formed by transistors of different conductivity types from each other. In addition, some of the plurality of pixel transistors T and others of the plurality of pixel transistors T may include semiconductor materials of different types from each other.

[0118] For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed by a P-type transistor (e.g., a P-type MOSFET) including an active layer formed of polysilicon, and the third transistor T3 and the fourth transistor T4 may be formed by an N-type transistor (e.g., an N-type MOSFET) including an active layer formed of an oxide semiconductor. In an embodiment, the transistor including an active layer formed of polysilicon and the transistor including an active layer formed of an oxide semiconductor may be arranged at different layers (e.g., in the middle or on) in the circuit layer 120.

[0119] Apart from Figure 5 In addition, refer to Figure 6 , the pixel circuit PCA may further include an eighth transistor T8. The eighth transistor T8 may include a gate electrode connected to the fifth scan line SL5, a first electrode connected to the bias power line VOBL, and a second electrode connected to the first electrode of the first transistor T1. The eighth transistor T8 may be turned on by the fifth scan signal supplied to the fifth scan line SL5 to electrically connect the first electrode of the first transistor T1 to the bias power line VOBL. When the eighth transistor T8 is turned on, the bias voltage VOBS supplied to the bias power line VOBL may be applied to the first electrode of the first transistor T1. In an embodiment, the bias voltage VOBS may have a voltage level suitable for compensating for the hysteresis characteristic of the first transistor T1. When the eighth transistor T8 is turned on, the first electrode of the first transistor T1 may be initialized to the bias voltage VOBS.

[0120] exist Figure 6 In the embodiment shown in , the gate electrode of the seventh transistor T7 may be connected to the fifth scan line SL5. Accordingly, the seventh transistor T7 may be turned on by the fifth scan signal supplied to the fifth scan line SL5 to connect the anode electrode of the light emitting element EL to the second initialization power line VAIL.

[0121] Figure 7 is a plan view showing the arrangement of a plurality of pixel circuits arranged in a display area of ​​a display device according to the embodiment. Figure 8 It is shown that the arrangement Figure 7 A plan view of a pixel circuit in a unit pixel area.

[0122] Reference Figure 7 and Figure 8 , the display device 10 (for example, referring to Figure 1 ) may include a plurality of pixel circuits PXC (e.g., pixel circuits PXC1, PXC2, PXC3, and PXC4) arranged in the display area DA. Each of the plurality of pixel circuits PXC may be electrically connected to a plurality of pixel circuits PXC included in sub-pixels SPX1, SPX2, and SPX3 (e.g., refer to Figure 4 ) in the light emitting element EL (for example, see Figure 5 or Figure 6 ). A plurality of circuit elements included in the pixel circuit PXC may be applied with an electrical signal to cause the light emitting element EL to emit light.

[0123] A plurality of pixel circuits PXC may be arranged in the first direction DR1 and the second direction DR2. For example, two pixel circuits PXC adjacent to each other in the second direction DR2 may constitute one unit pixel region UPX (e.g., unit pixel regions UPX1, UPX2, UPX3, and UPX4), and the plurality of unit pixel regions UPX may be arranged in the first direction DR1 and the second direction DR2. The first pixel circuit PXC1 and the second pixel circuit PXC2 adjacent to each other in the second direction DR2 may constitute one first unit pixel region UPX1. The third pixel circuit PXC3 and the fourth pixel circuit PXC4 adjacent to each other in the second direction DR2 may constitute one second unit pixel region UPX2. The first unit pixel region UPX1 and the second unit pixel region UPX2 may be arranged in the first direction DR1. Each of the third unit pixel region UPX3 and the fourth unit pixel region UPX4 may include two pixel circuits adjacent to each other in the second direction DR2, and the third unit pixel region UPX3 and the fourth unit pixel region UPX4 may be arranged in the first direction DR1. The first and second unit pixel regions UPX1 and UPX2 may be arranged in the second direction DR2 with respect to the third and fourth unit pixel regions UPX3 and UPX4 , respectively.

[0124] A plurality of wirings, conductive patterns, and semiconductor layers constituting a pixel circuit may repeat the same pattern with respect to one unit pixel region UPX, rather than repeating the same pattern with respect to the pixel circuit. For example, the arrangement structure of the wirings, conductive patterns, and semiconductor layers of the first unit pixel region UPX1 may have the same or substantially the same arrangement structure in the second unit pixel region UPX2, the third unit pixel region UPX3, and the fourth unit pixel region UPX4. The first pixel circuit PXC1 and the second pixel circuit PXC2 may have a symmetrical or substantially symmetrical structure in the arrangement of the conductive patterns and the semiconductor layers, and the conductive patterns and semiconductor layers constituting the two pixel circuits PXC1 and PXC2 may be repeatedly arranged over the entire surface of the display area DA.

[0125] According to an embodiment, the display device 10 may include a valley portion VA arranged to surround a unit pixel region UPX (e.g., around the periphery of the unit pixel region UPX). The valley portion VA may surround one unit pixel region UPX (e.g., around the periphery of one unit pixel region UPX), and may surround a plurality of unit pixel regions UPX (e.g., around the periphery of a plurality of unit pixel regions UPX) over the entire surface of the display region DA. The valley portion VA may be arranged to extend in a first direction DR1 and a second direction DR2, and two pixel circuits PXC may be arranged in an area surrounded by the valley portion VA by crossing or intersecting each other. A plurality of unit pixel regions UPX may be arranged to be spaced apart from each other with the valley portion VA arranged therebetween, and may be isolated in an area surrounded by the valley portion VA.

[0126] The valley portion VA may be formed to penetrate a plurality of conductive layers constituting the pixel circuit PXC and an interlayer insulating layer disposed between semiconductor layers. The valley portion VA may prevent an external impact applied to the display device 10 from being transmitted to elements of the pixel circuit PXC. In addition, the display device 10 may include the valley portion VA surrounding an area where the pixel circuit PXC is disposed so that when the flexible substrate 110 (e.g., referring to FIG. 1 ) is included, the valley portion VA may be formed to penetrate a plurality of conductive layers constituting the pixel circuit PXC and an interlayer insulating layer disposed between semiconductor layers. The valley portion VA may prevent an external impact applied to the display device 10 from being transmitted to elements of the pixel circuit PXC. Figure 3 ) can prevent or substantially prevent cracks that may be formed in multiple insulating layers when the display device 10 is folded.

[0127] According to an embodiment, the display device 10 may further include a plurality of stacked structures VPL arranged in the valley portion VA. The stacked structure VPL may be a structure in which a plurality of conductive layers and semiconductor layers constituting the pixel circuit PXC and at least one of the insulating layers arranged therebetween are stacked. The stacked structure VPL may be arranged in the valley portion VA to protect the circuit elements from external impact. An impact applied to the display device 10 may be absorbed by the valley portion VA and / or the stacked structure VPL surrounding the pixel circuit PXC.

[0128] Figure 8 It is shown that a plurality of stacked structures VPL are arranged in the portion of the valley portion VA extending in the first direction DR1, the portion of the valley portion VA extending in the second direction DR2, and the region where these portions intersect or intersect each other, so that each unit pixel region UPX is arranged with eight stacked structures VPL. However, the present disclosure is not limited to this. Each unit pixel region UPX may be arranged with a greater or lesser number of stacked structures VPL. Since the stacked structure VPL has a structure in which a conductive layer and / or a semiconductor layer constituting a pixel circuit PXC is stacked, the position and / or number of the stacked structures VPL may be variously modified according to the arrangement structure of the pixel circuit PXC. The structures of the display device 10, the valley portion VA, and the stacked structures VPL will be described in more detail below with reference to other drawings.

[0129] Fig. 9 is along Figure 8 A cross-sectional view taken along line IX-IX'. Fig. 9 A cross section of a portion of the display area DA corresponding to an area where one unit pixel area UPX is arranged and positioned is schematically shown. Fig. 9 A cross section crossing portions of the first pixel circuit PXC1 and the second pixel circuit PXC2 adjacent to each other in the second direction DR2 is shown.

[0130] Reference Fig. 9 , the display panel 100 (for example, see Figure 3 ) may include a substrate 110, a circuit layer 120 disposed on the substrate 110, a light emitting element layer 190, and an encapsulation layer 140. The circuit layer 120, the light emitting element layer 190, and the encapsulation layer 140 may be sequentially arranged or stacked on the substrate 110 along the third direction DR3.

[0131] The substrate 110 may include (eg, may be made of) a suitable material having flexible properties capable of bending, folding, etc. The substrate 110 may be formed of an insulating material such as a polymer resin. For example, the substrate 110 may be made of polyimide.

[0132] The circuit layer 120 may include a pixel circuit PXC and wiring. For example, the circuit layer 120 may include a circuit for each sub-pixel SPX (eg, referring to Figure 4 ) constituting the pixel circuit PXC (eg, the pixel transistor T and the capacitor Cst) and wiring electrically connected to the sub-pixel SPX (eg, including Figure 5 or Figure 6 Various power lines and signal lines such as the power line PL, the scan line SL, the emission control line ECL and the data line DL shown in FIG.

[0133] Among the elements that may be provided at (eg, in or on) the circuit layer 120, Fig. 9 1 and 2 show a first thin film transistor TFT1 (also referred to as a "first pixel transistor"), a second thin film transistor TFT2 (also referred to as a "second pixel transistor"), and a capacitor Cst included in a pixel circuit PXC of a corresponding sub-pixel SPX. The first thin film transistor TFT1 may be a first type transistor (e.g., a P-type transistor) including a first semiconductor material (e.g., polysilicon) among pixel transistors T constituting the pixel circuit PXC. For example, the first thin film transistor TFT1 may be Figure 5 and Figure 6 One of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 shown in FIG. Fig. 9A transistor (eg, a first connection electrode CNE1 and a second connection electrode CNE2) is shown as an example of a first thin film transistor TFT1 among first type transistors connected to the light emitting element EL through at least one connection electrode (eg, a first connection electrode CNE1 and a second connection electrode CNE2). Figure 5 or Figure 6 The second thin film transistor TFT2 may be a second type transistor (eg, an N-type transistor) including a second semiconductor material (eg, an oxide semiconductor) among the pixel transistors T. For example, the second thin film transistor TFT2 may be as follows: Figure 5 and Figure 6 One of the third transistor T3 and the fourth transistor T4 shown in FIG.

[0134] The cross-section of the subpixel SPX may be variously modified according to the type and / or structure of each of the subpixels SPX and the display panel 100 including the subpixel SPX. For example, the positions and formation order of the first thin film transistor TFT1, the second thin film transistor TFT2 and the capacitor Cst may be variously modified as needed or desired.

[0135] The circuit layer 120 may include a semiconductor layer, a conductive layer, and an insulating layer arranged between and / or around the conductive layer and the semiconductor layer for forming circuit elements, wiring, or the like. For example, the circuit layer 120 may include a first semiconductor layer SCL1 (e.g., a polysilicon semiconductor layer), a first insulating layer 123 (e.g., a first gate insulating layer), a first conductive layer CDL1 (e.g., a first gate conductive layer), a second insulating layer 124 (e.g., a second gate insulating layer), a second conductive layer CDL2 (e.g., a second gate conductive layer), a third insulating layer 125 (e.g., a first interlayer insulating layer), a second semiconductor layer SCL2 (e.g., an oxide semiconductor layer), a fourth insulating layer 126 (e.g., a third gate insulating layer), a third conductive layer CDL3 (e.g., a third gate conductive layer), a fifth insulating layer 127 (e.g., a second interlayer insulating layer), a fourth conductive layer CDL4 (e.g., a first source-drain conductive layer), and a sixth insulating layer 128 (e.g., a first through-hole layer or a first planarization layer) which may be sequentially arranged on the substrate 110 relative to the third direction DR3. In an embodiment, the circuit layer 120 may further include a fifth conductive layer CDL5 (e.g., a second source-drain conductive layer) and a seventh insulating layer 129 (e.g., a second via layer or a second planarization layer) sequentially disposed on the sixth insulating layer 128. In an embodiment, the circuit layer 120 may further include a lower conductive layer BCDL disposed between the substrate 110 and the first semiconductor layer SCL1, a barrier layer 121 disposed between the substrate 110 and the lower conductive layer BCDL, and a buffer layer 122 disposed between the lower conductive layer BCDL and the first semiconductor layer SCL1.

[0136] The barrier layer 121 may be disposed on the substrate 110. The barrier layer 121 may protect the elements disposed at (e.g., in or on) the circuit layer 120 and the light emitting element layer 190 from moisture that penetrates through the substrate 110 that may be easily permeated with moisture. The barrier layer 121 may include at least one inorganic layer containing an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another suitable inorganic insulating material). The material of the barrier layer 121 may be variously modified as needed or desired.

[0137] The lower conductive layer BCDL may be disposed on the barrier layer 121. The lower conductive layer BCDL may include a lower metal layer BML overlapping an active layer (eg, first active layer ACT1 and / or second active layer ACT2) of at least one pixel transistor T and / or at least one wiring (or a portion of at least one wiring). Fig. 9 The lower metal layer BML is shown to be arranged to overlap with the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst (e.g., only overlap with the first active layer ACT1 of the first thin film transistor TFT1 and the capacitor electrodes CAE1 and CAE2 of the capacitor Cst), but the present disclosure is not limited thereto. For example, the lower metal layer BML may be patterned into an appropriate size and / or shape as needed or desired, and may be arranged on a portion of the pixel circuit PXC or may be arranged on the entire surface of the pixel circuit PXC. For example, the lower metal layer BML may be arranged to overlap with only a portion of the unit pixel area. Figure 5 and Figure 6 In an embodiment, the lower metal layer BML may also be used as a light blocking pattern and / or a back gate electrode of at least one pixel transistor T, or the like.

[0138] The buffer layer 122 may be disposed on the lower conductive layer BCDL to cover the lower conductive layer BCDL. The buffer layer 122 may include at least one inorganic layer including an inorganic insulating material.

[0139] The first thin film transistor TFT1, the second thin film transistor TFT2, and the capacitor Cst may be arranged on one surface of the substrate 110 including the buffer layer 122. The first thin film transistor TFT1 may include a first active layer ACT1 and a first gate electrode G1. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2. In an embodiment, the second thin film transistor TFT2 may include a back gate electrode BG. The capacitor Cst may include a first capacitor electrode CAE1 and a second capacitor electrode CAE2.

[0140] The first semiconductor layer SCL1 may be disposed on the buffer layer 122. The first semiconductor layer SCL1 may include a first active layer ACT1 of the first thin film transistor TFT1. For example, the first semiconductor layer SCL1 may include a first active layer ACT1 of each of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0141] The first active layer ACT1 may be provided at (e.g., in or on) the first semiconductor layer SCL1 and may include a first semiconductor material (e.g., polysilicon). The first active layer ACT1 may include a first channel region CH1, a first source region S1, and a first drain region D1. The first channel region CH1 may overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 may be arranged on one side of the first channel region CH1, and the first drain region D1 may be arranged on the other side of the first channel region CH1. The first source region S1 and the first drain region D1 may be regions formed to have conductivity by doping ions or impurities into a semiconductor used to form the first active layer ACT1. In an embodiment, the first source region S1 may be a source electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate source electrode connected to the first source region S1. In an embodiment, the first drain region D1 may be a drain electrode of the first thin film transistor TFT1. In another embodiment, the first thin film transistor TFT1 may include a separate drain electrode connected to the first drain region D1.

[0142] The first insulating layer 123 may be disposed on the first semiconductor layer SCL1. The first insulating layer 123 may cover the first semiconductor layer SCL1.

[0143] The first conductive layer CDL1 may be arranged on the first insulating layer 123. The first conductive layer CDL1 may include a first gate electrode G1 of the first thin film transistor TFT1. The first gate electrode G1 may be arranged to overlap a portion of the first active layer ACT1 (e.g., with the first channel region CH1). In an embodiment, the first conductive layer CDL1 may further include at least one wiring (or a portion of at least one wiring), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode. For example, the first conductive layer CDL1 may further include a first capacitor electrode CAE1 of the capacitor Cst.

[0144] In an embodiment, the first capacitor electrode CAE1 may be integrally formed with (eg, formed together with) the gate electrode G1 of at least one first thin film transistor TFT1. Figure 5 and Figure 6For example, the first capacitor electrode CAE1 and the gate electrode of the first transistor T1 may be formed as one conductive pattern, and the second capacitor electrode CAE2 may be arranged to overlap the conductive pattern.

[0145] The second insulating layer 124 may be disposed on the first conductive layer CDL1. The second insulating layer 124 may cover the first conductive layer CDL1.

[0146] The second conductive layer CDL2 may be arranged on the second insulating layer 124. For example, the second conductive layer CDL2 may include one electrode of the capacitor Cst, such as the second capacitor electrode CAE2. In an embodiment, the second conductive layer CDL2 may further include at least one electrode, a wiring (or a portion of at least one wiring) and / or a metal pattern (e.g., a bridge pattern). For example, the second conductive layer CDL2 may further include a back gate electrode BG connected to the second gate electrode G2 of the second thin film transistor TFT2.

[0147] The third insulating layer 125 may be disposed on the second conductive layer CDL2. The third insulating layer 125 may cover the second conductive layer CDL2.

[0148] The second semiconductor layer SCL2 may be disposed on the third insulating layer 125. The second semiconductor layer SCL2 may include a second active layer ACT2 of the second thin film transistor TFT2. For example, the second semiconductor layer SCL2 may include a second active layer ACT2 of each of the third transistor T3 and the fourth transistor T4.

[0149] The second active layer ACT2 may be provided at (e.g., in or on) the second semiconductor layer SCL2, and may include a second semiconductor material (e.g., an oxide semiconductor) different from the first semiconductor material. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0150] The second active layer ACT2 may include a second channel region CH2, a second source region S2, and a second drain region D2. The second channel region CH2 may overlap with the second gate electrode G2 in the third direction DR3. The second source region S2 may be arranged on one side of the second channel region CH2, and the second drain region D2 may be arranged on the other side of the second channel region CH2. The second source region S2 and the second drain region D2 may be conductive regions by doping ions or impurities into the semiconductor used to form the second active layer ACT2. In an embodiment, the second source region S2 may be a source electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate source electrode connected to the second source region S2. In an embodiment, the second drain region D2 may be a drain electrode of the second thin film transistor TFT2. In another embodiment, the second thin film transistor TFT2 may include a separate drain electrode connected to the second drain region D2.

[0151] The fourth insulating layer 126 may be disposed on the second semiconductor layer SCL2. The fourth insulating layer 126 may cover the second semiconductor layer SCL2.

[0152] The third conductive layer CDL3 may be disposed on the fourth insulating layer 126. The third conductive layer CDL3 may include a second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be arranged to overlap a portion of the second active layer ACT2 (e.g., with the second channel region CH2). In an embodiment, the third conductive layer CDL3 may further include at least one wiring (or a portion of at least one wiring), a metal pattern (e.g., a bridge pattern), and / or a capacitor electrode.

[0153] In an embodiment, each of the electrodes, conductive patterns, and wirings provided at (e.g., in the middle or on) the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include a conductive material (e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), at least one of other metals, any suitable alloy thereof, or other suitable conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and wirings provided in the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include molybdenum (Mo) or other suitable metal materials. At least two conductive layers among the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 may include the same material as each other, or may include materials different from each other. The material of each of the lower conductive layer BCDL, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 is not particularly limited and may be variously modified as needed or desired.

[0154] The fifth insulating layer 127 may be disposed on the third conductive layer CDL3. The fifth insulating layer 127 may cover the third conductive layer CDL3.

[0155] In an embodiment, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be an inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another suitable inorganic insulating material), and each may have a single-layer or multi-layer structure. At least two insulating layers among the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may include the same material as each other, or may include materials different from each other. The material of each of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 may be variously modified as needed or desired.

[0156] The fourth conductive layer CDL4 may be disposed on the fifth insulating layer 127. The fourth conductive layer CDL4 may include a first connection electrode CNE1 (or a drain electrode of the first thin film transistor TFT1), a first bridge electrode BE1 (or a source electrode of the second thin film transistor TFT2), and a second bridge electrode BE2 (or a drain electrode of the second thin film transistor TFT2). The first connection electrode CNE1 may be provided at (e.g., in or on) the fourth conductive layer CDL4 and may be connected to the first drain region D1 of the first active layer ACT1 through a first contact hole CT1 penetrating the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The first bridge electrode BE1 may be provided at (e.g., in or on) the fourth conductive layer CDL4 and may be connected to the second source region S2 of the second active layer ACT2 through a second contact hole CT2 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. The second bridging electrode BE2 may be connected to the second drain region D2 of the second active layer ACT2 through the third contact hole CT3 penetrating the fourth insulating layer 126 and the fifth insulating layer 127. In an embodiment, the fourth conductive layer CDL4 may further include at least one wiring (or a portion of at least one wiring) and / or a metal pattern (e.g., a bridging pattern). For example, the fourth conductive layer CDL4 may include a power line PL (e.g., a power line PL provided inside and / or outside the display area DA) Figure 5 and Figure 6 Part of the first pixel power line VDL and / or the second pixel power line VSL) shown in FIG.

[0157] The valley portion VA may be formed to penetrate at least some of the plurality of insulating layers disposed on the barrier layer 121. For example, the valley portion VA may penetrate at least some of the buffer layer 122, the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The valley portion VA may penetrate at least some of the plurality of insulating layers overlapping the first thin film transistor TFT1 and the second thin film transistor TFT2. The valley portion VA may have a maximum depth when formed to penetrate the buffer layer 122 and all of the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. The valley portion VA may be formed not to penetrate the semiconductor layers SCL1 and SCL2 and the conductive layers CDL1, CDL2, and CDL3 disposed between the buffer layer 122 and the fifth insulating layer 127. Among the valley portions VA, the valley portions VA formed on portions overlapping the semiconductor layers SCL1 and SCL2 and the conductive layers CDL1 , CDL2 , CDL3 , and CDL4 may have a smaller depth. Fig. 9 A portion is shown penetrating all of the valley portions VA in the buffer layer 122 and the first, second, third, fourth, and fifth insulating layers 123, 124, 125, 126, and 127. However, the valley portion VA may overlap at least one of the semiconductor layers SCL1 and SCL2 and / or at least one of the conductive layers CDL1, CDL2, and CDL3 depending on its position, and in this case, its depth may be relatively small.

[0158] The stack structure VPL may be disposed within the valley portion VA. The stack structure VPL may have a structure in which one or more patterns disposed at the same layer (eg, in or above) as a layer in the lower conductive layer BCDL to the fifth insulating layer 127 are stacked on each other.

[0159] Fig.10 is a cross-sectional view illustrating a second thin film transistor, a valley portion, and a stack structure of a display device according to an embodiment.

[0160] Apart from Fig. 9 In addition, refer to Fig.10In the display device 10 according to the embodiment, the stacked structure VPL may include a plurality of patterns arranged at the same layer (e.g., in or above) as the lower conductive layer BCDL, the first semiconductor layer SCL1, the second semiconductor layer SCL2, the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3, the buffer layer 122, and the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127. For example, the stacked structure VPL may include a first metal pattern ML1 arranged at the same layer (e.g., in or above) as the lower conductive layer BCDL, a second metal pattern ML2 arranged at the same layer (e.g., in or above) as the first conductive layer CDL1, a third metal pattern ML3 arranged at the same layer (e.g., in or above) as the second conductive layer CDL2, and a fourth metal pattern ML4 arranged at the same layer (e.g., in or above) as the third conductive layer CDL3. In addition, the stacked structure VPL may include a first semiconductor pattern AL1 disposed at the same layer as that of the first semiconductor layer SCL1 (e.g., in the middle or on top) and a second semiconductor pattern AL2 disposed at the same layer as that of the second semiconductor layer SCL2 (e.g., in the middle or on top). In addition, the stacked structure VPL may further include a first insulating pattern IP1 disposed at the same layer as that of the buffer layer 122 (e.g., in the middle or on top) and a second insulating pattern IP2, a third insulating pattern IP3, a fourth insulating pattern IP4, a fifth insulating pattern IP5, and a sixth insulating pattern IP6 disposed at the same layer as that of the first to fifth insulating layers 123 to 127 (e.g., in the middle or on top).

[0161] The stacking order of each layer of the stacked structure VPL may be the same as the stacking order from the lower conductive layer BCDL to the fifth insulating layer 127. For example, the stacked structure VPL may have a structure in which a first metal pattern ML1, a first insulating pattern IP1, a first semiconductor pattern AL1, a second insulating pattern IP2, a second metal pattern ML2, a third insulating pattern IP3, a third metal pattern ML3, a fourth insulating pattern IP4, a second semiconductor pattern AL2, a fifth insulating pattern IP5, a fourth metal pattern ML4, and a sixth insulating pattern IP6 are sequentially stacked. Fig.10 A case is shown in which the stacked structure VPL includes all of the patterns arranged at the same layer (eg, middle or upper) as the layers from the lower conductive layer BCDL to the fifth insulating layer 127, but the present disclosure is not limited thereto. The stacked structure VPL may be formed with some of the stacked layers.

[0162] The plurality of patterns included in the stacked structure VPL may be portions remaining after patterning in a formation process of the same layer as the layers of the plurality of patterns. For example, when semiconductor layers, conductive layers, and wirings constituting circuit elements are formed in a formation process of the lower conductive layer BCDL, the first semiconductor layer SCL1, and the second semiconductor layer SCL2, and the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3, the plurality of patterns of the stacked structure VPL may be formed therewith. In addition, in a process of forming the valley portion VA, portions of the buffer layer 122 and the first insulating layer 123, the second insulating layer 124, the third insulating layer 125, the fourth insulating layer 126, and the fifth insulating layer 127 that overlap with the pattern may be stacked together without being removed to form the stacked structure VPL.

[0163] According to an embodiment, the display device 10 may have a height H2 of the stacked structure VPL higher than a height H1 of a position where the second active layer ACT2 including an oxide semiconductor is arranged, where the second thin film transistor TFT2 is arranged. The stacked structure VPL together with the valley portion VA may prevent or substantially prevent an external impact from being transmitted to a circuit element of the pixel circuit PXC. Thus, the stacked structure VPL may be formed to be at least higher than a position where the first thin film transistor TFT1 and the second thin film transistor TFT2 of the pixel circuit PXC are arranged, so that the first thin film transistor TFT1 and the second thin film transistor TFT2 may be prevented or substantially prevented from being damaged by an impact. Since the second thin film transistor TFT2 is arranged at a position higher than the position of the first thin film transistor TFT1, the height H2 of the stacked structure VPL may be at least greater than a height H1 of a position where the second active layer ACT2 of the second thin film transistor TFT2 is arranged. Each of the height H2 of the stacked structure VPL and the height H1 of the position where the second active layer ACT2 is arranged may be a height measured from the top surface of the barrier layer 121 or the top surface of the substrate 110 in the third direction DR3.

[0164] As described above, the depth H3 of the valley portion VA may vary depending on whether the valley portion VA overlaps the conductive layer or the semiconductor layer. However, the maximum depth H3 of the valley portion VA may be the depth of the portion that does not overlap the conductive layer or the semiconductor layer, and penetrates from the buffer layer 122 all the way to the fifth insulating layer 127. The maximum depth H3 of the valley portion VA may be greater than the height H1 of the position where the second active layer ACT2 of the second thin film transistor TFT2 is arranged, so that the valley portion VA can absorb the impact that may be applied to the circuit elements of the pixel circuit PXC.

[0165] In addition, the height H2 of the stacked structure VPL may be greater than the maximum depth H3 of the valley portion VA, but the present disclosure is not limited thereto. The height H2 of the stacked structure VPL may vary depending on the number of stacked patterns, and therefore, may be independent of the maximum depth H3 of the valley portion VA. However, as described above, the height H2 of the stacked structure VPL may be at least greater than the height H1 of the position where the second active layer ACT2 of the second thin film transistor TFT2 is arranged.

[0166] The sixth insulating layer 128 may be disposed on the fourth conductive layer CDL4. The sixth insulating layer 128 may cover the fourth conductive layer CDL4. In addition, the sixth insulating layer 128 may fill the inside of the valley portion VA and may surround the stack structure VPL (eg, around the periphery of the stack structure VPL).

[0167] The fifth conductive layer CDL5 may be arranged on the sixth insulating layer 128. The fifth conductive layer CDL5 may include a second connection electrode CNE2. The second connection electrode CNE2 may be provided in the fifth conductive layer CDL5 and may be connected to the first connection electrode CNE1 through a fourth contact hole CT4 (e.g., a first through hole) penetrating the sixth insulating layer 128. In an embodiment, the fifth conductive layer CDL5 may further include at least one wiring (or a portion of at least one wiring) and / or a metal pattern (e.g., a bridge pattern). For example, the fifth conductive layer CDL5 may include a portion of a power line PL (e.g., a first pixel power line VDL and / or a second pixel power line VSL) provided inside and / or outside the display area DA.

[0168] In an embodiment, each of the electrodes, conductive patterns, and wirings provided at (e.g., in the middle or on) the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include a conductive material (e.g., molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), at least one of other suitable metals, suitable alloys thereof, or other suitable conductive materials), and may have a single-layer or multi-layer structure. For example, each of the electrodes, conductive patterns, and wirings provided at (e.g., in the middle or on) the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be formed by a three-layer structure of titanium / aluminum / titanium (Ti / Al / Ti). The fourth conductive layer CDL4 and the fifth conductive layer CDL5 may include the same material as each other, or may include different materials from each other. The material of each of the fourth conductive layer CDL4 and the fifth conductive layer CDL5 may be variously modified as needed or desired.

[0169] The seventh insulating layer 129 may be disposed on the fifth conductive layer CDL5. The seventh insulating layer 129 may cover the fifth conductive layer CDL5.

[0170] In an embodiment, the sixth insulating layer 128 and the seventh insulating layer 129 may be organic insulating layers including an organic insulating material (e.g., acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin or other suitable organic insulating material) to planarize or substantially planarize the circuit layer 120, and each may have a single-layer or multi-layer structure. The sixth insulating layer 128 and the seventh insulating layer 129 may include the same material as each other, or may include materials different from each other. The material of each of the sixth insulating layer 128 and the seventh insulating layer 129 may be variously modified as needed or desired.

[0171] The light emitting element layer 190 may include a pixel defining layer 131 dividing emission areas EA of the sub-pixels SPX and light emitting elements EL respectively positioned in the emission areas EA. In an embodiment, the light emitting element layer 190 may further include a spacer 132 disposed on a portion of the pixel defining layer 131 .

[0172] Each of the light emitting elements EL may include a first electrode ET1 (e.g., an anode electrode) connected to at least one pixel transistor T (e.g., a first thin film transistor TFT1) included in a corresponding sub-pixel SPX through a first connection electrode CNE1 and / or a second connection electrode CNE2, and a light emitting layer EML and a second electrode ET2 (e.g., a cathode electrode) sequentially arranged on the first electrode ET1. In an embodiment, the light emitting element EL may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) between the first electrode ET1 and the light emitting layer EML, and a second intermediate layer (e.g., an electron layer including an electron transport layer) between the light emitting layer EML and the second electrode ET2.

[0173] The first electrode ET1 of the light emitting element EL may include a conductive material and may be disposed on the circuit layer 120. For example, the first electrode ET1 may be disposed on the seventh insulating layer 129 to correspond to each emission area EA. The first electrode ET1 may be connected to the second connection electrode CNE2 through a fifth contact hole CT5 (e.g., a second through hole) penetrating the seventh insulating layer 129.

[0174] In an embodiment, the first electrode ET1 may include a metal material having a high reflectivity. For example, the first electrode ET1 may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), or aluminum (Al), or may have a structure including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and a multilayer structure of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au) or nickel (Ni) (e.g., ITO / Mg, ITO / MgF, ITO / Ag and / or ITO / Ag / ITO).

[0175] The light emitting layer EML of the light emitting element EL may include a polymer material or a low molecular material. In an embodiment, a light emitting layer EML may be arranged for each sub-pixel SPX, and the light emitting layer EML of each sub-pixel SPX may emit visible light of a color corresponding to the corresponding sub-pixel SPX. In another embodiment, the light emitting layer EML may be a common layer shared by sub-pixels SPX of different colors, and a wavelength conversion layer and / or a color filter corresponding to the color (or wavelength band) of light desired to be emitted from each sub-pixel SPX may be arranged in the emission area EA of at least some of the plurality of sub-pixels SPX.

[0176] The second electrode ET2 of the light emitting element EL includes a conductive material and may be connected to the second pixel power line VSL. In an embodiment, the second electrode ET2 may be a common layer formed across the entire display area DA to cover the light emitting layer EML and the pixel defining layer 131. In an embodiment, the second electrode ET2 may be formed of a transparent conductive material (TCO) capable of transmitting light (such as ITO or IZO) or a semi-transmissive conductive material (such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag)). When the second electrode ET2 includes a semi-transmissive conductive material (e.g., made of a semi-transmissive conductive material), an improvement in light output efficiency due to a microcavity effect may be provided.

[0177] The pixel defining layer 131 may have an opening for (e.g., corresponding to) each of the emission areas EA, and the pixel defining layer 131 may surround the emission area EA (e.g., around the periphery of the emission area EA). For example, the pixel defining layer 131 may be formed to cover the edge of the first electrode ET1 of the light emitting element EL, and may include an opening that exposes the remaining portion of the first electrode ET1. The region where the exposed first electrode ET1 and the light emitting layer EML overlap each other (or the region including the exposed first electrode ET1 and the light emitting layer EML) may be defined as the emission area EA of each sub-pixel SPX.

[0178] In an embodiment, the pixel defining layer 131 may include at least one organic layer including an organic insulating material. For example, the pixel defining layer 131 may include acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, benzocyclobutene (BCB) or other suitable organic insulating materials.

[0179] The spacer 132 may be arranged on a portion of the pixel defining layer 131. The spacer 132 may include at least one organic layer including an organic insulating material. The spacer 132 may include the same material as the material of the pixel defining layer 131, or may include a material different from the material of the pixel defining layer 131. In an embodiment, the pixel defining layer 131 and the spacer 132 may be sequentially formed by separate mask processes. In another embodiment, the pixel defining layer 131 and the spacer 132 may be formed synchronously or simultaneously using a halftone mask. In this case, the pixel defining layer 131 and the spacer 132 may be regarded as a single insulating layer integrated with each other. The organic insulating material constituting the spacer 132 is not particularly limited, and various modifications may be made as needed or desired.

[0180] The encapsulation layer 140 may be disposed on the light emitting element layer 190 in the main area MA. For example, the encapsulation layer 140 may be disposed in the display area DA and the non-display area NA to cover the light emitting element layer 190. The encapsulation layer 140 may block oxygen and / or moisture from penetrating into the light emitting element layer 190, and may reduce electrical or physical impacts on the circuit layer 120 and the light emitting element layer 190.

[0181] In an embodiment, the encapsulation layer 140 may include a first inorganic encapsulation layer 141, an organic encapsulation layer 142, and a second inorganic encapsulation layer 143 sequentially disposed on the light emitting element layer 190. The first and second inorganic encapsulation layers 141 and 143 may include inorganic materials, and the organic encapsulation layer 142 may include organic materials.

[0182] The display device 10 according to the embodiment includes a valley portion VA surrounding a region where a plurality of pixel circuits PXC are arranged (e.g., around the periphery of the region where the plurality of pixel circuits PXC are arranged) and a stacked structure VPL arranged in the valley portion VA, so that damage to circuit elements due to an impact applied from the outside of the display device 10 can be prevented or substantially prevented. In addition, when the display device 10 has a flexible characteristic, the valley portion VA can prevent or substantially prevent cracks that may be formed in a plurality of insulating layers arranged on the substrate 110 when the substrate 110 is folded.

[0183] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0184] Fig.11 is a cross-sectional view showing a pixel circuit of a display device according to another embodiment. Fig.12 It is shown Fig.11 A cross-sectional view of a second thin film transistor, a valley portion, and a stacked structure of a display device.

[0185] Reference Fig.11 and Fig.12, in the display device 10_1, the stacked structure VPL_1 may be arranged in the valley portion VA and may include a plurality of layers. Fig.10 Unlike the embodiment shown in , the stacked structure VPL_1 may not include some layers. In an embodiment, the stacked structure VPL_1 may include a plurality of metal patterns ML1, ML2, ML3, and ML4 and a plurality of insulation patterns IP1, IP2, IP3, IP4, IP5, and IP6, but may not include semiconductor patterns AL1 and AL2 (e.g., referring to Fig.10 ). In the stacked structure VPL_1, the first metal pattern ML1, the first insulating pattern IP1, the second insulating pattern IP2, the second metal pattern ML2, the third insulating pattern IP3, the third metal pattern ML3, the fourth insulating pattern IP4, the fifth insulating pattern IP5, the fourth metal pattern ML4, and the sixth insulating pattern IP6 may be sequentially stacked. In the stacked structure VPL_1, the first insulating pattern IP1 and the second insulating pattern IP2 arranged at the same layer (e.g., in the middle or on) as the buffer layer 122 and the first insulating layer 123 arranged at the upper and lower layers of the first semiconductor layer SCL1 may contact each other. In the stacked structure VPL_1, the fourth insulating pattern IP4 and the fifth insulating pattern IP5 arranged at the same layer (e.g., in the middle or on) as the third insulating layer 125 and the fourth insulating layer 126 arranged at the upper and lower layers of the second semiconductor layer SCL2 may contact each other.

[0186] When the height H2 of the stacked structure VPL_1 is at least greater than the height H1 of the position where the second active layer ACT2 of the second thin film transistor TFT2 is arranged, the height of the stacked structure VPL_1 may be variously modified. In the stacked structure VPL_1, patterns of only some of the layers from the lower conductive layer BCDL to the fifth insulating layer 127 may be stacked. In the display device 10_1 according to the present embodiment, the height H2 of the stacked structure VPL_1 may be greater than the height H1 of the second active layer ACT2 of the second thin film transistor TFT2. Although the stacked structure VPL_1 does not include the semiconductor patterns AL1 and AL2, its height H2 may be greater than the depth H3 of the valley portion VA.

[0187] Fig.13 is a cross-sectional view showing a pixel circuit of a display device according to another embodiment. Fig.14 It is shown Fig.13 A cross-sectional view of a second thin film transistor, a valley portion, and a stacked structure of a display device.

[0188] Reference Fig.13 and Fig.14 , in the display device 10_2, the stacked structure VPL_2 may be arranged in the valley portion VA and may include a plurality of layers. Fig.10Unlike the embodiment shown in , the stacked structure VPL_2 may not include some layers. In an embodiment, the stacked structure VPL_2 may include a plurality of insulation patterns IP1, IP2, IP3, IP4, IP5, and IP6 and a plurality of semiconductor patterns AL1 and AL2, but may not include metal patterns ML1, ML2, ML3, and ML4 (e.g., referring to Fig.10 ). In the stacked structure VPL_2, the first insulation pattern IP1, the first semiconductor pattern AL1, the second insulation pattern IP2, the third insulation pattern IP3, the fourth insulation pattern IP4, the second semiconductor pattern AL2, the fifth insulation pattern IP5 and the sixth insulation pattern IP6 may be stacked sequentially. In the stacked structure VPL_2, the second insulation pattern IP2, the third insulation pattern IP3 and the fourth insulation pattern IP4 may be in direct contact, and the fifth insulation pattern IP5 and the sixth insulation pattern IP6 may be in direct contact with each other.

[0189] When the height H2 of the stacked structure VPL_2 is at least greater than the height H1 of the position where the second active layer ACT2 of the second thin film transistor TFT2 is arranged, the height of the stacked structure VPL_2 may be variously modified. In the stacked structure VPL_2, patterns of only some of the layers from the lower conductive layer BCDL to the fifth insulating layer 127 may be stacked. In the display device 10_2 according to the present embodiment, the height H2 of the stacked structure VPL_2 may be greater than the height H1 of the second active layer ACT2 of the second thin film transistor TFT2. The stacked structure VPL_2 may not include the metal patterns ML1, ML2, ML3, and ML4, and its height H2 may be less than the depth H3 of the valley portion VA.

[0190] Fig.15 is a plan view showing the arrangement of pixel circuits and stack structures arranged in a display area of ​​a display device according to an embodiment. Fig.16 is a plan view showing the arrangement of a plurality of pixel circuits and a plurality of stack structures arranged in a display area of ​​a display device according to an embodiment.

[0191] Reference Fig.15 and Fig.16 , in the display device 10 (for example, referring to Figure 1), a plurality of stacked structures VPL may be arranged, and each of the stacked structures VPL may be arranged in an area where the valley portions VA cross or intersect each other in the first direction DR1 and the second direction DR2. Each of the stacked structures VPL may be arranged in an area where the valley portions VA cross or intersect each other near the vertex of the unit pixel region UPX (for example, adjacent to the vertex of the unit pixel region UPX). The display device 10 may have four stacked structures VPL arranged relative to one unit pixel region UPX. As another example, nine stacked structures VPL may be arranged relative to four unit pixel regions UPX1, UPX2, UPX3, and UPX4.

[0192] The stacked structure VPL may be arranged in the valley portion VA, and may have stacked portions respectively arranged in parallel with the portions constituting the pixel circuits PXC (eg, referring to Figure 7 ) of a plurality of conductive layers CDL1, CDL2, CDL3 and CDL4 (for example, referring to Fig. 9 ), semiconductor layers SCL1 and SCL2 (for example, refer to Fig. 9 ) and the insulating layer of the same layer (for example, in or on). The stacked structure VPL may include a plurality of wirings arranged in a plurality of conductive layers CDL1, CDL2, CDL3, and CDL4 of the pixel circuit PXC, and the wirings may extend in the first direction DR1 and the second direction DR2 to be arranged across the pixel circuit PXC or the unit pixel region UPX. The portion of the valley portion VA that crosses or intersects in the first direction DR1 and the second direction DR2 may overlap with the wirings, and the portion of the valley portion VA that overlaps with the wirings may have a smaller depth than other portions of the valley portion VA.

[0193] The wiring may be a plurality of wirings arranged at (e.g., in or above) the lower conductive layer BCDL and the first conductive layer CDL1, the second conductive layer CDL2, and the third conductive layer CDL3 and connected to the pixel circuit PXC, or a conductive pattern electrically connected to the thin film transistors TFT1 and TFT2. Figure 5 and Figure 6 A plurality of scan lines SL, data lines DL, emission control lines ECL, power lines PL, or the like are described.

[0194] It is desirable that the stacked structure VPL has as many patterns as possible that are stacked to absorb external impacts. It is desirable that the stacked structure VPL has multiple layers that are stacked and arranged so as not to overlap with multiple wirings arranged in the pixel circuit PXC and the display area DA. In the display device 10, the stacked structure VPL may be arranged in an area where the stacked structure VPL does not overlap with multiple wirings arranged in the pixel circuit PXC. In some embodiments, the wirings extend in the first direction DR1 and the second direction DR2 and are arranged to cross the pixel circuit PXC, so that the stacked structure VPL may be arranged in an area where the stacked structure VPL does not overlap with the pixel circuit PXC in the first direction DR1 or the second direction DR2 at the boundary of the unit pixel area UPX. However, the present disclosure is not limited thereto, and when multiple stacked structures VPL are arranged in an area where multiple stacked structures VPL do not overlap with wirings at the boundary of the unit pixel area UPX, multiple stacked structures VPL may overlap with the pixel circuit PXC in the first direction DR1 or the second direction DR2.

[0195] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting the present disclosure. Although some embodiments have been described, it will be readily appreciated by those skilled in the art that various modifications are possible in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that, unless otherwise described, the description of the features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Therefore, as will be apparent to those of ordinary skill in the art, unless otherwise specifically indicated, the features, characteristics and / or elements described in conjunction with a particular embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it is to be understood that the foregoing is illustrative of various exemplary embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other exemplary embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the accompanying claims and their equivalents.

Claims

1. A display device, comprising: a first semiconductor layer, the first semiconductor layer comprising a first active layer on a substrate; a first insulating layer, wherein the first insulating layer is on the first active layer; a first conductive layer on the first insulating layer and including a first gate electrode overlapping the first active layer and including a first capacitor electrode; a second insulating layer, the second insulating layer being on the first conductive layer; a second conductive layer on the second insulating layer and including a second capacitor electrode overlapping the first capacitor electrode; a third insulating layer, the third insulating layer being on the second conductive layer; a second semiconductor layer, the second semiconductor layer comprising a second active layer on the third insulating layer; a fourth insulating layer, the fourth insulating layer being on the second active layer; a third conductive layer on the fourth insulating layer and comprising a second gate electrode overlapping the second active layer; a fifth insulating layer, the fifth insulating layer being on the third conductive layer; a valley portion that penetrates at least some of the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer; a stacked structure including one or more of a plurality of insulating patterns at the same layers as those of the first, second, third, fourth, and fifth insulating layers, respectively, in the valley portion; a sixth insulating layer on the fifth insulating layer and including at least a portion in the valley portion; as well as A light emitting element is provided on the sixth insulating layer.

2. The display device according to claim 1, further comprising: a barrier layer, the barrier layer being between the first active layer and the substrate; a lower metal layer, the lower metal layer being between the barrier layer and the first active layer; as well as a buffer layer, the buffer layer being between the lower metal layer and the first active layer, The valley partially penetrates the buffer layer, and the stacked structure is directly positioned on the barrier layer.

3. The display device according to claim 2, wherein: A height of the stacked structure measured from the barrier layer is greater than a height of the second active layer measured from the barrier layer.

4. The display device according to claim 3, wherein: The stack structure includes one or more of a plurality of metal patterns respectively positioned at the same layers as those of the lower metal layer, the first conductive layer, the second conductive layer, and the third conductive layer.

5. The display device according to claim 3, wherein: The stack structure includes one or more of a plurality of semiconductor patterns respectively positioned at the same layers as the first and second semiconductor layers.

6. The display device according to claim 3, wherein: The height of the stacked structure is greater than the depth of the valley portion.

7. The display device according to claim 3, wherein: The height of the stacked structure is smaller than the depth of the valley portion.

8. The display device according to claim 3, wherein: The stacking structure comprises: a first metal pattern at the same layer as that of the lower metal layer; a first insulating pattern at the same layer as that of the buffer layer; a first semiconductor pattern at the same layer as that of the first semiconductor layer; a second insulating pattern at the same layer as that of the first insulating layer; a second metal pattern at the same layer as that of the first conductive layer; a third insulating pattern at the same layer as that of the second insulating layer; a third metal pattern at the same layer as that of the second conductive layer; a fourth insulating pattern at the same layer as that of the third insulating layer; a second semiconductor pattern at the same layer as that of the second semiconductor layer; a fifth insulating pattern at the same layer as that of the fourth insulating layer; a fourth metal pattern at the same layer as the third conductive layer; and A sixth insulating pattern is at the same layer as that of the fifth insulating layer.

9. The display device according to claim 8, wherein: The first metal pattern, the first insulating pattern, the first semiconductor pattern, the second insulating pattern, the second metal pattern, the third insulating pattern, the third metal pattern, the fourth insulating pattern, the second semiconductor pattern, the fifth insulating pattern, the fourth metal pattern and the sixth insulating pattern are sequentially stacked in the stack structure.

10. The display device according to claim 1, wherein: The sixth insulating layer surrounds the stack structure.

11. The display device according to claim 1, wherein: In the valley portion, a depth of a portion that does not overlap with the first to third conductive layers, the first semiconductor layer, and the second semiconductor layer is greater than a depth of a portion that overlaps with any one of the first to third conductive layers, the first semiconductor layer, and the second semiconductor layer.

12. The display device according to claim 1, wherein: The first active layer includes silicon, and the second active layer includes an oxide semiconductor.

13. The display device according to claim 1, wherein: The second conductive layer further includes a back gate electrode overlapping the second active layer.

14. The display device according to claim 1, further comprising: a fourth conductive layer, the fourth conductive layer being between the fifth insulating layer and the sixth insulating layer, the fourth conductive layer comprising: a first connection electrode connected to the first active layer; and A bridging electrode connected to the second active layer.

15. A display device, comprising: A plurality of unit pixel regions; a first thin film transistor, the first thin film transistor being in a unit pixel region among the plurality of unit pixel regions and including a first active layer on a substrate; a second thin film transistor in the unit pixel region and including a second active layer at a layer different from that of the first active layer; a plurality of conductive layers, the plurality of conductive layers being in the unit pixel region and including a plurality of wirings and a plurality of conductive patterns electrically connected to the first thin film transistor and the second thin film transistor; a valley portion that surrounds the unit pixel region and penetrates at least some of the plurality of insulating layers overlapping the first thin film transistor and the second thin film transistor; as well as A plurality of stacked structures are in the valley portion and include one or more patterns at the same layer as and stacked with layers in the plurality of conductive layers and the plurality of insulating layers.

16. The display device according to claim 15, wherein: The plurality of unit pixel regions are positioned along a first direction and a second direction crossing the first direction, The valley portion includes portions extending in the first direction and the second direction.

17. The display device according to claim 16, wherein: The stacked structure among the plurality of stacked structures is positioned in a region where the portion of the valley portion extending in the first direction and the portion of the valley portion extending in the second direction cross each other.

18. The display device according to claim 15, wherein: The stacking structure among the plurality of stacking structures includes one or more of the following: a first semiconductor pattern at the same layer as that of the first active layer; as well as A second semiconductor pattern is at the same layer as that of the second active layer.

19. The display device according to claim 15, wherein: The stacking structure among the plurality of stacking structures includes one or more of the following: a plurality of metal patterns respectively at the same layers as the plurality of conductive layers; as well as A plurality of insulating patterns are respectively at the same layers as those of the plurality of insulating layers.

20. The display device according to claim 15, wherein: A stacked structure among the plurality of stacked structures does not overlap the conductive pattern and the wiring electrically connected to any one of the first thin film transistor and the second thin film transistor.

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