Display panel and method for manufacturing display panel

Abstract

A display panel and a method for manufacturing the same are provided. The display panel includes a base layer, an anode disposed on the base layer, a sacrificial pattern disposed on the anode and having a sacrificial opening exposing a portion of an upper surface of the anode, a pixel defining film disposed on the base layer and having a light emitting opening corresponding to the sacrificial opening, the sacrificial pattern includes a metal oxide containing a first metal, indium, and zinc, and the sacrificial pattern includes a metal oxide containing a second metal, indium, and zinc, and the sacrificial pattern includes a metal oxide containing a second metal, indium, and zinc, and the sacrificial pattern includes a first metal, a second metal, and a second metal, and the first metal and the second metal are electrically connected to the first metal and the second metal, and the second metal is electrically connected to the first metal. The first metal includes at least one of tin and gallium, and the sacrificial pattern protrudes from one side of the pixel defining film.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0107914, filed on August 17, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present invention relates generally to display panels, and more particularly to a display panel having improved display quality and a method of manufacturing the display panel. Background Art

[0004] Display devices such as televisions, monitors, smart phones, and tablet computers that provide images to users include display panels for displaying images. Various display panels such as liquid crystal display panels, organic light emitting display panels, electrowetting display panels, and electrophoretic display panels are being developed.

[0005] The organic light emitting display panel may include an anode, a cathode, and a light emitting pattern. The light emitting pattern is separated for each light emitting area, and the cathode may provide a common voltage to each light emitting area. Summary of the invention

[0006] The present invention provides a display panel with improved process reliability, wherein the display panel is configured to form a light emitting element without using a metal mask. A method for manufacturing the display panel is also provided.

[0007] An embodiment provides a display panel, which includes a base layer, an anode arranged on the base layer, a sacrificial pattern arranged on the anode and having a sacrificial opening defined therein and exposing a portion of an upper surface of the anode, a pixel defining film arranged on the base layer to cover at least a portion of the sacrificial pattern and having a light-emitting opening defined therein and corresponding to the sacrificial opening, a partition wall arranged on the pixel defining film and having a partition wall opening defined therein and corresponding to the light-emitting opening, a light-emitting pattern arranged on the anode in the partition wall opening, and a cathode arranged on the light-emitting pattern and in contact with the partition wall, wherein the sacrificial pattern includes a metal oxide including a first metal, indium and zinc, the first metal including at least one of tin and gallium, and wherein the sacrificial pattern has a shape protruding from one side of the pixel defining film.

[0008] In an implementation, the width of the sacrificial opening may be smaller than the width of the light emitting opening.

[0009] In an implementation, a content of the first metal included in the sacrificial pattern may be about 5.0 at % or more of a total content of the first metal, indium, and zinc included in the sacrificial pattern.

[0010] In an implementation, the sacrificial pattern may include indium tin zinc oxide (ITZO) or indium gallium zinc oxide (IGZO).

[0011] In an implementation, the metal oxide included in the sacrificial pattern may include an amorphous structure.

[0012] In an implementation, among the total contents of the first metal, indium, and zinc included in the sacrificial pattern, the content of indium may be about 35 at % to about 50 at %, and the content of zinc may be about 35 at % to about 50 at %.

[0013] In an implementation, a content ratio of indium to zinc included in the sacrificial pattern may be about 4:6 to about 6:4.

[0014] In an embodiment, the anode may include indium tin oxide (ITO).

[0015] In an embodiment, the anode may include a first layer disposed on the base layer and including indium tin oxide (ITO), a second layer disposed on the first layer and including silver, and a third layer disposed on the second layer and including indium tin oxide (ITO), wherein the sacrificial pattern may be directly disposed on the third layer.

[0016] In an implementation, the light emitting opening may expose a portion of an upper surface of the sacrificial pattern, and the portion of the upper surface of the sacrificial pattern exposed by the light emitting opening may contact the light emitting pattern.

[0017] In an implementation, the partition wall may include a first partition wall layer disposed on the pixel defining film and including a metal, and a second partition wall layer disposed on the first partition wall layer and including a metal or a silicon-based compound.

[0018] In embodiments, the cathode may be in contact with the first partition wall layer.

[0019] In an embodiment, the partition wall opening may include a first region where the light emitting pattern is arranged and a second region having a smaller width than the first region, wherein an inner side surface of the first partition wall layer may define the first region and an inner side surface of the second partition wall layer may define the second region.

[0020] In an implementation, the second partition wall layer may have an undercut shape protruding from one side of the first partition wall layer.

[0021] In an embodiment, the display panel may further include a thin film encapsulation layer arranged on the light emitting element (e.g., the light emitting pattern) and including a plurality of thin films, wherein the thin film encapsulation layer may include an inorganic encapsulation pattern covering the light emitting element (e.g., the light emitting pattern) and partially contacting the partition wall.

[0022] In an embodiment, a display panel includes a base layer, an anode arranged on the base layer, a sacrificial pattern arranged on the anode and having a sacrificial opening defined therein and exposing a portion of an upper surface of the anode, a pixel defining film arranged on the base layer to cover at least a portion of the sacrificial pattern and having a light-emitting opening defined therein and corresponding to the sacrificial opening, a partition wall arranged on the pixel defining film and having a partition wall opening defined therein and corresponding to the light-emitting opening, a light-emitting pattern arranged on the anode in the partition wall opening, and a cathode arranged on the light-emitting pattern and in contact with the partition wall, wherein the sacrificial pattern includes a first metal, indium and zinc, the first metal includes at least one of tin and gallium, and the content of the first metal included in the sacrificial pattern is approximately 5.0at% or greater of the total content of the first metal, indium and zinc included in the sacrificial pattern.

[0023] In an implementation, an inner side surface of the pixel defining film may be disposed closer to the center of the anode than an inner side surface of the sacrificial pattern.

[0024] In an implementation, an inner side surface of the pixel defining film may be aligned with an inner side surface of the sacrificial pattern.

[0025] In an embodiment, a method for manufacturing a display panel includes: forming an anode on a base layer; forming a preliminary sacrificial pattern including a metal oxide containing indium, zinc and a first metal including at least one of tin and gallium on the anode; forming a preliminary pixel defining film covering the anode and the preliminary sacrificial pattern; forming a preliminary partition wall on the preliminary pixel defining film; etching the preliminary partition wall to form a partition wall having a partition wall opening defined therein; etching the preliminary pixel defining film to form a pixel defining film having a light emitting opening defined therein and overlapping with the partition wall opening; etching the preliminary sacrificial pattern to form a sacrificial pattern having a sacrificial opening defined therein and overlapping with the partition wall opening; and forming a cathode in the partition wall opening that contacts the light emitting pattern and the partition wall, wherein, in forming the sacrificial pattern, the sacrificial pattern is formed to protrude from one side of the pixel defining film.

[0026] In an embodiment, in forming the sacrificial pattern, an etching rate of the anode may be lower than an etching rate of the preliminary sacrificial pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present invention. The accompanying drawings illustrate embodiments of the present invention and together with the description are used to explain the principles of the present invention. The above and other objects and features of the present invention will become more apparent by describing the embodiments of the present invention in detail with reference to the accompanying drawings.

[0028] Figure 1A is a perspective view of a display device according to an embodiment;

[0029] Figure 1Bis an exploded perspective view of a display device according to an embodiment;

[0030] Figure 2 is a cross-sectional view of a display module according to an embodiment;

[0031] Figure 3A is a plan view of a display panel according to an embodiment;

[0032] Figure 3B is an equivalent circuit diagram of a pixel according to an embodiment;

[0033] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment;

[0034] Figure 5A is a cross-sectional view of a display panel according to an embodiment;

[0035] Figure 5B is a cross-sectional view of a display panel according to an embodiment;

[0036] Figure 6 is a cross-sectional view of a display panel according to an embodiment;

[0037] Figure 7 is a cross-sectional view of a display panel according to an embodiment;

[0038] Fig. 8A is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0039] Figure 8B is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0040] Figure 8C is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0041] Fig.8D is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0042] Fig. 8E is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0043] Fig.8F is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0044] Figure 8G is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0045] Figure 8His a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0046] Fig.8I is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0047] Figure 8J is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment;

[0048] Figure 8K is a cross-sectional view showing steps of a method of manufacturing a display panel according to an embodiment; and

[0049] Figure 8L are cross-sectional views illustrating steps of a method of manufacturing a display panel according to an embodiment. DETAILED DESCRIPTION

[0050] In the present disclosure, it will be understood that when an element (or region, layer, portion, etc.) is referred to as being "on," "connected to" or "coupled to" another element, it can be directly on, directly connected to or directly coupled to the other element, or intervening elements may be present.

[0051] Throughout the specification, similar reference numerals refer to similar elements. In addition, in the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical features. As used herein, the term "and / or" includes any and all combinations that the associated components can define.

[0052] It will be understood that, although the terms first, second, etc. can be used to describe various elements in this article, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the scope of the present invention, the first element can be referred to as the second element. Similarly, the second element can also be referred to as the first element. Unless otherwise stated, the terms in the singular include plural forms.

[0053] In addition, terms such as "below", "on", "lower", "above", "upper" and the like are used herein for convenience of description to describe the relationship between one element and another element (other elements) as shown in the drawings. The above terms are relative concepts and are described based on the directions indicated in the drawings.

[0054] It will be understood that when the terms “include,” “comprise,” and / or “have,” are used in this specification, they specify the presence of stated features, integers, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0055] In this specification, the expression "directly arranged" may mean that there is no layer, film, region, plate or the like added between a portion and other portions of the layer, film, region, plate or the like. For example, the expression "directly arranged" may mean arranged between two layers or two members without an additional member such as an adhesive member therebetween.

[0056] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. It will also be understood that, unless explicitly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and the relevant art, and will not be interpreted in an idealized or overly formal sense.

[0057] Terms such as "part" and "unit" mean a software component or a hardware component that performs a specific function. For example, a hardware component may include a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). A software component may refer to executable code and / or data used by the executable code in an addressable storage medium. Thus, for example, a software component may be an object-oriented software component, a class component, and a task component, and may include a process, a function, a property, a program, a subroutine, a program code segment, a driver, firmware, microcode, a circuit, data, a database, a data structure, a table, an array, or a variable.

[0058] Hereinafter, a display device according to an embodiment will be described with reference to the accompanying drawings.

[0059] Figure 1A is a perspective view of a display device according to an embodiment. Figure 1B is an exploded perspective view of a display device according to an embodiment. Figure 2 is a cross-sectional view of a display module according to an embodiment.

[0060] In an embodiment, the display device DD may be a large electronic device such as a television, a monitor, or an external billboard. In addition, the display device DD may be a small or medium-sized electronic device such as a personal computer (e.g., a laptop computer, a tablet computer), a personal digital terminal, a car navigation unit, a game console, a smart phone, and a camera. These are presented only as examples, and the display device DD may be adopted as other display devices. In the present embodiment, the display device DD is exemplarily shown as a smart phone.

[0061] In the embodiments and with reference to Figure 1A , Figure 1B and Figure 2 , the display device DD may display an image IM toward a third direction DR3 on a display surface FS oriented parallel to each of the first direction DR1 and the second direction DR2. The image IM may include a still image as well as a dynamic image. Figure 1A A viewing window and a plurality of icons are shown as examples of an image IM. The display surface FS on which the image IM is displayed may correspond to a front surface of the display device DD.

[0062] In an embodiment, the front (or upper) surface and the rear (or lower) surface of each member are defined based on the direction in which the image IM is displayed. The front surface and the rear surface face each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be oriented parallel to the third direction DR3. On the other hand, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3, respectively, are relative concepts and may be converted to other directions. In this specification, the expression "on a plane" may mean when viewed from the third direction DR3.

[0063] In an embodiment and as Figure 1B As shown in , the display device DD may include a window WP, a display module DM, and a housing HAU. The window WP and the housing HAU may be coupled to each other to configure the appearance of the display device DD.

[0064] In an embodiment, the window WP may include an optically transparent insulating material. For example, the window WP may include glass or plastic. The front surface of the window WP may define a display surface FS of the display device DD. The display surface FS may include a transmission area TA and a frame area BZA. The transmission area TA may be an optically transparent area. For example, the transmission area TA may have a visible light transmittance of about 90% or more.

[0065] In an embodiment, the frame area BZA may have a relatively low light transmittance compared to the transmission area TA. The frame area BZA may define the shape of the transmission area TA. The frame area BZA may be arranged adjacent to the transmission area TA and may surround the transmission area TA. On the other hand, this is shown exemplarily, and in the window WP, according to an embodiment, the frame area BZA may be omitted. The window WP may include at least one functional layer among an anti-fingerprint layer, a hard coating layer, and an anti-reflection layer, but the present invention is not limited to any one embodiment.

[0066] In an embodiment, the display module DM may be arranged under the window WP. The display module DM may be configured to basically generate an image IM. The image IM generated by the display module DM is displayed on the display surface IS of the display module DM and is visually recognized by a user from the outside through the transmission area TA.

[0067] In an embodiment, the display module DM includes a display area DA and a non-display area NDA. The display area DA may be activated according to an electrical signal. The non-display area NDA is arranged adjacent to the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be covered by a bezel area BZA and may not be visually recognized from the outside.

[0068] In an embodiment and as Figure 1B As shown in , the housing HAU may be coupled to the window WP. The housing HAU may be coupled to the window WP to provide a predetermined inner space. The display module DM may be accommodated in the inner space.

[0069] In an embodiment, the housing HAU may include a material having relatively high rigidity. For example, the housing HAU may include a plurality of frames and / or plates made of glass, plastic, metal, or a combination thereof. The housing HAU may stably protect the components of the display device DD housed in the internal space from external impacts.

[0070] In the embodiments and with reference to Figure 2 , the display module DM may include a display panel DP and an input sensor INS. Although not shown separately, according to an embodiment, the display device DD (see Figure 1A ) may further include a protection member disposed on the lower surface of the display panel DP or an anti-reflection member and / or a window member disposed on the upper surface of the input sensor INS.

[0071] In an embodiment, the display panel DP may be a light-emitting display panel. However, this is an example, and the present invention is not particularly limited thereto. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of the organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of the inorganic light-emitting display panel may include quantum dots, quantum rods, or micro LEDs. Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0072] In an embodiment, the display panel DP may include a base layer BL, a circuit element layer DP-CL arranged on the base layer BL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The input sensor INS may be directly arranged on the thin film encapsulation layer TFE. In this specification, the expression "component A is directly arranged on component B" means that no adhesive layer is arranged between component A and component B.

[0073] In an embodiment, the base layer BL may include at least one plastic film. The base layer BL may be a flexible substrate, and include a plastic substrate, a glass substrate, a metal substrate, or an organic / inorganic composite material substrate. Figure 1B The display area DA and the non-display area NDA described in may be equally defined in the base layer BL.

[0074] In an embodiment, the circuit element layer DP-CL may include at least one insulating layer and a circuit element. The insulating layer includes at least one inorganic layer and at least one organic layer. The circuit element includes a signal line, a pixel driving circuit (may be referred to as a pixel circuit hereinafter), and the like.

[0075] In an embodiment, the display element layer DP-OLED may include a partition wall and a light emitting element. The light emitting element may include an anode, an intermediate layer, and a cathode.

[0076] In an embodiment, the thin film encapsulation layer TFE may include a plurality of thin films, some of which may be arranged to improve optical efficiency, and some of which may be arranged to protect the organic light emitting diode.

[0077] In an embodiment, the input sensor INS obtains coordinate information of an external input. The input sensor INS may have a multi-layer structure. The input sensor INS may include a single layer or multiple layers of conductive layers. In addition, the input sensor INS may include a single layer or multiple layers of insulating layers. The input sensor INS may sense the external input by a capacitive method. However, this is an example, and the present invention is not limited thereto. For example, in an embodiment, the input sensor INS may sense the external input by an electromagnetic induction method or by a pressure sensing method. On the other hand, in another embodiment, the input sensor INS may be omitted.

[0078] Figure 3A is a plan view of a display panel according to an embodiment.

[0079] In the embodiments and with reference to Figure 3AA display area DA and a non-display area NDA surrounding the display area DA may be defined in the display panel DP. The display area DA and the non-display area NDA may be distinguished from each other according to whether pixels PX are arranged. The pixels PX may be arranged in the display area DA. A scan driver SDV, a data driver, and a light emitting driver EDV may be arranged in the non-display area NDA. The data driver may be part of a circuit configured in the driver chip DIC.

[0080] In an embodiment, the display panel DP may include pixels PX, initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, data lines DL1 to DLn, first and second control lines CSL1 and CSL2, driving voltage lines PL, and a plurality of pads PD. Here, m and n are natural numbers greater than or equal to 2.

[0081] In an embodiment, the plurality of pixels PX may be connected to initialization scan lines GIL1 to GILm, compensation scan lines GCL1 to GCLm, write scan lines GWL1 to GWLm, black scan lines GBL1 to GBLm, emission control lines ECL1 to ECLm, and data lines DL1 to DLn.

[0082] In an embodiment, the initialization scan lines GIL1 to GILm, the compensation scan lines GCL1 to GCLm, the write scan lines GWL1 to GWLm, and the black scan lines GBL1 to GBLm may extend in the first direction DR1 to be electrically connected to the scan driver SDV. The data lines DL1 to DLn may extend in the second direction DR2 to be electrically connected to the driving chip DIC. The emission control lines ECL1 to ECLm may extend in the first direction DR1 to be electrically connected to the emission driver EDV.

[0083] In an embodiment, the driving voltage line PL may include a portion extending in the first direction DR1 and a portion extending in the second direction DR2. The portion extending in the first direction DR1 and the portion extending in the second direction DR2 may be arranged on (or in) different layers. The driving voltage line PL may provide a driving voltage to the pixel PX.

[0084] In an implementation, the first control line CSL1 may be connected to the scan driver SDV, and the second control line CSL2 may be connected to the light emitting driver EDV.

[0085] In an embodiment, the driving chip DIC, the driving voltage line PL, the first control line CSL1 and the second control line CSL2 may be electrically connected to the pad PD. The circuit board FCB may be electrically connected to the pad PD through an anisotropic conductive adhesive layer. The pad PD may connect the circuit board FCB to the display panel DP. The pad PD may be connected to the corresponding pixel PX through the driving voltage line PL, the first control line CSL1 and the second control line CSL2.

[0086] Furthermore, in an embodiment, the pads PD may further include input pads. The input pads may connect the circuit board FCB to the input sensor INS (see Figure 2 ). However, not limited thereto, the input pad may be arranged on the input sensor INS and connected to the pad PD and a separate circuit board. In an embodiment, the input sensor INS may be omitted, and the input pad may not be further included.

[0087] Figure 3B is an equivalent circuit diagram of a pixel according to an embodiment.

[0088] In an embodiment, Figure 3B A plurality of pixels PX are shown as an example (see Figure 3A ) is an equivalent circuit diagram of one pixel PXij among the plurality of pixels PX. Since each of the plurality of pixels PX has the same circuit structure, the description of the circuit structure of the pixel PXij will be applied to the remaining pixels PX, and a detailed description of the remaining pixels PX will be omitted.

[0089] In the embodiments and with reference to Figure 3A and Figure 3B , the pixel PXij is connected to the i-th data line DLi among the data lines DL1 to DLn, the j-th initialization scan line GILj among the initialization scan lines GIL1 to GILm, the j-th compensation scan line GCLj among the compensation scan lines GCL1 to GCLm, the j-th write scan line GWLj among the write scan lines GWL1 to GWLm, the j-th black scan line GBLj among the black scan lines GBL1 to GBLm, the j-th light emitting control line ECLj among the light emitting control lines ECL1 to ECLm, the first driving voltage line VL1 and the second driving voltage line VL2, and the first initialization voltage line VL3 and the second initialization voltage line VL4, where i is an integer from 1 to n, and j is an integer from 1 to m.

[0090] In an embodiment, the pixel PXij includes a light emitting element ED and a pixel circuit PDC. The light emitting element ED may be a light emitting diode. As an example, the light emitting element ED may be an organic light emitting diode including an organic light emitting layer, but the present invention is not particularly limited thereto. The pixel circuit PDC may control the amount of current flowing through the light emitting element ED in response to the i-th data signal Di. The light emitting element ED may emit light having a predetermined brightness in response to the amount of current provided from the pixel circuit PDC.

[0091] In an embodiment, the pixel circuit PDC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, and a first capacitor Cst, a second capacitor Cbst, and a third capacitor Nbst. The configuration of the pixel circuit PDC is not limited to Figure 3B The embodiment shown in . Figure 3B The pixel circuit PDC shown in FIG. 1 is merely an example, and the configuration of the pixel circuit PDC may be modified and implemented.

[0092] In an embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may have a low temperature polycrystalline silicon (LTPS) semiconductor layer. At least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may have an oxide semiconductor layer. For example, the third transistor T3 and the fourth transistor T4 may be oxide semiconductor transistors, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be LTPS transistors.

[0093] Specifically, in an embodiment, the first transistor T1 that directly affects the brightness of the light-emitting element ED may be configured to include a semiconductor layer composed of highly reliable polycrystalline silicon, and through this, it is possible to realize a high-resolution display device. On the other hand, since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large even when the driving time is long. That is, since the color change of the image caused by the voltage drop is not large even during low-frequency driving, low-frequency driving is possible. As described above, since the oxide semiconductor has the advantage of small leakage current, by adopting at least one of the third transistor T3 and the fourth transistor T4 connected to the gate electrode of the first transistor T1 as an oxide semiconductor, it is possible not only to prevent the leakage current that may flow to the gate electrode, but also to reduce power consumption.

[0094] In an embodiment, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the others may be N-type transistors. For example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors, and the third transistor T3 and the fourth transistor T4 may be N-type transistors.

[0095] The configuration of the pixel circuit PDC is not limited to Figure 3B In the embodiment shown in. In the embodiment, Figure 3B The pixel circuit PDC shown in is only an example, and the configuration of the pixel circuit PDC may be modified and implemented. For example, all of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type transistors or N-type transistors. Alternatively, the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be P-type transistors, and the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may be N-type transistors.

[0096] In an embodiment, the jth initialization scan line GILj, the jth compensation scan line GCLj, the jth write scan line GWLj, the jth black scan line GBLj, and the jth emission control line ECLj may transmit the jth initialization scan signal GIj, the jth compensation scan signal GCj, the jth write scan signal GWj, the jth black scan signal GBj, and the jth emission control signal EMj to the pixel PXij, respectively. The i-th data line DLi transmits the i-th data signal Di to the pixel PXij. The i-th data signal Di may have a signal similar to that input to the display device DD (see Figure 1A )’s image signal corresponding to the voltage level.

[0097] In an embodiment, the first and second driving voltage lines VL1 and VL2 may transmit the first and second driving voltages ELVDD and ELVSS to the pixels PXij, respectively. In addition, the first and second initialization voltage lines VL3 and VL4 may transmit the first and second initialization voltages VINT and VAINT to the pixels PXij, respectively.

[0098] In an embodiment, the first transistor T1 is connected between the light emitting element ED and a first driving voltage line VL1 configured to receive a first driving voltage ELVDD. The first transistor T1 includes a first electrode connected to the first driving voltage line VL1 via a fifth transistor T5, a second electrode connected to a pixel electrode (or referred to as an anode) of the light emitting element ED via a sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to one end (e.g., a first node N1) of the first capacitor Cst. The first transistor T1 may receive an i-th data signal Di transmitted from an i-th data line DLi according to a switching operation of the second transistor T2 to supply a driving current to the light emitting element ED.

[0099] In an embodiment, the second transistor T2 is connected between the i-th data line DLi and the first electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the i-th data line DLi, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th write scan line GWLj. The second transistor T2 may be turned on according to the j-th write scan signal GWj received through the j-th write scan line GWLj, and transmit the i-th data signal Di received from the i-th data line DLi to the first electrode of the first transistor T1. One end of the second capacitor Cbst may be connected to the third electrode of the second transistor T2, and the other end of the second capacitor Cbst may be connected to the first node N1.

[0100] In an embodiment, the third transistor T3 is connected between the second electrode of the first transistor T1 and the first node N1. The third transistor T3 includes a first electrode connected to the third electrode of the first transistor T1, a second electrode connected to the second electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the jth compensation scan line GCLj. The third transistor T3 may be turned on according to the jth compensation scan signal GCj received through the jth compensation scan line GCLj, so that the third electrode of the first transistor T1 and the second electrode of the first transistor T1 are connected to each other, thereby enabling the first transistor T1 to be connected in a diode manner. One end of the third capacitor Nbst may be connected to the third electrode of the third transistor T3, and the other end of the third capacitor Nbst may be connected to the first node N1.

[0101] In an embodiment, the fourth transistor T4 is connected between the first node N1 and the first initialization voltage line VL3 to which the first initialization voltage VINT is applied. The fourth transistor T4 includes a first electrode connected to the first initialization voltage line VL3 to which the first initialization voltage VINT is transmitted, a second electrode connected to the first node N1, and a third electrode (e.g., a gate electrode) connected to the jth initialization scan line GILj. The fourth transistor T4 is turned on according to the jth initialization scan signal GIj received through the jth initialization scan line GILj. The turned-on fourth transistor T4 transmits the first initialization voltage VINT to the first node N1 to initialize the potential of the third electrode of the first transistor T1 (i.e., the potential of the first node N1).

[0102] In an embodiment, the fifth transistor T5 includes a first electrode connected to the first driving voltage line VL1, a second electrode connected to the first electrode of the first transistor T1, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj. The sixth transistor T6 includes a first electrode connected to the second electrode of the first transistor T1, a second electrode connected to the pixel electrode of the light emitting element ED, and a third electrode (e.g., a gate electrode) connected to the j-th emission control line ECLj.

[0103] In an embodiment, the fifth transistor T5 and the sixth transistor T6 are synchronously turned on according to the jth light emitting control signal EMj received through the jth light emitting control line ECLj. The first driving voltage ELVDD applied by the turned-on fifth transistor T5 can be compensated by the first transistor T1 connected in a diode manner, and then transmitted to the light emitting element ED through the sixth transistor T6.

[0104] In an embodiment, the seventh transistor T7 includes a first electrode connected to a second initialization voltage line VL4 transmitting a second initialization voltage VAINT, a second electrode connected to a second electrode (or a second node N2) of the sixth transistor T6, and a third electrode (e.g., a gate electrode) connected to a j-th black scan line GBLj. The second initialization voltage VAINT may have a voltage level equal to or lower than a voltage level of the first initialization voltage VINT.

[0105] In an embodiment, one end of the first capacitor Cst is connected to the third electrode of the first transistor T1, and the other end of the first capacitor Cst is connected to the first driving voltage line VL1. The cathode of the light emitting element ED may be connected to the second driving voltage line VL2 configured to transmit the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the first driving voltage ELVDD.

[0106] Figure 4 is an enlarged plan view of a portion of a display area of ​​a display panel according to an embodiment. Figure 4 The display module DM (see Figure 1B ) of the display surface IS (see Figure 1B ) is a plane of the display module DM observed, and shows the arrangement of the light emitting areas PXA-R, PXA-G and PXA-B.

[0107] In the embodiments and with reference to Figure 4 , the display area DA may include a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B and a peripheral area NPXA surrounding the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B. The first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may correspond to the light emitting elements ED1, ED2, and ED3 (see FIG. Figure 6 ) is emitted. The first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B may be arranged according to the direction of the display module DM (see Figure 1B ) is classified by the color of the light emitted externally.

[0108] In an embodiment, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may respectively provide first color light, second color light, and third color light having different colors. For example, the first color light may be red light, the second color light may be green light, and the third color light may be blue light. However, the first color light to the third color light are not necessarily limited to the above examples.

[0109] In an embodiment, each of the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B may be defined as a region where the upper surface of the anode is exposed through a light-emitting opening to be described later. The peripheral region NPXA sets a boundary between the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B, and may prevent color mixing between the first light-emitting region PXA-R, the second light-emitting region PXA-G, and the third light-emitting region PXA-B.

[0110] In an embodiment, each of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may be provided in plurality, and they may be repeatedly arranged in a predetermined arrangement form in the display area DA. For example, the first light-emitting area PXA-R and the third light-emitting area PXA-B may be alternately arranged along the first direction DR1 to form a "first group". The second light-emitting area PXA-G may be arranged along the first direction DR1 to form a "second group". Each of the "first group" and the "second group" may be provided in plurality, and the "first group" and the "second group" may be alternately arranged along the second direction DR2.

[0111] In an embodiment, one second light emitting region PXA-G may be arranged to be spaced apart from one first light emitting region PXA-R or one third light emitting region PXA-B in the fourth direction DR4. The fourth direction DR4 may be defined as a direction between the first direction DR1 and the second direction DR2.

[0112] In an embodiment, Figure 4 The arrangement form of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B is exemplarily shown, but the arrangement form is not limited thereto, and they may be arranged in various forms. In an embodiment, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may have a configuration as follows: Figure 4 As shown in In another embodiment, the first light-emitting area PXA-R, the second light-emitting area PXA-G and the third light-emitting area PXA-B may have a stripe arrangement or a Diamond Pixel arrangement. TM Arrangement form.

[0113] In an embodiment, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may have various shapes on a plane. For example, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may have a polygonal, circular, or elliptical shape. Figure 4 The first and third light emitting regions PXA-R and PXA-B having a quadrangular shape (or a rhombus shape) and the second light emitting region PXA-G having an octagonal shape are exemplarily shown on a plane.

[0114] In an embodiment, the first light emitting region PXA-R, the second light emitting region PXA-G, and the third light emitting region PXA-B may have the same shape on a plane, or at least some of them may have different shapes. Figure 4 The first and third light emitting regions PXA-R and PXA-B having the same shape and the second light emitting region PXA-G having a shape different from those of the first and third light emitting regions PXA-R and PXA-B are exemplarily shown on a plane.

[0115] In an embodiment, at least some of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B may have different areas on a plane. In an embodiment, the area of ​​the first light-emitting area PXA-R configured to emit red light may be larger than the area of ​​the second light-emitting area PXA-G configured to emit green light, and smaller than the area of ​​the third light-emitting area PXA-B configured to emit blue light. However, the size relationship between the areas of the first light-emitting area PXA-R, the second light-emitting area PXA-G, and the third light-emitting area PXA-B according to the color of the emitted light is not limited thereto, and may be selected according to the display module DM (see Figure 2 ) is changed by the design. In addition, without being limited thereto, the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B may have the same area on a plane.

[0116] In an embodiment, the display module DM (see Figure 2 The shapes, areas and arrangements of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B can be determined according to the color of the emitted light or the display module DM (see Figure 2 ) can be designed in various ways, and the present invention is not limited to Figure 4 The embodiment shown in .

[0117] Figure 5A is a cross-sectional view of a display panel according to an embodiment. Figure 5A Shown along Figure 4 On the other hand, the reference Figure 2 describe Figure 5A , and the description of the same figure numbers will be omitted.

[0118] In an embodiment, Figure 5A is the display area DA (see Figure 4 ) is an enlarged view of a light emitting area PXA in FIG. 1 , and Figure 5A The light emitting area PXA may correspond to Figure 4 any one of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B.

[0119] In the embodiments and with reference to Figure 5A , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE.

[0120] In an embodiment, the display panel DP may include a plurality of insulating layers, semiconductor patterns, conductive patterns, signal lines, and the like. The insulating layers, semiconductor layers, and conductive layers are formed by methods such as coating and deposition. Thereafter, the insulating layers, semiconductor layers, and conductive layers may be selectively patterned by photolithography and etching processes. In this way, semiconductor patterns, conductive patterns, signal lines, and the like included in the circuit element layer DP-CL and the display element layer DP-OLED may be formed.

[0121] In an embodiment, the circuit element layer DP-CL may be disposed on the base layer BL. The circuit element layer DP-CL may include a buffer layer BFL, a transistor TR1, a signal transfer region SCL, a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50, an upper electrode EE, and a plurality of connection electrodes CNE1 and CNE2.

[0122] In an embodiment, a buffer layer BFL may be disposed on the base layer BL. The buffer layer BFL may improve the bonding strength between the base layer BL and the semiconductor pattern. The buffer layer BFL may include a silicon oxide layer and a silicon nitride layer. The silicon oxide layer and the silicon nitride layer may be alternately stacked with each other.

[0123] In an embodiment, the semiconductor pattern may be disposed on the buffer layer BFL. The semiconductor pattern may include polycrystalline silicon. However, not limited thereto, the semiconductor pattern may include amorphous silicon or metal oxide. Figure 5A Only a portion of the semiconductor pattern is exemplarily shown, and the semiconductor pattern may be further arranged in a plurality of light emitting regions PXA-R, PXA-G, and PXA-B (see Figure 4 ). The semiconductor pattern may be arranged across the plurality of light emitting regions PXA-R, PXA-G and PXA-B in a specific rule. The semiconductor pattern may have different electrical properties depending on whether it is doped. The semiconductor pattern may include a first region with a high doping concentration and a second region with a low doping concentration. The first region may be doped with an N-type dopant or a P-type dopant. The P-type transistor may include a first region doped with a P-type dopant.

[0124] In an embodiment, the first region has a higher conductivity than the second region and is substantially used as an electrode or a signal line. The second region may substantially correspond to an active portion (or channel) of a transistor. In other words, a portion of the semiconductor pattern may be an active portion of a transistor, another portion of the semiconductor pattern may be a source or drain of the transistor, and another portion of the semiconductor pattern may be a conductive region.

[0125] In an implementation, the source S, the active portion A, and the drain D of the transistor TR1 may be formed of a semiconductor pattern. Figure 5AA portion of a signal transmission region SCL formed of a semiconductor pattern is shown Although not separately shown, the signal transmission region SCL may be connected to the drain D of the transistor TR1 on a plane.

[0126] In an embodiment, the first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be disposed above the buffer layer BFL. The first insulating layer 10, the second insulating layer 20, the third insulating layer 30, the fourth insulating layer 40 and the fifth insulating layer 50 may be an inorganic layer or an organic layer.

[0127] In an embodiment, the first insulating layer 10 may be disposed on the buffer layer BFL. The first insulating layer 10 may cover the source S, the active portion A, the drain D, and the signal transmission region SCL of the transistor TR1 disposed on the buffer layer BFL. The gate G of the transistor TR1 may be disposed on the first insulating layer 10. Here, the gate G may refer to the gate electrode mentioned above. The second insulating layer 20 may be disposed on the first insulating layer 10 to cover the gate G. The upper electrode EE may be disposed on the second insulating layer 20. The third insulating layer 30 may be disposed on the second insulating layer 20 to cover the upper electrode EE.

[0128] In an embodiment, the first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the signal transfer region SCL through a contact hole CNT-1 passing through the first insulating layer 10, the second insulating layer 20, and the third insulating layer 30. The fourth insulating layer 40 may be disposed on the third insulating layer 30 to cover the first connection electrode CNE1. The fourth insulating layer 40 may be an organic layer.

[0129] In an embodiment, the second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 passing through the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 to cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0130] In an embodiment, the display element layer DP-OLED may be disposed on the circuit element layer DP-CL. The display element layer DP-OLED may include a light emitting element ED, a sacrificial pattern SP, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP.

[0131] In an embodiment, the light emitting element ED may include an anode AE ​​(or a first electrode), a light emitting pattern EP, and a cathode CE (or a second electrode). Each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 to be described later may have Figure 5AThe description of the anode AE, the emission pattern EP, and the cathode CE can be equally applied to all of the anode, the emission pattern, and the cathode of each of the first to third light emitting elements ED1 to ED3 to be described later.

[0132] In an embodiment, the anode AE ​​may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. The anode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. The anode AE ​​may be connected to the second connection electrode CNE2 through a connection contact hole CNT-3 defined through the fifth insulating layer 50. Therefore, the anode AE ​​may be electrically connected to the signal transmission region SCL through the first connection electrode CNE1 and the second connection electrode CNE2 so as to be electrically connected to the corresponding circuit element.

[0133] In an embodiment, the anode AE ​​has electrical conductivity. The anode AE ​​may be formed of a metal material, a metal alloy, or a conductive compound. The anode AE ​​may include at least one selected from the group consisting of Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF, Mo, Ti, W, In, Sn, and Zn, a compound selected from two or more of the clusters, a mixture of two or more of the clusters, or an oxide thereof. In another embodiment, the anode AE ​​may include a transparent metal oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO). In yet another embodiment, the anode AE ​​may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca (a stacked structure of LiF and Ca), LiF / Al (a stacked structure of LiF and Al), Mo, Ti, W, or a compound or mixture thereof (e.g., a mixture of Ag and Mg).

[0134] In an embodiment, the anode AE ​​may include a single layer or a multi-layer structure. The anode AE ​​may have a single layer structure including at least one of the above materials. For example, the anode AE ​​may have a single layer structure including indium tin oxide (ITO).

[0135] In an embodiment, the anode AE ​​may have a multilayer structure including a plurality of layers. Each of the plurality of layers included in the anode AE ​​may include at least one of different materials. In an embodiment, the anode AE ​​may include a plurality of layers including indium tin oxide (ITO) and silver (Ag). For example, the anode AE ​​may include a first layer disposed on the base layer BL and including indium tin oxide (ITO), a second layer disposed on the first layer and including silver (Ag), and a third layer disposed on the second layer and including indium tin oxide (ITO).

[0136] In an embodiment, the anode AE ​​may include a crystalline structure. The anode AE ​​may have a crystalline structure. For example, the anode AE ​​may have a single crystal structure or a polycrystalline structure. In an embodiment, when the anode AE ​​includes a plurality of layers, at least one of the plurality of layers included in the anode AE ​​may include a crystalline structure. In an embodiment, the uppermost layer of the plurality of layers included in the anode AE ​​may include a crystalline structure. That is, among the plurality of layers included in the anode AE, a layer in contact with the sacrificial pattern SP may include a crystalline structure.

[0137] In an embodiment, the thickness of the anode AE ​​may be about to about For example, the thickness of the anode AE ​​may be about to about

[0138] In an embodiment, a sacrificial pattern SP may be arranged between the anode AE ​​and the pixel defining film PDL. The sacrificial pattern SP may correspond to a portion of a layer provided to prevent the anode AE ​​from being damaged in a process of forming a partition wall opening OP-P to be described later. A sacrificial opening OP-S exposing a portion of the upper surface of the anode AE ​​may be defined in the sacrificial pattern SP. The sacrificial opening OP-S may overlap with a light emitting opening OP-E to be described later.

[0139] In an embodiment, the pixel defining film PDL may be disposed on the fifth insulating layer 50 of the circuit element layer DP-CL. A light emitting opening OP-E may be defined in the pixel defining film PDL. The light emitting opening OP-E may correspond to the anode AE, and the pixel defining film PDL may expose at least a portion of the anode AE ​​through the light emitting opening OP-E.

[0140] In an embodiment, the light emitting opening OP-E may correspond to the sacrificial opening OP-S of the sacrificial pattern SP. According to an embodiment, the upper surface of the anode AE ​​may be spaced apart from the pixel defining film PDL in a cross-section with the sacrificial pattern SP interposed therebetween, and thus, in a process of forming the light emitting opening OP-E, damage to the anode AE ​​may be prevented.

[0141] In an embodiment, the sacrificial opening OP-S may have a first width W in one direction (eg, a fourth direction DR4) extending from a center of the sacrificial opening OP-S toward the peripheral area NPXA. s The light emitting opening OP-E may have a second width W in one direction (eg, a fourth direction DR4) extending from the center of the light emitting opening OP-E toward the peripheral area NPXA. p In an embodiment, the first width W s Can be smaller than the second width W p In forming the sacrificial pattern SP, the first width W of the sacrificial opening OP-S is sThe preliminary sacrificial pattern SP-I (see Figure 8G )'s etching rate, which will be described later.

[0142] In an embodiment, when the first width W of the sacrificial opening OP-S s A second width W greater than the light emitting opening OP-E p When the anode AE ​​and the pixel definition film PDL are formed, a gap may be formed between the anode AE ​​and the pixel definition film PDL, thereby causing image defects. s It needs to be controlled to be equal to or smaller than the second width W of the light emitting opening OP-E. p When the first width W of the sacrificial opening OP-S s The second width W of the light emitting opening OP-E is controlled to be equal to or smaller than the second width W of the light emitting opening OP-E. p Therefore, the display device DD (for example, referring to Figure 1A ) reliability.

[0143] In an embodiment, the area of ​​the sacrificial opening OP-S may be smaller than the area of ​​the light emitting opening OP-E on a plane. For example, the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S may be arranged closer to the center of the anode AE ​​than the inner side surface of the light emitting opening OP-E defining the pixel defining film PDL.

[0144] In an implementation, the light emitting opening OP-E may expose a portion of an upper surface of the sacrificial pattern SP. The portion of the upper surface of the sacrificial pattern SP exposed by the light emitting opening OP-E may make contact with the light emitting pattern EP.

[0145] In an embodiment, the sacrificial pattern SP includes a first metal, indium (In), and zinc (Zn). The sacrificial pattern SP may include a metal oxide including the first metal, indium, and zinc. The first metal includes at least one of tin and gallium.

[0146] In an embodiment, the sacrificial pattern SP may include a first metal-indium-zinc oxide. In an embodiment, the sacrificial pattern SP may include indium tin zinc oxide (ITZO). For example, the sacrificial pattern SP may be composed of indium tin zinc oxide (ITZO). In an embodiment, the sacrificial pattern SP may include indium gallium zinc oxide (IGZO). For example, the sacrificial pattern SP may be composed of indium gallium zinc oxide (IGZO). In another embodiment, the sacrificial pattern SP may include indium gallium tin zinc oxide (IGTZO). For example, the sacrificial pattern SP may be composed of indium gallium tin zinc oxide (IGTZO).

[0147] In an embodiment, the sacrificial pattern SP includes a first metal. The first metal may be an element included in a metal oxide layer including indium and zinc and thus affecting an etching rate characteristic. Among the constituent parts of the sacrificial pattern SP, the first metal may control the etching rate of the sacrificial pattern SP. The first metal included in the metal oxide layer including indium and zinc may reduce the etching rate. The etching rate may be adjusted by adjusting the percentage of the first metal included in the sacrificial pattern SP. In an embodiment, the first metal may be at least one of tin (Sn) and gallium (Ga). On the other hand, the elemental composition included in the sacrificial pattern SP may be inspected by ICP (inductively coupled plasma), XPS (X-ray photoelectron spectroscopy), SIMS (secondary ion mass spectrometry), etc.

[0148] In an embodiment, when the sacrificial pattern SP does not include the first metal, in the etching process of the sacrificial pattern SP, the etching rate of the metal oxide layer including indium and zinc may be increased, thereby forming a gap between the pixel defining film PDL and the anode AE. Such a gap may cause not only image defects but also defects in the display device. Since the sacrificial pattern SP includes the first metal, over-etching of the metal oxide layer is suppressed during the etching process of the sacrificial pattern SP, thereby preventing defects that may be caused by the gap.

[0149] In an embodiment, the content of the first metal relative to the total content of the metal elements included in the sacrificial pattern SP may be about 5at% or more. The content of the first metal relative to the total content of the first metal, indium and zinc included in the sacrificial pattern SP may be about 5at% or more. For example, the content of the first metal relative to the total content of the first metal, indium and zinc included in the sacrificial pattern SP may be about 5at% to about 30at%, preferably, about 18at% to about 25at%. When the content of the first metal is less than about 5at%, a gap may occur between the anode AE ​​and the pixel definition film PDL due to over-etching of the sacrificial pattern SP during the etching process. In addition, when the content of the first metal is greater than about 30at%, the etching rate may be excessively reduced and the etching uniformity may be deteriorated. When the content of the first metal satisfies the above-mentioned range, the etching rate is easily controlled, and defects such as gaps can be prevented in the etching process of the sacrificial pattern SP. In addition, considering the type, component ratio, etching characteristics, etc. of the material included in the anode AE, the content of the first metal included in the sacrificial pattern SP may be appropriately adjusted within the above-mentioned range.

[0150] In an embodiment, the content of indium may be about 35 to about 50 at% relative to the total content of metal elements included in the sacrificial pattern SP. The content of indium may be about 35 to about 50 at% relative to the total content of the first metal, indium, and zinc included in the sacrificial pattern SP.

[0151] In an embodiment, the content of zinc may be about 35 at % to about 50 at % relative to the total content of metal elements included in the sacrificial pattern SP. The content of zinc may be about 35 at % to about 50 at % relative to the total content of the first metal, indium, and zinc included in the sacrificial pattern SP.

[0152] In an implementation, a content ratio of indium to zinc in the sacrificial pattern SP may be about 4:6 to about 6:4. For example, a content ratio of indium to zinc in the sacrificial pattern SP may be about 5:5.

[0153] In an embodiment, the metal oxide included in the sacrificial pattern SP may have an amorphous structure. The atomic arrangement of the amorphous metal oxide may be disordered and may not have a crystal component. However, without being limited thereto, the sacrificial pattern SP may include a metal oxide having an amorphous structure and a crystal structure mixed together.

[0154] In an embodiment, the sacrificial pattern SP may include amorphous indium tin zinc oxide (a-ITZO), amorphous indium gallium zinc oxide (a-IGZO), or amorphous indium gallium tin zinc oxide (a-IGTZO). For example, the sacrificial pattern SP may be made of amorphous indium tin zinc oxide (a-ITZO), amorphous indium gallium zinc oxide (a-IGZO), or amorphous indium gallium tin zinc oxide (a-IGTZO).

[0155] In an embodiment, the crystallinity of the metal oxide included in the sacrificial pattern SP can be obtained by X-ray diffraction (XRD) analysis. For example, in the X-ray diffraction (XRD) analysis, the crystallinity of the metal oxide included in the sacrificial pattern SP can be obtained from the peak area of ​​the crystalline phase relative to the sum of the peak area of ​​the crystalline phase and the peak area of ​​the amorphous phase. In this case, the peak area of ​​the crystalline phase can be obtained from the total area of ​​the peak representing the crystalline phase in the X-ray diffraction (XRD) pattern. In addition, the peak area of ​​the amorphous phase may mean the area of ​​the halo pattern (Halo Pattern) in the X-ray diffraction (XRD) pattern. When the metal oxide included in the sacrificial pattern SP has an amorphous structure, the peak representing the crystalline phase may not be detected in the X-ray diffraction (XRD) pattern. That is, a sharp peak corresponding to a specific value of 2θ may not appear in the X-ray diffraction (XRD) pattern. In addition, when the metal oxide has an amorphous structure, a halo pattern corresponding to a wide, progressive peak can be seen in the X-ray diffraction (XRD) pattern.

[0156] In an embodiment, an etching rate of the sacrificial pattern SP and an etching rate of the anode AE ​​may be different from each other. The anode AE ​​may be configured to be etched at a first etching rate, and the sacrificial pattern SP may be configured to be etched at a second etching rate greater than the first etching rate. In an etching process of the sacrificial pattern SP to be described later, the anode AE ​​is not etched or may not be substantially etched due to an etching rate of the sacrificial pattern SP greater than the etching rate of the anode AE.

[0157] In an embodiment, the etching rate of the sacrificial pattern SP may be about or greater to less than about For example, the etching rate of the sacrificial pattern SP may be about to about The “etching rate” of the sacrificial pattern SP may refer to the amount of etching per second in the film thickness direction. The “etching rate” may refer to the etching rate at room temperature (25° C.). The unit of the etching rate can be expressed in The “etching rate” of the sacrificial pattern SP can be calculated by the following equation 1. The etching rate of the sacrificial pattern SP can be achieved by controlling the content of the metal included in the sacrificial pattern SP. For example, the etching rate of the sacrificial pattern SP can be achieved by controlling the content of the first metal relative to the total content of the metal elements included in the sacrificial pattern SP.

[0158] Etching rate = (T 1 -T 2 ) / S 1 [Equation 1]

[0159] In Equation 1, T 1 is the initial film thickness before etching, T 2 refers to the film thickness after etching, and S 1 The etching time using the etching solution is expressed in seconds.

[0160] In an embodiment, the etching rate of the sacrificial pattern SP can be controlled by changing the composition of the sacrificial pattern SP. The etching rate of the sacrificial pattern SP can be controlled by changing the composition of the metal element included in the sacrificial pattern SP. Specifically, the etching rate of the sacrificial pattern SP can be controlled by adjusting the content of the first metal, indium and zinc included in the sacrificial pattern SP. In particular, when the first metal is a factor controlling the etching rate of the sacrificial pattern SP, the more the amount of the first metal included in the sacrificial pattern SP, the slower the etching rate can be. For example, in a metal oxide layer including a first metal, indium and zinc, the higher the component ratio of the first metal, the slower the etching rate can be. By adding the first metal to the sacrificial pattern SP, it is possible to suppress the occurrence of a gap between the anode AE ​​and the pixel defining film PDL due to over-etching of the sacrificial pattern SP.

[0161] In an embodiment, the pixel defining layer PDL may include an inorganic insulating material. The pixel defining layer PDL may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). For example, the pixel definition layer PDL may include silicon nitride (SiN x ). A pixel defining film PDL may be disposed between the anode AE ​​and the partition wall PW to prevent the anode AE ​​and the partition wall PW from being electrically connected to each other.

[0162] In an embodiment, the partition wall PW may be disposed on the pixel defining film PDL. A partition wall opening OP-P may be defined in the partition wall PW. The partition wall opening OP-P may correspond to the light emitting opening OP-E and expose at least a portion of the anode AE.

[0163] In an embodiment, the partition wall PW may have an undercut shape in cross section. The partition wall PW may include a plurality of sequentially stacked layers, and at least one of the plurality of layers may be recessed compared to the other layers. At least one of the plurality of layers included in the partition wall PW may protrude compared to the other layers. Therefore, the partition wall PW may include a tip portion.

[0164] In an embodiment, the partition wall PW may include a first partition wall layer L1 and a second partition wall layer L2. The first partition wall layer L1 may be relatively recessed relative to the second partition wall layer L2 based on the emission area PXA. That is, the first partition wall layer L1 may be formed by undercutting relative to the second partition wall layer L2.

[0165] In an embodiment, the partition wall opening OP-P defined in the partition wall PW may include the first area A1 (see Fig.8F ) and the second area A2 (see Fig.8F ). The first partition wall layer L1 may include a first region A1 defining a partition wall opening OP-P (see Fig.8F ) of the first inner side surface S1-P of the portion, and the second partition wall layer L2 may include a second region A2 (see Fig.8F ) of the second inner side surface S2-P. In an embodiment, the first partition wall layer L1 may include a first region A1 defining a partition wall opening OP-P (see Fig.8F ) of the first inner side surface S1-P, and the second partition wall layer L2 may include a second area A2 (see Fig.8F )'s second inner surface S2-P.

[0166] In an embodiment, the first inner surface S1-P of the first partition wall layer L1 may be recessed inwardly relative to the second inner surface S2-P of the second partition wall layer L2. That is, the first inner surface S1-P may be formed by undercutting relative to the second inner surface S2-P. The second partition wall layer L2 protruding toward the light emitting area PXA may define a tip portion.

[0167] In an embodiment, the first area A1 (see Fig.8F ) may be different from the width of the second area A2 (see Fig.8F ) width. The first area A1 (see Fig.8F ) may be larger than the width of the second area A2 (see Fig.8F ) width. In this case, the second area A2 of the partition wall opening OP-P (see Fig.8F ) may be a region defining a tip portion.

[0168] In an embodiment, due to the definition of the second area A2 (see Fig.8F ) of the second partition wall layer L2 is smaller than the second inner side surface S2-P defining the first area A1 (see Fig.8F ) protrudes, so the second inner surface S2-P of the second partition wall layer L2 may be arranged adjacent to the center of the anode AE ​​(e.g., in a plan view). That is, compared with the first inner surface S1-P, the second inner surface S2-P may be arranged adjacent to the center of the anode AE ​​in one direction (e.g., in the fourth direction DR4).

[0169] In an embodiment, the partition wall PW may include a first partition wall layer L1 disposed on the pixel definition film PDL and a second partition wall layer L2 disposed on the first partition wall layer L1. The second partition wall layer L2 may be configured to be etched at a first etching rate, and the first partition wall layer L1 may be configured to be etched at a second etching rate higher than the first etching rate. In the undercut etching process, since the etching rate of the first partition wall layer L1 is higher than the etching rate of the second partition wall layer L2, the inner side surface of the first partition wall layer L1 may be etched more than the inner side surface of the second partition wall layer L2. In another embodiment, in the undercut etching process, the second partition wall layer L2 is not etched or may be substantially not etched.

[0170] In the embodiments and again referring to Figure 5A , the first partition wall layer L1 included in the partition wall PW may be disposed on the pixel defining film PDL. The first partition wall layer L1 may be directly disposed on the pixel defining film PDL.

[0171] In an embodiment, the first partition wall layer L1 includes a conductive material. The first partition wall layer L1 may include a low resistance metal. The first partition wall layer L1 may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), copper (Cu) or an alloy thereof. For example, the first partition wall layer L1 may include aluminum (Al). The thickness of the first partition wall layer L1 may be about 6000 angstroms to about 100000 angstroms.

[0172] In an embodiment, if Figure 5A As shown in FIG. 1 , the cathode CE contacts the first inner side surface S1 -P of the first partition wall layer L1 and may receive the second driving voltage ELVSS (see FIG. 1 ) from the first partition wall layer L1. Figure 3B ).

[0173] In an embodiment, the second partition wall layer L2 may be disposed on the first partition wall layer L1. The second partition wall layer L2 may be disposed directly on the first partition wall layer L1. The second partition wall layer L2 may define a tip portion formed in the partition wall PW. An upper surface of the second partition wall layer L2 may form the uppermost surface of the partition wall PW and define an upper surface of the tip portion formed in the partition wall PW.

[0174] In an embodiment, the second partition wall layer L2 may include a material having a lower conductivity than that of the first partition wall layer L1 but having high strength. The second partition wall layer L2 may include a material having a high Young's modulus of about 300 GPa or more. Since the second partition wall layer L2 includes a material having a high Young's modulus, the degree of deformation of the second partition wall layer L2 may be reduced. As the degree of deformation of the second partition wall layer L2 forming the uppermost surface of the tip portion is reduced, the robustness of the undercut shape of the partition wall PW may be increased. Therefore, the phenomenon that the tip portion of the partition wall PW sags may be reduced or eliminated, and the phenomenon that the tip portion blocks the inner side surface of the partition wall PW in contact with the cathode CE may be reduced or eliminated.

[0175] In an implementation, the second partition wall layer L2 may include a second metal or a silicon-based compound.

[0176] In an embodiment, the second partition wall layer L2 may include a second metal. The second metal included in the second partition wall layer L2 may include gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu), or an alloy thereof. The second partition wall layer L2 may include a metal material different from the metal material of the first partition wall layer L1. For example, the second partition wall layer L2 may include titanium (Ti). The thickness of the second partition wall layer L2 may be about 400 angstroms to about 800 angstroms.

[0177] In an embodiment, unlike the first partition wall layer L1, the second partition wall layer L2 may not include a metal material. The second partition wall layer L2 may include a silicon-based compound. The second partition wall layer L2 may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y ). The second partition wall layer L2 may include, for example, silicon oxide (SiO x ). Unlike the first partition wall layer L1, the second partition wall layer L2 does not contact the cathode CE and is configured to form a tip portion to separate the cathode CE into each light emitting area PXA, and thus, the second partition wall layer L2 may include a silicon-based compound as an insulating material.

[0178] In an embodiment, Figure 5A It is exemplarily shown that each of the first inner side surface S1 -P and the second inner side surface S2 -P is perpendicular to the upper surface of the pixel defining film PDL and extends in the third direction DR3 , but the present invention is not limited thereto. For example, the partition wall PW may have a tapered shape or an inverse tapered shape.

[0179] In an embodiment, the light emitting pattern EP may be arranged on the anode AE. The light emitting pattern EP may include a light emitting layer including a light emitting material. The light emitting pattern EP may further include a hole injection layer (HIL) and a hole transport layer (HTL) arranged between the anode AE ​​and the light emitting layer, and may further include an electron transport layer (ETL) and an electron injection layer (EIL) arranged on the light emitting layer. The light emitting pattern EP may also be referred to as an "organic layer" or an "intermediate layer".

[0180] In an embodiment, the light emitting pattern EP may be patterned by a tip portion defined in the partition wall PW. The light emitting pattern EP may be arranged inside the sacrificial opening OP-S, the light emitting opening OP-E, and the partition wall opening OP-P. The light emitting pattern EP may cover a portion of the upper surface of the pixel defining film PDL exposed from the partition wall opening OP-P.

[0181] In an implementation, the cathode CE may be disposed on the light emitting pattern EP. The cathode CE may be patterned by a tip portion defined in the partition wall PW. The cathode CE may contact the first inner side surface S1 -P of the first partition wall layer L1 .

[0182] In an embodiment, the partition wall PW may receive a second driving voltage ELVSS (see Figure 3B ), and accordingly, when the cathode CE is electrically connected to the partition wall PW, the cathode CE may receive the second driving voltage ELVSS (see Figure 3B ).

[0183] According to an embodiment, the display panel DP may further include a cover pattern CP. The cover pattern CP may be disposed in the partition wall opening OP-P and may be disposed on the cathode CE. The cover pattern CP may be patterned by a tip portion formed in the partition wall PW.

[0184] although Figure 5A An embodiment in which the cover pattern CP does not contact the second inner surface S2-P of the second partition wall layer L2 is exemplarily shown, but the present invention is not limited thereto. For example, in an embodiment, the cover pattern CP may be formed to contact the second inner surface S2-P of the second partition wall layer L2. According to another embodiment, the cover pattern CP may be omitted.

[0185] In an embodiment, the dummy pattern DMP may be arranged on the partition wall PW. The dummy pattern DMP may include a first dummy pattern D1, a second dummy pattern D2, and a third dummy pattern D3. The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may be sequentially stacked on the upper surface of the second partition wall layer L2 of the partition wall PW along the third direction DR3.

[0186] In an embodiment, the first dummy pattern D1 may include an organic material. For example, the first dummy pattern D1 may include the same material as the light emitting pattern EP. The first dummy pattern D1 may be formed synchronously with the light emitting pattern EP through one process and may be formed separately from the light emitting pattern EP through the undercut shape of the partition wall PW.

[0187] In an embodiment, the second dummy pattern D2 may include a conductive material. For example, the second dummy pattern D2 may include the same material as the cathode CE. The second dummy pattern D2 may be formed synchronously with the cathode CE through one process and may be formed separately from the cathode CE through the undercut shape of the partition wall PW.

[0188] In an embodiment, the third dummy pattern D3 may include the same material as the capping pattern CP. The third dummy pattern D3 may be formed simultaneously with the capping pattern CP through one process, and may be formed separately from the capping pattern CP by an undercut shape of the partition wall PW.

[0189] In an embodiment, a dummy opening OP-D may be defined in the dummy pattern DMP. The dummy opening OP-D may correspond to the light emitting opening OP-E. The dummy opening OP-D may include first opening areas AA1 (see FIG. 1 ) sequentially arranged in the third direction DR3. Fig.8I ), the second opening area AA2 (see Fig.8I ) and the third opening area AA3 (see Fig.8I). A first opening area AA1 of the dummy opening OP-D may be defined by an inner side surface S1-D of the first dummy pattern D1, a second opening area AA2 may be defined by an inner side surface S2-D of the second dummy pattern D2, and a third opening area AA3 may be defined by an inner side surface S3-D of the third dummy pattern D3. On a plane, each of the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may have a closed line shape surrounding the light emitting area PXA.

[0190] In an embodiment, Figure 5A It is exemplarily shown that the inner surface S1-D of the first dummy pattern D1, the inner surface S2-D of the second dummy pattern D2, and the inner surface S3-D of the third dummy pattern D3 are aligned with the second inner surface S2-P of the second partition wall layer L2, but the present invention is not limited to this, and the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may cover the second inner surface S2-P of the second partition wall layer L2.

[0191] In an implementation, a thin film encapsulation layer TFE may be disposed on the display element layer DP-OLED. The thin film encapsulation layer TFE may include a lower inorganic encapsulation pattern LIL, an organic encapsulation film OL, and an upper inorganic encapsulation film UIL.

[0192] In an embodiment, the lower inorganic encapsulation pattern LIL may correspond to the light emitting opening OP-E. The lower inorganic encapsulation pattern LIL may cover the light emitting element ED and the dummy pattern DMP, and a portion of the lower inorganic encapsulation pattern LIL may be arranged in the partition wall opening OP-P. According to an embodiment, the lower inorganic encapsulation pattern LIL may contact each of the first inner side surface S1-P of the first partition wall layer L1 and the second inner side surface S2-P of the second partition wall layer L2.

[0193] In an implementation, the organic encapsulation film OL may cover the lower inorganic encapsulation pattern LIL and provide a flat upper surface. The upper inorganic encapsulation film UIL may be disposed on the organic encapsulation film OL.

[0194] In an embodiment, the lower inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation film OL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0195] Figure 5B is a cross-sectional view of a display panel according to an embodiment. Figure 5B According to an embodiment, Figure 4 In the following, in reference to Figure 5B The display panel DP according to the embodiment is described in detail. Figure 5AThe same components as those described in will be given the same reference numerals, and their detailed description will be omitted. Figure 5B is the display area DA (see Figure 4 ) is an enlarged view of an embodiment of a light emitting area PXA in FIG. , and Figure 5B The light emitting area PXA may correspond to Figure 4 any one of the first light emitting area PXA-R, the second light emitting area PXA-G and the third light emitting area PXA-B.

[0196] In the embodiments and with reference to Figure 5B , when Figure 5A When compared with the display panel DP shown in , the display panel DP has a difference in that the inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S is aligned with the inner side surface of the pixel defining film PDL defining the light emitting opening OP-E.

[0197] In the embodiments and with reference to Figure 5B , the first width of the sacrificial opening OP-S defined in the sacrificial pattern SP may be substantially equal to the second width of the light emitting opening OP-E defined in the pixel defining film PDL. The first width may refer to the width of the sacrificial opening OP-S passing through the center of the sacrificial opening OP-S in the fourth direction DR4. The second width may refer to the width of the light emitting opening OP-E passing through the center of the light emitting opening OP-E in the fourth direction DR4. In forming the sacrificial pattern SP, the first width of the sacrificial pattern SP may be obtained by forming the preliminary sacrificial pattern SP-I (see Figure 8G )'s etching rate, which will be described later.

[0198] In an embodiment, when the first width of the sacrificial opening OP-S is greater than the second width of the light emitting opening OP-E, a gap may be formed between the anode AE ​​and the pixel defining film PDL, thereby causing image defects or the like. s (For example, see Figure 5A ) needs to be controlled to be equal to or less than the second width W of the light emitting opening OP-E p (For example, see Figure 5A ). When the first width W of the sacrificial opening OP-S s The second width W of the light emitting opening OP-E is controlled to be equal to or smaller than the second width W of the light emitting opening OP-E. p When the display device DD is formed, defects due to the occurrence of voids can be prevented. Therefore, the reliability of the display device DD can be further improved.

[0199] In an embodiment, on a plane, an area of ​​the sacrificial opening OP-S may be substantially equal to an area of ​​the light emitting opening OP-E. An inner side surface of the sacrificial pattern SP defining the sacrificial opening OP-S and an inner side surface of the pixel defining film PDL defining the light emitting opening OP-E may be aligned with each other in the third direction DR3.

[0200] Figure 6 is a cross-sectional view of a display panel according to an embodiment. Figure 6 is along Figure 4 A cross-sectional view taken along line II-II'. Figure 6 is an enlarged view of a first light emitting area PXA-R, a second light emitting area PXA-G, and a third light emitting area PXA-B, and Figure 5A The description of the light emitting area PXA of FIG. 1 may be equally applied to each of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B.

[0201] In the embodiments and with reference to Figure 6 , the display panel DP may include a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED, and a thin film encapsulation layer TFE. The display element layer DP-OLED may include light emitting elements ED1, ED2, and ED3, sacrificial patterns SP1, SP2, and SP3, a pixel defining film PDL, a partition wall PW, and a dummy pattern DMP. On the other hand, each of the sacrificial patterns SP1, SP2, and SP3 may include Figure 5A or Figure 5B The components of the sacrificial pattern SP described in the foregoing are substantially the same as those of the foregoing. Figure 5A and Figure 5B The contents described for the sacrificial pattern SP in 2004 are equally applicable to the sacrificial patterns SP1, SP2, and SP3.

[0202] In an embodiment, the light emitting elements ED1, ED2, and ED3 may include a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3. The first light emitting element ED1 may include a first anode AE1, a first light emitting pattern EP1, and a first cathode CE1. The second light emitting element ED2 may include a second anode AE2, a second light emitting pattern EP2, and a second cathode CE2. The third light emitting element ED3 may include a third anode AE3, a third light emitting pattern EP3, and a third cathode CE3. The first anode AE1, the second anode AE2, and the third anode AE3 may be provided in a plurality of patterns. In an embodiment, the first light emitting pattern EP1 may provide red light, the second light emitting pattern EP2 may provide green light, and the third light emitting pattern EP3 may provide blue light.

[0203] In an embodiment, a first light emitting opening OP1-E, a second light emitting opening OP2-E, and a third light emitting opening OP3-E may be defined in the pixel defining film PDL. The first light emitting opening OP1-E may expose at least a portion of the first anode AE1. The first light emitting region PXA-R may be defined as a region exposed by the first light emitting opening OP1-E in the upper surface of the first anode AE1. The second light emitting opening OP2-E may expose at least a portion of the second anode AE2. The second light emitting region PXA-G may be defined as a region exposed by the second light emitting opening OP2-E in the upper surface of the second anode AE2. The third light emitting opening OP3-E may expose at least a portion of the third anode AE3. The third light emitting region PXA-B may be defined as a region exposed by the third light emitting opening OP3-E in the upper surface of the third anode AE3.

[0204] In an embodiment, the sacrificial patterns SP1, SP2, and SP3 may include a first sacrificial pattern SP1, a second sacrificial pattern SP2, and a third sacrificial pattern SP3. The first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3 may be arranged on the upper surfaces of the first anode AE1, the second anode AE2, and the third anode AE3, respectively. A first sacrificial opening OP1-S, a second sacrificial opening OP2-S, and a third sacrificial opening OP3-S corresponding to the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, may be defined in the first sacrificial pattern SP1, the second sacrificial pattern SP2, and the third sacrificial pattern SP3.

[0205] In an embodiment, the widths of the first sacrificial opening OP1-S, the second sacrificial opening OP2-S, and the third sacrificial opening OP3-S may be smaller than the widths of the corresponding first light-emitting opening OP1-E, the second light-emitting opening OP2-E, and the third light-emitting opening OP3-E. The width of the first sacrificial opening OP1-S passing through the center of the first sacrificial opening OP1-S in one direction may be smaller than the width of the first light-emitting opening OP1-E passing through the center of the first light-emitting opening OP1-E in one direction. The width of the second sacrificial opening OP2-S passing through the center of the second sacrificial opening OP2-S in one direction may be smaller than the width of the second light-emitting opening OP2-E passing through the center of the second light-emitting opening OP2-E in one direction. The width of the third sacrificial opening OP3-S passing through the center of the third sacrificial opening OP3-S in one direction may be smaller than the width of the third light-emitting opening OP3-E passing through the center of the third light-emitting opening OP3-E in one direction. In forming the first, second and third sacrificial patterns SP1, SP2 and SP3, the width of each of the first, second and third sacrificial openings OP1-S, OP2-S and OP3-S may be adjusted by an etching rate of a corresponding one of the first, second and third sacrificial patterns SP1, SP2 and SP3.

[0206] In an embodiment, on a plane, the areas of the first sacrificial opening OP1-S, the second sacrificial opening OP2-S, and the third sacrificial opening OP3-S may be equal to or smaller than the areas of the corresponding first light-emitting opening OP1-E, the second light-emitting opening OP2-E, and the third light-emitting opening OP3-E. On a plane, the area of ​​the first sacrificial opening OP1-S may be equal to or smaller than the area of ​​the first light-emitting opening OP1-E. On a plane, the area of ​​the second sacrificial opening OP2-S may be equal to or smaller than the area of ​​the second light-emitting opening OP2-E. On a plane, the area of ​​the third sacrificial opening OP3-S may be equal to or smaller than the area of ​​the third light-emitting opening OP3-E.

[0207] In an embodiment, each of the inner side surfaces of the first sacrificial pattern SP1 defining the first sacrificial opening OP1-S, the second sacrificial pattern SP2 defining the second sacrificial opening OP2-S, and the third sacrificial pattern SP3 defining the third sacrificial opening OP3-S may be comparable to the light emitting opening OP-E defined by the pixel defining film PDL (for example, refer to Figure 5A , and it may refer to the inner side surface of a corresponding one of the first light emitting opening OP1-E, the second light emitting opening OP2-E and the third light emitting opening OP3-E) close to the anode AE ​​(for example, refer to Figure 5A, and it may refer to the center of a corresponding one of the first anode AE1, the second anode AE2, and the third anode AE3). In another embodiment, each of the inner side surfaces of the first sacrificial pattern SP1 defining the first sacrificial opening OP1-S, the second sacrificial pattern SP2 defining the second sacrificial opening OP2-S, and the third sacrificial pattern SP3 defining the third sacrificial opening OP3-S may be aligned with the light emitting opening OP-E defined by the pixel defining film PDL (for example, refer to Figure 5A , and it may refer to the alignment of the inner side surface of a corresponding one of the first light emitting opening OP1-E, the second light emitting opening OP2-E and the third light emitting opening OP3-E).

[0208] In an embodiment, the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E may expose portions of the upper surfaces of the corresponding first sacrificial opening OP1-S, the second sacrificial opening OP2-S, and the third sacrificial opening OP3-S. The first light emitting opening OP1-E may expose portions of the upper surface of the first sacrificial opening OP1-S. The upper surface of the first sacrificial opening OP1-S exposed by the first light emitting opening OP1-E may contact the first light emitting pattern EP1. The second light emitting opening OP2-E may expose portions of the upper surface of the second sacrificial opening OP2-S. The upper surface of the second sacrificial opening OP2-S exposed by the second light emitting opening OP2-E may contact the second light emitting pattern EP2. The third light emitting opening OP3-E may expose portions of the upper surface of the third sacrificial opening OP3-S. The upper surface of the third sacrificial opening OP3-S exposed by the third light emitting opening OP3-E may contact the third light emitting pattern EP3.

[0209] In an embodiment, a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P, respectively corresponding to the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, may be defined in the partition wall PW. Each of the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P may include the above Figure 5A The first area A1 described in Fig.8F ) and the second area A2 (see Fig.8F ). The first partition wall layer L1 may include a first inner side surface S1-P of a portion of the first area A1 defining the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P (see Figure 5A ). The second partition wall layer L2 may include a second inner side surface S2-P of the second area A2 defining the first partition wall opening OP1-P, the second partition wall opening OP2-P, and the third partition wall opening OP3-P (see Figure 5A). In an embodiment, the first partition wall layer L1 may include a first inner side surface S1-P of a first area A1 defining a first partition wall opening OP1-P, a second partition wall opening OP2-P, and a third partition wall opening OP3-P (see Figure 5A ).

[0210] In an embodiment, the first light emitting pattern EP1 and the first cathode CE1 may be arranged in the first partition wall opening OP1-P, the second light emitting pattern EP2 and the second cathode CE2 may be arranged in the second partition wall opening OP2-P, and the third light emitting pattern EP3 and the third cathode CE3 may be arranged in the third partition wall opening OP3-P. Each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 may contact the first inner side surface S1-P of the first partition wall layer L1.

[0211] In an embodiment, the first cathode CE1, the second cathode CE2, and the third cathode CE3 are physically separated by the second partition wall layer L2 forming the tip portion, are respectively formed in the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, and are electrically connected to each other by contacting with the first partition wall layer L1, so that they can receive a common voltage. The first partition wall layer L1 contacting each of the first cathode CE1, the second cathode CE2, and the third cathode CE3 has a higher conductivity than the second partition wall layer L2, and therefore, it is possible to reduce the contact resistance with the first cathode CE1, the second cathode CE2, and the third cathode CE3. Therefore, the common cathode voltage (which may refer to the common voltage mentioned above) can be uniformly provided to the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B.

[0212] According to an embodiment, a plurality of light emitting patterns EP1, EP2, and EP3 may be patterned by a tip portion defined in a partition wall PW and deposited in each pixel unit. That is, a plurality of light emitting patterns EP1, EP2, and EP3 are not commonly formed by using an open mask, but they can be easily divided in each pixel unit by a partition wall PW.

[0213] In an embodiment, when a plurality of light emitting patterns EP1, EP2, and EP3 are patterned by using a fine metal mask (FMM), a support spacer protruding from a conductive partition wall should be provided to support the fine metal mask. In addition, since the fine metal mask is spaced apart from the base surface where patterning is performed by a height as large as the height of the partition wall and the support spacer, there may be limitations in achieving high resolution. In addition, since the fine metal mask is in contact with the support spacer, after the patterning process of the plurality of light emitting patterns EP1, EP2, and EP3, foreign matter may remain on the support spacer, or the support spacer may be damaged by being punctured by the fine metal mask. Therefore, a defective display panel may be formed.

[0214] According to the embodiment, since the partition wall PW is included, physical separation between the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3 can be easily achieved. Therefore, it is possible not only to prevent current leakage or driving error between the adjacent first light emitting areas PXA-R, second light emitting areas PXA-G, and third light emitting areas PXA-B, but also to independently drive each of the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3.

[0215] In an embodiment, by not having a connection with the display area DA (see Figure 1B ), the defect rate can be reduced, thereby making it possible to provide a display panel DP with improved process reliability. Since patterning is possible even when a separate supporting spacer protruding from the partition wall PW is not provided, the areas of the first light emitting area PXA-R, the second light emitting area PXA-G, and the third light emitting area PXA-B can be minimized, and therefore, it is possible to provide a display panel DP that can easily achieve high resolution.

[0216] In an embodiment, when manufacturing a display panel DP having a large area, process cost may be reduced by omitting manufacturing of a mask having a large area, and it is possible to provide a display panel DP having improved process reliability by not being affected by defects that may occur in the large area mask.

[0217] In an embodiment, the cover patterns CP1, CP2, and CP3 may include a first cover pattern CP1, a second cover pattern CP2, and a third cover pattern CP3. The first cover pattern CP1, the second cover pattern CP2, and the third cover pattern CP3 may be disposed on the first cathode CE1 in the first partition wall opening OP1-P, the second cathode CE2 in the second partition wall opening OP2-P, and the third cathode CE3 in the third partition wall opening OP3-P, respectively.

[0218] In an implementation, the dummy pattern DMP may include a plurality of first dummy patterns D1 , a plurality of second dummy patterns D2 , and a plurality of third dummy patterns D3 .

[0219] In an embodiment, the first dummy pattern D1 may include a (1-1)th dummy pattern D11, a (1-2)th dummy pattern D12, and a (1-3)th dummy pattern D13 surrounding the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 on a plane, respectively. The (1-1)th dummy pattern D11, the (1-2)th dummy pattern D12, and the (1-3)th dummy pattern D13 may include the same materials as the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3, respectively, and may be formed by the same process as the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3.

[0220] In an embodiment, the second dummy pattern D2 may include a (2-1)th dummy pattern D21, a (2-2)th dummy pattern D22, and a (2-3)th dummy pattern D23 surrounding the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 on a plane, respectively. The (2-1)th dummy pattern D21, the (2-2)th dummy pattern D22, and the (2-3)th dummy pattern D23 may include the same materials as the first cathode CE1, the second cathode CE2, and the third cathode CE3, respectively, and may be formed by the same process as the first cathode CE1, the second cathode CE2, and the third cathode CE3.

[0221] In an embodiment, the third dummy pattern D3 may include a (3-1)th dummy pattern D31, a (3-2)th dummy pattern D32, and a (3-3)th dummy pattern D33 surrounding the first light emitting pattern EP1, the second light emitting pattern EP2, and the third light emitting pattern EP3 on a plane, respectively. The (3-1)th dummy pattern D31, the (3-2)th dummy pattern D32, and the (3-3)th dummy pattern D33 may include the same materials as the first covering pattern CP1, the second covering pattern CP2, and the third covering pattern CP3, respectively, and may be formed by the same process as the first covering pattern CP1, the second covering pattern CP2, and the third covering pattern CP3.

[0222] In an embodiment, a first dummy opening OP1-D, a second dummy opening OP2-D, and a third dummy opening OP3-D corresponding to the first light emitting opening OP1-E, the second light emitting opening OP2-E, and the third light emitting opening OP3-E, respectively, may be defined in the dummy pattern DMP. Each of the first dummy opening OP1-D, the second dummy opening OP2-D, and the third dummy opening OP3-D may include a first opening area AA1 sequentially arranged in the third direction DR3 (see Fig.8I), the second opening area AA2 (see Fig.8I ) and the third opening area AA3 (see Fig.8I ). The first dummy opening OP1-D may be defined by the inner surfaces of the (1-1)th dummy pattern D11, the (2-1)th dummy pattern D21, and the (3-1)th dummy pattern D31, the second dummy opening OP2-D may be defined by the inner surfaces of the (1-2)th dummy pattern D12, the (2-2)th dummy pattern D22, and the (3-2)th dummy pattern D32, and the third dummy opening OP3-D may be defined by the inner surfaces of the (1-3)th dummy pattern D13, the (2-3)th dummy pattern D23, and the (3-3)th dummy pattern D33.

[0223] In an embodiment, the thin film encapsulation layer TFE may include lower inorganic encapsulation patterns LIL1, LIL2 and LIL3, an organic encapsulation film OL and an upper inorganic encapsulation film UIL. In an embodiment, the lower inorganic encapsulation patterns LIL1, LIL2 and LIL3 may include a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2 and a third lower inorganic encapsulation pattern LIL3. The first lower inorganic encapsulation pattern LIL1, the second lower inorganic encapsulation pattern LIL2 and the third lower inorganic encapsulation pattern LIL3 may correspond to the first light emitting opening OP1-E, the second light emitting opening OP2-E and the third light emitting opening OP3-E, respectively. In addition, in Figure 6 In the embodiment, a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2, and a third lower inorganic encapsulation pattern LIL3 may be included in the lower inorganic encapsulation pattern LIL.

[0224] In an embodiment, the first lower inorganic encapsulation pattern LIL1 may cover the first light emitting element ED1 and the (1-1)th dummy pattern D11, the (2-1)th dummy pattern D21, and the (3-1)th dummy pattern D31, and a portion of the first lower inorganic encapsulation pattern LIL1 may be arranged inside the first partition wall opening OP1-P. The second lower inorganic encapsulation pattern LIL2 may cover the second light emitting element ED2 and the (1-2)th dummy pattern D12, the (2-2)th dummy pattern D22, and the (3-2)th dummy pattern D32, and a portion of the second lower inorganic encapsulation pattern LIL2 may be arranged inside the second partition wall opening OP2-P. The third lower inorganic encapsulation pattern LIL3 may cover the third light emitting element ED3 and the (1-3)th dummy pattern D13, the (2-3)th dummy pattern D23, and the (3-3)th dummy pattern D33, and a portion of the third lower inorganic encapsulation pattern LIL3 may be arranged inside the third partition wall opening OP3-P. The first lower inorganic encapsulation pattern LIL1 , the second lower inorganic encapsulation pattern LIL2 , and the third lower inorganic encapsulation pattern LIL3 may be provided in the form of patterns spaced apart from each other.

[0225] Figure 7According to the implementation method Figure 3A A cross-sectional view of the display panel taken along line III-III'.

[0226] Figure 7 1 is an enlarged view showing a display panel DP including a non-display area NDA and a display area DA arranged adjacent to the non-display area NDA. The same / similar reference numerals will be used with reference to Figures 1A to 6 The components described are the same / similar components, and duplicate description will be omitted.

[0227] In the embodiments and with reference to Figure 7 , the second driving voltage line VL2 may be arranged in the non-display area NDA. In an embodiment, the second driving voltage line VL2 may include a plurality of layers. For example, the second driving voltage line VL2 may include a first electrode layer SD1 and a second electrode layer SD2.

[0228] In an embodiment, the first electrode layer SD1 may be disposed on the third insulating layer 30. The first electrode layer SD1 may be formed by the same process as the first connection electrode CNE1, include the same material as the first connection electrode CNE1, and have the same structure as the first connection electrode CNE1. At least a portion of the first electrode layer SD1 may be exposed from the fourth insulating layer 40, the fifth insulating layer 50, and the pixel defining film PDL.

[0229] In an embodiment, the second electrode layer SD2 may cover an end portion of the fourth insulating layer 40 and be disposed on the first electrode layer SD1 exposed from the fourth insulating layer 40. That is, the second electrode layer SD2 is disposed in contact with an upper surface of the first electrode layer SD1 and thus may be electrically connected to the first electrode layer SD1. The second electrode layer SD2 may be formed by the same process as the second connection electrode CNE2, include the same material as the second connection electrode CNE2, and have the same structure as the second connection electrode CNE2.

[0230] However, not limited thereto, in an embodiment, the second driving voltage line VL2 may include only one of the first electrode layer SD1 and the second electrode layer SD2 .

[0231] In an embodiment, an auxiliary electrode AE-A may be arranged on the second driving voltage line VL2. Specifically, the auxiliary electrode AE-A may cover an end of the fifth insulating layer 50 and be arranged on the second electrode layer SD2. That is, the auxiliary electrode AE-A is arranged to contact the upper surface of the second electrode layer SD2, and thus may be electrically connected to the second driving voltage line VL2. The auxiliary electrode AE-A may be formed by the same process as the anode AE, include the same material as the anode AE, and have the same configuration as the anode AE. In an embodiment, the auxiliary electrode AE-A may include ITO / Ag / ITO.

[0232] In an embodiment, the partition wall PW may overlap the non-display area NDA. The partition wall PW may extend from the display area DA to a portion of the non-display area NDA where the second driving voltage line VL2 is arranged. The partition wall PW may directly contact the auxiliary electrode AE-A arranged on the second driving voltage line VL2. Therefore, the partition wall PW may receive the second driving voltage ELVSS (see FIG. 1 ) from the second driving voltage line VL2 through the auxiliary electrode AE-A. Figure 3B ), and the cathode CE in contact with the partition wall PW in the display area DA may receive the second driving voltage ELVSS through the partition wall PW (see Figure 3B According to an embodiment, due to the second driving voltage ELVSS (see Figure 3B ) is transferred to the cathode CE through the partition wall PW having a relatively large thickness, and thus a voltage drop phenomenon can be reduced.

[0233] In an embodiment, the scan driver SDV may include a pixel circuit PDC (see Figure 3B )'s conductive pattern is formed by the same process into multiple thin film transistors. Figure 7 It is exemplarily shown that the thin film transistors constituting the scan driver SDV according to the embodiment are arranged on the third insulating layer 30 .

[0234] In an embodiment, a dam DMM may be arranged in the non-display area NDA. The dam DMM may be composed of a plurality of insulating layers. For example, the dam DMM may include a first layer formed in the same process as the fourth insulating layer 40, a second layer formed in the same process as the fifth insulating layer 50, and a third layer formed in the same process as the pixel definition film PDL. However, it is not limited thereto. Figure 7 Different from that shown in , in an embodiment, the dam DMM may be composed of a single layer or two layers, or the dam DMM may include four or more layers.

[0235] In an embodiment, the lower inorganic encapsulation pattern LIL, the organic encapsulation film OL, and the upper inorganic encapsulation film UIL may be arranged in the non-display area NDA. The organic encapsulation film OL may extend from the display area DA to the area where the dam DMM is arranged. When the organic encapsulation film OL is formed, the dam DMM may play a role in controlling the flow of the monomer. The lower inorganic encapsulation pattern LIL and the upper inorganic encapsulation film UIL may extend from the display area DA to the area where the dam DMM is arranged to cover the dam DMM, and may contact each other on the dam DMM to seal the organic encapsulation film OL.

[0236] In an embodiment, the display panel DP may further include an additional auxiliary electrode AE-A'. The additional auxiliary electrode AE-A' may contact the first partition wall layer L1 of the partition wall PW. By this, it is possible to increase the area in which the first partition wall layer L1 contacts the electrode providing the driving voltage and reduce the contact resistance of the first partition wall layer L1. The additional auxiliary electrode AE-A' may be formed in the same process as the anode AE, include the same material as the anode AE, and have the same configuration as the anode AE. In another embodiment, the additional auxiliary electrode AE-A' may be omitted.

[0237] FIG. 8A to FIG. 8L is a cross-sectional view showing steps of a method for manufacturing a display panel according to an embodiment. FIG. 8A to FIG. 8L The same / similar reference numerals will be used when referring to Figures 1A to 7 The components described are the same / similar components, and duplicate description will be omitted.

[0238] In an embodiment, a method for manufacturing a display panel (which may also be referred to herein as a method for manufacturing a display panel) may include: forming an anode on a base layer; forming a preliminary sacrificial pattern on the anode including a metal oxide containing indium, zinc, and a first metal including at least one of tin and gallium; forming a preliminary pixel defining film covering the anode and the preliminary sacrificial pattern; forming a preliminary partition wall on the preliminary pixel defining film; etching the preliminary partition wall to form a partition wall having a partition wall opening defined therein; etching the preliminary pixel defining film to form a pixel defining film having a light emitting opening defined therein and overlapping with the partition wall opening; etching the preliminary sacrificial pattern to form a sacrificial pattern having a sacrificial opening defined therein and overlapping with the partition wall opening; and forming a cathode in the partition wall opening in contact with the light emitting pattern and the partition wall.

[0239] In the embodiments and with reference to Fig. 8A , the method of manufacturing a display panel may include providing a preliminary display panel DP-I. The preliminary display panel DP-I may include a base layer BL, a circuit element layer DP-CL, an anode AE, a preliminary sacrificial pattern SP-I, and a preliminary pixel definition film PDL-I.

[0240] In an embodiment, providing the preliminary display panel DP-I may include: forming an anode AE ​​on the base layer BL; forming a preliminary sacrificial pattern SP-I on the anode AE; and forming a preliminary pixel defining film PDL-I covering the anode AE ​​and the preliminary sacrificial pattern SP-I. In addition, providing the preliminary display panel DP-I may further include forming a circuit element layer DP-CL on the base layer BL before forming the anode AE.

[0241] In an embodiment, in the circuit element layer DP-CL, an insulating layer, a semiconductor layer, and a conductive layer may be formed by methods such as coating and deposition, and then the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned by photolithography and etching processes to form semiconductor patterns, conductive patterns, signal lines, and the like.

[0242] In an implementation, the anode AE ​​may be formed on the circuit element layer DP-CL. The anode AE ​​may be formed by using various methods such as a deposition process or a sputtering process.

[0243] In an embodiment, a preliminary sacrificial pattern SP-I may be formed on the anode AE. The preliminary sacrificial pattern SP-I may be formed by using various methods such as a deposition process or a sputtering process. The preliminary sacrificial pattern SP-I may be directly disposed on the anode AE. The lower surface of the preliminary sacrificial pattern SP-I may contact the upper surface of the anode AE.

[0244] In an embodiment, the preliminary sacrificial pattern SP-I may include a first metal, indium, and zinc. Figure 5A The description given of the first metal may be equally applied to the first metal included in the preliminary sacrificial pattern SP-I. The anode AE ​​and the preliminary sacrificial pattern SP-I may be formed through the same patterning process as each other.

[0245] In an implementation, a preliminary pixel defining film PDL-I may be formed on the anode electrode AE ​​and the preliminary sacrificial pattern SP-I. The preliminary pixel defining film PDL-I may cover both the anode electrode AE ​​and the preliminary sacrificial pattern SP-I.

[0246] Reference Figure 8B According to an embodiment, a method for manufacturing a display panel may include forming a first preliminary partition wall layer L1-I on a preliminary pixel defining film PDL-I. The formation of the first preliminary partition wall layer L1-I may be performed by a deposition process of a conductive material. In an embodiment, the conductive material forming the first preliminary partition wall layer L1-I may include a low-resistance metal. For example, the conductive material forming the first preliminary partition wall layer L1-I may be gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), copper (Cu), or an alloy thereof. The conductive material forming the first preliminary partition wall layer L1-I may be aluminum (Al).

[0247] In the embodiments and with reference to Figure 8C , the method of manufacturing a display panel may include forming a second preliminary partition wall layer L2-I on the first preliminary partition wall layer L1-I to form a preliminary partition wall PW-I.

[0248] In an embodiment, the formation of the second preliminary partition wall layer L2-I may be performed by a deposition process of a conductive material. In an embodiment, the conductive material forming the second preliminary partition wall layer L2-I may be a metal material. For example, the conductive material forming the second preliminary partition wall layer L2-I may be gold (Au), silver (Ag), aluminum (Al), magnesium (Mg), lithium (Li), molybdenum (Mo), titanium (Ti), copper (Cu) or an alloy thereof. The metal forming the second preliminary partition wall layer L2-I may be different from the metal forming the first preliminary partition wall layer L1-I. For example, the metal forming the second preliminary partition wall layer L2-I may be titanium (Ti).

[0249] In an embodiment, the second preliminary partition wall layer L2-I may not include a metal material. The second preliminary partition wall layer L2-I may be formed of a silicon-based compound. For example, the second preliminary partition wall layer L2-I may include silicon oxide (SiO x ), silicon nitride (SiN x ) and silicon oxynitride (SiO x N y )

[0250] In an implementation, the preliminary partition wall PW-I may include a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I.

[0251] In the embodiments and with reference to FIG. 8D to FIG. 8F , a method of manufacturing a display panel may include etching a preliminary partition wall PW-I to form a partition wall PW having a partition wall opening OP-P defined therein. The formation of the partition wall PW may include forming a first photoresist layer PR1 on the preliminary partition wall PW-I and etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I.

[0252] In the embodiments and with reference to Fig.8D , a method of manufacturing a display panel may include forming a first photoresist layer PR1 on a preliminary partition wall PW-I. The first photoresist layer PR1 may be formed by forming a preliminary photoresist layer on the preliminary partition wall PW-I and then patterning the preliminary photoresist layer by using a photomask. Through the patterning process, an optical opening OP-PR overlapping the anode AE ​​may be formed in the first photoresist layer PR1.

[0253] In the embodiments and with reference to Fig. 8E and Fig.8F, the method of manufacturing a display panel may include etching a first preliminary partition wall layer L1-I and a second preliminary partition wall layer L2-I to form a partition wall PW from the preliminary partition wall PW-I. The etching of the preliminary partition wall PW-I may be performed twice. The etching of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include a primary etching step and a secondary etching step.

[0254] In the embodiments and with reference to Fig. 8E The primary etching step of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I may include dry etching the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I by using the first photoresist layer PR1 as a mask. Since the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I are formed of a metal material, the primary dry etching process can be easily performed.

[0255] In an embodiment, the primary dry etching process may be performed in an etching environment in which the etching selectivities of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I are substantially the same as each other. Therefore, the inner side surfaces of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I defining the preliminary partition wall opening OP-PI may be substantially aligned with each other.

[0256] In the embodiments and with reference to Fig.8F , after the primary etching step of the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I, a secondary etching step of the first preliminary partition wall layer L1-I may be performed. The secondary etching step of the first preliminary partition wall layer L1-I may include forming a partition wall opening OP-P by wet etching the first preliminary partition wall layer L1-I using the first photoresist layer PR1 as a mask. In this specification, the secondary etching step of the first preliminary partition wall layer L1-I may be referred to as an “undercut etching process”.

[0257] In the embodiments and with reference to Figure 8G , the first partition wall layer L1 and the second partition wall layer L2 may be formed in the secondary etching step of the first preliminary partition wall layer L1-I. Since the first preliminary partition wall layer L1-I is selectively etched in the secondary etching step of the first preliminary partition wall layer L1-I, the inner side surface of the partition wall PW may have an undercut shape in cross section. When compared with the first partition wall layer L1, a tip portion may be formed in the partition wall PW by a protruding portion of the second partition wall layer L2 protruding toward the center of the anode AE.

[0258] In an embodiment, the partition wall opening OP-P may include first regions A1 (see FIG. 1 ) sequentially arranged in the thickness direction (ie, in the third direction DR3 ). Fig.8F ) and the second area A2 (see Fig.8F ). The first partition wall layer L1 may include a first inner side surface S1-P of a portion of the first area A1 defining the partition wall opening OP-P, and the second partition wall layer L2 may include a second inner side surface S2-P defining the second area A2.

[0259] In an embodiment, the secondary wet etching process may be performed in an environment where the etching selectivity ratio between the first preliminary partition wall layer L1-I and the second preliminary partition wall layer L2-I is high. Therefore, the inner surface of the partition wall PW defining the partition wall opening OP-P may have an undercut shape in cross section. Specifically, since the etching rate of the first partition wall layer L1 relative to the etching solution is greater than the etching rate of the second partition wall layer L2, the etching degree of the first partition wall layer L1 may be greater than the etching degree of the second partition wall layer L2. Therefore, the first inner surface S1-P of the first partition wall layer L1 may be formed to be recessed inwardly than the second inner surface S2-P of the second partition wall layer L2. When compared with the first partition wall layer L1, a tip portion may be formed in the partition wall PW by a protruding portion of the second partition wall layer L2 protruding toward the center of the anode AE.

[0260] In the embodiments and with reference to Fig.8F and Figure 8G , the method of manufacturing a display panel may include etching a preliminary pixel defining film PDL-I to form a pixel defining film PDL. The etching process of the preliminary pixel defining film PDL-I may be performed by using a dry etching method, and the etching process may be performed by using the first photoresist layer PR1 and a portion of the partition wall PW (i.e., the second partition wall layer L2) as a mask. A light emitting opening OP-E corresponding to the partition wall opening OP-P may be formed in the pixel defining film PDL.

[0261] In the embodiments and with reference to Figure 8H , the method of manufacturing a display panel may include etching a preliminary sacrificial pattern SP-I. The etching process of the preliminary sacrificial pattern SP-I may be performed by using a wet etching method, and the etching process may be performed by using the first photoresist layer PR1 and a portion of the partition wall PW (ie, the second partition wall layer L2) as a mask.

[0262] In an embodiment, the etching of the preliminary sacrificial pattern SP-I may include etching the preliminary sacrificial pattern SP-I by providing an etching solution to the preliminary sacrificial pattern SP-I.

[0263] In an embodiment, the preliminary sacrificial pattern SP-I may include a first metal, indium, and zinc. Figure 5AThe description of the first metal given may be equally applied to the first metal included in the preliminary sacrificial pattern SP-I. When the preliminary sacrificial pattern SP-I includes the first metal, the preliminary sacrificial pattern SP-I may maintain an amorphous form during the etching process of the preliminary sacrificial pattern SP-I, and thus may have a high etching selectivity ratio with respect to the anode AE.

[0264] In the embodiment, again referring to Figure 8G and Figure 8H , forming the sacrificial pattern SP may be performed by etching the preliminary sacrificial pattern SP-I. A sacrificial pattern SP having a sacrificial opening OP-S defined therein may be formed by removing a region of the preliminary sacrificial pattern SP-I through a wet etching process. The sacrificial opening OP-S may be formed by the sacrificial pattern SP and may expose a portion of the upper surface of the anode AE.

[0265] In an embodiment, the preliminary sacrificial pattern SP-I may include a first metal-indium-zinc oxide. In an embodiment, the preliminary sacrificial pattern SP-I may include indium tin zinc oxide (ITZO). For example, the preliminary sacrificial pattern SP-I may be composed of indium tin zinc oxide (ITZO). In another embodiment, the preliminary sacrificial pattern SP-I may include indium gallium zinc oxide (IGZO). For example, the preliminary sacrificial pattern SP-I may be composed of indium gallium zinc oxide (IGZO). In another embodiment, the preliminary sacrificial pattern SP-I may include indium gallium tin zinc oxide (IGTZO). For example, the preliminary sacrificial pattern SP-I may be composed of indium gallium tin zinc oxide (IGTZO).

[0266] In an embodiment, the content of the first metal relative to the total content of the metal elements included in the preliminary sacrificial pattern SP-I may be about 5 at % or more. The content of the first metal relative to the total content of the first metal, indium, and zinc included in the preliminary sacrificial pattern SP-I may be about 5 at % or more. For example, the content of the first metal relative to the total content of the first metal, indium, and zinc included in the preliminary sacrificial pattern SP-I may be about 5 at % to about 30 at %.

[0267] In an implementation, a content ratio of indium to zinc in the preliminary sacrificial pattern SP-I may be about 4:6 to about 6:4. For example, a content ratio of indium to zinc in the preliminary sacrificial pattern SP-I may be about 5:5.

[0268] In an embodiment, the metal oxide included in the preliminary sacrificial pattern SP-I may include an amorphous structure. The metal oxide included in the preliminary sacrificial pattern SP-I may have an amorphous structure. In an embodiment, the preliminary sacrificial pattern SP-I may include amorphous indium tin zinc oxide (a-ITZO), amorphous indium gallium zinc oxide (a-IGZO), or amorphous indium gallium tin zinc oxide (a-IGTZO). For example, the preliminary sacrificial pattern SP-I may be made of amorphous indium tin zinc oxide (a-ITZO), amorphous indium gallium zinc oxide (a-IGZO), or amorphous indium gallium tin zinc oxide (a-IGTZO).

[0269] The etching solution for etching the preliminary sacrificial pattern SP-1 is not limited, but may be an acid etching solution in an embodiment. In an embodiment, the acid etching solution may include at least one of an organic acid etching solution and an inorganic acid etching solution. For example, the organic acid etching solution may be oxalic acid. The inorganic acid etching solution may include a phosphoric acid etching solution or a hydrogen peroxide etching solution. For example, the inorganic acid etching solution may be an etching solution including phosphoric acid, nitric acid, and acetic acid. In addition, the inorganic acid etching solution may also include substances other than phosphoric acid, nitric acid, and acetic acid.

[0270] In an embodiment, the etching process of the preliminary sacrificial pattern SP-I may be performed in an environment where the etching selectivity ratio between the preliminary sacrificial pattern SP-I and the anode AE ​​is high, and through this, it is possible to prevent the anode AE ​​from being etched together. That is, by arranging the preliminary sacrificial pattern SP-I having a higher etching rate than the anode AE ​​between the pixel defining film PDL and the anode AE, it is possible to prevent the anode AE ​​from being etched together and damaged in the etching process.

[0271] In an embodiment, the etching rate of the preliminary sacrificial pattern SP-I and the etching rate of the anode AE ​​may be different from each other. The anode AE ​​may be configured to be etched at a first etching rate, and the preliminary sacrificial pattern SP-I may be configured to be etched at a second etching rate greater than the first etching rate. In the etching process of the preliminary sacrificial pattern SP-I, the anode AE ​​is not etched or may not be substantially etched due to the etching rate of the preliminary sacrificial pattern SP-I being greater than the etching rate of the anode AE. In an embodiment, the etching rate of the preliminary sacrificial pattern SP-I may be about to about An etching rate of the preliminary sacrificial pattern SP-I may be achieved by controlling the content of the first metal with respect to the total content of metal elements included in the preliminary sacrificial pattern SP-I.

[0272] In an embodiment, the preliminary sacrificial pattern SP-I and the anode AE ​​may have different crystallinities at the first temperature. In an embodiment, the preliminary sacrificial pattern SP-I may have a first crystallinity at the first temperature, and the anode AE ​​may have a second crystallinity greater than the first crystallinity at the first temperature. For example, the preliminary sacrificial pattern SP-I may have an amorphous structure at the first temperature, and the anode AE ​​may have a crystalline structure at the first temperature. On the other hand, in the present specification, the first temperature may be about 250°C. "Crystallinity" may be represented by the following Equation 2.

[0273] Crystallinity = P 1 / (P 1 +P 2 )[Equation 2],

[0274] Where, in the above equation 2, P 1 refers to the sum of the crystal peak areas in the X-ray diffraction (XRD) pattern, and P 2 It refers to the sum of the amorphous peak areas in the X-ray diffraction pattern.

[0275] In the process of manufacturing the display device according to the embodiment, the preliminary sacrificial pattern SP-I may be exposed to high temperature conditions, and the amorphous structure of the metal oxide of the preliminary sacrificial pattern SP-I may be partially crystallized due to the high temperature. When the metal oxide included in the preliminary sacrificial pattern SP-I is crystallized, it may be difficult to obtain the desired pattern of the sacrificial pattern SP because the etching selectivity relative to the anode AE ​​in the etching process of the preliminary sacrificial pattern SP-I is reduced. When the preliminary sacrificial pattern SP-I includes the first metal, the metal oxide included in the preliminary sacrificial pattern SP-I may maintain an amorphous structure in the etching process of the preliminary sacrificial pattern SP-I, thereby being able to increase the etching selectivity relative to the anode AE ​​having a crystal structure. For example, in the etching of the preliminary sacrificial pattern SP-I, selective etching may occur between the anode AE ​​having a crystal structure and the preliminary sacrificial pattern SP-I having an amorphous structure. Therefore, the preliminary sacrificial pattern SP-I having an amorphous structure may be etched, and the anode AE ​​having a crystal structure may be retained.

[0276] In an embodiment, the etching rate of the sacrificial pattern SP relative to the etching solution can be reduced by adding a first metal to indium zinc oxide included in the sacrificial pattern SP, thereby preventing the occurrence of voids in the sacrificial pattern SP during etching. When the inner surface of the sacrificial pattern SP is recessed compared to the inner surface of the pixel defining film PDL due to over-etching of the sacrificial pattern SP, the void formed in the sacrificial pattern SP can be defined as a void formed between the anode AE ​​and the pixel defining film PDL. When foreign matter enters such a void during the manufacturing process or use of the display device, pixel defects or afterimages or stains may occur in the display area. According to an embodiment, since the sacrificial pattern SP includes the first metal, the formation of voids in the sacrificial pattern SP can be suppressed by controlling the etching rate, thereby preventing the occurrence of pixel defects. Therefore, the display device DD (for example, refer to Figure 1A ) reliability.

[0277] In the embodiment, again referring to Figure 8H In the sacrificial pattern SP formed by etching the preliminary sacrificial pattern SP-I, a sacrificial opening OP-S overlapping the light emitting opening OP-E may be formed. At least a portion of the anode AE ​​may be exposed from the sacrificial pattern SP and the pixel defining film PDL through the sacrificial opening OP-S and the light emitting opening OP-E.

[0278] In an embodiment, the etching process of the sacrificial pattern SP may be performed in an environment where an etching selectivity ratio between the sacrificial pattern SP and the first and second partition wall layers L1 and L2 of the partition wall PW is high, and by this, it is possible to prevent the first and second partition wall layers L1 and L2 from being etched together.

[0279] In an embodiment, the sacrificial opening OP-S defined in the sacrificial pattern SP may have a first width W s The light emitting opening OP-E defined in the pixel defining film PDL may have a second width W p In an embodiment, the first width W of the sacrificial opening OP-S is s may be smaller than the second width W of the light emitting opening OP-E p That is, the inner side surface of the sacrificial pattern SP may be arranged closer to the center of the anode AE ​​(eg, in a plan view) than the inner side surface of the pixel defining film PDL. However, this is not limited thereto. Figure 8H Unlike that shown in FIG. 1 , the first width W of the sacrificial opening OP-S s The second width W of the light emitting opening OP-E may be substantially equal to p That is, the inner side surface of the sacrificial pattern SP may be aligned with the inner side surface of the pixel defining film PDL.

[0280] In an embodiment, when the first width W of the sacrificial opening OP-Ss A second width W greater than the light emitting opening OP-E p When the anode AE ​​and the pixel definition film PDL are connected, a gap may be formed between the anode AE ​​and the pixel definition film PDL, thereby causing image defects. Therefore, it is necessary to set the first width W of the sacrificial opening OP-S to s The second width W of the light emitting opening OP-E is controlled to be equal to or smaller than the second width W of the light emitting opening OP-E. p When the first width W of the sacrificial opening OP-S s The second width W of the light emitting opening OP-E is controlled to be equal to or smaller than the second width W of the light emitting opening OP-E. p When the display device DD is formed, defects due to the occurrence of voids can be prevented. Therefore, the reliability of the display device DD can be further improved.

[0281] In an embodiment, reference is made to Figure 8H and Fig.8I , the method of manufacturing a display panel may include removing the first photoresist layer PR1, forming a light emitting pattern EP, forming a cathode CE, and forming a capping pattern CP.

[0282] In an embodiment, each of the formation of the light emitting pattern EP, the formation of the cathode CE, and the formation of the cover pattern CP may be performed by a deposition process. In an embodiment, the formation of the light emitting pattern EP may be performed by a thermal evaporation process, the formation of the cathode CE may be performed by a sputtering process, and the formation of the cover pattern CP may be performed by a thermal evaporation process. However, the present invention is not limited thereto.

[0283] In an embodiment, in forming the light emitting pattern EP, the light emitting pattern EP may be separated by a tip portion formed in the partition wall PW, and may be arranged in the light emitting opening OP-E and the partition wall opening OP-P. In forming the light emitting pattern EP, a first preliminary dummy pattern D1-I spaced apart from the light emitting pattern EP may be formed together on the partition wall PW. The light emitting pattern EP may be formed on the anode AE. The light emitting pattern EP may be arranged on a portion of the sacrificial pattern SP exposed by the light emitting opening OP-E (hereinafter referred to as a sacrificial opening portion). The light emitting pattern EP may be arranged on the anode AE ​​and the sacrificial opening portion. The light emitting pattern EP may cover the upper surface of the anode AE ​​exposed by the sacrificial opening OP-S and the sacrificial opening portion. In an embodiment, the light emitting pattern EP may be in contact with the sacrificial opening portion of the sacrificial pattern SP.

[0284] In an embodiment, in forming the cathode CE, the cathode CE may be separated by a tip portion formed in the partition wall PW and arranged in the partition wall opening OP-P. The cathode CE may be provided at a high incident angle compared to the light emitting pattern EP and may be formed to contact the first inner side surface S1-P of the first partition wall layer L1. In forming the cathode CE, a second preliminary dummy pattern D2-I spaced apart from the cathode CE may be formed together on the partition wall PW. The anode AE, the light emitting pattern EP, and the cathode CE may constitute a light emitting element ED.

[0285] In an embodiment, in forming the covering pattern CP, the covering pattern CP may be separated by a tip portion formed in the partition wall PW and may be arranged in the partition wall opening OP-P. In forming the covering pattern CP, a third preliminary dummy pattern D3-I spaced apart from the covering pattern CP may be formed together on the partition wall PW. On the other hand, according to another embodiment, the formation of the covering pattern CP may be omitted.

[0286] In an embodiment, the first preliminary dummy pattern D1-I, the second preliminary dummy pattern D2-I, and the third preliminary dummy pattern D3-I form a preliminary dummy pattern DMP-I, and the dummy opening OP-D may be formed in the preliminary dummy pattern DMP-I. The dummy opening OP-D may include a first opening area AA1, a second opening area AA2, and a third opening area AA3 sequentially arranged in the thickness direction (i.e., in the third direction DR3). The first opening area AA1 of the dummy opening OP-D may be defined by an inner side surface S1-D of the first dummy pattern D1 (specifically, the first preliminary dummy pattern D1-I in this step), the second opening area AA2 may be defined by an inner side surface S2-D of the second dummy pattern D2 (specifically, the second preliminary dummy pattern D2-I in this step), and the third opening area AA3 may be defined by an inner side surface S3-D of the third dummy pattern D3 (specifically, the third preliminary dummy pattern D3-I in this step).

[0287] In the embodiments and with reference to Figure 8J , the method of manufacturing a display panel may include forming a preliminary lower inorganic encapsulation pattern LIL-I. The preliminary lower inorganic encapsulation pattern LIL-I may be formed by a deposition process. In an embodiment, the preliminary lower inorganic encapsulation pattern LIL-I may be formed by a chemical vapor deposition (CVD) process. The preliminary lower inorganic encapsulation pattern LIL-I may be formed on the partition wall PW and the cathode CE, and a portion of the preliminary lower inorganic encapsulation pattern LIL-I may be formed on the inner side of the partition wall opening OP-P.

[0288] In the embodiments and with reference to Figure 8K The method for manufacturing a display panel may include: forming a second photoresist layer PR2; forming a preliminary lower inorganic encapsulation pattern LIL-I (see Figure 8J ) is patterned to form a lower inorganic encapsulation pattern LIL; and a preliminary dummy pattern DMP-I (see Figure 8J ) is patterned to form a dummy pattern DMP.

[0289] In an embodiment, in forming the second photoresist layer PR2, the second photoresist layer PR2 may be formed by forming a preliminary photoresist layer and then patterning the preliminary photoresist layer using a photomask. Through the patterning process, the second photoresist layer PR2 may be formed into a pattern shape corresponding to the light emitting opening OP-E.

[0290] In the embodiments and with reference to Figure 8J and Figure 8K , patterning the preliminary lower inorganic encapsulation pattern LIL-I may include patterning the preliminary lower inorganic encapsulation pattern LIL-I by dry-etching the preliminary lower inorganic encapsulation pattern LIL-I so that a portion of the preliminary lower inorganic encapsulation pattern LIL-I overlapping with the remaining anodes AE except for the corresponding anode AE ​​is removed. For example, when the preliminary lower inorganic encapsulation pattern LIL-I corresponds to the first anode AE1 (see Figure 6 ), the preliminary lower inorganic encapsulation pattern LIL-I and the second anode AE2 (see Figure 6 ) and the third anode AE3 (see Figure 6 ) overlapping part.

[0291] In an embodiment, the lower inorganic encapsulation pattern LIL overlapping the corresponding light emitting opening OP-E may be formed by a patterned preliminary lower inorganic encapsulation pattern LIL-I. A portion of the lower inorganic encapsulation pattern LIL may be arranged in the partition wall opening OP-P to cover the light emitting element ED, and another portion of the lower inorganic encapsulation pattern LIL may be arranged on the partition wall PW.

[0292] In an embodiment, patterning of the preliminary dummy pattern DMP-I may include patterning the first preliminary dummy pattern D1-I, the second preliminary dummy pattern D2-I, and the third preliminary dummy pattern D3-I by dry etching the first preliminary dummy pattern D1-I, the second preliminary dummy pattern D2-I, and the third preliminary dummy pattern D3-I so that portions of the first preliminary dummy pattern D1-I, the second preliminary dummy pattern D2-I, and the third preliminary dummy pattern D3-I that overlap with the remaining anodes AE other than the corresponding anodes AE are removed. For example, when the first preliminary dummy pattern D1-I, the second preliminary dummy pattern D2-I, and the third preliminary dummy pattern D3-I correspond to the first anode AE1 (see Figure 6 ), the first preliminary dummy pattern D1-I, the second preliminary dummy pattern D2-I, and the third preliminary dummy pattern D3-I that are connected to the second anode AE2 (see Figure 6 ) and the third anode AE3 (see Figure 6 ) overlapping part.

[0293] In an embodiment, the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 whose dummy openings OP-D overlap with the corresponding light emitting openings OP-E may be formed by patterning the first preliminary dummy pattern D1-I, the second preliminary dummy pattern D2-I, and the third preliminary dummy pattern D3-I, so that a dummy pattern DMP including the first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may be formed. The first dummy pattern D1, the second dummy pattern D2, and the third dummy pattern D3 may have a plane surrounding the corresponding light emitting area PXA (see Figure 5A ) of the closed line shape.

[0294] In the embodiments and with reference to Figure 8L , the method of manufacturing a display panel may include removing the second photoresist layer PR2 (see Figure 8K ) and then form an organic encapsulation film OL and an upper inorganic encapsulation film UIL to complete the display panel. The organic encapsulation film OL can be formed by applying an organic material by an inkjet method, but the present invention is not limited to this. The organic encapsulation film OL provides a flat upper surface. Thereafter, an upper inorganic encapsulation film UIL can be formed by depositing an inorganic material. By this, a display panel DP including a base layer BL, a circuit element layer DP-CL, a display element layer DP-OLED and a thin film encapsulation layer TFE can be formed.

[0295] In an embodiment, between the formation of the lower inorganic encapsulation pattern LIL and the completion of the display panel DP, the following may be further performed: forming a partition wall opening and a light emitting opening corresponding to light emitting areas of different colors in the partition wall PW and the pixel definition film PDL; forming a light emitting element configured to provide different colors; and forming a lower inorganic encapsulation pattern covering the light emitting element configured to provide different colors. Figure 6 As shown in, a display panel DP including a first light emitting element ED1, a second light emitting element ED2, and a third light emitting element ED3, a first covering pattern CP1, a second covering pattern CP2, and a third covering pattern CP3, a (1-1)th dummy pattern D11, a (1-2)th dummy pattern D12, and a (1-3)th dummy pattern D13, a (2-1)th dummy pattern D21, a (2-2)th dummy pattern D22, and a (2-3)th dummy pattern D23, a (3-1)th dummy pattern D31, a (3-2)th dummy pattern D32, and a (3-3)th dummy pattern D33, and a first lower inorganic encapsulation pattern LIL1, a second lower inorganic encapsulation pattern LIL2, and a third lower inorganic encapsulation pattern LIL3 can be formed.

[0296] The display panel according to the embodiment can prevent the sacrificial pattern from being over-etched in the etching of the sacrificial pattern, thereby improving the process reliability of the display panel.

[0297] Although described above with reference to embodiments of the present invention, it will be understood by those skilled in the art or those of ordinary skill in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical field of the present invention. Therefore, it will be understood that the present invention should not be limited to these embodiments. In addition, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A display panel, comprising: Base layer; an anode disposed on the base layer; a sacrificial pattern disposed on the anode and having a sacrificial opening defined in the sacrificial pattern and exposing a portion of an upper surface of the anode; a pixel defining film disposed on the base layer to cover at least a portion of the sacrificial pattern and having a light emitting opening, the light emitting opening being defined in the pixel defining film and corresponding to the sacrificial opening; a partition wall disposed on the pixel defining film and having a partition wall opening defined in the partition wall and corresponding to the light emitting opening; a light emitting pattern arranged on the anode in the partition wall opening; as well as a cathode disposed on the light emitting pattern and in contact with the partition wall, wherein the sacrificial pattern comprises a metal oxide including a first metal, indium and zinc, the first metal comprising at least one of tin and gallium; and The sacrificial pattern has a shape protruding from one side of the pixel defining film.

2. The display panel according to claim 1, wherein: The width of the sacrificial opening is smaller than the width of the light emitting opening.

3. The display panel according to claim 1, wherein: The content of the first metal included in the sacrificial pattern is 5.0 at % or more of the total content of the first metal, the indium, and the zinc included in the sacrificial pattern.

4. The display panel according to claim 1, wherein: The sacrificial pattern includes indium tin zinc oxide or indium gallium zinc oxide.

5. The display panel according to claim 4, wherein: The metal oxide included in the sacrificial pattern includes an amorphous structure.

6. The display panel according to claim 1, wherein: Among the total contents of the first metal, the indium, and the zinc included in the sacrificial pattern: The indium content is 35 at % to 50 at %; and The content of zinc is 35 at % to 50 at %.

7. The display panel according to claim 1, wherein: A content ratio of the indium to the zinc included in the sacrificial pattern is 4:6 to 6:

4.

8. The display panel according to claim 1, wherein: The anode includes indium tin oxide.

9. The display panel according to claim 1, wherein: The anode comprises: a first layer disposed on the base layer and comprising indium tin oxide; a second layer disposed on the first layer and comprising silver; and a third layer disposed on the second layer and comprising indium tin oxide, Wherein, the sacrificial pattern is directly arranged on the third layer.

10. The display panel according to claim 1, wherein: The light emitting opening exposes a portion of an upper surface of the sacrificial pattern, and The portion of the upper surface of the sacrificial pattern exposed by the light emitting opening is in contact with the light emitting pattern.

11. The display panel according to claim 1, wherein: The partition wall comprises: a first partition wall layer disposed on the pixel definition film and including a metal; and The second partition wall layer is disposed on the first partition wall layer and includes a metal or a silicon-based compound.

12. The display panel according to claim 11, wherein: The cathode contacts the first partition wall layer.

13. The display panel according to claim 11, wherein: The partition wall opening comprises: a first area in which the light emitting pattern is arranged; and a second region, the second region having a smaller width than the first region, wherein the inner surface of the first partition wall layer defines the first region; and The inner side surface of the second partition wall layer defines the second region.

14. The display panel according to claim 11, wherein: The second partition wall layer has an undercut shape protruding from one side of the first partition wall layer.

15. The display panel according to claim 1, further comprising a thin film encapsulation layer disposed on the light emitting pattern and comprising a plurality of thin films, in, The thin film encapsulation layer includes an inorganic encapsulation pattern covering the light emitting pattern and partially contacting the partition wall.

16. A method for manufacturing a display panel, the method comprising: forming an anode on the base layer; forming a preliminary sacrificial pattern on the anode, the preliminary sacrificial pattern comprising a metal oxide including indium, zinc and a first metal, the first metal comprising at least one of tin and gallium; forming a preliminary pixel definition film covering the anode and the preliminary sacrificial pattern; forming a preliminary partition wall on the preliminary pixel definition film; etching the preliminary partition wall to form a partition wall having a partition wall opening defined in the partition wall; etching the preliminary pixel definition film to form a pixel definition film having a light emitting opening defined in the pixel definition film and overlapping the partition wall opening; etching the preliminary sacrificial pattern to form a sacrificial pattern having a sacrificial opening defined in the sacrificial pattern and overlapping the partition wall opening; forming a light emitting pattern on the anode in the partition wall opening; as well as forming a cathode in the partition wall opening so as to contact the light emitting pattern and the partition wall, Wherein, in forming the sacrificial pattern, the sacrificial pattern is formed to protrude from one side of the pixel defining film.

17. The method according to claim 16, wherein: In forming the sacrificial pattern, an etching rate of the anode is lower than an etching rate of the preliminary sacrificial pattern.

Images