Power device and preparation method, power module, power conversion circuit and vehicle

Abstract

The present invention discloses a power device and a preparation method, a power module, a power conversion circuit and a vehicle. The power device comprises: a semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a well region and a contact region; the well region is at least located on a side of the contact region adjacent to the second surface; a gate structure is located on the first surface; a first piezoelectric material layer is located on a side of the gate structure away from the second surface; the first piezoelectric material layer covers the gate structure and part of the contact region; a first electrode layer is located on the second surface; the first electrode layer comprises a first electrode and a second piezoelectric material layer, and the second piezoelectric material layer is located on a side of the first electrode away from the second surface; the second piezoelectric material layer is provided with a plurality of cavities, and the plurality of cavities penetrate the second piezoelectric material layer; the first electrode covers the second surface, and the first electrode fills the plurality of cavities. The present invention can reduce power consumption and improve the switching speed and conductive performance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Silicon carbide (SiC) is a typical third-generation wide bandgap semiconductor material with excellent characteristics such as high critical breakdown electric field, wide bandgap, high thermal conductivity and high electron saturation drift velocity. The critical breakdown electric field of SiC is nearly 10 times that of silicon (Si), the bandgap of SiC is nearly 3 times that of Si, and the thermal conductivity of SiC is nearly 3 times that of Si. When it is used as the channel material of metal oxide semiconductor field effect transistor (MOSFET), the device exhibits advantages such as high breakdown voltage, low on-resistance, high current density, high heat dissipation and high switching speed. The industry's SiC MOSFET power devices have epitaxial defects and interface defects, resulting in low mobility and slow switching speed. Summary of the invention

[0003] The present invention provides a power device and a preparation method thereof, a power module, a power conversion circuit and a vehicle, which can reduce power consumption and improve the switching speed and conductive performance of the device.

[0004] According to one aspect of the present invention, there is provided a power device, comprising:

[0005] A semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprising a well region and a contact region; the contact region is located on the first surface, and the well region is located at least on a side of the contact region adjacent to the second surface;

[0006] A gate structure, the gate structure is located on the first surface;

[0007] A first piezoelectric material layer, the first piezoelectric material layer is located on a side of the gate structure away from the second surface; the first piezoelectric material layer covers the gate structure and a portion of the contact area;

[0008] A first electrode layer, the first electrode layer is located on the second surface; the first electrode layer includes a first electrode and a second piezoelectric material layer, the second piezoelectric material layer is located on a side of the first electrode away from the second surface; the second piezoelectric material layer is provided with a plurality of cavities, and the plurality of cavities penetrate the second piezoelectric material layer; the first electrode covers the second surface, and the first electrode fills the plurality of cavities.

[0009] Optionally, the contact region includes a first conductive type region and a second conductive type region; the first conductive type region has a first side and a second side opposite to each other in a first direction, the first direction being perpendicular to a direction of the first electrode layer pointing toward the semiconductor body; the second conductive type region is located on a first side of the first conductive type region, and the second conductive type region and the first conductive type region are in contact with each other;

[0010] The well region includes a first sub-region and a second sub-region connected to each other. The first sub-region is located on a side of the first conductive type region adjacent to the second surface; the second sub-region is located on a second side of the first conductive type region.

[0011] Optionally, the number of the contact region and the well region is two;

[0012] The semiconductor body further includes a JFET region, which is located between the two well regions and on a side of the well region away from the first surface;

[0013] The gate structure includes a first insulating layer and a first gate, wherein the first insulating layer is located on a side of the first surface away from the second surface, and the first insulating layer covers the JFET region, the second sub-region and a portion of the first conductive type region between the two well regions; the first gate is located on a side of the first insulating layer away from the first surface, and the first gate covers a portion of the first insulating layer;

[0014] The first piezoelectric material layer is located at a side of the first grid electrode away from the first surface, and the first piezoelectric material layer covers the first grid electrode and the first insulating layer not covered by the first grid electrode.

[0015] Optionally, the first surface is provided with at least one groove, and the groove extends from the first surface into the semiconductor body;

[0016] The gate structure is located in the trench.

[0017] Optionally, a gate trench is provided on the first surface;

[0018] The gate structure is located in the gate trench, the gate structure includes a second insulating layer and a second gate, and the second insulating layer is located between the gate trench and the second gate;

[0019] The contact region includes a first conductive type region and a second conductive type region, the second conductive type region is located at a side of the first conductive type region away from the gate trench, and the second conductive type region and the first conductive type region are in contact with each other;

[0020] The well region is located at a side of the first conductive type region and the second conductive type region away from the first surface;

[0021] The first piezoelectric material layer covers the gate structure and a portion of the first conductive type region.

[0022] Optionally, the power device further includes:

[0023] The first surface is provided with a first source trench, a gate trench, and a second source trench at intervals;

[0024] The gate trench, the first source trench and the second source trench all include a third insulating layer and a polysilicon layer, and the polysilicon layer is located on a side of the third insulating layer away from the second surface; the third insulating layer and the polysilicon layer in the gate trench are a gate structure;

[0025] The contact region includes a first conductive type region and a second conductive type region, the first conductive type region is located on the first surface and between the gate trench and the first source trench and between the gate trench and the second source trench; the well region is located on a side of the first conductive type region away from the first surface;

[0026] The second conductive type region is located in the semiconductor body at the bottom and sidewall of the first source trench and the bottom and sidewall of the second source trench, and the second conductive type region is located in the semiconductor body at the bottom of the gate trench; the second conductive type region is in contact with the third insulating layer;

[0027] The first piezoelectric material layer covers the gate structure and a portion of the first conductive type region.

[0028] Optionally, the power device further includes:

[0029] a second electrode layer, the second electrode layer being located on the first surface, and the second electrode layer covering the contact area not covered by the first piezoelectric material layer;

[0030] The material of the second electrode layer includes metal, and the material of the first electrode includes graphene.

[0031] According to another aspect of the present invention, a power module is provided, comprising a substrate and a power device according to any embodiment of the present invention, wherein the substrate is used for carrying the power device.

[0032] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0033] The power conversion circuit comprises a circuit board and at least one power device according to any embodiment of the present invention, and the power body device is electrically connected to the circuit board.

[0034] According to another aspect of the present invention, a vehicle is provided, comprising a load and a power conversion circuit as described in any embodiment of the present invention, the power conversion circuit being used to convert alternating current into direct current, convert alternating current into alternating current, convert direct current into direct current, or convert direct current into alternating current and then input into the load.

[0035] According to another aspect of the present invention, there is provided a method for preparing a power device, which is used to prepare the power device according to any embodiment of the present invention, comprising:

[0036] A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a well region and a contact region; the contact region is located on the first surface, and the well region is located at least on a side of the contact region adjacent to the second surface;

[0037] forming a gate structure on the first surface;

[0038] A first electrode layer is formed on the second surface; the first electrode layer includes a first electrode and a second piezoelectric material layer, the second piezoelectric material layer is located on a side of the first electrode away from the second surface; the second piezoelectric material layer is provided with a plurality of cavities, the plurality of cavities passing through the second piezoelectric material layer; the first electrode covers the second surface, and the first electrode fills the plurality of cavities;

[0039] A first piezoelectric material layer is formed on a side of the gate structure away from the second surface; the first piezoelectric material layer covers the gate structure and a portion of the contact area.

[0040] Optionally, forming a first electrode layer on the second surface includes:

[0041] forming a first electrode sublayer on the second surface; the first electrode sublayer covers the second surface;

[0042] forming a second piezoelectric material sublayer on a side of the first electrode sublayer away from the second surface; the second piezoelectric material sublayer covers the first electrode sublayer;

[0043] Etching the second piezoelectric material sublayer to form a plurality of cavities to form a second piezoelectric material layer;

[0044] A second electrode sublayer is formed in the plurality of cavities; the first electrode sublayer and the second electrode sublayer are first electrodes, and the first electrode and the second piezoelectric material layer are first electrode layers.

[0045] Optionally, a semiconductor body is provided, comprising:

[0046] An epitaxial layer is formed on one side of the substrate; a surface of the epitaxial layer away from the substrate is a first surface;

[0047] forming a second conductivity type region on the first surface;

[0048] forming a well sub-region on the first surface;

[0049] A first conductive type region and a well region are formed on the first surface; the first conductive type region and the second conductive type region are contact regions; the first conductive type region has a first side and a second side opposite to each other in a first direction, the first direction being perpendicular to the direction of the substrate pointing to the epitaxial layer; the second conductive type region is located on a first side of the first conductive type region, and the second conductive type region and the first conductive type region are in contact with each other; the well region includes a first sub-region and a second sub-region connected to each other; the first sub-region is located on a side of the first conductive type region adjacent to the substrate; the second sub-region is located on a second side of the first conductive type region;

[0050] After forming a gate structure on the first surface, the method further includes:

[0051] A sacrificial layer is formed on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and the first surface not covered by the gate structure;

[0052] removing the substrate;

[0053] After forming the first electrode layer on the second surface, the method further comprises:

[0054] The sacrificial layer is removed.

[0055] Optionally, the number of the contact region and the well region is two, and after the first conductive type region and the well region are formed on the first surface, the method further includes:

[0056] A JFET region is formed between the two well regions and on a side of the well region away from the first surface.

[0057] Optionally, a semiconductor body is provided, comprising:

[0058] An epitaxial layer is formed on one side of the substrate; a surface of the epitaxial layer away from the substrate is a first surface;

[0059] Etching the first surface to form a gate trench;

[0060] forming a second conductivity type region on the first surface;

[0061] forming a well region in the second conductivity type region away from the first surface;

[0062] A first conductive type region is formed on the first surface; the first conductive type region and the second conductive type region are contact regions; the second conductive type region is located on a side of the first conductive type region away from the gate trench, and the second conductive type region is in contact with the first conductive type region;

[0063] A gate structure is formed on the first surface, comprising:

[0064] A gate structure is formed in the gate trench; the gate structure comprises a second insulating layer and a second gate, and the second insulating layer is located between the gate trench and the second gate;

[0065] After forming a gate structure on the first surface, the method further includes:

[0066] A sacrificial layer is formed on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and the first surface not covered by the gate structure;

[0067] removing the substrate;

[0068] After forming the first electrode layer on the second surface, the method further comprises:

[0069] The sacrificial layer is removed.

[0070] Optionally, a semiconductor body is provided, comprising:

[0071] An epitaxial layer is formed on one side of the substrate; a surface of the epitaxial layer away from the substrate is a first surface;

[0072] Etching the first surface to form a first source trench, a gate trench, and a second source trench;

[0073] forming a second conductive type region; the second conductive type region is located in the epitaxial layer at the bottom and sidewall of the first source trench and the bottom and sidewall of the second source trench, and is located in the epitaxial layer at the bottom of the gate trench;

[0074] forming a well region;

[0075] A first conductive type region is formed on the first surface; the first conductive type region is located between the gate trench and the first source trench and between the gate trench and the second source trench; and the well region is located on a side of the first conductive type region away from the first surface;

[0076] A gate structure is formed on the first surface, comprising:

[0077] forming a third insulating layer in the gate trench, in the first source trench, and in the second source trench;

[0078] A polysilicon layer is formed on a side of the third insulating layer away from the substrate; the third insulating layer and the polysilicon layer in the gate trench form a gate structure;

[0079] After forming a gate structure on the first surface, the method further includes:

[0080] A sacrificial layer is formed on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and the first surface not covered by the gate structure;

[0081] removing the substrate;

[0082] After forming the first electrode layer on the second surface, the method further comprises:

[0083] The sacrificial layer is removed.

[0084] Optionally, after forming the first piezoelectric material layer on the side of the gate structure away from the second surface, the method further includes:

[0085] A second electrode layer is formed on the first surface; the second electrode layer covers the contact area not covered by the first piezoelectric material layer.

[0086] The power device provided by the technical solution of the embodiment of the present invention includes: a semiconductor body, the semiconductor body includes a first surface and a second surface arranged opposite to each other, and the semiconductor body also includes a well region and a contact region; the contact region is located on the first surface, and the well region is at least located on the side of the contact region adjacent to the second surface; a gate structure, the gate structure is located on the first surface; a first piezoelectric material layer, the first piezoelectric material layer is located on the side of the gate structure away from the second surface; the first piezoelectric material layer covers the gate structure and part of the contact region; a first electrode layer, the first electrode layer is located on the second surface; the first electrode layer includes a first electrode and a second piezoelectric material layer, the second piezoelectric material layer is located on the side of the first electrode away from the second surface; the second piezoelectric material layer is provided with a plurality of cavities, and the plurality of cavities penetrate the second piezoelectric material layer; the first electrode covers the second surface, and the first electrode fills the plurality of cavities. The embodiment of the present invention adopts a second piezoelectric material layer and a first electrode to replace the substrate, which, on the one hand, eliminates the substrate resistance and reduces the on-resistance; on the other hand, when a voltage is applied to the first piezoelectric material layer and the second piezoelectric material layer, the first piezoelectric material layer and the second piezoelectric material layer will be deformed, and an additional electric field will be generated on the gate structure, thereby improving the mobility and conductivity of the charge carriers in the semiconductor structure, thereby improving the switching speed and conductivity of the device. And due to the existence of the piezoelectric effect, when the first piezoelectric material layer and the second piezoelectric material layer are subjected to external force, an electric potential will be generated, which can realize the switching of the power device at an extremely low voltage, and even directly respond to mechanical stress, without the need for external voltage control, to achieve self-driven power supply, thereby realizing a low-power power device.

[0087] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0089] Figure 1 It is a schematic diagram of the structure of a power device provided by an embodiment of the present invention.

[0090] Figure 2 It is a schematic diagram of the structure of another power device provided by an embodiment of the present invention.

[0091] Figure 3 It is a schematic diagram of the structure of another power device provided by an embodiment of the present invention.

[0092] Figure 4 It is a flow chart of a method for preparing a power device provided by an embodiment of the present invention.

[0093] Figure 5 yes Figure 4 A detailed flow chart included in S130.

[0094] Figure 6-Figure 15 It is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention.

[0095] Fig.16 yes Figure 4 A detailed flow chart included in S110.

[0096] Fig.17 yes Figure 4 Another detailed flow chart included in S110.

[0097] Fig.18 yes Figure 4 Another detailed flow chart included in S110. DETAILED DESCRIPTION

[0098] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0099] It should be noted that the terms "first", "second", etc. in the present invention are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0100] An embodiment of the present invention provides a power device, Figure 1 is a schematic diagram of a power device provided by an embodiment of the present invention, with reference to Figure 1 , power devices include:

[0101] A semiconductor body 10, the semiconductor body 10 includes a first surface 01 and a second surface 02 arranged opposite to each other, and the semiconductor body 10 also includes a well region 12 and a contact region 16; the contact region 16 is located on the first surface 01, and the well region 12 is at least located on a side of the contact region 16 adjacent to the second surface 02; a gate structure 20, the gate structure 20 is located on the first surface 01; a first piezoelectric material layer 30, the first piezoelectric material layer 30 is located on a side of the gate structure 20 away from the second surface 02; the first piezoelectric material layer 30 covers the gate structure 20 and a portion of the contact region 16.

[0102] The first electrode layer 40 is located on the second surface 02; the first electrode layer 40 includes a first electrode 41 and a second piezoelectric material layer 42, the second piezoelectric material layer 42 is located on the side of the first electrode 41 away from the second surface 02; the second piezoelectric material layer 42 is provided with a plurality of cavities 421, and the plurality of cavities penetrate the second piezoelectric material layer 42; the first electrode 41 covers the second surface 02, and the first electrode 41 fills the plurality of cavities 421.

[0103] The power device may be a metal oxide semiconductor field effect transistor (MOSFET) device, and the contact region 16 includes a first conductive type region 13 and a second conductive type region 14; if the device is an N-type device, the conductivity type of the first conductive type region 13 is N-type, and the conductivity type of the well region 12 and the second conductive type region 14 is P-type; if the device is a P-type device, the conductivity type of the first conductive type region 13 is P-type, and the conductivity type of the well region 12 and the second conductive type region 14 is N-type. The material of the semiconductor body 10 may be SiC, and the power device in the embodiment of the present invention may be a SiC MOSFET device. Figure 1 The gate structure 20 includes a first insulating layer 21 and a first gate 22. The first insulating layer 21 may be a gate oxide layer, such as silicon oxide, and the first gate 22 may be polysilicon.

[0104] The second piezoelectric material layer 42 is provided with a plurality of cavities 421, wherein the plurality of cavities 421 are a plurality of grooves arranged at intervals along a first direction X and extending along a second direction, wherein the first direction X is perpendicular to the direction of the semiconductor body 10 pointing to the first electrode layer 40, and the second direction is perpendicular to the first direction X and the direction of the semiconductor body 10 pointing to the first electrode layer 40; or the plurality of cavities 421 are a plurality of through holes, and the plurality of through holes penetrate the second piezoelectric material layer 42.

[0105] The material of the first electrode 41 includes graphene; the materials of the first piezoelectric material layer 30 and the second piezoelectric material layer 42 are both piezoelectric materials. The first piezoelectric material layer 30 is used to encapsulate the gate structure 20, and the first piezoelectric material layer 30 is used to encapsulate the first gate 22. The entire gate structure 20 is covered by piezoelectric material, which plays a role in protecting the device and isolating it from external impurities. At the same time, it can directly control the switch of the gate structure 20 through the piezoelectric effect. Figure 1 The first piezoelectric material layer 30 covers the gate structure 20 and part of the first conductive type area 13 to form a conductive path; the piezoelectric material has a piezoelectric effect, which refers to the phenomenon that the piezoelectric material will generate electric charges when subjected to mechanical stress and will undergo mechanical deformation under the action of an electric field.

[0106] The embodiment of the present invention does not need to adopt a traditional substrate structure, but instead adopts a second piezoelectric material layer 42 and a first electrode 41. Therefore, the on-resistance of the device is composed of contact resistance, channel resistance, JFET resistance, and epitaxial resistance in series, and there is no substrate resistance in the on-resistance, thereby realizing a low on-resistance device and reducing the on-resistance; on the other hand, when voltage is applied to the first piezoelectric material layer 30 and the second piezoelectric material layer 42, the first piezoelectric material layer 30 and the second piezoelectric material layer 42 will be deformed, and an additional electric field will be generated on the gate structure 20, thereby improving the mobility and conductivity of the charge carriers in the semiconductor structure; the embodiment of the present invention can dynamically adjust the transfer characteristics such as the mobility and conductivity of the charge carriers in the semiconductor structure through the piezoelectric effect, thereby effectively improving the response speed and sensitivity of the device to the input signal, thereby improving the switching speed and conductivity of the device. And due to the existence of the piezoelectric effect, when the first piezoelectric material layer 30 and the second piezoelectric material layer 42 are subjected to external force, an electric potential will be generated, which can realize the switching of the power device at an extremely low voltage, and even directly respond to mechanical stress without external voltage control, thereby realizing self-driven power supply, thereby realizing a low-power power device.

[0107] The inventor found that: There are currently two ways to change the mobility of SiC power devices, namely boron doping annealing technology and optimized groove structure; if boron doping annealing technology is used, high temperature annealing is usually at 1700°C, SiC material will evaporate, thus affecting the dimensional stability and surface roughness of the device, and annealing uniformity is difficult to control, affecting the consistency of the device; if the optimized groove structure is used, the groove device has a right angle or obtuse angle structure at the groove angle and the bottom, which will intensify the electric field and make the gate oxide layer easy to break down. The embodiment of the present invention uses the piezoelectric effect of the first piezoelectric material layer 30 and the second piezoelectric material layer 42 to dynamically adjust the transfer characteristics such as the mobility and conductivity of the charge carrier in the semiconductor structure, and the embodiment of the present invention does not use a groove structure, which can improve the mobility and conductivity of the device, and will not affect the consistency of the device, avoiding the problem of intensifying the electric field and making the gate oxide layer easy to break down.

[0108] The power device provided by the technical solution of the embodiment of the present invention includes: a semiconductor body 10, the semiconductor body 10 includes a first surface 01 and a second surface 02 arranged opposite to each other, and the semiconductor body 10 also includes a well region 12 and a contact region 16; the contact region 16 is located on the first surface 01, and the well region 12 is at least located on the side of the contact region 16 adjacent to the second surface 02; a gate structure 20, the gate structure 20 is located on the first surface 01; a first piezoelectric material layer 30, the first piezoelectric material layer 30 is located on the side of the gate structure 20 away from the second surface 02; the first piezoelectric material layer 30 covers the gate structure 20 and a portion of the contact region 16; a first electrode layer 40, the first electrode layer 40 is located on the second surface 02; the first electrode layer 40 includes a first electrode 41 and a second piezoelectric material layer 42, the second piezoelectric material layer 42 is located on the side of the first electrode 41 away from the second surface 02; the second piezoelectric material layer 42 is provided with a plurality of cavities 421, and the plurality of cavities 421 penetrate the second piezoelectric material layer 42; the first electrode 41 covers the second surface 02, and the first electrode 41 fills the plurality of cavities 421. The embodiment of the present invention adopts the second piezoelectric material layer 42 and the first electrode 41 to replace the substrate, which, on the one hand, eliminates the substrate resistance and reduces the on-resistance; on the other hand, when voltage is applied to the first piezoelectric material layer 30 and the second piezoelectric material layer 42, the first piezoelectric material layer 30 and the second piezoelectric material layer 42 will be deformed, and an additional electric field will be generated on the gate structure 20, thereby improving the mobility and conductivity of the charge carriers in the semiconductor structure, thereby improving the switching speed and conductivity of the device. And due to the existence of the piezoelectric effect, when the first piezoelectric material layer 30 and the second piezoelectric material layer 42 are subjected to external force, an electric potential will be generated, which can realize the switching of the power device at an extremely low voltage, and even directly respond to mechanical stress, without the need for external voltage control, to achieve self-driven power supply, thereby realizing a low-power power device.

[0109] Based on the above embodiment, optionally, refer to Figure 1 The contact area 16 includes a first conductive type area 13 and a second conductive type area 14; the first conductive type area 13 has a first side and a second side opposite to each other in a first direction X, and the first direction X is perpendicular to the direction of the first electrode layer 40 pointing to the semiconductor body 10; the second conductive type area 14 is located on the first side of the first conductive type area 13, and the second conductive type area 14 and the first conductive type area 13 are in contact with each other; the well area 12 includes a first sub-area 121 and a second sub-area 122 connected to each other, the first sub-area 121 is located on the side of the first conductive type area 13 adjacent to the second surface 02; the second sub-area 122 is located on the second side of the first conductive type area 13.

[0110] Wherein, in the case where the power device is an N-type device, the first conductive type region 13 may be an NN region, which may be formed by injecting N-type ions at the position of the first conductive type region 13, and the N-type ions may be phosphorus (P) ions or nitrogen (N) ions; the second conductive type region 14 may be a PP region, which may be formed by injecting P-type ions at the position of the second conductive type region 14, and the well region 12 may be a P-type well region (PW region), which may be formed by injecting P-type ions at the position of the well region 12, and the P-type ions may be aluminum (Al) ions or boron (B) ions. The first conductive type region 13 and the second conductive type region 14 are used to improve the conductivity of the device, form a good contact region 16, and improve the performance of the device. The first conductive type region 13, the second conductive type region 14, and the well region 12 in any embodiment of the present invention may be prepared by the above method.

[0111] Based on the above embodiment, optionally, refer to Figure 1 , the number of the contact region 16 and the well region 12 is two; the semiconductor body 10 further includes a JFET region 15 , which is located between the two well regions 12 and on a side of the well region 12 away from the first surface 01 .

[0112] The gate structure 20 includes a first insulating layer 21 and a first gate 22. The first insulating layer 21 is located on a side of the first surface 01 away from the second surface 02, and the first insulating layer 21 covers the JFET region 15 between the two well regions 12, the second sub-region 122 and a portion of the first conductive type region 121; the first gate 22 is located on a side of the first insulating layer 21 away from the first surface 01, and the first gate 22 covers a portion of the first insulating layer 21.

[0113] The first piezoelectric material layer 30 is located at a side of the first gate 22 away from the first surface 01 , and the first piezoelectric material layer 30 covers the first gate 20 and the first insulating layer 21 not covered by the first gate 20 .

[0114] Among them, the JFET region 15 is a junction field effect transistor region, and the JFET region 15 can be formed by injecting N-type ions at the position of the JFET region 15. The N-type ions can be phosphorus (P) ions or nitrogen (N) ions. The doping concentration of the JFET region 15 is greater than the doping concentration of the semiconductor body 10. The JFET region 15 can improve the conductivity of the device. The first insulating layer 21 in the gate structure 20 can be used as a gate oxide layer; the first gate 22 can be a polysilicon layer. The first piezoelectric material layer 30 is a piezoelectric material. The piezoelectric material is an insulating piezoelectric material. When subjected to external force, it will generate an electric potential, which can realize the switching of power devices at extremely low voltages, and even directly respond to mechanical stress. No external voltage control is required to achieve self-driven power supply, thereby realizing low-power power devices.

[0115] Based on the above embodiment, optionally, Figure 2 is a schematic diagram of the structure of another power device provided by an embodiment of the present invention, Figure 3 is a schematic diagram of the structure of another power device provided by an embodiment of the present invention, referring to Figure 2 and Figure 3 The first surface is provided with at least one trench, the trench extending from the first surface 01 into the semiconductor body 10; the gate structure 20 is located in the trench.

[0116] Among them, at least one groove can be formed by etching the first surface through an etching process, and the gate structure 20 is located in the groove to form a trench-type silicon carbide power device. The first piezoelectric material layer 30 and the second piezoelectric material layer 42 in the technical solution of the embodiment of the present invention can be used in the trench-type device, which can further improve the performance of the trench-type device.

[0117] Based on the above embodiment, optionally, refer to Figure 2 A gate trench 03 is provided on the first surface 01 ; a gate structure 20 is located in the gate trench 03 , and the gate structure 20 includes a second insulating layer 23 and a second gate 24 , and the second insulating layer 23 is located between the gate trench 03 and the second gate 24 .

[0118] The contact area 16 includes a first conductive type area 13 and a second conductive type area 14, the second conductive type area 14 is located on a side of the first conductive type area 13 away from the gate trench 03, and the second conductive type area 14 is in contact with the first conductive type area 13; the well area 12 is located on a side of the first conductive type area 13 and the second conductive type area 14 away from the first surface 01; the first piezoelectric material layer 30 covers the gate structure 20 and part of the first conductive type area 13.

[0119] Among them, the first surface 01 of the semiconductor body 10 is provided with a gate groove 03, and the gate structure 20 is located in the gate groove 03, so that the gate structure 20 extends from the first surface 03 to the semiconductor body 10, wherein the contact area 16 and the well area 12 are both located on both sides of the gate structure 20 and contact the sidewalls of the gate structure 20. The gate structure 20 includes a second gate 24 and a second insulating layer 23 located between the polysilicon gate and the gate groove. The material of the second insulating layer 23 may include at least one of aluminum oxide and silicon oxide, and the second gate 24 may be a polysilicon layer. The gate groove may be a V-shaped groove or a U-shaped groove, or other shapes, which can be set according to actual needs. That is, the embodiment of the present invention Figure 2 The power device in the embodiment is a single trench SiC power device.

[0120] Specifically, in a single-groove power device, a substrate is not required, but a second piezoelectric material layer 42 is used instead, which eliminates the substrate resistance and reduces the on-resistance; and the first piezoelectric material layer 30 and the second piezoelectric material layer 42 can dynamically adjust the transfer characteristics such as the mobility and conductivity of the charge carrier in the semiconductor structure through the piezoelectric effect, so that the response speed and sensitivity of the device to the input signal can be effectively improved, thereby improving the switching speed and conductivity of the device. And due to the existence of the piezoelectric effect, when the first piezoelectric material layer 30 and the second piezoelectric material layer 42 are subjected to external force, an electric potential will be generated, which can realize the switching of the trench power device at an extremely low voltage, or even self-driven power supply, to realize a low-power power device and improve the performance of the single-groove device.

[0121] Based on the above embodiment, optionally, refer to Figure 3 The first surface 01 is provided with a first source trench 04, a gate trench 03 and a second source trench 05 at intervals; the gate trench 03, the first source trench 04 and the second source trench 05 all include a third insulating layer 25 and a polysilicon layer 26, and the polysilicon layer 26 is located on the side of the third insulating layer 25 away from the second surface 02; the third insulating layer 25 and the polysilicon layer 26 in the gate trench 03 are a gate structure.

[0122] The contact area includes a first conductive type area 13 and a second conductive type area 14. The first conductive type area 13 is located on the first surface 01 and between the gate trench 03 and the first source trench 04 and between the gate trench 03 and the second source trench 05. The well area 12 is located on the side of the first conductive type area 13 away from the first surface 01.

[0123] The second conductive type region 14 is located in the semiconductor body 10 at the bottom and side walls of the first source trench 04 and the bottom and side walls of the second source trench 05, and the second conductive type region 14 is located in the semiconductor body 10 at the bottom of the gate trench 03; the second conductive type region 14 is in contact with the third insulating layer 25; the first piezoelectric material layer 30 covers the gate structure and part of the first conductive type region.

[0124] The first source groove 04 and the second source groove 05 may be the same source groove, and may be located on one side of the gate groove 03, with the source groove surrounding the gate groove 03; or, the first source groove 04 and the second source groove 05 are different source grooves, with the gate groove 03 located between the first source groove 04 and the second source groove 05, and the first source groove 04 and the second source groove 05 may be symmetrically arranged with respect to the gate groove 03, or may be asymmetrically arranged. The first source groove 04, the gate groove 03, and the second source groove 05 may be formed simultaneously by the same etching process, and the process is simple and easy to operate. Embodiments of the present invention Figure 3The power device in may be a double trench SiC power device.

[0125] Specifically, in the dual-groove power device, there is no need to use a substrate, but a second piezoelectric material layer 42 is used instead, which eliminates the substrate resistance and reduces the on-resistance; and the first piezoelectric material layer 30 and the second piezoelectric material layer 42 can dynamically adjust the transfer characteristics such as the mobility and conductivity of the charge carrier in the semiconductor structure through the piezoelectric effect, so that the response speed and sensitivity of the device to the input signal can be effectively improved, thereby improving the switching speed and conductivity of the device. And due to the existence of the piezoelectric effect, when the first piezoelectric material layer 30 and the second piezoelectric material layer 42 are subjected to external force, an electric potential will be generated, which can realize the switching of the trench power device at an extremely low voltage, or even self-driven power supply, to realize a low-power power device and improve the performance of the dual-groove device.

[0126] Based on the above embodiment, optionally, refer to Figure 1-3 , power devices also include:

[0127] The second electrode layer 50 is located on the first surface 01 , and covers the contact area 16 not covered by the first piezoelectric material layer 30 ; the material of the second electrode layer 50 includes metal, and the material of the first electrode 41 includes graphene.

[0128] The second electrode layer 50 may be a source metal, and the first electrode 41 in the first electrode layer 40 may be a drain metal, for realizing conduction of the device. The material of the first electrode 41 includes graphene, and the high conductivity of the graphene material can improve the electrode efficiency.

[0129] An embodiment of the present invention further provides a power module based on the above embodiment, comprising a substrate and the power device described in any embodiment of the present invention, wherein the substrate is used to carry the power device.

[0130] The power module provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0131] An embodiment of the present invention further provides a power conversion circuit based on the above embodiments, and the power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and the power device described in any embodiment of the present invention, and the power device is electrically connected to the circuit board.

[0132] The power conversion circuit provided by the technical solution of the embodiment of the present invention has the same beneficial effects as the power device described in any embodiment of the present invention.

[0133] An embodiment of the present invention further provides a vehicle based on the above embodiments, including a load and the power conversion circuit described in any embodiment of the present invention, the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0134] The vehicle provided by the technical solution of the embodiment of the present invention and the power device described in any embodiment of the present invention have the same beneficial effects.

[0135] An embodiment of the present invention provides a method for preparing a power device based on the above embodiment, which is used to prepare the power device described in any embodiment of the present invention. Figure 4 is a flow chart of a method for preparing a power device provided by an embodiment of the present invention, with reference to Figure 4 , the preparation method comprises:

[0136] S110, providing a semiconductor body; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a well region and a contact region; the contact region is located on the first surface, and the well region is located at least on a side of the contact region adjacent to the second surface.

[0137] S120, forming a gate structure on the first surface;

[0138] S130, forming a first electrode layer on the second surface; the first electrode layer includes a first electrode and a second piezoelectric material layer, the second piezoelectric material layer is located on a side of the first electrode away from the second surface; the second piezoelectric material layer is provided with a plurality of cavities, and the plurality of cavities penetrate the second piezoelectric material layer; the first electrode covers the second surface, and the first electrode fills the plurality of cavities.

[0139] S140, forming a first piezoelectric material layer on a side of the gate structure away from the second surface; the first piezoelectric material layer covers the gate structure and a portion of the contact area.

[0140] The method for preparing a power device provided by the technical solution of the embodiment of the present invention adopts a second piezoelectric material layer and a first electrode to replace the substrate. On the one hand, the substrate resistance is eliminated and the on-resistance is reduced; on the other hand, when a voltage is applied to the first piezoelectric material layer and the second piezoelectric material layer, the first piezoelectric material layer and the second piezoelectric material layer will be deformed, and an additional electric field will be generated on the gate structure, thereby improving the mobility and conductivity of the charge carriers in the semiconductor structure, thereby improving the switching speed and conductivity of the device. And due to the existence of the piezoelectric effect, when the first piezoelectric material layer and the second piezoelectric material layer are subjected to external force, an electric potential will be generated, which can realize the switching of the power device at an extremely low voltage, and even directly respond to mechanical stress, without the need for external voltage control, to achieve self-driven power supply, thereby realizing a low-power power device.

[0141] Based on the above embodiment, optionally, Figure 5 yes Figure 4 A detailed flow chart included in S130, Figure 6-Figure 15 is a schematic diagram of an intermediate structure of a power device provided by an embodiment of the present invention, with reference to Figure 5-Figure 15 , S130, forming a first electrode layer on the second surface, comprising:

[0142] S131, forming a first electrode sublayer on the second surface; the first electrode sublayer covers the second surface.

[0143] Among them, reference Fig.12 , a first electrode sublayer 411 can be formed on the second surface 02 by a sputtering process.

[0144] S132. Form a second piezoelectric material sublayer on a side of the first electrode sublayer away from the second surface; the second piezoelectric material sublayer covers the first electrode sublayer.

[0145] Among them, reference Fig.13 , a second piezoelectric material sublayer 422 can be formed on a side of the first electrode sublayer 411 away from the second surface 02 through a bonding process.

[0146] S133, etching the second piezoelectric material sublayer to form a plurality of cavities, thereby forming a second piezoelectric material layer.

[0147] Among them, reference Fig.13 and Fig.14 , the second piezoelectric material sublayer 422 can be etched by a dry etching process to form a plurality of cavities 421 to form a second piezoelectric material layer 42 .

[0148] S134, forming a second electrode sublayer in the plurality of cavities; the first electrode sublayer and the second electrode sublayer are the first electrode, and the first electrode and the second piezoelectric material layer are the first electrode layer.

[0149] Among them, reference Fig.14 , a second electrode sublayer 412 may be formed in the cavity 421 by a sputtering process.

[0150] The embodiment of the present invention can be used to form Figure 1 In the structure, based on the above embodiment, optionally, Fig.16 yes Figure 4 A detailed flow chart included in S110, refer to Fig.16 , S110, providing a semiconductor body, including:

[0151] S111, forming an epitaxial layer on one side of the substrate; a surface of the epitaxial layer away from the substrate is a first surface.

[0152] Among them, reference Figure 6An epitaxial layer 11 may be formed on one side of the substrate 17 by epitaxial growth. The substrate 17 may be an N+ silicon carbide substrate, and the epitaxial layer 11 may be an N- silicon carbide epitaxial layer.

[0153] S112, forming a second conductive type region on the first surface.

[0154] Among them, reference Figure 6 The second conductive type region 14 is formed by an ion implantation process. If the device is an N-type device, P-type ions may be implanted into the first surface 01 to form the second conductive type region 14 .

[0155] S113, forming a well sub-region on the first surface.

[0156] Among them, reference Figure 7 , a well sub-region 06 is formed by an ion implantation process; if the device is an N-type device, P-type ions can be implanted on a side of the second conductive type region 14 away from the first surface 01 to form the well sub-region 06 .

[0157] S114. A first conductive type region and a well region are formed on the first surface; the first conductive type region and the second conductive type region are contact regions; the first conductive type region has a first side and a second side opposite to each other in a first direction, and the first direction is perpendicular to the direction of the substrate pointing to the epitaxial layer; the second conductive type region is located on the first side of the first conductive type region, and the second conductive type region and the first conductive type region are in contact with each other; the well region includes a first sub-region and a second sub-region connected to each other; the first sub-region is located on a side of the first conductive type region adjacent to the substrate; the second sub-region is located on the second side of the first conductive type region.

[0158] Among them, reference Figure 8 , a first conductive type region 13 is formed on the first surface 01 , and N-type ions can be implanted into the first surface to form the first conductive type region 13 .

[0159] The number of the contact region and the well region is two. After forming the first conductive type region and the well region on the first surface in S114, the method further includes:

[0160] A JFET region is formed; the JFET region is located between the two well regions and on a side of the well region away from the first surface

[0161] Among them, reference Fig. 9 The JFET region 15 can be formed by implanting N-type ions at the location of the JFET region 15 . The N-type ions can be phosphorus (P) ions or nitrogen (N) ions. The doping concentration of the JFET region 15 is greater than the doping concentration of the epitaxial layer 11 .

[0162] S120, forming a gate structure on the first surface, including:

[0163] Among them, reference Fig.10A first insulating layer 21 may be formed on the first surface 01 through etching and deposition processes, and a first gate 22 may be formed on a side of the first insulating layer 21 away from the substrate 17 .

[0164] After forming the gate structure on the first surface at S120, the method further includes:

[0165] A sacrificial layer is formed on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and a first surface not covered by the gate structure; and the substrate is removed.

[0166] Among them, reference Fig.10 and Fig.11 The sacrificial layer 60 can protect the device and avoid device fragmentation. The material of the sacrificial layer 60 can be silicon. After the sacrificial layer 60 is formed, the substrate 17 is removed by laser. The substrate is a heavily doped silicon carbide substrate.

[0167] After forming the first electrode layer on the second surface in S130, the method further includes: removing the sacrificial layer. Fig.14 and Fig.15 , the sacrificial layer 60 can be removed by conventional removal process to form Fig.15 The structure in .

[0168] After forming the first piezoelectric material layer on the side of the gate structure away from the second surface at S140, the method further includes: forming a second electrode layer on the first surface; the second electrode layer covers the contact area not covered by the first piezoelectric material layer.

[0169] The embodiment of the present invention can be used to form Figure 2 In the structure, based on the above embodiment, optionally, Fig.17 yes Figure 4 Another detailed flow chart included in S110 is shown in FIG. Fig.17 , S110, providing a semiconductor body, including:

[0170] S210, forming an epitaxial layer on one side of the substrate; a surface of the epitaxial layer away from the substrate is a first surface.

[0171] Among them, reference Figure 2 , an epitaxial layer 11 can be formed on one side of the substrate by epitaxial growth.

[0172] S220, etching the first surface to form a gate trench.

[0173] Among them, reference Figure 2 The gate trench 03 can be formed by etching the first surface through a dry etching or wet etching process.

[0174] S230 , forming a second conductive type region on the first surface.

[0175] Among them, reference Figure 2 , the second conductive type region 14 is formed by an ion implantation process. If the device is an N-type device, P-type ions may be implanted into the first surface to form the second conductive type region 14.

[0176] S240, forming a well region in the second conductive type region away from the first surface.

[0177] Among them, reference Figure 2 , a well region 12 is formed by an ion implantation process; if the device is an N-type device, P-type ions may be implanted on a side of the second conductive type region 14 away from the first surface 01 to form the well region 12 .

[0178] S250, forming a first conductive type region on the first surface; the first conductive type region and the second conductive type region are contact regions; the second conductive type region is located on a side of the first conductive type region away from the gate trench, and the second conductive type region is in contact with the first conductive type region.

[0179] Among them, reference Figure 2 , a first conductive type region 13 is formed on the first surface 01 , and N-type ions may be implanted into the first surface 01 to form the first conductive type region 13 .

[0180] S120, forming a gate structure on the first surface, including:

[0181] A gate structure is formed in the gate trench; the gate structure includes a second insulating layer and a second gate, and the second insulating layer is located between the gate trench and the second gate.

[0182] Among them, reference Figure 2 A second insulating layer 23 may be formed in the gate trench through an oxidation process and an etching process, and a second gate 24 may be formed on a side of the second insulating layer 23 away from the second surface 02 .

[0183] After forming the gate structure on the first surface at S120, the method further includes:

[0184] A sacrificial layer is formed on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and a first surface not covered by the gate structure; and the substrate is removed.

[0185] Among them, the sacrificial layer can play a role in protecting the device and avoiding device fragments. The material of the sacrificial layer can be silicon. After the sacrificial layer is formed, the substrate is removed by laser, and the substrate is a heavily doped silicon carbide substrate.

[0186] After forming the first electrode layer on the second surface at S130 , the step further includes: removing the sacrificial layer.

[0187] After forming the first piezoelectric material layer on the side of the gate structure away from the second surface at S140, the method further includes: forming a second electrode layer on the first surface; the second electrode layer covers the contact area not covered by the first piezoelectric material layer.

[0188] The embodiment of the present invention can be used to form Figure 3 In the structure, based on the above embodiment, Fig.18 yes Figure 4 Another detailed flow chart included in S110 is shown in FIG. Fig.18 , optionally, providing a semiconductor body, comprising:

[0189] S310, forming an epitaxial layer on one side of a substrate; a surface of the epitaxial layer away from the substrate is a first surface.

[0190] S320, etching the first surface to form a first source trench, a gate trench, and a second source trench.

[0191] Among them, reference Figure 3 The first surface can be etched by dry etching or wet etching to form the first source trench 04, the gate trench 03 and the second source trench 05.

[0192] S330, forming a second conductive type region; the second conductive type region is located in the epitaxial layer at the bottom and sidewall of the first source trench and the bottom and sidewall of the second source trench, and is located in the epitaxial layer at the bottom of the gate trench.

[0193] Among them, reference Figure 3 , the second conductive type region 14 is formed by an ion implantation process. If the device is an N-type device, P-type ions may be implanted into the first surface to form the second conductive type region 14.

[0194] S340, forming a well region.

[0195] Among them, reference Figure 3 , a well region 12 is formed by an ion implantation process; if the device is an N-type device, P-type ions may be implanted into the first surface 01 to form the well region 12 .

[0196] S350, forming a first conductive type region on the first surface; the first conductive type region is located between the gate trench and the first source trench and between the gate trench and the second source trench; the well region is located on a side of the first conductive type region away from the first surface.

[0197] Among them, reference Figure 3 , a first conductive type region 13 is formed on the first surface 01 , and N-type ions may be implanted into the first surface 01 to form the first conductive type region 13 .

[0198] S120, forming a gate structure on the first surface, including:

[0199] forming a third insulating layer in the gate trench, in the first source trench, and in the second source trench;

[0200] A polysilicon layer is formed on a side of the third insulating layer away from the substrate; the third insulating layer and the polysilicon layer in the gate trench form a gate structure.

[0201] Among them, reference Figure 3 A third insulating layer 25 can be formed in the gate trench 03, the first source trench 04, and the second source trench 05 through an oxidation process and an etching process, and a polysilicon layer 26 is formed on a side of the third insulating layer 25 away from the substrate.

[0202] After forming the gate structure on the first surface at S120, the method further includes:

[0203] A sacrificial layer is formed on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and a first surface not covered by the gate structure; and the substrate is removed.

[0204] Among them, the sacrificial layer can play a role in protecting the device and avoiding device fragments. The material of the sacrificial layer can be silicon. After the sacrificial layer is formed, the substrate is removed by laser, and the substrate is a heavily doped silicon carbide substrate.

[0205] After forming the first electrode layer on the second surface at S130 , the step further includes: removing the sacrificial layer.

[0206] After forming the first piezoelectric material layer on the side of the gate structure away from the second surface at S140, the method further includes: forming a second electrode layer on the first surface; the second electrode layer covers the contact area not covered by the first piezoelectric material layer.

[0207] The method for preparing a power device provided in an embodiment of the present invention has the same beneficial effects as the power device in any embodiment of the present invention.

[0208] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0209] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A power device, characterized in that: include: A semiconductor body, the semiconductor body comprising a first surface and a second surface arranged opposite to each other, the semiconductor body further comprising a well region and a contact region; the contact region is located on the first surface, and the well region is located at least on a side of the contact region adjacent to the second surface; a gate structure, the gate structure being located on the first surface; or the first surface being provided with at least one trench, the trench extending from the first surface into the semiconductor body; The gate structure is located in the trench; A first piezoelectric material layer, wherein the first piezoelectric material layer is located on a side of the gate structure away from the second surface; The first piezoelectric material layer covers the gate structure and a portion of the contact area; a first electrode layer, the first electrode layer being located on the second surface; the first electrode layer comprising a first electrode and a second piezoelectric material layer, the second piezoelectric material layer being located on a side of the first electrode away from the second surface; the second piezoelectric material layer being provided with a plurality of cavities, the plurality of cavities penetrating the second piezoelectric material layer; The first electrode covers the second surface, and the first electrode fills the plurality of cavities.

2. The power device according to claim 1, characterized in that: In the case where the gate structure is located on the first surface, The contact region comprises a first conductive type region and a second conductive type region; the first conductive type region has a first side and a second side opposite to each other in a first direction, the first direction being perpendicular to a direction of the first electrode layer pointing to the semiconductor body; the second conductive type region is located on a first side of the first conductive type region, and the second conductive type region and the first conductive type region are in contact with each other; The well region includes a first sub-region and a second sub-region connected to each other, the first sub-region is located on a side of the first conductive type region adjacent to the second surface; the second sub-region is located on a second side of the first conductive type region.

3. The power device according to claim 2, characterized in that: In the case where the gate structure is located on the first surface, The number of the contact region and the well region is two; The semiconductor body further comprises a JFET region, wherein the JFET region is located between the two well regions and on a side of the well region away from the first surface; The gate structure comprises a first insulating layer and a first gate, wherein the first insulating layer is located on a side of the first surface away from the second surface, and the first insulating layer covers the JFET region, the second sub-region and a portion of the first conductive type region between the two well regions; the first gate is located on a side of the first insulating layer away from the first surface, and the first gate covers a portion of the first insulating layer; The first piezoelectric material layer is located on a side of the first grid electrode away from the first surface, and the first piezoelectric material layer covers the first grid electrode and the first insulating layer not covered by the first grid electrode.

4. The power device according to claim 1, characterized in that: In the case where the gate structure is located within the trench, The first surface is provided with a gate trench; The gate structure is located in the gate trench, the gate structure includes a second insulating layer and a second gate, and the second insulating layer is located between the gate trench and the second gate; The contact region includes a first conductive type region and a second conductive type region, the second conductive type region is located at a side of the first conductive type region away from the gate trench, and the second conductive type region is in contact with the first conductive type region; The well region is located on a side of the first conductive type region and the second conductive type region away from the first surface; The first piezoelectric material layer covers the gate structure and a portion of the first conductive type region.

5. The power device according to claim 1, characterized in that: In the case where the gate structure is located within the trench, Also includes: The first surface is provided with a first source trench, a gate trench, and a second source trench at intervals; The gate trench, the first source trench and the second source trench all include a third insulating layer and a polysilicon layer, and the polysilicon layer is located on a side of the third insulating layer away from the second surface; the third insulating layer and the polysilicon layer in the gate trench are the gate structure; The contact region includes a first conductive type region and a second conductive type region, the first conductive type region is located on the first surface, and is located between the gate trench and the first source trench and between the gate trench and the second source trench; the well region is located on a side of the first conductive type region away from the first surface; The second conductive type region is located in the semiconductor body at the bottom and sidewall of the first source trench and the bottom and sidewall of the second source trench, and the second conductive type region is located in the semiconductor body at the bottom of the gate trench; the second conductive type region is in contact with the third insulating layer; The first piezoelectric material layer covers the gate structure and a portion of the first conductive type region.

6. The power device according to claim 1, characterized in that: Also includes: a second electrode layer, the second electrode layer being located on the first surface, and the second electrode layer covering the contact area not covered by the first piezoelectric material layer; The material of the second electrode layer includes metal, and the material of the first electrode includes graphene.

7. A power module, characterized in that: The invention comprises a substrate and at least one power device according to any one of claims 1 to 6, wherein the substrate is used for supporting the power device.

8. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit comprises a circuit board and at least one power device according to any one of claims 1 to 6, wherein the power device is electrically connected to the circuit board.

9. A vehicle, characterized in that: It includes a load and a power conversion circuit as described in claim 8, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

10. A method for preparing a power device, characterized in that: Used to prepare the power device according to any one of claims 1 to 6, comprising: A semiconductor body is provided; the semiconductor body comprises a first surface and a second surface arranged opposite to each other, and the semiconductor body further comprises a well region and a contact region; the contact region is located on the first surface, and the well region is located at least on a side of the contact region adjacent to the second surface; Forming a gate structure on the first surface; or etching the first surface to form at least one trench, the trench extending from the first surface into the semiconductor body, the gate structure being located in the trench; A first electrode layer is formed on the second surface; the first electrode layer includes a first electrode and a second piezoelectric material layer, the second piezoelectric material layer is located on a side of the first electrode away from the second surface; the second piezoelectric material layer is provided with a plurality of cavities, the plurality of cavities passing through the second piezoelectric material layer; the first electrode covers the second surface, and the first electrode fills the plurality of cavities; A first piezoelectric material layer is formed on a side of the gate structure away from the second surface; the first piezoelectric material layer covers the gate structure and a portion of the contact area.

11. The preparation method according to claim 10, characterized in that: Forming a first electrode layer on the second surface includes: forming a first electrode sublayer on the second surface; the first electrode sublayer covers the second surface; forming a second piezoelectric material sublayer on a side of the first electrode sublayer away from the second surface; the second piezoelectric material sublayer covers the first electrode sublayer; Etching the second piezoelectric material sublayer to form a plurality of cavities to form a second piezoelectric material layer; A second electrode sublayer is formed in the plurality of cavities; the first electrode sublayer and the second electrode sublayer are first electrodes, and the first electrode and the second piezoelectric material layer are the first electrode layer.

12. The preparation method according to claim 10, characterized in that: Provide a semiconductor body, including: An epitaxial layer is formed on one side of a substrate; a surface of the epitaxial layer away from the substrate is a first surface; forming a second conductive type region on the first surface; forming a well sub-region on the first surface; A first conductive type region and a well region are formed on the first surface; the first conductive type region and the second conductive type region are contact regions; the first conductive type region has a first side and a second side opposite to each other in a first direction, the first direction being perpendicular to the direction of the substrate pointing to the epitaxial layer; the second conductive type region is located on a first side of the first conductive type region, and the second conductive type region and the first conductive type region are in contact with each other; the well region includes a first sub-region and a second sub-region connected to each other; the first sub-region is located on a side of the first conductive type region adjacent to the substrate; the second sub-region is located on a second side of the first conductive type region; After forming a gate structure on the first surface, the method further includes: forming a sacrificial layer on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and the first surface not covered by the gate structure; removing the substrate; After forming the first electrode layer on the second surface, the method further comprises: The sacrificial layer is removed.

13. The preparation method according to claim 12, characterized in that: The number of the contact area and the well area is two, and after the first conductive type area and the well area are formed on the first surface, the method further includes: A JFET region is formed between the two well regions and on a side of the well region away from the first surface.

14. The preparation method according to claim 10, characterized in that: Provide a semiconductor body, including: An epitaxial layer is formed on one side of a substrate; a surface of the epitaxial layer away from the substrate is a first surface; Etching the first surface to form a gate trench; forming a second conductive type region on the first surface; forming a well region in the second conductive type region away from the first surface; A first conductive type region is formed on the first surface; the first conductive type region and the second conductive type region are contact regions; the second conductive type region is located on a side of the first conductive type region away from the gate trench, and the second conductive type region is in contact with the first conductive type region; A gate structure is formed on the first surface, comprising: A gate structure is formed in the gate trench; the gate structure comprises a second insulating layer and a second gate, and the second insulating layer is located between the gate trench and the second gate; After forming a gate structure on the first surface, the method further includes: A sacrificial layer is formed on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and the first surface not covered by the gate structure; removing the substrate; After forming the first electrode layer on the second surface, the method further comprises: The sacrificial layer is removed.

15. The preparation method according to claim 10, characterized in that: Provide a semiconductor body, including: An epitaxial layer is formed on one side of a substrate; a surface of the epitaxial layer away from the substrate is a first surface; Etching the first surface to form a first source trench, a gate trench, and a second source trench; Forming a second conductive type region; the second conductive type region is located in the epitaxial layer at the bottom and sidewalls of the first source trench and the bottom and sidewalls of the second source trench, and is located in the epitaxial layer at the bottom of the gate trench; forming a well region; A first conductive type region is formed on the first surface; the first conductive type region is located between the gate trench and the first source trench and between the gate trench and the second source trench; the well region is located on a side of the first conductive type region away from the first surface; A gate structure is formed on the first surface, comprising: forming a third insulating layer in the gate trench, in the first source trench, and in the second source trench; A polysilicon layer is formed on a side of the third insulating layer away from the substrate; the third insulating layer and the polysilicon layer in the gate trench form a gate structure; After forming a gate structure on the first surface, the method further includes: forming a sacrificial layer on a side of the gate structure away from the substrate; the sacrificial layer covers the gate structure and the first surface not covered by the gate structure; removing the substrate; After forming the first electrode layer on the second surface, the method further comprises: The sacrificial layer is removed.

16. The preparation method according to claim 10, characterized in that: After forming a first piezoelectric material layer on a side of the gate structure away from the second surface, the method further includes: A second electrode layer is formed on the first surface; the second electrode layer covers the contact area not covered by the first piezoelectric material layer.

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