Multiplication spread spectrum generator

Abstract

In some examples, a circuit (104) includes a phase frequency detector (PFD) (206) having a first input, a second input, and an output. The circuit also includes a control circuit (208) having an input and an output, the control circuit input coupled to the output of the PFD. The circuit also includes a modulation circuit (210) having an input and an output, the modulation circuit being input-coupled to the output of the control circuit. The circuit also includes an oscillator (212) having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit, and the output of the oscillator coupled to the second input of the PFD.

Description

Background Art

[0001] A phase-locked loop (PLL) is a circuit that provides an output signal having a phase related to the phase of the input signal of the PLL. The phase of the output signal has a relationship with the phase of the input signal such that the frequency of the output signal has a relationship with the frequency of the input signal. For example, the output frequency is a multiple of the input frequency. Summary of the invention

[0002] In some examples, a circuit includes a phase frequency detector (PFD) having a first input, a second input, and an output. The circuit also includes a control circuit having an input and an output, the control circuit input coupled to the output of the PFD. The circuit also includes a modulation circuit having an input and an output, the modulation circuit input coupled to the output of the control circuit. The circuit also includes an oscillator having an oscillator input and an oscillator output, the oscillator input coupled to the output of the modulation circuit, and the output of the oscillator coupled to the second input of the PFD.

[0003] In some examples, a PLL includes an input, an output, a PFD, a control circuit, a modulation circuit, and an oscillator. The PFD is coupled to the input of the PLL and can be used to provide a first control signal in response to receiving a reference signal having a reference signal frequency and a feedback signal having a feedback signal frequency and comparing the reference signal to the feedback signal. The control circuit is coupled to the PFD and can be used to receive the first control signal and provide a second control signal having a current value determined based on the first control signal. The modulation circuit is coupled to the control circuit and can be used to modulate the second control signal to provide a modulated control signal that varies in value within a cycle of the reference signal. The oscillator is coupled between the modulation circuit and the output of the PLL, and can be used to provide a signal having an output frequency proportional to the value of the second control signal, wherein at a rising edge of the reference signal, the second control signal has a value sufficient to make the output frequency equal to the reference signal frequency.

[0004] In some examples, a method includes receiving a reference signal having a reference signal frequency, comparing the reference signal frequency to a frequency of a feedback signal, providing a first control signal having a value based on a result of the comparison, providing a second control signal having a value proportional to the reference signal frequency and based on the first control signal, modulating the second control signal based on a modulation signal to form a modulated control signal, and providing a signal having a frequency proportional to the modulated control signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 is a block diagram of a system in various embodiments.

[0006] Figure 2 is a block diagram of a PLL in various examples.

[0007] Figure 3 Schematic diagram of modulation circuits in various examples.

[0008] Figure 4 is a timing diagram of the signals in various examples.

[0009] Figure 5 Flowchart of a method of operating a PLL in various examples.

[0010] The same reference numbers or other reference designators are used in the drawings to indicate the same or similar features (functionally and / or structurally). DETAILED DESCRIPTION

[0011] The PLL may be applicable in various circuits, systems or devices where signal synchronization is useful. For example, the PLL may be applicable in clock synchronization, demodulation, frequency generation or other use cases in application environments such as communications, digital device control (e.g., clock generation), etc. Based on the frequency (F_IN) of a received signal (e.g., a reference clock (CLK_IN) or other reference signal), the PLL provides an output signal having a frequency (F_PLL) that is a multiple of F_IN.

[0012] PLL can be applied to the operation of direct current (DC) to DC power converter. However, the operation of DC to DC power converter can generate electromagnetic interference (EMI) based on the frequency of F_PLL (e.g., the switching frequency of DC to DC power converter). For example, due to government regulations, industry standards, etc., some use cases of DC to DC power converter may be sensitive to the generation of EMI, or may be limited by the generated EMI. Although it may be challenging to completely prevent the generation of EMI, certain technologies can reduce or otherwise mitigate EMI. One such method is spread spectrum clock (SSC). SSC modulates the output signal (CLK_PLL) of PLL to have a frequency within a predetermined range centered on F_PLL. This modulation prevents or mitigates EMI concentration under F_PLL, and alternatively, distributes radiated EMI between the frequencies distributed in the range around F_PLL and determined based on SSC. In order to limit the generated EMI to a specific amount, given a specific F_PLL, there may be an ideal or optimal modulation frequency and amplitude for SSC modulation. In at least one application environment, this modulation frequency is about 120 kilohertz (kHz). Some use cases of the PLL may include boundary conditions that place the SSC modulation frequency outside the bandwidth of the PLL. In at least some instances, the bandwidth of the PLL is about one-tenth or less of F_IN, which may be about 120 kHz.

[0013] This specification includes various examples of PLLs that can be configured to provide an output signal CLK_PLL that has been modulated according to an SSC modulation frequency (F_ssc), which may not be within the bandwidth of the PLL. At least some of the examples include circuitry (e.g., analog, digital, or a combination thereof) suitable for performing this modulation to provide CLK_PLL. In some examples, the amplitude of the modulated signal is not adjusted by the PLL, but may be insensitive to process, voltage, or temperature (PVT) changes. At least some embodiments of the PLL include an oscillator. The oscillator can be detuned to produce frequency modulation. Detuning can be performed by modulating a control signal of the oscillator, the control signal being, for example, a current value provided to the oscillator so that the oscillator provides CLK_PLL. For example, the oscillator can be detuned according to a modulation signal (I_ssm), the modulation signal being determined according to F_ssc, and the F_ssc can be an integer multiple of F_IN. The PLL can adjust F_PLL based on the average value of F_PLL within one clock cycle of CLK_REF. In this way, CLK_PLL can be modulated in both positive and negative directions relative to F_PLL according to F_ssc (e.g., in one example, by equal amounts in both positive and negative directions—in other words, by a certain amount greater or less than F_PLL), wherein the modulation does not affect the average value of F_PLL and F_ssc is not within the PLL bandwidth. Thus, the modulation can be said to be invisible to the PLL.

[0014] Figure 1 1 is a block diagram of system 100 in various examples. In some embodiments, system 100 may benefit from the implementation of a PLL. Thus, system 100 includes device 102, which includes PLL 104, circuit 106, and circuit 108. Device 102 may be any suitable device, such as a computer system, a router, a smart phone, a wearable device, an audio and / or video device, a component of a transportation vehicle, etc., which may benefit from a PLL as described herein, such as PLL 104. PLL 104 may be implemented according to any suitable technology including analog and / or digital components, and may be implemented in a single integrated circuit or multiple integrated circuits coupled together. In addition, PLL 104 may be implemented on the same integrated circuit as at least some components of other circuits, such as circuit 106, circuit 108, and / or Figure 1104. The circuit 106 provides CLK_IN to the PLL 104. In some examples, CLK_IN is received by the circuit 106 as an input from another component or provided by a user, and the circuit 106 in turn provides CLK_IN to the PLL 104. In other examples, CLK_IN is generated or otherwise provided by the circuit 106 based on one or more other signals, which may be received by the system 100 from a user and / or generated by the system 100. The circuit 106 may be implemented according to any suitable technology including analog and / or digital components, and may include, for example, a processor, a state machine, a logic circuit system, a digital circuit system, a memory, an analog circuit system, software, and / or any combination thereof adapted to perform at least the operations or functions attributed to the circuit 106 herein. The circuit 108 receives the output signal (CLK_PLL) of the PLL 104. In some examples, circuit 108 operates at least in part according to CLK_PLL (e.g., can be timed according to CLK_PLL, synchronized based on CLK_PLL, or otherwise process another signal, etc.). As described herein, CLK_PLL has a frequency F_PLL, which has a relationship, such as an integer relationship, with F_IN (which is, for example, the frequency of the received clock signal CLK_IN). As used herein, an integer relationship between two values ​​means that one of the values ​​is multiplied by an integer to obtain the other value, or one of the values ​​is divided by an integer to obtain the other value. Circuit 108 can be implemented according to any suitable technology including analog and / or digital components, and can include, for example, a processor, a state machine, a logic circuit system, a digital circuit system, a memory, an analog circuit system, software, and / or any combination thereof suitable for performing at least the operations or functions attributed to circuit 108 herein.

[0015] PLL 104 can be used to receive CLK_IN and manipulate CLK_IN to form a signal CLK_REF having a frequency F_ref. F_ref has an integer relationship with F_IN. For example, PLL 104 divides CLK_IN to form CLK_REF so that F_ref is a part of F_IN. PLL 104 compares the frequency and phase of CLK_REF with the frequency and phase of a feedback signal, which has an integer relationship with CLK_PLL. Based on the comparison, PLL 104 provides a control signal for controlling an oscillator (not shown) within PLL 104. In at least some instances, the control signal is a current-based control signal (I_ctrl0). The control signal can be provided to a modulation circuit (not shown) within PLL 104, which determines I_ssm based on F_ssm and CLK_IN and adds the modulation signal to I_ctrl0 to form a second control signal (I_ctrl). In at least some instances, I_ssm is expressed in current. PLL 104 controls the oscillator based on I_ctrl to provide CLK_PLL 104. In some examples, PLL 104 further manipulates (eg, amplifies or divides) the output signal of the oscillator before providing the manipulated signal as CLK_PLL.

[0016] Figure 2 1 is a block diagram of a PLL 104 in various examples. PLL 104 includes a frequency divider 202, a frequency divider 204, a phase frequency detector (PFD) 206, a control circuit 208, a modulation circuit 210, an oscillator 212, a control circuit 216, and a frequency divider 218. Frequency divider 202, frequency divider 204, and frequency divider 218 may employ any suitable technology including digital and / or analog components that may be used to divide the frequency of a signal so as to reduce the frequency of an output signal of the frequency divider relative to the frequency of an input signal received by the frequency divider. PFD 206 may employ any suitable technology including digital and / or analog components that may be used to receive a plurality of signals and compare the frequency and / or phase values ​​of the signals to determine an output value. The output value of PFD 206 may indicate that a control signal for controlling oscillator 212 should be increased in value or should be decreased in value. In an example, control circuit 216 may be any suitable control circuit that may be used to receive an input signal and provide a DACCODE based on the received input signal. In some examples, the input signal to the control circuit 216 is CLK_IN. The control circuit 216 may include, for example, a processor, a state machine, logic circuitry, digital circuitry, memory, analog circuitry, software, and / or any combination thereof suitable for performing at least the operations or functions attributed to the control circuit 216 herein.

[0017] The control circuit 208 may employ any suitable technology including digital and / or analog components that can be used to receive a signal and provide a control signal based on the received signal. In some examples, the control circuit 208 is implemented as or includes a charge pump that is capable of providing a control signal having a current value determined based on the output value of the PFD 206. The modulation circuit 210 may employ any suitable technology including digital and / or analog components (e.g., transistors, resistors, amplifiers, etc.) that can be used to receive a control signal from the control circuit 216 and control the oscillator 212 to provide an output signal having a frequency proportional to the value of the control signal (e.g., a frequency proportional to the value of the current of the control signal). The oscillator 212 may employ any suitable technology including digital and / or analog components that can be used to provide a signal having a frequency proportional to the value of the input signal received by the oscillator 212 or otherwise determined based on the value. In some examples, the oscillator 212 has a ring oscillator architecture and / or includes a bulk acoustic wave device (BAW). In some examples, the oscillator 212 can be used to provide its output signal as CLK_PLL. In other examples, the output signal of oscillator 212 is provided to a frequency divider (not shown) or other circuitry that manipulates the output signal of oscillator 212 to provide CLK_PLL. Control circuit 216 may employ any suitable technology including digital and / or analog components that may be used to receive the input signal of PLL 104 or other signals and provide a digital (or other) control signal to modulation circuit 210. For example, a digital signal may control the value of the modulation signal of modulation circuit 210, such as by multiplying digital-to-analog converter (DAC) 220. For example, control circuit 216 may include a counter, such as a digital up / down counter (not shown), adapted to determine DACCODE as a digital signal and provide DACCODE as a digital signal. Frequency divider 218 may be coupled between the output of oscillator 212 and the input of PFD 206 and may be used to provide a feedback signal to PFD 206 that is a scaled representation (e.g., with a lower frequency or divided frequency) of the output signal of oscillator 212.

[0018] In an example of operation of PLL 104, a clock signal CLK_IN (having a frequency of F_IN) is received at an input of PLL 104. In an example of PLL 104 that includes frequency divider 202 and frequency divider 204, CLK_IN is divided by frequency divider 202 and frequency divider 204 to form CLK_REF having a frequency of F_ref. In one example, frequency divider 202 is a divide-by-2 circuit and frequency divider 204 is a divide-by-16 circuit. Although in Figure 2218, but in various examples, more or fewer frequency dividers each having any suitable frequency divider value may be implemented. PFD 206 receives CLK_REF and compares CLK_REF to the output of frequency divider 218. Based on the comparison, PFD 206 provides a control signal to control circuit 208. For example, in response to F_ref being greater than the frequency of the output signal of frequency divider 218, PFD 206 provides a control signal to control circuit 208, which control signal may be used to cause control circuit 208 to increase the value of the control signal provided for controlling oscillator 212. Similarly, in response to F_ref being less than the frequency of the output signal of frequency divider 218, PFD 206 provides a control signal to control circuit 208, which control signal may be used to cause control circuit 208 to decrease the value of the control signal provided for controlling oscillator 212. PFD 206 may perform phase and / or frequency comparisons according to any suitable hardware architecture, software process, or combination thereof.

[0019] Based on the control signal provided by PFD 206, control circuit 208 may be used to provide a control signal for controlling oscillator 212. For example, control circuit 208 may receive the output signal of PFD 206 and provide a control signal having a value that is proportional to the value of the output signal of PFD 206. In some examples, the control signal provided by control circuit 208 has a current that is proportional to or otherwise related to the value of the output signal of PFD 206. For example, control circuit 208 may include a charge pump of any suitable architecture that receives the output signal of PFD 206 and provides a control signal having a current value that has a relationship to the value of the output signal of PFD 206. The control signal provided by control circuit 208 is Figure 2 The middle one is indicated as I_ctrl0.

[0020] The modulation circuit 210 receives I_ctrl0 and provides the current I_ctrl to the oscillator 212 based in part on I_ctrl0. For example, in various embodiments, the modulation circuit 210 can be used to modulate I_ctrl0 to generate I_ctrl. In some examples, the modulation of I_ctrl0 provides SSC, as described above in this article, to mitigate the generation of EMI under the harmonics of F_PLL and / or F_PLL. In order to modulate I_ctrl0, the DAC 220 receives DACCODE from the control circuit 216. The control circuit 216 provides DACCODE based on CLK_IN and / or F_IN according to any suitable process, and the scope of the process is not limited herein. For example, the control circuit 216 can determine and provide DACCODE based on the shape used for modulation, such as having a value suitable for forming a sine wave approximation, a triangle wave approximation, a square wave approximation, or any other suitable modulation mode. Based on DACCODE, the DAC220 can be used to provide I_ssm. In some examples, I_ssm is a current having a value proportional to the value of DACCODE. Modulation circuit 210 may be used to add I_ctrl0 and I_ssm to provide I_ctrl. In some examples, the addition is performed via a direct coupling between the output of control circuit 208 and the output of DAC 220 (e.g., summation of currents at nodes in modulation circuit 210). In other examples, modulation circuit 210 includes circuit structures or components (not shown) that receive both I_ctrl0 and I_ssm and provide I_ctrl as the sum of I_ctrl0 and I_ssm.

[0021] The modulation circuit 210 provides I_ctrl to an oscillator 212. The oscillator 212 can be used to provide an output signal having a frequency that is proportional to the value of I_ctrl. For example, the frequency of the output signal of the oscillator 212 can be proportional to the current value of I_ctrl or have another relationship. In some examples, the oscillator 212 has a ring oscillator architecture, while in other examples, the oscillator 212 has any suitable architecture for providing a signal having a frequency that has a programmed or predictable relationship to the value of I_ctrl.

[0022] In some examples, PLL 104 includes an additional divider (not shown) after oscillator 212, so that the output signal of oscillator 212 can be divided by the divider to form CLK_PLL with a frequency F_PLL. The division can be performed by any suitable division value (e.g., a division value of 4) based on the application environment of PLL 104. The output signal of oscillator 212 can be divided by divider 218 to form a feedback signal for providing to PFD 206, as described above. Divider 218 can divide by any suitable division value based on the application environment of PLL 104.

[0023] By controlling the generation of I_ctrl according to both I_ctrl0 and I_ssm, CLK_PLL (and thus, F_PLL) can be modulated around the programmed or target frequency output by PLL 104. By modulating F_PLL, the peak value of EMI generated and / or radiated by F_PLL can be reduced. However, based on the control applied according to DACCODE, at each rising clock edge of CLK_REF, F_PLL can have a value substantially equal to the programmed or target frequency output by PLL 104, so that the modulation is effectively transparent to PLL 104.

[0024] Figure 3 is a schematic diagram of modulation circuit 210 in various examples. In some examples, modulation circuit 210 includes transistor 302, transistor 304, transistor 306, transistor 308, transistor 310, transistor 312, transistor 314, DAC 316, amplifier 318, and resistor 320. In some examples, at least some of the various transistors of modulation circuit 210 are field effect transistors (FETs), such as metal oxide semiconductor FETs (MOSFETs).

[0025] In an exemplary architecture of modulation circuit 210, transistor 302 is an n-channel MOSFET (nMOSFET) and has a drain that can be used to receive I_ctrl0 (e.g., by coupling to the output of control circuit 208) and a source coupled to ground 322. Transistor 304 has a gate coupled to the gate and drain of transistor 302, a source coupled to ground 322, and a drain coupled to oscillator 212 (e.g., so that I_ctrl can be provided at the drain of transistor 304). In at least some examples, transistor 302 and transistor 304 form a current mirror so that a scaled amount of current flowing through transistor 302 also flows through transistor 304. For example, if transistors 302 and 304 are the same size (e.g., channel width and channel length), the current flowing through transistor 302 will be equal to the current flowing through transistor 304. Otherwise, the scaled current will be proportional to the size difference of the transistors. Transistor 306 has a gate coupled to the gate of transistor 302, a source coupled to ground 322, and a drain. In at least some instances, transistor 302 and transistor 306 form a current mirror so that a scaled amount of current flowing through transistor 302 also flows through transistor 306. Transistor 308 is a p-channel transistor (pMOSFET) and has a gate coupled to the drain of transistor 306 and the drain of transistor 308, and a source coupled to power supply 324. Transistor 310 has a gate coupled to the drain of transistor 306 and the gate of transistor 308, a drain, and a source coupled to power supply 324. In at least some instances, transistor 308 and transistor 310 form a current mirror so that a scaled amount of current flowing through transistor 310 is based on an amount of current flowing through transistor 308. Transistor 312 has a gate coupled to the drain of transistor 306, a drain, and a source coupled to power supply 324. In at least some instances, transistor 308 and transistor 312 form a current mirror such that a scaled amount of current flowing through transistor 312 is based on the amount of current flowing through transistor 308. In some instances, the ratio of the current mirror is 1:1, while in other instances, the ratio is 1:X, where X is related to the size difference of the transistors forming the current mirror. Transistor 314 has a gate, a drain coupled to the drain of transistor 312, and a source.

[0026] DAC 316 has a first terminal coupled to the drain of transistor 312, a second terminal coupled to ground 322, a control terminal coupled to control circuit 216, and an output terminal. DAC 316 can have any suitable architecture, such as a resistor DAC. Amplifier 318 has a first input terminal (e.g., a non-inverting input) coupled to the output terminal of DAC 316, an output terminal coupled to the gate of transistor 314, and a second input terminal (e.g., an inverting input) coupled to the source of transistor 314. Resistor 320 is coupled between the source of transistor 314 and ground 322. In some examples, DAC 316, amplifier 318, transistor 314, and resistor 320 collectively form Figure 2 DAC 220.

[0027] In an example of the operation of the modulation circuit 210, the current I_ctrl0 may be received from the PLL control loop as a control signal (e.g., as an output of the control circuit 208). The modulation circuit 210 mirrors (and in some examples scales I_ctrl0) I_ctrl0 via transistors 302, 304, and 312 and provides it at the output of the modulation circuit 210 (e.g., at the drain of transistor 304). The modulation circuit 210 also mirrors (and in some examples scales I_ctrl0) I_ctrl0 via transistors 302, 306 and 308, 310 and applies it to the DAC 316. For example, the current I_ctrl0 flows through transistor 302 and is mirrored to flow through transistor 306. Through its coupling, the current flowing through transistor 306 also flows through transistor 308. The current flowing through transistor 308 is mirrored to flow through transistor 310 and into DAC 316. In some examples, the DAC 316 is a resistor ladder. For example, the DAC 316 may be a resistor ladder having 17 taps, wherein the resistor ladder includes a plurality of switches coupled between respective taps of the resistor ladder and a first input terminal of the amplifier 318. Each of these switches may be controlled according to a respective bit of the DACCODE. In other examples, the number of taps of the resistor ladder, and therefore the accuracy of the DAC 316, may correspond to the number of unique values ​​possible based on the number of bits included in the DACCODE.

[0028] Based on the value of DACCODE, DAC 316 provides a value (e.g., a tap voltage) at a first input terminal of amplifier 318. Amplifier 318 and transistor 314 provide a tap voltage at the source of transistor 314, so that a voltage is provided across resistor 320. The voltage across resistor 320 generates a current I_ssm, which can be added to I_ctrl0 at the output of modulation circuit 210 based on node summation. In some examples, modulation circuit 210 provides I_ssm so that I_ssm has a value that is substantially equal to a portion of I_ctrl0 multiplied by the value of DACCODE. As described above, combining I_ctrl0 with I_ssm facilitates modulation of PLL 104 to mitigate EMI formation at F_PLL or its harmonics, while facilitating PLL 104 to provide a signal having an average frequency of F_PLL.

[0029] For example, the oscillator 212 may be a current controlled oscillator (CCO), as described above. I_ctrl0 may be a base current for controlling the oscillator 212, and an average CCO frequency of the oscillator 212 may be determined or otherwise specified or programmed. I_ctrl is a CCO control current derived from I_ctrl0 and I_ssm for controlling the oscillator 212. As described above, I_ssm is a modulation current derived from I_ctrl0 and depends on the component ratios of the PLL 104 (e.g., the ratios of the current mirrors of the PLL 104, as described above) and the value of DACCODE, and therefore, has a well-controlled amplitude. For example, I_ssm may be determined based on the following equation 1, where K is a scaling factor determined by the size (and therefore, the current mirror ratio) of the transistors (e.g., 302, 304, 306, 308, 310, 312) of the PLL 104.

[0030] I ssm =K*DACCIDE*I_ctrl0 (1)

[0031] Figure 4 4 is a timing diagram 400 of signals in various examples. In at least some examples, the signals represented in diagram 400 are signals of or associated with PLL 104 as described above. Thus, reference may be made to components or signals of PLL 104 as described above with reference to other figures herein. Diagram 400 includes CLK_IN, CLK_REF, and F_PLL. Figure 4 CLK_IN and CLK_REF are shown in Figure 4 Having a horizontal axis representing time and a vertical axis representing voltage (e.g., binary values—logic high and logic low). Figure 4 F_PLL is shown in Figure 4There is a horizontal axis representing time and a vertical axis representing frequency.

[0032] As shown in diagram 400, CLK_IN may be divided to form CLK_REF. CLK_IN may be divided by 32 (e.g., divider 202 is a divide-by-2 circuit and divider 204 is a divide-by-16 circuit) to form CLK_REF as shown in diagram 400, while in other examples, any other suitable divisor may be used (e.g., based on the divider values ​​of divider 202 and divider 204). As further shown in diagram 400, F_PLL may be modulated so that it may have a substantially nominal or target value at each rising edge of CLK_REF, but may change by +ΔF from the nominal value at ¼ of the cycle of F_PLL and by -ΔF at ¾ of the cycle of CLK_REF. The change of F_PLL from the nominal value (e.g., modulation of F_PLL) may be controlled based on the value of DACCODE so that F_PLL may progressively step to different values ​​at the rising clock edge of CLK_IN. In this way, SSC can be implemented so that EMI generation based on F_PLL or its harmonics can be mitigated. Although shown in diagram 400 as having a triangle wave approximate shape and having a maximum positive deviation at approximately 1 / 4 of the period of CLK_REF and having a maximum negative deviation at approximately 3 / 4 of the period of CLK_REF, in various examples, F_PLL (e.g., based on a modulation mode provided according to DACCODE) can have any other suitable shape and have a maximum point of positive or negative deviation at any suitable point in the period of CLK_REF.

[0033] Figure 5 Flowchart of method 500 of operating PLL in various examples. In at least some examples, the PLL is PLL 104. Therefore, reference may be made to components or signals of PLL 104 as described above with reference to other figures herein. In some examples, the PLL may be used to provide a signal (e.g., a clock signal) for synchronizing the operation of some other components. As described elsewhere herein, in some cases, EMI may be generated at the operating frequency of the PLL or at various harmonics of the operating frequency. In order to mitigate such generation of EMI, method 500 includes modulating the operating frequency of the PLL to implement SSC.

[0034] At operation 502, a reference signal is received as an input signal. In some examples, as described herein above, the input signal is CLK_IN and has a frequency F_IN. In some examples, the input signal may be divided (to reduce the value of F_IN) to form CLK_REF having a frequency F_ref.

[0035] At operation 504, F_ref is compared to the frequency of the feedback signal. In some examples, the feedback signal may be an output signal of an oscillator, such as a PLL of oscillator 212 (e.g., CLK_PLL having a frequency F_PLL), or may be a scaled representation of the output signal. In some examples, the comparison may be performed by a PFD, such as PFD 206. Based on the comparison, a first control signal may be provided that indicates whether F_ref is greater than or less than the feedback signal.

[0036] At operation 506, a second control signal is provided. In some examples, a second control signal having a current or other characteristic proportional to F_PLL may be provided. In response to the comparison of operation 504 indicating that F_ref is greater than the feedback signal, the value of the second control signal may be increased so that the frequency of the output signal of the oscillator increases. In response to the comparison of operation 504 indicating that F_ref is less than the feedback signal, the value of the second control signal may be decreased so that the frequency of the output signal of the oscillator decreases.

[0037] At operation 508, the second control signal is modulated to form an SSC control signal. In some examples, the SSC control signal may be modulated to increase or decrease the frequency of the output signal of the oscillator relative to F_PLL within one cycle of CLK_REF. In some examples, the frequency of the output signal of the oscillator is increased or decreased from F_PLL to ΔF. In at least some examples, the modulation may be controlled based on DACCODE, as described above. In some embodiments, operation 508 may be repeated for each received rising edge of CLK_IN.

[0038] At operation 510, a signal having a frequency proportional to the SSC control signal is provided. In some examples, the signal may alternatively have a frequency related to but not proportional to the SSC control signal. In at least some examples, the oscillator may be used to provide the signal as an output signal of the oscillator. In some examples, modulating the second control signal to form the SSC control signal mitigates the formation of EMI at the F_PLL or its harmonics while facilitating the PLL to provide a signal having an average frequency of the F_PLL.

[0039] The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: in a first instance, device A is coupled to device B; or in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not substantially change the functional relationship between device A and device B, so that device B is controlled by device A via the control signal generated by device A.

[0040] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be performed by firmware and / or software programming of the device, by construction and / or layout of hardware components and interconnects of the device, or a combination thereof. A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device.

[0041] As used herein, the terms "terminal" and "node", "interconnect", "pin", "ball", and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components, or their terminals. Although some elements of the described examples are included in the circuit and other elements are external to the circuit, in other examples, additional or fewer features may be incorporated into the circuit. In addition, some or all of the features shown as external to the circuit may be included in the circuit, and / or some features shown as internal to the circuit may be incorporated outside the circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board. Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead with little or no change to the remaining circuitry. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs (nMOSFETs), or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, such as NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extension mode devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on silicon substrates (Si), silicon carbide substrates (SiC), gallium nitride substrates (GaN), or gallium arsenide substrates (GaAs).

[0042] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. Unless otherwise stated, "about", "approximately", or "substantially" preceding a value means + / - 10% of the stated value, or if the value is zero, means a reasonable range of values ​​around zero.

[0043] Modifications are possible in the examples described, and other examples are possible within the scope of the claims.

Claims

1. A circuit comprising: a phase frequency detector (PFD) having a first input, a second input, and an output; a control circuit having an input and an output, said control circuit input being coupled to said output of said PFD; a modulation circuit having an input and an output, said modulation circuit input being coupled to said output of said control circuit; as well as An oscillator has an oscillator input and an oscillator output, the oscillator input is coupled to the output of the modulation circuit, and the output of the oscillator is coupled to the second input of the PFD.

2. The circuit of claim 1, wherein the modulation circuit comprises a multiplying digital-to-analog converter (DAC).

3. The circuit of claim 2, further comprising a second control circuit coupled to the multiplying DAC and operable to control the DAC to modulate a signal received by the modulation circuit to form a modulated signal.

4. The circuit of claim 3 , wherein the first PFD input is operable to receive a reference signal having a reference signal frequency, and the second PFD input is operable to receive a feedback signal having a feedback signal frequency, wherein the PFD is operable to compare the reference signal frequency with the feedback signal frequency to provide a first control signal indicating whether the reference signal frequency is greater than or less than the feedback signal frequency.

5. The circuit of claim 4 , wherein the control circuit is operable to receive the first control signal and provide a second control signal based on the first control signal, wherein the second control signal has a first value, and the first value increases in response to the first control signal indicating that the reference signal frequency is greater than the feedback signal frequency, and the first value decreases in response to the first control signal indicating that the reference signal frequency is less than the feedback signal frequency. The circuit of claim 5 , wherein the first value is a current of the second control signal.

7. The circuit of claim 5 , wherein the modulation circuit is operable to modulate the second control signal to form a modulated signal, the modulated signal varying in current within one cycle of the reference signal so that the output signal of the oscillator varies in frequency within the cycle of the reference signal and has a value of the reference signal frequency at each pair of rising edges of the reference signal.

8. A circuit according to claim 7, wherein the modulation circuit is capable of modulating the second control signal equally in a positive direction and a negative direction relative to the reference signal during one period of the reference signal so that the signal provided at the oscillator output has an average frequency of the reference signal frequency within the period of the reference signal.

9. A phase-locked loop (PLL), comprising: enter; Output; a phase frequency detector (PFD) coupled to the input of the PLL and operable to provide a first control signal in response to receiving a reference signal having a reference signal frequency and a feedback signal having a feedback signal frequency and comparing the reference signal to the feedback signal; a control circuit coupled to the PFD and operable to receive the first control signal and provide a second control signal having a current value determined based on the first control signal; a modulation circuit coupled to the control circuit and operable to modulate the second control signal to provide a modulated control signal that varies in value within one period of the reference signal; as well as an oscillator coupled between the modulation circuit and the output of the PLL, the oscillator being operable to provide a signal having an output frequency proportional to the value of the second control signal, wherein at a rising edge of the reference signal, the second control signal has a value sufficient to make the output frequency equal to the reference signal frequency.

10. The PLL of claim 9, wherein the modulation circuit is operable to modulate the second control signal by a first amount in a positive direction and by a second amount in a negative direction during one period of the reference signal so that the signal has an average frequency of the reference signal frequency taken across one period of the reference signal.

11. The PLL of claim 9, wherein the first control signal indicates whether the reference signal frequency is greater than or less than the feedback signal frequency.

12. The PLL of claim 11 , wherein the second control signal has a first value, and the control circuit is operable to increase the first value in response to the first control signal indicating that the reference signal frequency is greater than the feedback signal frequency, and to decrease the first value in response to the first control signal indicating that the reference signal frequency is less than the feedback signal frequency.

13. The PLL of claim 12, wherein the first value is a current value, and wherein the modulation circuit is operable to sum the second control signal with a modulation signal to modulate the second control signal to provide the modulated control signal.

14. The PLL of claim 12, wherein the modulation circuit is operable to provide a modulated second control signal by: replicating the second control signal to form a first replica signal; replicating and scaling the second control signal to form a second replica signal; applying the second replica signal to a digital-to-analog converter (DAC) to provide the modulated signal; as well as The modulated signal is summed with the first replica signal to form a modulated second control signal.

15. The PLL of claim 14, wherein the DAC is a resistor ladder having a plurality of taps, and wherein a selected tap of the resistor ladder determines a value of the modulation signal.

16. A method comprising: receiving a reference signal having a reference signal frequency; comparing the reference signal frequency with the frequency of the feedback signal; providing a first control signal having a value based on a result of the comparing; providing a second control signal having a value proportional to the reference signal frequency and based on the first control signal; modulating the second control signal based on a modulation signal to form a modulated control signal; as well as A signal having a frequency proportional to the modulated control signal is provided.

17. The method of claim 16, comprising modulating the second control signal equally in a positive direction and a negative direction within one period of the reference signal.

18. The method of claim 16, comprising modulating the second control signal by summing the second control signal with the modulation signal to form the modulated control signal.

19. The method of claim 18 , comprising providing a digital code to a digital-to-analog converter (DAC) so that the DAC provides the modulated signal, the digital code varying within a period of the reference signal so that the modulated control signal varies in a positive direction and a negative direction during the period of the reference signal.

20. The method of claim 16, comprising providing the feedback signal based on the signal having the frequency proportional to the modulated control signal.

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