Carbon mold for DRAM capacitor

Abstract

Memory devices and methods of forming memory devices are described. Methods of forming electronic devices are described in which carbon is used as a removable mold material for forming DRAM capacitors. A dense high temperature (500 DEG C or higher) PECVD carbon material is used as a removable mold material (e.g., a core material) in place of an oxide. The carbon material may be removed by isotropic etch under exposure to free radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic devices and electronic device manufacturing. More particularly, embodiments of the present disclosure provide electronic devices including carbon as a removable mold material when forming DRAM capacitors. Background Art

[0002] DRAM manufacturing is a highly competitive business. Dynamic random access memory (DRAM) can be programmed to store a voltage representing one of two binary values, but requires periodic reprogramming or "refreshing" to maintain this voltage for more than a very short period of time. DRAM memory circuits are manufactured by replicating billions of identical circuit elements (called DRAM cells) on a single semiconductor wafer. Each DRAM cell is an addressable location that can store one bit (binary digit) of data. In its most common form, a DRAM cell consists of two circuit components: a field effect transistor (FET) and a capacitor.

[0003] There is a constant pressure to reduce the size of individual DRAM cells and to increase memory cell density to allow more memory to be squeezed onto a single memory die, especially for densities greater than 8 Gigabits. Limitations to cell size reduction include the path of the bitline and wordline through the cell, the size of the cell capacitor, and compatibility of array devices with non-array devices.

[0004] The important obstacle to further reduction of DRAM size is to maintain sufficient cell capacitance, good leakage and low inter-cell shorting density. The average space between cells is 15 nm to 20 nm in order to fit high-k dielectrics and have at least 10 nm margin for inter-cell leakage.

[0005] In addition, another difficulty in reducing the size of DRAM is the small pitch of the capacitor, which is a hexagonal layout with a pitch equal to the bit line (BL) pitch. High aspect ratio (HAR) etching fixes the gap between holes to meet the final minimum gap of 12 nm, which means that the hole size is decreasing rapidly. The etching profile needs to be as vertical as possible, which requires an etching mask material with high selectivity. So far, silicon oxide (SiO x ) has been used as a film that is etched in high aspect ratio (HAR) capacitors and subsequently removed to form the capacitor using the outer surface of the titanium nitride (TiN) electrode. This is called a "mold" oxide, or "core".

[0006] Prior to depositing the bottom electrode (e.g., TiN), the oxide is isotropically etched during pre-cleaning. While this wet etch can be used to help straighten the tapered etch profile, it also means that the initial critical dimension (CD) needs to be smaller to account for CD growth after cleaning, pushing the aspect ratio of HAR reactive ion etching (RIE) even further.

[0007] The oxide mold removal needs to be done isotropically and strong hydrofluoric acid (HF) is used to remove the mold oxide while improving selectivity to the supporting layer (SiN-based) in the mold. Nevertheless, during this HF etch process, the supporting layer is still removed by 100 Å to 300 Å, which means that the deposition thickness needs to be thickened by 200 Å to 600 Å, making HAR reactive ion etching (RIE) more difficult. Therefore, there is a need in the art for materials and methods for forming DRAM capacitors that avoid these problems. Summary of the invention

[0008] One or more embodiments of the present disclosure are directed to a semiconductor device. In one or more embodiments, the semiconductor device includes: a plurality of pillars extending through a mold stack, the mold stack including a first core carbon layer on an etch stop layer on a substrate, a first support layer on a top surface of the first core carbon layer, a second core carbon layer on the first support layer, a second support layer on the second core carbon layer, and a hard mask layer on the second support layer.

[0009] Additional embodiments of the present disclosure relate to a method of forming a semiconductor device. In one or more embodiments, the method includes: forming a mold stack on an etch stop layer on a substrate, the mold stack including a first core carbon layer on the etch stop layer on the substrate, a first support layer on a top surface of the first core carbon layer, a second core carbon layer on the first support layer, a second support layer on the second core carbon layer, a hard mask layer on the second support layer, and a hard mask opening layer on the hard mask layer; etching a plurality of openings in the mold stack, the plurality of openings extending from a top surface of the hard mask opening layer to a top surface of the substrate; conformally depositing an electrode layer in the plurality of openings; depositing a core layer on the electrode layer; performing a high aspect ratio etch to remove a portion of the first support layer and a portion of the second support layer; and exposing the mold stack to an isotropic etch to remove the first core carbon layer and the second core carbon layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to be able to understand in detail the manner in which the above-mentioned features of the present disclosure are used, reference may be made to the embodiments for a more specific description of the present disclosure briefly summarized above, some of which are shown in the accompanying drawings. However, it will be noted that the accompanying drawings only illustrate common embodiments of the present disclosure and are not to be considered as limiting the scope thereof, as the present disclosure may admit of other equally effective embodiments. The embodiments as described herein are shown by way of example and are not limited in the various figures of the accompanying drawings, in which the same reference numerals indicate similar elements.

[0011] Figure 1 A process flow diagram of a method according to one or more embodiments is shown;

[0012] Figure 2 shows a cross-sectional view of a DRAM device according to one or more embodiments;

[0013] Figure 3 shows a cross-sectional view of a DRAM device according to one or more embodiments;

[0014] Figure 4A According to one or more embodiments, Figure 3 A top view of a DRAM device;

[0015] Figure 4B According to one or more alternative embodiments, Figure 3 A top view of a DRAM device;

[0016] Figure 5 shows a cross-sectional view of a DRAM device according to one or more embodiments; and

[0017] Figure 6 A cross-sectional view of a DRAM device according to one or more embodiments is shown. DETAILED DESCRIPTION

[0018] Before describing several exemplary embodiments of the present disclosure, it will be understood that the present disclosure is not limited to the details of construction or processing steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or carried out in various ways.

[0019] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which a process acts. As will also be understood by those skilled in the art, references to a substrate may also refer to only a portion of a substrate unless the context clearly indicates otherwise. In addition, references to depositing on a substrate may mean both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0020] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during the manufacturing process. For example, depending on the application, the substrate surface on which processing can be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metal, metal nitride, metal alloy, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to pre-processing treatments to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, as disclosed in more detail below, any film processing step disclosed may also be performed on a lower layer formed on the substrate, and the term "substrate surface" is intended to include such lower layers as indicated in the context. Thus, for example, in the case where a film / layer or a portion of a film / layer has been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0021] The term “on” indicates that there is direct contact between elements. The term “directly on” indicates that there is direct contact between elements without intervening elements.

[0022] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to refer to any gas species that can react with a substrate surface.

[0023] As used herein, "atomic layer deposition" or "cyclic deposition" refers to sequential exposure to two or more reactive compounds to deposit a layer of material on a substrate surface. The substrate, or a portion of the substrate, is individually exposed to two or more reactive compounds introduced into a reaction zone of a processing chamber. In a time-domain ALD process, exposure to each reactive compound is separated by a time delay to allow each compound to adhere to the substrate surface and / or react on the substrate surface and then purged from the processing chamber. These reactive compounds are considered to be exposed to the substrate in succession. In a spatial ALD process, different portions of the substrate surface, or materials on the substrate surface, are simultaneously exposed to two or more reactive compounds, so that any given point on the substrate is not substantially exposed to more than one reactive compound at the same time. As used in this specification and the appended claims, as will be understood by those skilled in the art, the term "substantially" used in this regard means that there is a possibility that a small portion of the substrate may be exposed to multiple reactive gases simultaneously due to diffusion, and this simultaneous exposure is not intentional.

[0024] In one aspect of a time-domain ALD process, a first reactive gas (i.e., a first precursor or compound A) is pulsed into a reaction zone, followed by a first time delay. Next, a second precursor or compound B is pulsed into the reaction zone, followed by a second delay. During each time delay, a purge gas (such as argon) is introduced into the processing chamber to purge the reaction zone or otherwise remove any residual reactive compounds or reaction byproducts from the reaction zone. Alternatively, the purge gas may flow continuously throughout the deposition process, such that only the purge gas flows during the time delay between pulses of the reactive compounds. The reactive compounds are pulsed alternately until a desired film or film thickness is formed on the substrate surface. In either case, the ALD process of pulsing compound A, purge gas, compound B, and purge gas is a cycle. The cycle may start with compound A or compound B and continue in the corresponding cycle sequence until a film having a predetermined thickness is obtained.

[0025] In one embodiment of a spatial ALD process, a first reactive gas and a second reactive gas (e.g., nitrogen) are delivered to the reaction zone simultaneously, but separated by an inert gas curtain and / or a vacuum curtain. The substrate moves relative to the gas delivery apparatus so that any given point on the substrate is exposed to the first reactive gas and the second reactive gas.

[0026] As used herein, "chemical vapor deposition" refers to a process in which a substrate surface is exposed to precursors and / or auxiliary reagents simultaneously or substantially simultaneously. As used herein, "substantially simultaneously" refers to co-flow or situations in which there is overlap in the exposure of a large portion of the precursors.

[0027] Plasma enhanced chemical vapor deposition (PECVD) is widely used to deposit thin films due to its cost effectiveness and versatility in film properties. In a PECVD process, for example, a hydrocarbon source (such as vapor of a gas phase hydrocarbon or a liquid phase hydrocarbon that has been entrained in a carrier gas) is introduced into a PECVD chamber. A plasma initiating gas (typically helium) is also introduced into the chamber. A plasma is then initiated in the chamber to produce excited CH- radicals. The excited CH- radicals chemically bond to the surface of a substrate positioned in the chamber, thereby forming a desired film thereon. The embodiments described herein with reference to the PECVD process may be performed using any suitable thin film deposition system. Any apparatus description described herein is illustrative and should not be understood or interpreted as limiting the scope of the embodiments described herein.

[0028] As used herein, the term "dynamic random access memory" or "DRAM" refers to a memory cell that stores a data bit by storing a charge packet (i.e., a binary one) on a capacitor, or storing no charge (i.e., a binary zero). The charge is gated onto the capacitor via an access transistor and sensed by turning on the same transistor and observing the voltage disturbance on the interconnect wire produced by dumping the charge packet onto the transistor output. Thus, a single DRAM cell consists of one transistor and one capacitor.

[0029] As used herein, the term "capacitor" refers to an electrical component of a memory cell. A capacitor has two electrical conductors separated by an electrically insulating material.

[0030] As used herein, the phrase "amorphous hydrogenated carbon," also referred to as "amorphous carbon" and denoted as aC:H, refers to a carbon material that does not have long-range crystalline order, which may contain a significant hydrogen content, for example, on the order of about 10 to 45 atomic %. Amorphous carbon is used as a hard mask material in semiconductor applications due to its chemical inertness, optical transparency, and good mechanical properties.

[0031] One or more embodiments provide DRAM capacitors in which carbon is used as a removable core, or as a removable mold material, as an alternative to oxides. Other embodiments provide methods of manufacturing DRAM capacitors in which carbon is a removable core material. In one or more embodiments, a dense high temperature (500°C or higher) plasma enhanced chemical vapor deposition (PECVD) carbon material is used as a removable mold material, as an alternative to oxides.

[0032] In one or more embodiments, a carbon deposition process is needed that can deposit on SiN based films for etch stop layers and films used as intermediate support layers. Therefore, in one or more embodiments, a SiN based film that can be deposited on carbon is needed.

[0033] In one or more embodiments, titanium nitride (TiN) or other metal nitride films are needed that can be deposited on carbon and still retain the necessary Rs and electrode properties to form DRAM capacitors.

[0034] In one or more embodiments, a suitable hard mask film is required that has very high selectivity to the carbon etch chemistry and etches "through" the intermediate support layer.

[0035] In one or more embodiments, an isotropic etch process is required to remove carbon through small high aspect ratio openings in the support layer.

[0036] In one or more embodiments, 400 nm to 600 nm of 500°C PECVD carbon is deposited on a standard off-the-shelf silicon boron nitride (SiBN) etch stop layer. A film of approximately 15 nm of carbon-doped silicon nitride (SiCN) is deposited as an intermediate support layer. In some embodiments, silicon oxide (SiO x ), or one or more of silicon oxynitride (SiON) may be the middle and upper support layers. In some embodiments, 3 nm to 10 nm, or about 5 nm of silicon oxynitride (SiON) and the remainder is silicon oxide (SiO x ) can be the intermediate and upper support layers. A 500°C PECVD carbon layer of about 300 nm to 400 nm is deposited on the carbon-doped silicon nitride (SiCN) to form the upper mold carbon. Then a layer of about 80 nm to about 100 nm of carbon-doped silicon nitride (SiCN) is deposited on the upper core carbon to form the top support. In one or more embodiments, the carbon deposition process advantageously forms adhesion on the SiN-based film to prevent it from peeling off. In one or more embodiments, the carbon-doped silicon nitride (SiCN) deposition process advantageously forms adhesion on the carbon to prevent it from peeling off, while in other applications, silicon nitride (SiN) films may be used.

[0037] In one or more embodiments, atomic layer deposition (ALD) of titanium tetrachloride (TiCl4) at 400°C to 500°C is used to deposit low resistivity (<500 µohm-cm) TiN inside the HAR carbon pores.

[0038] In one or more embodiments, a boron nitride (BN) based film is used as a hard mask film, with little to no carbon in the film, thus allowing very small holes that will not be "clogged" during the HAR etching process.

[0039] In one or more embodiments, an etch chamber used to open holes in the support layer after the bottom electrode (eg, TiN) is formed is used to isotropically remove part or all of the mold carbon using a combination of O and NH radicals.

[0040] Embodiments of the present disclosure are described by way of drawings that illustrate devices (e.g., DRAMs) and processes for forming DRAMs according to one or more embodiments of the present disclosure. The processes shown are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the applications shown.

[0041] Example embodiments are described herein with reference to cross-sectional illustrations that are illustrations of example embodiments (and intermediate structures). Therefore, variations in the illustrated shapes are expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the example embodiments should not be understood as limited to regions of the specific shapes shown herein, but may include shape deviations, for example, caused by manufacturing. For example, an implanted region shown as a rectangle may typically have rounded corners or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may have some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the drawings are schematic and their shapes may not be intended to illustrate the actual shape of a region of the device and are not intended to limit the scope of the example embodiments.

[0042] Figure 1 A process flow diagram of a method 10 for forming a semiconductor device according to some embodiments of the present disclosure is shown. Figures 2 to 6 A cross-sectional view of a semiconductor device according to one or more embodiments is shown. Figures 2 to 6 Method 10 is described. Method 10 may be part of a multi-step manufacturing process for a semiconductor device, particularly a DRAM.

[0043] In one or more embodiments, method 10 may be performed in any suitable processing chamber coupled to a cluster tool. A cluster tool may include a processing chamber for fabricating semiconductor devices, such as a chamber configured for etching, deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), oxidation, or any other suitable chamber for fabricating semiconductor devices.

[0044] See also Figure 1 At operation 12 of method 10, a mold stack for a capacitor is provided. As used in this specification and the appended claims, the term "providing" means that the mold stack is available for processing (e.g., positioned in a processing chamber). In one or more embodiments, the mold stack is first formed by a series of deposition steps, as described below with respect to Figure 2 Description. At operation 14, holes are etched. At operation 16, pillars are formed (ie, lower electrode deposition). At operation 18, HAR holes are patterned and etched in the support layer. At operation 20, the carbon layer is isotropically removed. At operation 22, the stack is optionally post-processed.

[0045] Figure 2A cross-sectional view of a mold stack layer used in forming a DRAM capacitor is shown. In one or more embodiments, the stack 100 includes an etch stop layer 104 formed on a substrate 102. The etch stop layer 104 may include any suitable material known to those skilled in the art. In one or more embodiments, the etch stop layer 104 includes one or more of the following: a conformal layer of a dielectric; SiN, SiCN, SiBN, SiON, and combinations thereof. The etch stop layer 104 may be deposited by any suitable technique known to those skilled in the art. In one or more embodiments, the etch stop layer 104 is deposited using a technique selected from CVD, PECVD, ALD deposition. The etch stop layer 104 may have any suitable thickness known to those skilled in the art. In one or more embodiments, the etch stop layer has a thickness in the range of from 0.7 nm to 70 nm, including in the range of from 1.75 nm to 28 nm, including in the range of from 3.5 nm to 14 nm.

[0046] In one or more embodiments, the first core carbon layer 106 a is deposited on a top surface of the etch stop layer 104 .

[0047] In one or more embodiments, the first core carbon layer 106a may be deposited at a very high temperature and have a low hydrogen (H) content. In one or more embodiments, the first core carbon layer 106a comprises a dense high temperature (500°C or higher) plasma enhanced chemical vapor deposition (PECVD) carbon material. In some embodiments, the first core carbon layer 106a may be mainly sp 2 , resulting in lower density and modulus, which can in some cases lead to advantageously higher lateral etch rates or improved etch rates for RIE or isotropic removal etching.

[0048] In one or more embodiments, high sp 3 The amorphous carbon material is advantageously deposited as the first core carbon layer 106a. In one or more embodiments, the deposition is done at low temperature using a diamondoid precursor.

[0049] In one or more embodiments, in order to achieve higher etch selectivity, the density of the first core carbon layer 106a is improved, and more importantly, the Young's modulus is improved. One of the main challenges in achieving higher etch selectivity and improved Young's modulus is the high compressive stress of such films, which makes them unsuitable for applications due to high wafer bow. Therefore, it is desirable to have a high density and modulus (e.g., higher sp 3 content, more diamond-like), and having high etch selectivity along with low stress (e.g., <-500 MPa).

[0050] As used herein, the term "diamondoid" and / or "adamantanes" refers to a class of compounds having a diamond lattice. Diamondanes may include one or more carbon cages (e.g., adamantane, diadamantanes, triadamantanes, and polyadamantanes). The adamantane series of adamantane is a hydrocarbon composed of fused cyclohexane rings that form an interlocking cage structure. The adamantanes may be substituted and unsubstituted cage compounds. These compounds may occur naturally or may be synthesized. Diamondanes have high sp 3 content, and also has a high C:H ratio. In general, diamond-like carbon materials are strong, rigid structures with dense covalently bonded 3D networks.

[0051] In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b is greater than 1.8 g / cc, including greater than 1.9 g / cc, and including greater than 2.0 g / cc. In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b is about 2.1 g / cc. In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b is in the range of about greater than 1.8 g / cc to about 2.2 g / cc. In one or more embodiments, the density of the first core carbon layer 106a and the second core carbon layer 106b is greater than about 2.2 g / cc.

[0052] See again Figure 2 In one or more embodiments, the first core carbon layer 106a may have any suitable thickness known to those skilled in the art. In one or more embodiments, the first core carbon layer 106a has a thickness in the range of from 60 nm to 6000 nm, including in the range of from 150 nm to 2400 nm, including in the range of from 300 nm to 1200 nm, and including in the range of from 400 nm to 700 nm.

[0053] In one or more embodiments, the first core carbon layer 106a may be deposited by any suitable means known to those skilled in the art. In one or more embodiments, the first core carbon layer 106a is deposited by plasma enhanced chemical vapor deposition (PECVD). In one or more embodiments, PECVD may be performed at any suitable temperature. In a specific embodiment, the PECVD deposition of the first core carbon layer 106a is performed at a temperature in the range of from 300°C to 700°C, including in the range of from 400°C to 600°C, including in the range of from 450°C to 550°C.

[0054] refer to Figure 2, the first support layer 108a is deposited on the top surface of the first core carbon layer 106a. The first support layer 108a may include any suitable material known to those skilled in the art. In one or more embodiments, the first support layer 108a includes a dielectric material.

[0055] As used herein, the term "dielectric material" refers to a material layer that is an electrical insulator that can be polarized in an electric field. In one or more embodiments, the dielectric layer comprises one or more of the following: an oxide, a carbon-doped oxide, a silicon oxide (SiO x ), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, carbon oxide, nitride, oxynitride, oxycarbon nitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), silicon carbide (SiCN). In one or more embodiments, the dielectric layer includes, but is not limited to, furnace deposited, CVD deposited, PVD deposited, ALD deposited, and spin-on-coat (SoC) deposited films. In one or more embodiments, the dielectric layer may be exposed to in-situ or ex-situ pre-treatment and post-treatment treatments to dope, infuse, inject, heat, freeze, polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure and / or bake the surface or body of the dielectric. In one or more specific embodiments, the first support layer 108a comprises silicon nitride (SiN). The silicon nitride (SiN) may be doped or undoped. In some embodiments, the silicon nitride is doped with carbon (SiCN).

[0056] In one or more embodiments, the first support layer 108a can have any suitable thickness. In some embodiments, the first support layer 108a has a thickness in the range of from 2 nm to 100 nm, including in the range of from 5 nm to 50 nm, including in the range of from 10 nm to 20 nm. There may also be 2 or more support layers in the carbon mold to balance the need for increased mechanical support with the increased complexity and difficulty of reactive ion etching (RIE) of the film stack.

[0057] See also Figure 2 , the second core carbon layer 106b is deposited on the top surface of the first support layer 108a. The second core carbon layer 106b may include any suitable material known to those skilled in the art. In some embodiments, the second core carbon layer 106b includes the same material as the first core carbon layer 106a described above.

[0058] In one or more embodiments, the second core carbon layer 106b may be deposited at a very high temperature and have a low hydrogen (H) content. In one or more embodiments, the second core carbon layer 106b comprises a dense high temperature (500°C or higher) plasma enhanced chemical vapor deposition (PECVD) carbon material. In some embodiments, the second core carbon layer 106b may be mainly sp 2 , resulting in lower density and modulus, which can in some cases lead to lower etch selectivity and pattern integrity. Modulus is a measure of the mechanical strength of the film.

[0059] In one or more embodiments, high sp 3 The amorphous carbon material is advantageously deposited as the second core carbon layer 106b. In one or more embodiments, the deposition is done at low temperature using a diamondane precursor.

[0060] In one or more embodiments, the second core carbon layer 106b may have any suitable thickness known to those skilled in the art. In one or more embodiments, the second core carbon layer 106b has a thickness less than the thickness of the first core carbon layer 106a. In one or more embodiments, the second core carbon layer 106b has a thickness in the range of from 45 nm to 4500 nm, including in the range of from 110 nm to 1800 nm, and including in the range of from 225 nm to 900 nm.

[0061] In one or more embodiments, the second core carbon layer 106b may be deposited by any suitable means known to those skilled in the art. In one or more embodiments, the second core carbon layer 106b is deposited by plasma enhanced chemical vapor deposition (PECVD). In one or more embodiments, PECVD may be performed at any suitable temperature. In a specific embodiment, the PECVD deposition of the second core carbon layer 106b is performed at a temperature in the range of from 300°C to 700°C, including in the range of from 400°C to 600°C, including in the range of from 450°C to 550°C.

[0062] refer to Figure 2 , a second support layer 108b is deposited on the top surface of the second core carbon layer 106b. The second support layer 108b may comprise any suitable material known to those skilled in the art. In one or more embodiments, the second support layer 108b comprises the same material as the first support layer 108a. In one or more embodiments, the second support layer 108b comprises a dielectric material.

[0063] In one or more embodiments, the second supporting layer 108b comprises one or more of the following: oxide, carbon-doped oxide, silicon oxide (SiO x), silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), silicon carbide nitride (SiCN). In one or more specific embodiments, the second support layer 108b includes silicon nitride (SiN). Silicon nitride (SiN) can be doped or undoped. In some embodiments, silicon nitride is doped with carbon (SiCN). The top support layer may also include all or part of the hard mask film remaining after RIE etching.

[0064] In one or more embodiments, the second support layer 108b can have any suitable thickness. In one or more embodiments, the second support layer 108b has a thickness greater than the thickness of the first support layer 108a. In some embodiments, the top support layer 108b has a thickness in the range from 8 nm to 800 nm, including in the range from 20 nm to 300 nm, including in the range from 30 nm to 150 nm.

[0065] Without intending to be bound by theory, it is believed that the deposition of the first core carbon layer 106a and the deposition of the second core carbon layer 106b form adhesion to the lower etch stop layer 104 and the first support layer 108a, respectively, which advantageously prevents the first support layer 108a and the second support layer 108b from separating or peeling off.

[0066] See also Figure 2 , a hard mask layer 110 is deposited on the top surface of the second support layer 108b. The hard mask layer 110 may include any suitable material known to those skilled in the art. In one or more embodiments, the hard mask layer 110 includes one or more of the following: silicon oxide (SiO x ), silicon carbide (SiC), boron and boron nitride (BN). In one or more specific embodiments, the hard mask layer 110 includes boron nitride (BN).

[0067] The hard mask layer 110 can have any suitable thickness. In one or more embodiments, the hard mask layer 110 has a thickness in a range from 20 nm to 1000 nm, including in a range from 30 nm to 500 nm, including in a range from 50 nm to 300 nm.

[0068] refer to Figure 2 The hard mask opening layer 112 is deposited on the top surface of the hard mask layer 110. The hard mask opening layer 112 may include any suitable material. In one or more embodiments, the hard mask opening layer 112 includes carbon or silicon oxide (SiO x). In some embodiments, the hard mask opening layer 112 comprises the same material as the first core carbon layer 106a. In other embodiments, the hard mask opening layer 112 comprises the same material as the second core carbon layer 106b. The hard mask opening layer 112 can have any suitable thickness. In one or more embodiments, the hard mask opening layer 112 has a thickness in a range from 20 nm to 1000 nm, including a range from 30 nm to 500 nm, including a range from 50 nm to 300 nm.

[0069] Figure 3 A cross-sectional view 100 of a mold stack having a plurality of openings 114 etched therein for use in forming a DRAM capacitor is shown. Figure 1 and Figure 3 At operation 14, in one or more embodiments, a plurality of openings 114 are formed in the stack by etching from the top surface of the hard mask opening layer 112 through the hard mask layer 110, through the second support layer 108b, through the second core carbon layer 106b, through the first support layer 108a, through the first core carbon layer 106a, and through the etch stop layer 104 to expose the top surface of the substrate 102. Thus, in one or more embodiments, each of the plurality of openings 114 extends from the top surface of the hard mask opening layer 112 to the top surface of the substrate 102.

[0070] In one or more embodiments, sidewall surfaces 115, 117, 119, 121, 123, 125, 127 and bottom 116 are formed within stacked opening 114. In one or more embodiments, opening 114 extends from a top surface of hard mask opening layer 112 through to a bottom surface of substrate 102.

[0071] Figure 4A According to one or more embodiments, Figure 3 FIG. 1 is a top view of a DRAM device of FIG. 1. An opening 114 can be seen in the hard mask opening layer 112.

[0072] Figure 4B According to one or more alternative embodiments, Figure 3 1. A top view of a DRAM device of FIG. 1. Openings 114A and 114B can be seen in the hard mask opening layer 112. In one or more embodiments, the second HARC pattern holes or openings 114B are larger in size than the first HARC pattern holes or openings 114A, and the number of hole openings 114B is only one-third compared to the number of openings 114A.

[0073] Figure 5A cross-sectional view 100 of a mold stack layer used in forming a DRAM capacitor is shown, wherein a plurality of openings 114 have been filled to form pillars. Figure 1 and Figure 5 At operation 16, the pillar lower electrode layer 116 can be deposited in the plurality of openings 114 by any suitable technique known to those skilled in the art. In some embodiments, the pillar lower electrode layer 116 can be deposited by atomic layer deposition (ALD).

[0074] The pillar lower electrode layer 116 may include any suitable material known to those skilled in the art. In one or more embodiments, the pillar lower electrode layer 116 includes one or more of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or tungsten (W). In one or more embodiments, titanium nitride (TiN) is deposited at 400°C to 500°C atomic layer deposition (ALD) using titanium tetrachloride (TiCl4) for depositing low resistivity (<500 µohm-cm) TiN inside the HAR opening 114.

[0075] In one or more embodiments, the pillar lower electrode layer 116 is conformally deposited in each of the plurality of openings 114. As used herein, the term "conformal" means that the layer adapts to the contours of a feature or layer. The conformality of a layer is typically quantified by the ratio of the average thickness of the layer deposited on the sidewalls of the feature to the average thickness of the same layer deposited on the substrate field or upper surface. In one or more embodiments, the pillar lower electrode layer 116 has a thickness in the range from 1 nm to 50 nm, including in the range from 3 nm to 20 nm, including in the range from 4 nm to 10 nm. The membrane may partially or completely fill the hole.

[0076] refer to Figure 5 , a column core layer 118 is deposited on the column lower electrode layer 116 in a plurality of openings 114. The column core layer 118 may be deposited by any suitable means known to those skilled in the art, including but not limited to ALD, CVD, PVD, and the like. In one or more embodiments, the deposition of the column core layer 118 is a final gap filling process. In one or more embodiments, the column core layer 118 has a thickness in a range from 1 nm to 50 nm, including in a range from 3 nm to 20 nm, including in a range from 4 nm to 10 nm. The membrane may partially or completely fill the pores.

[0077] The column core layer 118 may include any suitable material known to those skilled in the art. In one or more embodiments, the column core layer 118 includes polysilicon, oxide, carbon-doped oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, spin on dielectric (SOD) glass, organosilicate glass (SiOCH), silicon carbide nitride (SiCN).

[0078] Figure 6 A cross-sectional view 100 of a mold stack used in forming a DRAM capacitor is shown, wherein the first core carbon layer 106a and the second core carbon layer 106b have been removed. Figure 1 and Figure 6 At operation 18, high aspect ratio (HAR) holes are patterned and etched in the support layers 108a, 108b. In one or more embodiments, the etching comprises reactive ion etching (RIE). In one or more embodiments, an etching chamber is used to open holes in the support layers 108a, 108b after forming the pillar lower electrode layer 116.

[0079] At operation 20, the first core carbon layer 106a and the second core carbon layer 106b are removed by isotropic etching to form a first core opening 120a and a second core opening 120b. In one or more embodiments, the first core carbon layer 106a and the second core carbon layer 106b are removed by isotropic etching using a suitable chemistry of nitrogen (N), hydrogen (H), oxygen (O2) and / or ammonia (NH3). In one or more embodiments, a combination of O, N, H, and NH radicals is used to isotropically remove all mold carbon.

[0080] In one or more embodiments, the first and second core carbon layers 106a and 106b may be isotropically removed in the same chamber as the etching support layers 108a and 108b, thereby saving costs and eliminating wet processing that may cause pattern collapse.

[0081] exist Figure 1 In the embodiment shown in method 10 of , the device may optionally be post-processed at operation 22. The optional post-processing operation 22 may be, for example, a treatment to modify film properties (e.g., annealing or plasma treatment) or an additional film deposition process prior to final deposition of a suitable dielectric material to form a DRAM capacitor by ALD and / or CVD processing.

[0082] Unless otherwise indicated herein or explicitly denied by the context, the use of the terms "a" and "an" and "the" and similar references in the context of describing the materials and methods discussed herein (particularly in the context of the appended claims) will be understood to cover the singular and the plural. Unless otherwise indicated herein, the recording of the numerical ranges herein is intended only to be used as a shorthand method to refer independently to each individual value falling into the range, and each individual value is incorporated into the specification as if it is independently recorded herein. Unless otherwise indicated herein or explicitly denied by the context, all methods described herein can be performed in any suitable order. The use of any and all examples, or exemplary language (e.g., "such as") provided herein is intended only to better illustrate the materials and methods, and does not confer limitations on the scope unless otherwise claimed. The language in the specification should not be interpreted as indicating that any unclaimed element is essential to practicing the disclosed materials and methods.

[0083] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" that appear in various places throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Furthermore, in one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0084] Although the disclosure herein has been described with reference to specific embodiments, it will be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A semiconductor device comprising: A plurality of pillars extend through a mold stack, the mold stack comprising a first core carbon layer on an etch stop layer on a substrate, a first support layer on a top surface of the first core carbon layer, a second core carbon layer on the first support layer, a second support layer on the second core carbon layer, and a hard mask layer on the second support layer. 2 . The semiconductor device according to claim 1 , wherein the first core carbon layer and the second core carbon layer independently comprise a diamond-like carbon material.

3. The semiconductor device according to claim 2, wherein the diamond-like carbon material has a sp 3 content.

4. The semiconductor device according to claim 1, wherein the first supporting layer and the second supporting layer independently comprise one or more of the following: oxide, carbon-doped oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or silicon carbide nitride (SiCN). 5 . The semiconductor device according to claim 1 , wherein the first supporting layer and the second supporting layer comprise silicon carbide nitride (SiCN). The semiconductor device according to claim 1 , wherein the first supporting layer comprises silicon nitride (SiN).

7. The semiconductor device according to claim 1, wherein the hard mask layer comprises one or more of the following: silicon oxide (SiO x ), silicon carbide (SiC), carbon-doped hydrogenated silicon oxide (SiOCH), boron, and boron nitride (BN). 8 . The semiconductor device of claim 7 , wherein the hard mask layer comprises boron nitride (BN). 9 . The semiconductor device according to claim 1 , wherein the plurality of pillars include an electrode layer and a core layer. 10 . The semiconductor device according to claim 9 , wherein the electrode layer comprises one or more of the following: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN).

11. The semiconductor device of claim 9, wherein the core layer comprises one or more of the following: polysilicon, oxide, carbon-doped oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, spin-on dielectric (SOD) glass, organosilicate glass (SiOCH), and silicon carbide nitride (SiCN). 12 . The semiconductor device according to claim 1 , wherein the etch stop layer comprises SiN, SiCN, SiBN, SiON, or a combination thereof.

13. A method for forming a semiconductor device, the method comprising the following steps: forming a mold stack on the etch stop layer on the substrate, the mold stack comprising a first core carbon layer on the etch stop layer on the substrate, a first support layer on a top surface of the first core carbon layer, a second core carbon layer on the first support layer, a second support layer on the second core carbon layer, a hard mask layer on the second support layer, and a hard mask opening layer on the hard mask layer; etching a plurality of openings in the mold stack, the plurality of openings extending from a top surface of the hard mask opening layer to a top surface of the substrate; conformally depositing an electrode layer in the plurality of openings; depositing a core layer on the electrode layer; performing a high aspect ratio etch to remove a portion of the first supporting layer and a portion of the second supporting layer; as well as The mold stack is exposed to an isotropic etch to remove the first core carbon layer and the second core carbon layer.

14. The method of claim 13, wherein the isotropic etching comprises exposure to free radicals of oxygen (O2), nitrogen (N2), hydrogen (H2), ammonia (NH3), and combinations thereof. 15 . The method of claim 13 , wherein the first core carbon layer and the second core carbon layer independently comprise a diamond-like carbon material.

16. The method of claim 13, wherein the first and second supporting layers independently comprise one or more of the following: silicon carbide nitride (SiCN), silicon nitride (SiN), and silicon oxide (SiO2).

17. The method of claim 13, wherein the hard mask layer comprises one or more of: silicon oxide (SiO x ), silicon carbide (SiC), carbon-doped hydrogenated silicon oxide (SiOCH), boron (B), and boron nitride (BN). 18 . The method of claim 17 , wherein the hard mask layer comprises boron (B) or boron nitride (BN).

19. The method of claim 13, wherein the electrode layer comprises one or more of: titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

20. The method of claim 13, wherein the core layer comprises one or more of the following: polysilicon, oxide, carbon-doped oxide, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxide / silicon nitride, carbide, oxycarbide, nitride, oxynitride, oxycarbonitride, polymer, phosphosilicate glass, spin-on dielectric (SOD) glass, organosilicate glass (SiOCH), and silicon carbide nitride (SiCN).

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