Solid-state imaging device and method for manufacturing same

Abstract

The invention provides a solid-state imaging device capable of appropriately arranging a plug on a substrate and a method for manufacturing the solid-state imaging device. This solid-state imaging device is provided with: a first substrate; a first transistor disposed on the first substrate; a first insulating film disposed on the first substrate and the first transistor; a first wiring provided in the first insulating film and electrically connected to the first substrate or the first transistor; a second substrate disposed on the first insulating film; and a first plug disposed in the first insulating film and the second substrate and disposed on the first wiring to be electrically connected with the first wiring.

Description

Technical Field

[0001] The present invention relates to a solid-state imaging device and a method for manufacturing the solid-state imaging device. Background Art

[0002] For example, a solid-state imaging device can be manufactured by bonding a first substrate provided with a photodiode, a floating diffusion, a transfer transistor, etc., to a second substrate different from the first substrate. In this case, when a contact plug (through plug) penetrating the second substrate is provided in the second substrate, it may be difficult to lay out a pixel transistor on the second substrate. Therefore, the layout freedom of the second substrate may be reduced.

[0003] Citation List

[0004] Patent Literature

[0005] Patent Document 1: WO 2019 / 130702 A

[0006] Patent Document 2: Japanese Patent Application Publication No. 2019-84191 Summary of the invention

[0007] Problems to be solved by the present invention

[0008] The present invention provides a solid-state imaging device capable of appropriately laying out a plug in a substrate and a method for manufacturing the solid-state imaging device.

[0009] Solution to the problem

[0010] A solid-state imaging device according to a first aspect of the present invention includes: a first substrate; a first transistor, the first transistor is arranged on the first substrate; a first insulating film, the first insulating film is arranged on the first substrate and the first transistor; a first wiring, the first wiring is arranged in the first insulating film and is electrically connected to the first substrate or the first transistor; a second substrate, the second substrate is arranged on the first insulating film; and a first plug, the first plug is arranged in the first insulating film and the second substrate, and is arranged on the first wiring to be electrically connected to the first wiring. Therefore, for example, the first plug can be arranged in the second substrate, so that the transistor can be easily arranged on the second substrate, and the first plug can be appropriately arranged in the second substrate.

[0011] In addition, the solid-state imaging device according to the first aspect may further include a photoelectric conversion unit and a floating diffusion unit, wherein the photoelectric conversion unit and the floating diffusion unit are provided in the first substrate. Therefore, for example, the first plug can be appropriately arranged in the second substrate bonded to the first substrate provided with the photoelectric conversion unit and the floating diffusion unit.

[0012] Furthermore, in the first aspect, the first transistor may include a transfer transistor, an amplifying transistor, a switching transistor, or a reset transistor. Therefore, for example, the first plug may be appropriately arranged in a second substrate joined to a first substrate provided with such a first transistor.

[0013] Furthermore, in the first aspect, the first wiring may include a semiconductor layer. Thus, for example, the contact resistance between the first substrate or the first transistor and the first wiring can be reduced.

[0014] Furthermore, in the first aspect, the semiconductor layer may include a P-type semiconductor layer or an N-type semiconductor layer. Therefore, for example, the contact resistance between the first substrate or the first transistor and the first wiring can be reduced.

[0015] Furthermore, in the first aspect, the first plug may include a metal layer. Therefore, for example, a first plug having a low resistance may be formed.

[0016] In addition, the solid-state imaging device of the first aspect may further include: a second transistor, the second transistor is arranged on the second substrate; and a second insulating film, the second insulating film is arranged on the second substrate and the second transistor. Therefore, for example, the pixel transistor can be arranged on the second substrate.

[0017] Furthermore, in the first aspect, the second transistor may include a selection transistor. Therefore, for example, the first plug may be appropriately arranged in the second substrate provided with the selection transistor.

[0018] Furthermore, in the first aspect, the first plug may be provided in the first insulating film, the second substrate, and the second insulating film. Thus, for example, the first plug may be provided to penetrate the second substrate.

[0019] Furthermore, in the first aspect, the second transistor may include an amplifying transistor, a switching transistor, or a reset transistor. Therefore, for example, the first plug may be appropriately arranged in the second substrate provided with such a second transistor.

[0020] Furthermore, in the first aspect, the first plug may be electrically connected to the floating diffusion provided in the first substrate via the first wiring. Therefore, for example, a plug (first plug) of the floating diffusion may be appropriately arranged.

[0021] In addition, the solid-state imaging device of the first aspect may further include a second plug provided in the first insulating film and the second substrate and provided on the first substrate to be electrically connected to the first substrate. Therefore, for example, the second plug may be dropped directly on the upper surface of the first substrate.

[0022] Furthermore, in the first aspect, the second plug may be provided on a diffusion region provided in the first substrate. Thus, for example, the second plug may be dropped directly onto the upper surface of the diffusion region.

[0023] Furthermore, in the first aspect, the second plug may include a metal layer. Therefore, for example, a second plug having a low resistance can be formed.

[0024] In addition, in the first aspect, the first transistor may be provided on the first surface side of the first substrate, and the solid-state imaging device may further include a lens provided on the second surface side of the first substrate. Therefore, for example, in a back-illuminated solid-state imaging device, the first plug may be appropriately arranged in the second substrate.

[0025] In addition, the solid-state imaging device of the first aspect may further include: a third substrate disposed above the second substrate; a third transistor disposed below the third substrate; and a third insulating film disposed below the third substrate and the third insulating film and disposed on the second insulating film. Therefore, for example, a logic circuit including the third transistor can be disposed on the third substrate.

[0026] The manufacturing method of the solid-state imaging device according to the second aspect of the present invention includes: forming a first transistor on a first substrate; forming a first portion of a first insulating film on the first substrate and the first transistor; forming a first wiring on the first portion of the first insulating film to be electrically connected to the first substrate or the first transistor; forming a second portion of the first insulating film on the first portion of the first insulating film and the first wiring; laying out a second substrate on the first insulating film; and forming a first plug in the first insulating film and the second substrate, the first plug being arranged on the first wiring and electrically connected to the first wiring. Therefore, for example, the first plug can be laid out in the second substrate, so that the transistor can be easily laid out on the second substrate, and the first plug can be appropriately laid out in the second substrate.

[0027] Furthermore, in the second aspect, the first wiring may be formed to include a semiconductor layer. Therefore, for example, the contact resistance between the first substrate or the first transistor and the first wiring may be reduced.

[0028] The method for manufacturing a solid-state imaging device according to the second aspect may further include implanting P-type impurities or N-type impurities into the semiconductor layer. Thus, for example, the contact resistance between the first substrate or the first transistor and the first wiring can be reduced.

[0029] Furthermore, in the second aspect, the first plug may be formed to include a metal layer. Thus, for example, the first plug having a low resistance may be formed. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 is a block diagram showing the configuration of the solid-state imaging device of the first embodiment.

[0031] Figure 2 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment.

[0032] Figure 3 is a plan view showing the structure of the solid-state imaging device of the first embodiment.

[0033] Figure 4 is a plan view showing a structure of a solid-state imaging device according to a comparative example of the first embodiment.

[0034] Figure 5 is another plan view showing the structure of the solid-state imaging device of the first embodiment.

[0035] Figure 6 is a circuit diagram showing the configuration of the solid-state imaging device of the first embodiment.

[0036] Figure 7 is a cross-sectional view showing the structure of a solid-state imaging device according to a second embodiment.

[0037] Figure 8 is a cross-sectional view showing the structure of a solid-state imaging device according to a third embodiment.

[0038] Fig. 9 is a plan view showing the structure of a solid-state imaging device according to a third embodiment.

[0039] Fig.10 is a plan view showing a structure of a solid-state imaging device according to a comparative example of the third embodiment.

[0040] Fig.11 1 is a cross-sectional view (1 / 10) showing a method for manufacturing the solid-state imaging device according to the fourth embodiment.

[0041] Fig.12 It is a cross-sectional view (2 / 10) showing the manufacturing method of the solid-state imaging device of the fourth embodiment.

[0042] Fig.13 It is a cross-sectional view (3 / 10) showing the manufacturing method of the solid-state imaging device of the fourth embodiment.

[0043] Fig.14 It is a cross-sectional view (4 / 10) showing a method for manufacturing the solid-state imaging device according to the fourth embodiment.

[0044] Fig.15 It is a cross-sectional view (5 / 10) showing the manufacturing method of the solid-state imaging device of the fourth embodiment.

[0045] Fig.16 It is a cross-sectional view (6 / 10) showing the manufacturing method of the solid-state imaging device of the fourth embodiment.

[0046] Fig.17 It is a cross-sectional view (7 / 10) showing the manufacturing method of the solid-state imaging device of the fourth embodiment.

[0047] Fig.18 It is a cross-sectional view (8 / 10) showing the method for manufacturing the solid-state imaging device according to the fourth embodiment.

[0048] Fig.19 It is a cross-sectional view (9 / 10) showing the manufacturing method of the solid-state imaging device of the fourth embodiment.

[0049] Fig. 20 It is a cross-sectional view (10 / 10) showing the method for manufacturing the solid-state imaging device according to the fourth embodiment.

[0050] Fig.21 is a circuit diagram showing the configuration of the solid-state imaging device of the fifth and sixth embodiments.

[0051] Fig. 22 is a circuit diagram showing the configuration of the solid-state imaging device of the seventh and eighth embodiments.

[0052] Fig.23 is a circuit diagram showing the configuration of a solid-state imaging device of a ninth embodiment.

[0053] Fig.24 is a circuit diagram showing the configuration of a solid-state imaging device of a tenth embodiment.

[0054] Fig.25 is a circuit diagram showing the configuration of a solid-state imaging device of an eleventh embodiment.

[0055] Fig.26 is a circuit diagram showing the configuration of a solid-state imaging device of a twelfth embodiment.

[0056] Fig. 27 is a circuit diagram showing the configuration of a solid-state imaging device of a thirteenth embodiment.

[0057] Fig.28 is a sectional view showing the structure of a solid-state imaging device according to a fourteenth embodiment.

[0058] Fig.29 is a block diagram showing a configuration example of an electronic device.

[0059] Fig.30 is a block diagram showing a configuration example of a moving body control system.

[0060] Fig.31 It is shown Fig.30 A plan view of a specific example of the setting position of the imaging section in FIG.

[0061] Fig.32 is a diagram showing a schematic configuration example of an endoscopic surgery system.

[0062] Fig.33 is a block diagram showing a functional configuration example of a camera and a CCU. DETAILED DESCRIPTION

[0063] Embodiments of the present invention will be described below with reference to the accompanying drawings.

[0064] (First embodiment)

[0065] Figure 1 is a block diagram showing the configuration of the solid-state imaging device of the first embodiment.

[0066] Figure 1 The solid-state imaging device is a complementary metal oxide semiconductor (CMOS) type image sensor (CIS), and includes: a pixel array area 2 including a plurality of pixels 1; a control circuit 3; a vertical drive circuit 4; a plurality of column signal processing circuits 5; a horizontal drive circuit 6; an output circuit 7; a plurality of vertical signal lines (VSL) 8; and a horizontal signal line (HSL) 9.

[0067] Each pixel 1 includes a photodiode used as a photoelectric conversion unit and a MOS transistor used as a pixel transistor. Examples of pixel transistors include transfer transistors, reset transistors, amplifier transistors, selection transistors, and switch transistors. These pixel transistors can be shared by multiple pixels 1.

[0068] The pixel array area 2 includes a plurality of pixels 1 arranged in a two-dimensional array. The pixel array area 2 includes an effective pixel area that receives light, performs photoelectric conversion, and outputs signal charges generated by the photoelectric conversion, and a black reference pixel area that outputs optical black as a black level reference. Typically, the black reference pixel area is arranged on the peripheral portion of the effective pixel area.

[0069] The control circuit 3 generates various signals based on the vertical synchronization signal, the horizontal synchronization signal, the main clock, etc., which serve as operation references for the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc. The signals generated by the control circuit 3 are, for example, clock signals and control signals, and are input to the vertical drive circuit 4, the column signal processing circuit 5, the horizontal drive circuit 6, etc.

[0070] The vertical drive circuit 4 includes, for example, a shift register, and vertically scans each pixel 1 in the pixel array area 2 row by row. The vertical drive circuit 4 also supplies a pixel signal based on a signal charge generated by each pixel 1 to the column signal processing circuit 5 through a vertical signal line 8.

[0071] For example, each column signal processing circuit 5 is arranged for each column of pixels 1 in the pixel array area 2, and performs signal processing on signals output from a row of pixels 1 according to signals from the black reference pixel area for each column. Examples of such signal processing include noise removal and signal amplification.

[0072] The horizontal drive circuit 6 includes, for example, a shift register, and supplies the pixel signal from each column signal processing circuit 5 to the horizontal signal line 9 .

[0073] The output circuit 7 performs signal processing on the signal supplied from each column signal processing circuit 5 through the horizontal signal line 9 and outputs the signal-processed signal.

[0074] Note that the pixel array region 2 of the present embodiment may include only one of pixels 1 for detecting visible light and pixels 1 for detecting light other than visible light, or may include both pixels 1 for detecting visible light and pixels 1 for detecting light other than visible light. For example, light other than visible light is infrared light.

[0075] Figure 2 is a cross-sectional view showing the structure of the solid-state imaging device of the first embodiment. Figure 2 One pixel 1 in the solid-state imaging device of this embodiment is shown.

[0076] Figure 2 The X-axis, Y-axis, and Z-axis are shown to be perpendicular to each other. The X-direction and the Y-direction correspond to the lateral direction (horizontal direction), and the Z-direction corresponds to the longitudinal direction (vertical direction). In addition, the +Z direction corresponds to the upward direction, and the -Z direction corresponds to the downward direction. Note that the -Z direction may or may not strictly match the direction of gravity.

[0077] like Figure 2 As shown, the solid-state imaging device of the present embodiment includes a substrate 11, a pixel transistor 12, a pixel transistor 13, an interlayer insulating film 14, a plurality of contact plugs 15, a wiring layer 16, a substrate 21, an insulating film 22, a pixel transistor 23, an interlayer insulating film 24, a plurality of contact plugs 25, and a plurality of through plugs 31. The substrate 11, the pixel transistors 12 and 13, and the interlayer insulating film 14 are examples of the first substrate, the first transistor, and the first insulating film of the present invention, respectively. The substrate 21, the pixel transistor 23, and the interlayer insulating film 24 are examples of the second substrate, the second transistor, and the second insulating film of the present invention, respectively. Each through plug 31 is an example of the first plug of the present invention.

[0078] The substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. Figure 2 In FIG. 1 , the X direction and the Y direction are parallel to the upper surface of the substrate 11, and the Z direction is perpendicular to the upper surface of the substrate 11. The substrate 11 includes a well region 11a, a diffusion region 11b, a diffusion region 11c, and a diffusion region 11d. Figure 2 Also shown are a photodiode PD and a floating diffusion FD formed in the substrate 11. The photodiode PD is formed by a PN junction between the well region 11a and the diffusion region 11b, etc. The diffusion regions 11b and 11c also serve as source and drain regions of the pixel transistor 12. The diffusion region 11c also serves as a floating diffusion FD. The diffusion regions 11b to 11d are also referred to as active regions. The well region 11a, the diffusion region 11b, the diffusion region 11c, and the diffusion region 11d are, for example, a P-type semiconductor region, an N-type semiconductor region, an N-type semiconductor region, and a P-type semiconductor region, respectively.

[0079] The pixel transistor 12 includes a gate insulating film 12a and a gate electrode 12b formed in sequence on the substrate 11. The gate insulating film 12a is, for example, a silicon oxide film. The gate electrode 12b is, for example, an N-type semiconductor layer (for example, a polysilicon layer). The gate electrode 12b is arranged between the diffusion region 11b and the diffusion region 11c. The pixel transistor 12 is, for example, a transfer transistor TG.

[0080] The pixel transistor 13 includes a gate insulating film 13a and a gate electrode 13b which are sequentially formed on the substrate 11. The gate insulating film 13a is, for example, a silicon oxide film. The gate electrode 13b is, for example, an N-type semiconductor layer (eg, a polysilicon layer). Figure 2 As shown, the gate electrode 13b is electrically connected to the diffusion region 11c. The pixel transistor 13 is, for example, an amplifier transistor AMP.

[0081] The interlayer insulating film 14 is formed on the substrate 11 and the pixel transistors 12 and 13, and covers the pixel transistors 12 and 13. The interlayer insulating film 14 is, for example, a multilayer insulating film including a silicon oxide film and other insulating films.

[0082] Each contact plug 15 is formed in the interlayer insulating film 14 and is arranged on the substrate 11 , the gate electrode 12 b , or the gate electrode 13 b . Figure 2 Plug 15a, plug 15b, plug 15c, and plug 15d are shown as examples of contact plug 15. Plug 15a is arranged on diffusion region 11d. Plug 15b is arranged on gate electrode 12b. Plug 15c is arranged on diffusion region 11c. Plug 15d is arranged on gate electrode 13b. Plugs 15a, 15b, 15c, and 15d are, for example, a P-type semiconductor layer, an N-type semiconductor layer, an N-type semiconductor layer, and an N-type semiconductor layer (e.g., a polysilicon layer), respectively.

[0083] The wiring layer 16 is formed in the interlayer insulating film 14 and arranged on the contact plug 15. Figure 2 In the embodiment, the wiring layer 16 includes wirings 16a, 16b and 16c separated from each other. Wiring 16a is arranged on plug 15a. Wiring 16b is arranged on plug 15b. Wiring 16c is arranged on plugs 15c and 15d, and electrically connects plug 15c and plug 15d. Wiring 16a, 16b and 16c are, for example, a P-type semiconductor layer, an N-type semiconductor layer and an N-type semiconductor layer (for example, a polysilicon layer), respectively. Wiring 16a to 16c are also referred to as local wiring. Wiring 16a to 16c are examples of the first wiring of the present invention.

[0084] The substrate 21 is arranged on the interlayer insulating film 14. The solid-state imaging device of the present embodiment is formed by the substrates 11 and 21 bonded to each other. The substrate 21 is bonded to the substrate 11 through the interlayer insulating film 14. The substrate 21 is, for example, a semiconductor substrate such as a silicon substrate. Figure 2 , the X direction and the Y direction are parallel to the upper surface of the substrate 21 , and the Z direction is perpendicular to the upper surface of the substrate 21 .

[0085] The insulating film 22 is embedded in an opening provided in the substrate 21. The opening penetrates the substrate 21. Therefore, the insulating film 22 is arranged on the interlayer insulating film 14 similarly to the substrate 21. The insulating film 22 is, for example, a silicon oxide film.

[0086] The pixel transistor 23 includes a gate insulating film 23a and a gate electrode 23b which are sequentially formed on the substrate 21. The gate insulating film 23a is, for example, a silicon oxide film. The gate electrode 23b is, for example, an N-type semiconductor layer (eg, a polysilicon layer). The pixel transistor 23 is, for example, a selection transistor SEL.

[0087] The interlayer insulating film 24 is formed on the substrate 21, the insulating film 22, and the pixel transistor 23, and covers the pixel transistor 23. The interlayer insulating film 24 is, for example, a multilayer insulating film including a silicon oxide film and other insulating films.

[0088] Each contact plug 25 is formed in the interlayer insulating film 24 and is arranged on the substrate 21 or the gate electrode 23 b. Figure 2 Plug 25a, plug 25b and plug 25c are shown as examples of contact plug 25. Plug 25a is arranged on gate electrode 23b. Plug 25b is arranged on a diffusion region (not shown) formed in substrate 21. Plug 25c is arranged on another diffusion region (not shown) formed in substrate 21. These diffusion regions serve as source and drain regions of pixel transistor 23. Plugs 25a, 25b and 25c are, for example, an N-type semiconductor layer, an N-type semiconductor layer and an N-type semiconductor layer (e.g., a polysilicon layer), respectively.

[0089] The through plug 31 is formed in the interlayer insulating film 14, the insulating film 22, and the interlayer insulating film 24, and penetrates the substrate 21. The insulating film 22 is interposed between the substrate 21 and each through plug 31, and electrically insulates the substrate 21 from each through plug 31. The through plug 31 has, for example, a columnar shape extending in the Z direction, the lower end of the through plug 31 is located in the interlayer insulating film 16, and the upper end of the through plug 31 is located in the interlayer insulating film 24. Each through plug 31 is, for example, a metal layer. Each through plug 31 includes, for example, an aluminum (Al) layer, a tungsten (W) layer, or a copper (Cu) layer. Figure 2 Plug 31a and plug 31b are shown as examples of through plugs 31. Plug 31a is arranged on wiring 16a and electrically connected to wiring 16a. Plug 31b is arranged on wiring 16b and electrically connected to wiring 16b. Note that each through plug 31 is arranged below a wiring (not shown) provided in, for example, an interlayer insulating film 24 and electrically connected to the wiring. The through plug 31 is also referred to as a TCS.

[0090] The solid-state imaging device of the present embodiment has a double-layer structure including a substrate 11 (first layer) and a substrate 21 (second layer). The area within the substrate 11 and the interlayer insulating film 14 is referred to as the "first level", and the area within the substrate 21 and the interlayer insulating film 24 is referred to as the "second level". For example, the photodiode PD, the floating diffusion FD, and the pixel transistors 12 and 13 are arranged on the first level, and the pixel transistor 23 is arranged on the second level. In addition, the through plug 31 is arranged to span the first level and the second level.

[0091] Note that the pixel transistors 12, 13, and 23 may be transistors other than the transfer transistor TG, the amplifier transistor AMP, and the selection transistor SEL, respectively. For example, one of the pixel transistors 12 and 13 may be a reset transistor or a switch transistor.

[0092] As described above, the solid-state imaging device of the present embodiment includes plugs 31a and 31b (through plugs 31) that penetrate the substrate 21. When the plugs 31a and 31b are arranged in the substrate 21, the presence of the plugs 31a and 31b may become an obstacle, and it is difficult to arrange the pixel transistor 23 on the substrate 21. However, according to the present embodiment, by arranging the plugs 31a and 31b on the wirings 16a and 16b, the plugs 31a and 31b can be arranged in the substrate 21, so that the pixel transistor 23 can be easily arranged on the substrate 21. The reason is that by arranging the wirings 16a and 16b in appropriate positions, the plugs 31a and 31b can be arranged in positions that do not hinder the placement of the pixel transistor 23. The following will refer to Figure 3 and 4 Describe the details of this effect in detail.

[0093] Figure 3 is a plan view showing the structure of the solid-state imaging device of the first embodiment. Figure 2 similar, Figure 3 One pixel 1 in the solid-state imaging device of this embodiment is shown.

[0094] Figure 3 1 and 2 show a transfer transistor TG, a reset transistor RST, an amplifier transistor AMP, a switch transistor SW, and a capacitor transistor FDG disposed in an interlayer insulating film 14 on a substrate 11. Figure 3 In FIG. 1 , the setting range of the gate electrodes of these pixel transistors is represented by quadrilaterals or the like. These pixel transistors are arranged on the first level of the solid-state imaging device of this embodiment. On the other hand, the selection transistor SEL (see Figure 2 ) is arranged on the second level of the solid-state imaging device of this embodiment. Note that Figure 3 The transfer transistor TG and the amplifier transistor AMP shown are not arranged in the same XZ cross section, but for ease of understanding of the description, Figure 2 The transfer transistor TG and the amplifier transistor AMP shown are drawn in the same XZ cross section.

[0095] Figure 3 A substrate 21 disposed above the substrate 11 is also shown. The solid-state imaging device according to the present embodiment includes an insulating film 22 (see FIG. 1 ) embedded in an opening provided in the substrate 21. Figure 2 ). Figure 3 The area within the bold line shown indicates the area where the substrate 21 exists, and Figure 3 The area outside the illustrated bold line indicates the area where the insulating film 22 exists.

[0096] Figure 3 Also shown are a plurality of wirings included in the wiring layer 16 and a plurality of through-plugs 31 penetrating the substrate 21. Since the through-plugs 31 pass through the openings, the insulating film 22 is interposed between the substrate 21 and the through-plugs 31.

[0097] Figure 4 is a plan view showing the structure of a solid-state imaging device of a comparative example of the first embodiment. Figure 4 One pixel 1 in the solid-state imaging device of this comparative example is shown.

[0098] and Figure 3 similar, Figure 4 Various pixel transistors provided in the interlayer insulating film 14 on the substrate 11 , the substrate 21 arranged above the substrate 11 , and a plurality of through-plugs 31 penetrating the substrate 21 are shown.

[0099] Next, Figure 3 (First Embodiment) Figure 4 (Comparative Example) For comparison.

[0100] exist Figure 4 In the embodiment, the through plugs 31 are arranged at various positions of the pixel 1. Therefore, the area of ​​the substrate 21 in the pixel 1 (ie, Figure 4 The area of ​​the area within the bold line shown in the figure) is set to be narrower. The reason is that in order to arrange the through plug 31 at various positions of the pixel 1, the area of ​​the opening needs to be set larger, and thus the area of ​​the substrate 21 in the pixel 1 is reduced. This means that the area where the selection transistor SEL can be arranged becomes narrower, and it is difficult to arrange the selection transistor SEL. As described above, the through plug 31 of the present comparative example hinders the placement of pixel transistors such as the selection transistor SEL on the substrate 21.

[0101] on the other hand, Figure 3 The through plugs 31 are arranged in a concentrated manner near the left end and the right end of the pixel 1. Therefore, the area of ​​the substrate 21 in the pixel 1 (ie, Figure 3 The area of ​​the region within the bold line shown in FIG. 1 is set wider. Therefore, the area in which the selection transistor SEL can be arranged increases, and the selection transistor SEL can be easily arranged. As described above, according to the present embodiment, the through plug 31 can be arranged at a position that does not hinder the placement of a pixel transistor such as the selection transistor SEL.

[0102] exist Figure 3 In the embodiment, some pixel transistors are arranged directly below the substrate 21, that is, Figure 3 Directly below the area within the bold line shown. When the through plug 31 is arranged near these pixel transistors, the area of ​​the substrate 21 in the pixel 1 needs to be reduced. The reason is that an opening needs to be provided near the through plug 31. However, in the present embodiment, some wirings in the wiring layer 16 extend from these pixel transistors to near the left end and near the right end in the pixel 1, and the through plug 31 is arranged on these wirings. Thus, the through plug 31 can be concentrated near the left end or near the right end of the pixel 1. As described above, according to the present embodiment, by arranging the wirings in the wiring layer 16 at appropriate positions, the through plug 31 can be arranged at a position that does not hinder the placement of pixel transistors such as the selection transistor SEL.

[0103] Figure 5 is another plan view showing the structure of the solid-state imaging device of the first embodiment.

[0104] Figure 5 A shows the structure of the first level of four pixels 1 in the solid-state imaging device of this embodiment. Figure 5 In A, each pixel 1 includes a transfer transistor TG, a reset transistor RST, an amplifier transistor AMP, a switch transistor SW and a capacitor transistor FDG. Figure 5 The structure shown in A is Figure 3 However, in Figure 5 In FIG. 1A , the wiring layer 16 and the through-plug 31 are omitted from illustration.

[0105] Figure 5 B shows the structure of the second layer of four pixels 1 in the solid-state imaging device of this embodiment. Figure 5 In B, each pixel 1 includes a switch transistor S1, a switch transistor S2, a current source transistor PC and a subsequent current source transistor VB. In addition, Figure 5 The four pixels 1 shown in B share the selection transistor SEL, the post-stage amplifier transistor SF2 and the VREG voltage transistor RB.

[0106] Figure 5 B further shows a plurality of through-plugs 31 provided in each pixel 1. These through-plugs 31 are concentratedly arranged near the left end and near the right end in each pixel 1. According to the present embodiment, the through-plugs 31 may be arranged at positions that do not hinder placement of the switch transistor S1, the switch transistor S2, the current source transistor PC, the subsequent current source transistor VB, the selection transistor SEL, the subsequent amplifier transistor SF2, and the VREG voltage transistor RB.

[0107] Figure 6 is a circuit diagram showing the configuration of the solid-state imaging device of the first embodiment.

[0108] like Figure 6 As shown, each pixel 1 includes a photodiode PD, a floating diffusion FD, a transfer transistor TG, a reset transistor RST, a capacitor transistor FDG, an amplifier transistor SF1 (=AMP) and a switch transistor SW. Each pixel 1 also includes a current source transistor PC, a subsequent current source transistor VB, capacitors C1 and C2, switch transistors S1 and S2, a VREG voltage transistor RB, a subsequent amplifier transistor SF2 and a selection transistor SEL. At least one of these transistors can be shared by multiple pixels 1. The solid-state imaging device of this embodiment is a voltage domain type CIS (VD-GS), which realizes a global shutter function by converting the charge generated in the photodiode PD into voltages in all pixels at the same time and maintaining these voltages until the reading is completed.

[0109] The photodiode PD performs photoelectric conversion on incident light. The anode of the photodiode PD is electrically connected to the ground potential, and the cathode of the photodiode PD is electrically connected to the transfer transistor TG. The light incident on the photodiode PD is referred to as exposure of the photodiode PD.

[0110] The transfer transistor TG transfers the charge generated by the above-mentioned photoelectric conversion to the floating diffusion FD. One of the source and drain of the transfer transistor TG is electrically connected to the photodiode PD, and the other of the source and drain of the transfer transistor TG is electrically connected to the capacitance transistor FDG and the amplification transistor SF1.

[0111] The floating diffusion FD accumulates the charges transferred by the transfer transistor TG. Figure 6 As shown, the floating diffusion FD acts as a capacitor. The floating diffusion FD is electrically connected to the capacitance transistor FDG and the reset transistor RST.

[0112] The reset transistor RST releases the charge from the floating diffusion FD and resets the potential of the floating diffusion FD to the power supply voltage (VDD) before the photodiode PD starts to be exposed. One of the source and the drain of the reset transistor RST is electrically connected to the power supply voltage, and the other of the source and the drain of the reset transistor RST is electrically connected to the floating diffusion FD and the capacitor transistor FDG.

[0113] The capacitor transistor FDG acts as a switch for switching the photoelectric conversion efficiency of the photodiode PD. One of the source and drain of the capacitor transistor FDG is electrically connected to the floating diffusion FD and the reset transistor RST, and the other of the source and drain of the capacitor transistor FDG is electrically connected to the transfer transistor TG and the amplification transistor SF1.

[0114] The amplifier transistor SF1 receives the charge transferred to the floating diffusion FD at the gate and outputs the charge to the switch transistor SW through the source follower. The gate of the amplifier transistor SF1 is electrically connected to the transfer transistor TG and the capacitor transistor FDG. One of the source and the drain of the amplifier transistor SF1 is electrically connected to the power supply voltage, and the other of the source and the drain of the amplifier transistor SF1 is electrically connected to the switch transistor SW.

[0115] The switching transistor SW may electrically connect the amplifying transistor SF1 and the capacitors C1 and C2. When the switching transistor SW is turned on, the amplifying transistor SF1 is electrically connected to the capacitors C1 and C2, and when the switching transistor SW is turned off, the amplifying transistor SF1 is electrically isolated from the capacitors C1 and C2. One of the source and the drain of the switching transistor SW is electrically connected to the amplifying transistor SF1, and the other of the source and the drain of the switching transistor SW is electrically connected to the current source transistor PC and the capacitors C1 and C2.

[0116] Capacitors C1 and C2 are electrically connected to a node V1 between the switch transistor SW and the current source transistor PC. One electrode of capacitor C1 is electrically connected to the node V1, and the other electrode of capacitor C1 is electrically connected to the switch transistor S1. One electrode of capacitor C2 is electrically connected to the node V1, and the other electrode of capacitor C2 is electrically connected to the switch transistor S2. Capacitors C1 and C2 are connected to the node V1 in parallel.

[0117] The switch transistor S1 can electrically connect the capacitor C1 and the post-stage amplifier transistor SF2. When the switch transistor S1 is turned on, the capacitor C1 is electrically connected to the post-stage amplifier transistor SF2, and when the switch transistor S1 is turned off, the capacitor C1 is electrically isolated from the post-stage amplifier transistor SF2. One of the source and the drain of the switch transistor S1 is electrically connected to the capacitor C1, and the other of the source and the drain of the switch transistor S1 is electrically connected to the VREG voltage transistor RB and the post-stage amplifier transistor SF2.

[0118] The switch transistor S2 can electrically connect the capacitor C2 and the post-stage amplifier transistor SF2. When the switch transistor S2 is turned on, the capacitor C2 is electrically connected to the post-stage amplifier transistor SF2, and when the switch transistor S2 is turned off, the capacitor C2 is electrically isolated from the post-stage amplifier transistor SF2. One of the source and the drain of the switch transistor S2 is electrically connected to the capacitor C2, and the other of the source and the drain of the switch transistor S2 is electrically connected to the VREG voltage transistor RB and the post-stage amplifier transistor SF2.

[0119] The VREG voltage transistor RB is electrically connected to a node V2 between the switch transistors S1 and S2 and the subsequent-stage amplifier transistor SF2. When the VREG voltage transistor RB is turned on, the VREG voltage is supplied to the node V2.

[0120] The post-stage amplifier transistor SF2 receives the charge output from the capacitors C1 and C2 at the gate, and outputs the charge to the vertical signal line 8 (VSL) through the source follower. The gate of the post-stage amplifier transistor SF2 is electrically connected to the capacitors C1 and C2 and the VREG voltage transistor RB. One of the source and the drain of the post-stage amplifier transistor SF2 is electrically connected to the power supply voltage, and the other of the source and the drain of the post-stage amplifier transistor SF2 is electrically connected to the selection transistor SEL.

[0121] The selection transistor SEL may electrically connect the post-stage amplifier transistor SF2 and the vertical signal line 8. When the selection transistor SEL is turned on, the post-stage amplifier transistor SF2 is electrically connected to the vertical signal line 8, and when the selection transistor SEL is turned off, the post-stage amplifier transistor SF2 is electrically isolated from the vertical signal line 8. One of the source and the drain of the selection transistor SEL is electrically connected to the post-stage amplifier transistor SF2, and the other of the source and the drain of the selection transistor SEL is electrically connected to the vertical signal line 8.

[0122] The current source transistor PC and the subsequent current source transistor VB act as current sources. One of the source and drain of the current source transistor PC is electrically connected to the switch transistor SW, and the other of the source and drain of the current source transistor PC is electrically connected to the subsequent current source transistor VB. One of the source and drain of the subsequent current source transistor VB is electrically connected to the current source transistor PC.

[0123] As described above, the solid-state imaging device of the present embodiment includes the wiring layer 16 provided in the interlayer insulating film 14 on the substrate 11 and the plurality of through-plugs 31 penetrating the substrate 21, and these through-plugs 31 are provided on the wiring layer 16. Therefore, according to the present embodiment, the through-plugs 31 can be appropriately arranged in the substrate 21, for example, so as to arrange the through-plugs 31 at positions that do not hinder placement of transistors on the substrate 21.

[0124] (Second embodiment)

[0125] Figure 7 is a cross-sectional view showing the structure of a solid-state imaging device according to a second embodiment.

[0126] The solid-state imaging device ( Figure 7 ) has the same solid-state imaging device as the first embodiment ( Figure 2 ). However, the solid-state imaging device of the present embodiment does not include the wiring 16a or the plug 15a for the plug 31a (through plug 31), and the lower end of the plug 31a reaches the upper surface of the diffusion region 11d. Therefore, the plug 31a of the present embodiment is electrically connected to the substrate 11 by being directly formed on the substrate 11. The plug 31a of the present embodiment is an example of the second plug of the present invention.

[0127] like Figure 7 As shown in FIG. 1 , the plug 31a is arranged directly above the diffusion area 11d, that is, arranged in the Z direction of the diffusion area 11d. Therefore, by increasing the length of the plug 31a in the Z direction, rather than arranging the plug 31a above the wiring 16a ( Figure 2 ), the plug 31a can be arranged on the diffusion area 11d. Therefore, in this embodiment, a structure without providing the wiring 16a and the plug 15a is adopted.

[0128] The contact plug 15 and the wiring layer 16 of the first embodiment include the plug 15a and the wiring 16a as the P-type layer and the plugs 15b to 15d and the wiring 16b to 16c as the N-type layer. On the other hand, the contact plug 15 and the wiring layer 16 of the present embodiment do not include the P-type layer, but only include the plugs 15b to 15d and the wiring 16b and 16c as the N-type layer. Therefore, according to the present embodiment, the contact plug 15 and the wiring layer 16 can be easily formed compared with the first embodiment. On the other hand, according to the first embodiment, a plurality of through plugs 31 can be easily formed by making the lengths of the plurality of through plugs 31 in the Z direction the same.

[0129] (Third Embodiment)

[0130] Figure 8 is a cross-sectional view showing the structure of a solid-state imaging device of a third embodiment.

[0131] The solid-state imaging device ( Figure 8 ) has the same solid-state imaging device as the first embodiment ( Figure 2 ) is a structure similar to that of the substrate 21 in each pixel 1. However, in order to utilize the fact that the area of ​​the substrate 21 in each pixel 1 is wide, in addition to the selection transistor SEL, the solid-state imaging device according to the present embodiment also includes an amplification transistor AMP, a switching transistor SW, a reset transistor RST, etc. on the substrate 21. Therefore, the area of ​​the substrate 11 of each pixel 1 can be reduced, so that the plane size (area) of the solid-state imaging device can be reduced.

[0132] In addition to the plugs 31a and 31b, the through plug 31 of the present embodiment further includes a plug 31c. The plug 31c is arranged on the wiring 16c and is electrically connected to the diffusion region 11c (floating diffusion portion FD) through the wiring 16c and the plug 15c. Since the amplifier transistor AMP of the present embodiment is arranged on the substrate 21, the gate electrode of the amplifier transistor AMP of the present embodiment is electrically connected to the diffusion region 11c through the plug 31c, the wiring 16c and the plug 15c. Note that the plug 31c may be formed directly on the diffusion region 11c, similarly to the plug 31a of the second embodiment.

[0133] Fig. 9 is a plan view showing the structure of a solid-state imaging device according to a third embodiment. Figure 3 similar, Fig. 9 The planar structure of one pixel 1 of this embodiment is schematically shown.

[0134] exist Fig. 9 In the figure, the area where the substrate 21 exists in the pixel 1 is indicated by thick cross-hatching. In this embodiment, the area of ​​the area where the substrate 21 exists is relatively large. Fig. 9A plurality of through-plugs 31 penetrating the substrate 21 are also shown. In the present embodiment, these through-plugs 31 are concentratedly arranged near the upper end and near the lower end in the pixel 1. However, only one through-plug 31 is arranged near the floating diffusion FD. Fig. 9 In FIG. 1 , the location of the floating diffusion portion FD is indicated by a dotted arrow. The through plug 31 disposed near the floating diffusion portion FD corresponds to Figure 8 Plug 31c is shown.

[0135] Fig.10 is a plan view showing the structure of a solid-state imaging device of a comparative example of the third embodiment. Fig.10 The planar structure of one pixel 1 of this comparative example is schematically shown.

[0136] Fig.10 Also shown are the area where the substrate 21 exists in the pixel 1, the plurality of through-plugs 31 penetrating the substrate 21, and the arrangement positions of the floating diffusion FD. In this comparative example, these through-plugs 31 are arranged at various positions in the pixel 1, and the area of ​​the area where the substrate 21 exists is reduced.

[0137] As described above, the solid-state imaging device according to this embodiment includes an amplifier transistor AMP, a switch transistor SW, a reset transistor RST, etc. on the substrate 21 in addition to the selection transistor SEL. Therefore, according to this embodiment, the size of the solid-state imaging device in a plan view can be reduced.

[0138] (Fourth embodiment)

[0139] Figures 11 to 20 2 is a cross-sectional view showing a method for manufacturing a solid-state imaging device according to a fourth embodiment. According to the method of this embodiment, for example, the solid-state imaging device of the first embodiment can be manufactured.

[0140] First, a well region 11a, a diffusion region 11b (not shown), a diffusion region 11c, and a diffusion region 11d ( Fig.11 ). Therefore, a floating diffusion portion FD and a photodiode PD (not shown) are also formed in the substrate 11. Next, an insulating film 14a constituting the interlayer insulating film 14 is formed on the substrate 11, and an element isolation insulating film 41 ( Fig.11 ).

[0141] Next, a plurality of openings are formed in the insulating film 14a, and pixel transistors 12 and 13 are formed on the substrate 11 in the openings ( Fig.11). The pixel transistor 12 is formed by sequentially forming a gate insulating film 12a and a gate electrode 12b on the substrate 11 and forming a sidewall insulating film 12c on both sides of the gate electrode 12b. Similarly, the pixel transistor 13 is formed by sequentially forming a gate insulating film 13a and a gate electrode 13b on the substrate 11 and forming a sidewall insulating film 13c on both sides of the gate electrode 13b. Other pixel transistors on the substrate 11 are also formed similarly.

[0142] Next, insulating films 14b and 14c constituting the interlayer insulating film 14 are sequentially formed on the pixel transistors 12 and 13, the insulating film 14a, and the element isolation insulating film 41, and then the upper surface of the insulating film 14c is flattened by chemical mechanical polishing (CMP). Fig.11 ). The insulating films 14a to 14c are examples of a first portion of a first insulating film of the present invention.

[0143] Next, contact holes H1, H2, H3, H4, and H5 (H5) penetrating the insulating films 14a to 14c are formed by photolithography and reactive ion etching (RIE). Fig.12 ). The contact hole H1 is formed to reach the upper surface of the gate electrode 13b. The contact hole H2 is formed to reach the upper surface of the diffusion region 11c. The contact hole H3 is formed to reach the upper surface of the diffusion region 11d. The contact hole H4 is formed to reach the upper surface of the gate electrode 12b. The contact hole H5 is formed to reach the upper surface of the substrate 11.

[0144] Next, a semiconductor layer 42 ( Fig.13 ). Thus, a semiconductor layer 42 is formed in the contact holes H1 to H5 and on the insulating film 14c. The semiconductor layer 42 is, for example, a polysilicon layer having heat resistance. Fig.13 In the illustrated step, other layers having a heat-resistant layer may be formed instead of the semiconductor layer 42. Examples of such layers are metal layers such as a tungsten (W) layer and a ruthenium (Ru) layer.

[0145] Next, N-type impurities are injected into a predetermined region of the semiconductor layer 42, and P-type impurities are injected into other predetermined regions of the semiconductor layer 42 ( Fig.14 ). Therefore, N-type regions 42a, 42c, and 42d are formed in or near the contact holes H1, H2, H4, and H5 in the semiconductor layer 42, and a P-type region 42b is formed in or near the contact hole H3 in the semiconductor layer 42. When the N-type impurities are injected, the upper surface of the semiconductor layer 42 except for the portion where the N-type regions 42a, 42c, and 42d are to be formed is covered by the mask layer. Similarly, when the P-type impurities are injected, the upper surface of the semiconductor layer 42 except for the portion where the P-type region 42b is to be formed is covered by the mask layer.

[0146] Next, a mask layer 43 is formed on the entire surface of the substrate 11, and the mask layer 43 is processed by photolithography and RIE ( Fig.15 ). At this time, the mask layer 43 is processed to remain on the N-type regions 42a, 42c and 42d and the P-type region 42b.

[0147] Next, the semiconductor layer 42 is processed by RIE using the mask layer 43 ( Fig.15 ). Therefore, the semiconductor layer 42 is divided into an N-type region 42a, a P-type region 42b, an N-type region 42c, and an N-type region 42d. The N-type region 42a in the contact hole H1, the N-type region 42a in the contact hole H2, the P-type region 42b in the contact hole H3, the N-type region 42c in the contact hole H4, and the N-type region 42d in the contact hole H5 become plugs 15d, 15c, 15a, 15b, and 15e (contact plugs 15), respectively. The N-type region 42a on the contact holes H1 and H2, the P-type region 42b on the contact hole H3, the N-type region 42c on the contact hole H4, and the N-type region 42d on the contact hole H5 become wiring 16c, wiring 16a, wiring 16b, and wiring 16d in the wiring layer 16, respectively. The N-type regions 42 a , 42 c , and 42 d are all formed on, for example, an N-type layer in the substrate 11 , and the P-type region 42 b is formed on a P-type layer in the substrate 11 .

[0148] Next, we will refer to Figures 16 to 20 The subsequent part of the method for manufacturing the solid-state imaging device of the present embodiment will be described. Figures 16 to 20 The cross-section diagram is based on Figure 2 The cross-section diagram is drawn in a similar manner.

[0149] Next, an insulating film 14d constituting the interlayer insulating film 14 is formed on the insulating film 14c and the wiring layer 16, and then the upper surface of the insulating film 14d is planarized by CMP ( Fig.16 ). The insulating film 14d is an example of the second portion of the first insulating film of the present invention. Fig.16 Next, the substrate 11 and the substrate 21 are bonded to each other with the interlayer insulating film 14 interposed between the substrate 11 and the substrate 21 ( Fig.16 ). Therefore, the substrate 21 is arranged on the interlayer insulating film 14 (insulating film 14d).

[0150] Next, an opening H ( Fig.17 ). Next, the insulating film 22 is embedded in the opening H, and then the upper surface of the insulating film 22 is planarized by CMP ( Fig.17 ).

[0151] Next, a pixel transistor 23 ( Fig.18 ). The pixel transistor 23 is formed by sequentially forming a gate insulating film 23a and a gate electrode 23b on the substrate 21 and forming a sidewall insulating film (not shown) on both sides of the gate electrode 23b. Other pixel transistors on the substrate 21 are also formed in a similar manner. Next, an interlayer insulating film 24 is formed on the substrate 21, the insulating film 22, and the pixel transistor 23, and then the upper surface of the interlayer insulating film 24 is flattened by CMP ( Fig.18 ).

[0152] Next, through holes Ha and Hb and contact holes Hc, Hd and He are formed in the interlayer insulating film 24, the insulating film 22 and the interlayer insulating film 14 by photolithography and RIE. Fig.19 ). The through hole Ha is formed to reach the upper surface of the wiring 16a. The through hole Hb is formed to reach the upper surface of the wiring 16b. The contact hole Hc is formed to reach the upper surface of the substrate 21. The contact hole Hd is formed to reach the upper surface of the gate electrode 23b. The contact hole He is formed to reach the upper surface of the substrate 21. The step of forming the through holes Ha and Hb may be performed simultaneously with the step of forming the contact holes Hc to He, or may be performed before or after the step of forming the contact holes Hc, Hd, and He.

[0153] Next, a plug-forming material is embedded in the through holes Ha and Hb and the contact holes Hc, Hd, and He. Fig. 20 ). Therefore, plugs 31a and 31b (through plugs 31) are formed in the through holes H and Hb, respectively, and plugs 25b, 25a, and 25c (contact plugs 25) are formed in the contact holes Hc, Hd, and He, respectively. The material forming the plugs is, for example, a barrier metal layer containing a Ti (titanium) element or a Ta (tantalum) element and a plug material layer containing an Al (aluminum) element, a W (tungsten) element, or a Cu (copper) element. In this case, the through plug 31 and the contact plug 25 are formed by sequentially forming a barrier metal layer and a plug material layer in the through holes H and Hb and the contact holes Hc, Hd, and He. The step of forming the through plug 31 may be performed simultaneously with the step of forming the contact plug 25, or may be performed before or after the step of forming the contact plug 25.

[0154] According to this embodiment, the solid-state imaging device of the first embodiment can be Figures 11 to 20 Note that in the case of manufacturing the solid-state imaging device of the second embodiment, the steps of forming the plug 15a and the wiring 16a are omitted, and the through hole Ha is formed to reach the upper surface of the diffusion region 11d. In addition, in the case of manufacturing the solid-state imaging device of the third embodiment, a through hole reaching the upper surface of the wiring 16c is formed together with the through holes Ha and Hb, and the plug 31c is formed in the through hole.

[0155] (Fifth to Thirteenth Embodiments)

[0156] Fig.21 is a circuit diagram showing the configuration of the solid-state imaging device of the fifth and sixth embodiments. Fig. 22 is a circuit diagram showing the configuration of the solid-state imaging device of the seventh and eighth embodiments.

[0157] exist Fig.21 In the solid-state imaging device of the fifth embodiment shown in FIG. 1A , four pixels 1 share a reset transistor RST, an amplifier transistor AMP, and a selection transistor SEL. Each pixel 1 includes a photodiode PD, a transfer transistor TG, and a floating diffusion portion FD. The placement of these constituent elements is similar to Figure 6 The placement shown is generally the same, but differs in that the various pixel transistors and capacitors are not arranged.

[0158] Fig.21 The solid-state imaging device of the sixth embodiment shown in B has Fig.21 The configuration of the solid-state imaging device of the fifth embodiment shown in A is similar to that of FIG. However, the selection transistor SEL of the present embodiment is not arranged between the amplifier transistor AMP and the vertical signal line 8, but is arranged between the amplifier transistor AMP and the power supply voltage (VDD).

[0159] Fig. 22 The solid-state imaging device of the seventh embodiment shown in A has Fig.21 The configuration of the solid-state imaging device of the fifth embodiment shown in A is similar to that of the pixels 1. However, the four pixels 1 also share the capacitance transistor FDG disposed between the reset transistor RST and the amplifier transistor AMP.

[0160] Fig. 22 The solid-state imaging device of the eighth embodiment shown in B has Fig.21 The configuration of the solid-state imaging device of the sixth embodiment shown in A is similar to that of the first embodiment. However, the four pixels 1 also share the capacitance transistor FDG disposed between the reset transistor RST and the amplifier transistor AMP.

[0161] Fig.23 is a circuit diagram showing the configuration of a solid-state imaging device of a ninth embodiment.

[0162] Fig.23 The pixel 1 shown has Figure 6 The structure obtained by removing the capacitor transistor FDG from the pixel 1 shown. Note that Fig.23 The position of the floating diffusion FD in the illustrated pixel 1 can be set, for example, in a manner similar to each of the pixels 1 of the fifth to eighth embodiments.

[0163] Fig.24is a circuit diagram showing a configuration of a solid-state imaging device according to a tenth embodiment.

[0164] Fig.24 The pixel 1 shown has Fig.23 The pixel 1 shown is similarly constructed but includes another post-stage amplification transistor SF2 and another selection transistor SEL instead of the post-stage current source transistor VB and the VREG voltage transistor RB. Fig.24 The pixel 1 shown includes a circuit portion including a switching transistor S1, a capacitor C1, a subsequent-stage amplifying transistor SF2 and a selecting transistor SEL and a circuit portion including a switching transistor S2, a capacitor C2, a subsequent-stage amplifying transistor SF2 and a selecting transistor SEL in a subsequent stage of the amplifying transistor AMP.

[0165] Fig.25 is a circuit diagram showing a configuration of a solid-state imaging device according to an eleventh embodiment.

[0166] Fig.25 The pixel 1 shown has Fig.23 The pixel 1 shown in FIG. 1 is a structure obtained by removing the rear-stage current source transistor VB and the VREG voltage transistor RB. Fig.25 In the embodiment, the switch transistor S1 is arranged at the rear stage of the amplifier transistor AMP, and the capacitor C2 is arranged between the amplifier transistor AMP and the rear stage amplifier transistor SF2. Fig.25 In the embodiment, the capacitor C1 is electrically connected to a node between the switching transistor S1 and the capacitor C2, and the switching transistor S2 is electrically connected to a node between the capacitor C2 and the subsequent-stage amplifying transistor SF2.

[0167] Fig.26 is a circuit diagram showing a configuration of a solid-state imaging device according to a twelfth embodiment.

[0168] Fig.26 The pixel 1 shown has Fig.23 The pixel 1 shown in FIG. 1 is similar in structure to the pixel 1 shown in FIG. 1 , but includes a switch transistor SH instead of a VREG voltage transistor RB. The switch transistor SH is arranged at a subsequent stage of the amplifier transistor AMP. Fig.26 In the embodiment, the switching transistors S1 and S2 are electrically connected to a node between the switching transistor SH and the subsequent stage amplifying transistor SF2 (connected in parallel). The capacitors C1 and C2 are arranged at subsequent stages of the switching transistors S1 and S2, respectively.

[0169] Fig. 27 is a circuit diagram showing a configuration of a solid-state imaging device according to a thirteenth embodiment.

[0170] Fig. 27Four pixels 1 of the solid-state imaging device of this embodiment are shown. Each of these pixels 1 has Fig.23 The pixel 1 shown is similarly constructed. However, these pixels 1 share a circuit portion T. The circuit portion T includes a VREG voltage transistor RB, a post-stage amplifier transistor SF2, and a selection transistor SEL.

[0171] According to the fifth to thirteenth embodiments, the pixel 1 in the solid-state imaging device can be provided in various configurations. The configurations of the fifth to thirteenth embodiments can be applied to any pixel 1 of the first to fourth embodiments.

[0172] (Fourteenth embodiment)

[0173] Fig.28 is a cross-sectional view showing the structure of a solid-state imaging device according to a fourteenth embodiment. Figure 2 And similar, Fig.28 One pixel 1 in the solid-state imaging device of this embodiment is shown.

[0174] Apart from Figure 2 In addition to the constituent elements shown, the solid-state imaging device of the present embodiment includes an on-chip filter 51, an on-chip lens 52, a substrate 61, a transistor 62, and an interlayer insulating film 63. The substrate 61, the transistor 62, and the interlayer insulating film 63 are examples of a third substrate, a third transistor, and a third insulating film of the present invention, respectively.

[0175] exist Fig.28 In the embodiment, the upper surface of the substrate 11 is the front surface of the substrate 11, and the lower surface of the substrate 11 is the back surface of the substrate 11. The solid-state imaging device according to the present embodiment is a back-illuminated type, and the lower surface (back surface) of the substrate 11 is the light incident surface (light receiving surface) of the substrate 11. Fig.28 , the upper surface and the lower surface of the substrate 11 are examples of the first surface and the second surface of the present invention, respectively.

[0176] exist Fig.28 In the embodiment, the pixel transistor 12 and the pixel transistor 13 are formed on the upper surface side of the substrate 11, and the on-chip filter 51 and the on-chip lens 52 are formed on the lower surface side of the substrate 11. Specifically, the on-chip filter 51 and the on-chip lens 52 are formed below the substrate 11 in this order.

[0177] The on-chip filter 51 has a function of transmitting light having a predetermined wavelength, and is formed on the upper surface of the substrate 11 for each pixel 1. For example, the on-chip filters 51 for red (R), green (G), and blue (B) are respectively arranged below the photodiodes PD of the red, green, and blue pixels 1. In addition, the on-chip filter 51 for infrared light may be arranged below the photodiode PD of the infrared light pixel 1.

[0178] The on-chip lens 52 has a function of collecting incident light, and is formed below the on-chip filter 51 for each pixel 1. In the present embodiment, light incident on the on-chip lens 52 is collected by the on-chip lens 52, passes through the on-chip filter 51, and is incident on the photodiode PD. The photodiode PD converts the light into electric charge by photoelectric conversion to generate a signal charge.

[0179] The substrate 61 is disposed above the substrate 21. The substrate 61 is, for example, a semiconductor substrate such as a silicon substrate. Fig.28 , the X direction and the Y direction are parallel to the lower surface of the substrate 61 , and the Z direction is perpendicular to the lower surface of the substrate 61 .

[0180] The transistor 62 includes a gate insulating film 62a and a gate electrode 62b which are sequentially formed under the substrate 61. The gate insulating film 62a is, for example, a silicon oxide film. The gate electrode 62b is, for example, an N-type semiconductor layer (eg, a polysilicon layer). The transistor 62 constitutes a logic circuit of the solid-state imaging device of this embodiment.

[0181] The interlayer insulating film 63 is formed under the substrate 61 and the transistor 62 and covers the transistor 62. The interlayer insulating film 63 is, for example, a multilayer insulating film including a silicon oxide film and other insulating films. In the present embodiment, the interlayer insulating film 63 is formed on the interlayer insulating film 24, and the lower surface of the interlayer insulating film 63 is in contact with the upper surface of the interlayer insulating film 24. The substrate 61 of the present embodiment is bonded to the substrate 21 through the interlayer insulating films 63 and 24.

[0182] As described above, the solid-state imaging device of the present embodiment has a three-layer structure including a substrate 11 (first layer), a substrate 21 (second layer), and a substrate 61 (third layer). The area within the substrate 11 and the interlayer insulating film 14 is referred to as the "first level", the area within the substrate 21 and the interlayer insulating film 24 is referred to as the "second level", and the area within the substrate 61 and the interlayer insulating film 63 is referred to as the "third level". For example, the photodiode PD, the floating diffusion FD, and the pixel transistors 12 and 13 are arranged on the first level, the pixel transistor 23 is arranged on the second level, and the transistor 62 is arranged on the third level. In addition, the through plug 31 is arranged to span the first level and the second level.

[0183] According to this embodiment, by applying the three-layer structure to the solid-state imaging device, for example, the number of transistors arranged in the first layer or the second layer can be reduced. Therefore, the area of ​​each pixel 1 in the plan view can be reduced, and the size (area) of the solid-state imaging device in the plan view can be reduced.

[0184] Note that the structures of the first, second, and third levels of this embodiment can be the same as Fig.28 The structures shown are different. For example, Fig.28Part of the constituent elements of the first level shown may be moved to the second level or the third level. The same applies to Fig.28 The constituent elements on the second level shown and Fig.28 The constituent elements on the third level are shown.

[0185] (Application Example)

[0186] Fig.29 is a block diagram showing a configuration example of an electronic device. Fig.29 The electronic device shown is a camera 100 .

[0187] The camera 100 includes: an optical section 101 including a lens group and the like; an imaging device 102 which is a solid-state imaging device according to any one of the first to fourteenth embodiments; a digital signal processor (DSP) circuit 103 which is a camera signal processing circuit; a frame memory 104; a display section 105; a recording section 106; an operation section 107; and a power supply section 108. In addition, the DSP circuit 103, the frame memory 104, the display section 105, the recording section 106, the operation section 107, and the power supply section 108 are connected to each other via a bus 109.

[0188] The optical section 101 captures incident light (image light) from a subject and forms an image on an imaging surface of the imaging device 102. The imaging device 102 converts the light amount of the incident light formed as an image on the imaging surface by the optical section 101 into an electrical signal pixel by pixel, and outputs the electrical signal as a pixel signal.

[0189] The DSP circuit 103 performs signal processing on the pixel signal output from the imaging device 102. The frame memory 104 is a memory for storing one screen of a moving image or a still image captured by the imaging device 102.

[0190] The display section 105 includes, for example, a panel-type display device such as a liquid crystal panel or an organic EL panel, and displays a moving image or a still image obtained by imaging of the imaging device 102. The recording section 106 records the moving image or the still image obtained by imaging of the imaging device 102 on a recording medium such as a hard disk or a semiconductor memory.

[0191] The operation section 107 issues operation commands for various functions of the camera 100 in response to operations performed by the user. The power supply section 108 appropriately provides various power supplies to the DSP circuit 103, the frame memory 104, the display section 105, the recording section 106, and the operation section 107 as operating power supplies of these power supply targets.

[0192] By using the solid-state imaging device according to any one of the first to fourteenth embodiments as the imaging device 102 , it can be expected to acquire a good image.

[0193] The solid-state imaging device can be applied to various other products. For example, the solid-state imaging device can be installed on any type of mobile body, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobile devices, airplanes, drones, ships, and robots.

[0194] Fig.30 is a block diagram showing a configuration example of a moving body control system. Fig.30 The illustrated moving object control system is a vehicle control system 200 .

[0195] The vehicle control system 200 includes a plurality of electronic control units connected to each other via a communication network 201. Fig.30 In the example shown, the vehicle control system 200 includes a drive system control unit 210 , a body system control unit 220 , an exterior information detection unit 230 , an interior information detection unit 240 , and an integrated control unit 250 . Fig.30 A microcomputer 251 , a sound / image output section 252 , and an in-vehicle network interface (I / F) 253 are also shown as components of the integrated control unit 250 .

[0196] The drive system control unit 210 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 210 acts as a control device for the following devices: a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the vehicle steering angle, a braking device for generating a vehicle braking force, etc.

[0197] The body system control unit 220 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 220 acts as a control device for the following devices: a smart key system, a keyless entry system, a power window device, or various types of vehicle lights (e.g., headlights, reverse lights, brake lights, turn signals, fog lights, etc.). In this case, radio waves transmitted from a mobile device as a key substitute or signals of various switches may be input to the body system control unit 220. The body system control unit 220 receives input of these radio waves or signals, and controls the door lock device, power window device, vehicle lights, etc. of the vehicle.

[0198] The vehicle exterior information detection unit 230 detects external information of the vehicle including the vehicle control system 200. For example, the vehicle exterior information detection unit 230 is connected to the imaging section 231. The vehicle exterior information detection unit 230 causes the imaging section 231 to capture an image of the vehicle exterior and receives the captured image from the imaging section 231. Based on the received image, the vehicle exterior information detection unit 230 may perform a process for detecting objects such as a person, a car, an obstacle, a sign, characters on a road surface, etc., or a process for detecting their distances.

[0199] The imaging section 231 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging section 231 may also output an electrical signal as an image, or may output an electrical signal as measured distance information. The light received by the imaging section 231 may be visible light, or may be invisible light such as infrared rays, etc. The imaging section 231 includes a solid-state imaging device according to any one of the first to fourteenth embodiments.

[0200] The in-vehicle information detection unit 240 detects the interior information of the vehicle including the vehicle control system 200. For example, the in-vehicle information detection unit 240 is connected to a driver state detection unit 241 for detecting the driver's state. For example, the driver state detection unit 241 includes a camera for capturing an image of the driver, and based on the detection information input from the driver state detection unit 241, the in-vehicle information detection unit 240 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off. The camera may include a solid-state imaging device according to any one of the first to fourteenth embodiments, and may be, for example, Fig.29 A camera 100 is shown.

[0201] The microcomputer 251 can calculate the control target value of the driving force generating device, the steering mechanism or the braking device based on the vehicle interior or exterior information obtained by the vehicle exterior information detection unit 230 or the vehicle interior information detection unit 240, and output a control command to the driving system control unit 210. For example, the microcomputer 251 can perform coordinated control of functions intended to implement an advanced driver assistance system (ADAS), including collision avoidance or shock absorption of the vehicle, following driving based on a following distance, speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc.

[0202] In addition, based on the vehicle environment information obtained by the external information detection unit 230 or the internal information detection unit 240, the microcomputer 251 can perform coordinated control intended for automatic driving, etc. by controlling the driving force generating device, steering mechanism or braking device, which enables the vehicle to drive automatically without relying on the driver's operation.

[0203] Furthermore, the microcomputer 251 may output a control command to the body system control unit 230 based on the vehicle exterior information obtained by the vehicle exterior information detection unit 230. For example, the microcomputer 251 may perform coordinated control for the purpose of preventing glare (e.g., switching from a high beam to a low beam) by, for example, controlling the headlights according to the position of a preceding vehicle or an oncoming vehicle detected by the vehicle exterior information detection unit 230.

[0204] The sound / image output unit 252 transmits an output signal of at least one of sound and image to an output device capable of providing information to the vehicle occupants or the outside of the vehicle in a visual or auditory manner. Fig.30 In the example of FIG. 2 , an audio speaker 261, a display unit 262, and a dashboard 263 are shown as the output devices. The display unit 262 may include, for example, an in-vehicle display or a head-up display.

[0205] Fig.31 2 is a plan view showing a specific example of the arrangement position of the imaging section 231 .

[0206] Fig.31 The illustrated vehicle 300 includes imaging units 301, 302, 303, 304, and 305 as the imaging unit 231. The imaging units 301, 302, 303, 304, and 305 are provided at positions such as the front nose, rearview mirrors, rear bumpers, and rear doors of the vehicle 300, and an upper portion of a windshield in the vehicle.

[0207] The imaging unit 301 disposed at the front nose mainly acquires the image in front of the vehicle 300. The imaging unit 302 disposed at the left rearview mirror and the imaging unit 303 disposed at the right rearview mirror mainly acquire the images on both sides of the vehicle 300. The imaging unit 304 disposed at the rear bumper or rear door mainly acquires the image behind the vehicle 300. The imaging unit 305 disposed at the upper part of the windshield in the vehicle mainly acquires the image in front of the vehicle 300. The imaging unit 305 is used, for example, to detect the vehicle in front, pedestrians, obstacles, signal lights, traffic signs, lanes, etc.

[0208] Fig.31Examples of imaging ranges of imaging units 301, 302, 303, and 304 (hereinafter referred to as 301 to 304) are shown. Imaging range 311 represents the imaging range of the imaging unit 301 disposed at the front nose. Imaging range 312 represents the imaging range of the imaging unit 302 disposed at the left rearview mirror. Imaging range 313 represents the imaging range of the imaging unit 303 disposed at the right rearview mirror. Imaging range 314 represents the imaging range of the imaging unit 304 disposed at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 300 observed from above is obtained by superimposing image data captured by the imaging units 301 to 304. Hereinafter, imaging ranges 311, 312, 313, and 314 are referred to as "imaging ranges 311 to 314."

[0209] At least one of the imaging sections 301 to 304 may have a function for obtaining distance information. For example, at least one of the imaging sections 301 to 304 may be a stereo camera including a plurality of imaging devices, or may be an imaging device including pixels for phase difference detection.

[0210] For example, microcomputer 251 ( Fig.30 ) can determine the distance of each three-dimensional object within the imaging range 311 to 314 and the time change of the distance (relative speed relative to the vehicle 300) based on the distance information obtained from the imaging units 301 to 304. Based on the calculation result, the microcomputer 251 can extract the nearest three-dimensional object as a leading vehicle, which exists on the driving path of the vehicle 300 and travels in the same direction as the vehicle 300 at a predetermined speed (for example, equal to or greater than 0 km / h). In addition, the microcomputer 251 is able to pre-set the following distance that should be maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. According to this example, coordinated control of automatic driving intended for automatically driving the vehicle can be performed without relying on the driver's operation.

[0211] For example, the microcomputer 251 can classify the three-dimensional object data related to the three-dimensional object into two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 301 to 304, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 251 identifies obstacles around the vehicle 300 as obstacles that can be visually recognized by the driver of the vehicle 300 and obstacles that are difficult to be visually recognized by the driver of the vehicle 300. Then, the microcomputer 251 determines a collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 251 outputs a warning to the driver through the audio speaker 261 or the display unit 262, and performs forced deceleration or evasive steering through the driving system control unit 210 to assist driving and avoid collision.

[0212] At least one of the imaging units 301 to 304 may be an infrared camera that detects infrared rays. For example, the microcomputer 251 may identify a pedestrian by determining whether there is a pedestrian in the image captured by the imaging units 301 to 304. This pedestrian recognition is performed, for example, by the following process: a process of extracting feature points in the image captured by the imaging units 301 to 304 as infrared cameras; and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the contour of the object. When the microcomputer 251 determines that there is a pedestrian in the captured image captured by the imaging units 301 to 304 and identifies the pedestrian, the sound / image output unit 252 may control the display unit 262 so as to display a square contour line for emphasis superimposed on the identified pedestrian. In addition, the sound / image output unit 252 may also control the display unit 262 so as to display an icon or the like representing a pedestrian at a desired position.

[0213] Fig.32 : is a diagram showing a schematic configuration example of an endoscopic surgery system to which the technology according to the present invention (present technology) can be applied.

[0214] Fig.32 The figure shows a state in which a surgical operator (surgeon) 531 is using an endoscopic surgical system 400 to perform surgery on a patient 532 on a bed 533. As shown in the figure, the endoscopic surgical system 400 includes an endoscope 500, other surgical tools 510 such as a pneumoperitoneum tube 511 and an energy treatment tool 512, a support arm device 520 for supporting the endoscope 500, and a cart 600 on which various endoscopic surgical devices are mounted.

[0215] The endoscope 500 includes a lens barrel 501 and a camera head 502 connected to the proximal end of the lens barrel 501, and a region of a predetermined length starting from the distal end of the lens barrel 501 is inserted into a body cavity of a patient 532. Although the illustrated example shows that the endoscope 500 is constructed as a so-called hard endoscope having a hard lens barrel 501, the endoscope 500 may also be a so-called flexible endoscope having a flexible lens barrel.

[0216] An opening is provided at the distal end of the lens barrel 501, and the objective lens is fitted into the opening. A light source device 603 is connected to the endoscope 500, and light generated by the light source device 603 is guided to the distal end of the lens barrel through a light guide extending in the lens barrel 501, and irradiated toward an observation target in the body cavity of the patient 532 through the objective lens. Note that the endoscope 500 may be a forward-looking endoscope, an oblique-looking endoscope, or a side-looking endoscope.

[0217] An optical system and an imaging element are provided in the camera head 502, and the light reflected by the observed object (observation light) is collected on the imaging element through the optical system. The observation light is photoelectrically converted by the imaging element to generate an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observed image. The image signal is transmitted to the camera control unit (CCU) 601 as raw data.

[0218] The CCU 601 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and integrally controls the operations of the endoscope 500 and the display device 602. In addition, the CCU 601 receives an image signal from the camera 502, and performs various image processing such as development processing (demosaic processing) on ​​the image signal to display an image based on the image signal.

[0219] Under the control of the CCU 601 , the display device 602 displays an image based on an image signal on which the CCU 601 has performed image processing.

[0220] The light source device 603 includes, for example, a light source such as a light emitting diode (LED), and supplies the endoscope 500 with irradiation light for capturing an image of a surgical region.

[0221] The input device 604 is an input interface of the endoscopic surgery system 400. The user can input various types of information or instructions to the endoscopic surgery system 400 through the input device 604. For example, the user can input instructions to change the imaging conditions of the endoscope 500 (type of irradiation light, magnification factor, focal length, etc.).

[0222] The treatment tool control device 605 controls the driving of the energy treatment device 512 for burning tissue, cutting tissue, sealing blood vessels, etc. The pneumoperitoneum device 606 sends gas into the body cavity of the patient 532 through the pneumoperitoneum tube 511 to expand the body cavity, thereby ensuring the field of view of the endoscope 500 and ensuring the working space of the surgical operator. The recorder 607 is a device capable of recording various information related to the surgery. The printer 608 is a device capable of recording various information related to the surgery. - A device capable of printing various information related to surgery in various forms such as text, images and charts.

[0223] Note that, for example, the light source device 603 that provides the endoscope 500 with irradiation light for imaging the surgical site may include an LED, a laser light source, or a white light source obtained by a combination thereof. In the case where the white light source includes a combination of RGB laser light sources, since the output intensity and output timing of each color (each wavelength) can be controlled with high precision, the light source device 603 is able to adjust the white balance of the captured image. In addition, in this case, by irradiating the observation target with laser light from each of the R, G, and B laser light sources in a time-division manner and controlling the drive of the imaging element of the camera 502 in synchronization with the irradiation timing, images corresponding to R, G, and B can be captured in a time-division manner. According to this method, even if a color filter is not provided for the imaging element, a color image can be acquired.

[0224] In addition, the driving of the light source device 603 can be controlled so that the intensity of the output light is changed at every predetermined time. By controlling the driving of the imaging element of the camera 502 in synchronization with the timing of the change in light intensity so as to acquire images in a time-division manner and synthesize the images, a high dynamic range image without underexposed shadows and overexposed highlights can be created.

[0225] In addition, the light source device 603 may be capable of providing light within a predetermined wavelength region domain suitable for specific light observation. In specific light observation, for example, by utilizing the wavelength dependence of light absorption in body tissue to irradiate light having a narrower band than the irradiation light (i.e., white light) during normal observation, imaging (narrow-band imaging) for predetermined tissues such as blood vessels in the surface part of the mucosal layer with high contrast is performed. Alternatively, in specific light observation, fluorescence observation for obtaining an image based on fluorescence generated by irradiation of excitation light may be performed. In fluorescence observation, observation of fluorescence from body tissue (autofluorescence observation) may be performed by irradiating body tissue, or a fluorescence image may be obtained by locally injecting a reagent such as indocyanine green (ICG) into body tissue and irradiating the body tissue with excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 603 may be configured to provide narrow-band light and / or excitation light suitable for specific light observation as described above.

[0226] Fig.33 It is shown Fig.32 A block diagram of an example of the functional configuration of the camera 502 and the CCU 601 shown.

[0227] The camera 502 includes a lens unit 701, an imaging section 702, a driving section 703, a communication section 704, and a camera control section 705. The CCU 601 includes a communication section 711, an image processing section 712, and a control section 713. The camera 502 and the CCU 601 are communicatively connected to each other via a transmission cable 700.

[0228] The lens unit 701 is an optical system provided at a portion connected to the lens barrel 501. Observation light acquired from the distal end of the lens barrel 501 is guided to the camera 502 and enters the lens unit 701. The lens unit 701 is configured by combining a plurality of lenses including a zoom lens and a focus lens.

[0229] The imaging unit 702 includes an imaging element. The number of imaging elements included in the imaging unit 702 may be one (single-board type) or multiple (multi-board type). In the case where the imaging unit 702 is configured as a multi-board type, for example, image signals corresponding to R, G, and B can be generated by the respective imaging elements, and a color image can be obtained by combining the generated image signals. Alternatively, the imaging unit 702 may also include a pair of imaging elements for obtaining right-eye and left-eye image signals corresponding to a three-dimensional (3D) display. By performing a 3D display, the surgeon 531 is able to more accurately perceive the depth of body tissue at the surgical site. Note that in the case where the imaging unit 702 is configured as a multi-board type, a plurality of systems of the lens unit 701 may be arranged in a manner corresponding to the respective imaging elements. For example, the imaging unit 702 may be a solid-state imaging device according to any one of the first to fourteenth embodiments.

[0230] In addition, the imaging unit 702 may not necessarily be disposed in the camera head 502. For example, the imaging unit 702 may be disposed immediately inside the lens barrel 501 and directly behind the objective lens.

[0231] The driving section 703 includes an actuator and moves the zoom lens and the focus lens of the lens unit 701 by a predetermined distance along the optical axis under the control of the camera control section 705. With this arrangement, the magnification and focus of the image captured by the imaging section 702 can be appropriately adjusted.

[0232] The communication section 704 includes a communication device for transmitting / receiving various information to / from the CCU 601. The communication section 704 transmits the image signal obtained from the imaging section 702 to the CCU 601 through the transmission cable 700 as raw data.

[0233] In addition, the communication section 704 receives a control signal for controlling the driving of the camera 502 from the CCU 601, and provides the control signal to the camera control section 705. For example, the control signal includes information related to imaging conditions, such as information for specifying a frame rate for capturing an image and information for specifying an exposure value when capturing an image and / or information for specifying a magnification and a focus of a captured image.

[0234] Note that image capturing conditions such as frame rate, exposure value, magnification, and focus may be appropriately specified by the user, or may be automatically set based on the acquired image signal by the control section 713 of the CCU 601. In the latter case, the endoscope 500 is equipped with an automatic exposure (AE) function, an automatic focus (AF) function, and an automatic white balance (AWB) function.

[0235] The camera control section 705 controls the driving of the camera 502 based on a control signal received from the CCU 601 through the communication section 704 .

[0236] The communication section 711 includes a communication device for transmitting and receiving various types of information to and from the camera 502. The communication section 711 receives an image signal transmitted from the camera 502 through the transmission cable 700.

[0237] In addition, the communication unit 711 transmits a control signal for controlling the driving of the camera 502 to the camera 502. The image signal and the control signal can be transmitted by electrical communication, optical communication, or the like.

[0238] The image processing unit 712 performs various image processing on the image signal transmitted from the camera 502 in the form of raw data.

[0239] The control section 713 performs various types of control related to imaging of a surgical site, etc. performed by the endoscope 500 and display of a captured image obtained by the imaging of the surgical site, etc. For example, the control section 713 generates a control signal for controlling the driving of the camera head 502 .

[0240] In addition, the control unit 713 controls the display device 602 to display a captured image depicting a surgical site, etc., based on an image signal that has been image-processed by the image processing unit 712. At this time, the control unit 713 can identify various objects in the captured image by using various image recognition technologies. For example, the control unit 713 can identify surgical tools such as forceps, specific living parts, bleeding, fog when using the energy device 512, etc. by detecting the shape, color, etc. of the edge of the object included in the captured image. When causing the display device 602 to display the captured image, the control unit 713 can display various surgical auxiliary information in a manner superimposed with the image of the surgical site by using the recognition result. By causing the surgical auxiliary information to be displayed and presented to the surgeon 531 in a superimposed manner, the burden on the surgeon 531 can be reduced, or the surgeon 531 can be enabled to perform surgery more reliably.

[0241] The transmission cable 700 connecting the camera head 502 and the CCU 601 to each other is an electric signal cable compatible with communication of electric signals, an optical fiber compatible with optical fiber for optical communication, or a composite cable thereof.

[0242] Here, in the illustrated example, although communication is performed wired by using the transmission cable 700 , communication between the camera head 502 and the CCU 601 may be performed wirelessly.

[0243] The embodiments of the present invention have been described above, but these embodiments can be implemented in various modifications within the scope not departing from the gist of the present invention. For example, two or more embodiments can be implemented in combination.

[0244] Note that the present invention may also have the following configurations.

[0245] (1) A solid-state imaging device comprising:

[0246] a first substrate;

[0247] a first transistor, wherein the first transistor is disposed on the first substrate;

[0248] a first insulating film, the first insulating film being disposed on the first substrate and the first transistor;

[0249] a first wiring provided in the first insulating film and electrically connected to the first substrate or the first transistor;

[0250] a second substrate disposed on the first insulating film; and

[0251] A first plug is provided in the first insulating film and the second substrate and is provided on the first wiring to be electrically connected to the first wiring.

[0252] (2) The solid-state imaging device according to (1), further comprising a photoelectric conversion portion and a floating diffusion portion, the photoelectric conversion portion and the floating diffusion portion being provided in the first substrate.

[0253] (3) The solid-state imaging device according to (1), wherein the first transistor includes a transfer transistor, an amplification transistor, a switch transistor, or a reset transistor.

[0254] (4) The solid-state imaging device according to (1), wherein the first wiring includes a semiconductor layer.

[0255] (5) The solid-state imaging device according to (4), wherein the semiconductor layer includes a P-type semiconductor layer or an N-type semiconductor layer.

[0256] (6) The solid-state imaging device according to (1), wherein the first plug includes a metal layer.

[0257] (7) The solid-state imaging device according to (1), further comprising:

[0258] a second transistor, the second transistor being disposed on the second substrate; and

[0259] A second insulating film is provided on the second substrate and the second transistor.

[0260] (8) The solid-state imaging device according to (7), wherein the second transistor includes a selection transistor.

[0261] (9) The solid-state imaging device according to (7), wherein the first plug is provided in the first insulating film, the second substrate, and the second insulating film.

[0262] (10) The solid-state imaging device according to (7), wherein the second transistor includes an amplification transistor, a switching transistor, or a reset transistor.

[0263] (11) The solid-state imaging device according to (1), wherein the first plug is electrically connected to a floating diffusion provided in the first substrate via the first wiring.

[0264] (12) The solid-state imaging device according to (1), further comprising a second plug provided in the first insulating film and the second substrate and provided on the first substrate to be electrically connected to the first substrate.

[0265] (13) The solid-state imaging device according to (12), wherein the second plug is provided on a diffusion region provided in the first substrate.

[0266] (14) The solid-state imaging device according to (12), wherein the second plug includes a metal layer.

[0267] (15) The solid-state imaging device according to (1), further comprising:

[0268] a lens disposed on the second surface side of the first substrate,

[0269] The first transistor is arranged on the first surface side of the first substrate.

[0270] (16) The solid-state imaging device according to (7), further comprising:

[0271] a third substrate, the third substrate being disposed above the second substrate;

[0272] a third transistor, the third transistor being disposed below the third substrate; and

[0273] A third insulating film is provided below the third substrate and the third insulating film and on the second insulating film.

[0274] (17) A method for manufacturing a solid-state imaging device, the method comprising:

[0275] forming a first transistor on a first substrate;

[0276] forming a first portion of a first insulating film on the first substrate and the first transistor;

[0277] forming a first wiring on the first portion of the first insulating film to be electrically connected to the first substrate or the first transistor;

[0278] forming a second portion of the first insulating film on the first portion of the first insulating film and the first wiring;

[0279] disposing a second substrate on the first insulating film; and

[0280] A first plug is formed in the first insulating film and the second substrate, the first plug being provided on the first wiring and electrically connected to the first wiring.

[0281] (18) The method for manufacturing a solid-state imaging device according to (17), wherein the first wiring is formed to include a semiconductor layer.

[0282] (19) The method for manufacturing a solid-state imaging device according to (18), further comprising implanting a P-type impurity or an N-type impurity into the semiconductor layer.

[0283] (20) The method for manufacturing a solid-state imaging device according to (17), wherein the first plug is formed to include a metal layer.

[0284] Reference numerals list

[0285] 1 pixel

[0286] 2 pixel array area

[0287] 3. Control circuit

[0288] 4Vertical drive circuit

[0289] 5-column signal processing circuit

[0290] 6Horizontal drive circuit

[0291] 7 Output Circuit

[0292] 8 vertical signal lines

[0293] 9 horizontal signal lines

[0294] 11 substrate

[0295] 11a well region

[0296] 11b Diffusion area

[0297] 11c diffusion area

[0298] 11d diffusion area

[0299] 12 pixel transistors

[0300] 12a Gate insulating film

[0301] 12b Gate electrode

[0302] 12c Side wall insulation film

[0303] 13 pixel transistors

[0304] 13a Gate insulating film

[0305] 13b Gate electrode

[0306] 13c Side wall insulation film

[0307] 14Interlayer insulation film

[0308] 14a Insulation film

[0309] 14b Insulation film

[0310] 14c Insulation film

[0311] 14d insulation film

[0312] 15 contact plug

[0313] 15a plug

[0314] 15b plug

[0315] 15c plug

[0316] 15d plug

[0317] 15e plug

[0318] 16 wiring layers

[0319] 16a wiring

[0320] 16b wiring

[0321] 16c wiring

[0322] 21 substrate

[0323] 22 Insulation film

[0324] 23 pixel transistors

[0325] 23a Gate insulating film

[0326] 23b Gate electrode

[0327] 24 interlayer insulation film

[0328] 25 contact plug

[0329] 25a plug

[0330] 25b plug

[0331] 25c plug

[0332] 31 through plug

[0333] 31a plug

[0334] 31b plug

[0335] 31c plug

[0336] 41 Component isolation insulating film

[0337] 42Semiconductor layer

[0338] 42a N-type region

[0339] 42b P-type region

[0340] 42c N-type region

[0341] 42d N-type area

[0342] 43 Mask layer

[0343] 51 On-chip filter

[0344] 52 on-chip lenses

[0345] 61 substrate

[0346] 62 transistors

[0347] 62a Gate insulating film

[0348] 62b Gate electrode

[0349] 63Interlayer insulation film

Claims

1. A solid-state imaging device, comprising: a first substrate; a first transistor, wherein the first transistor is disposed on the first substrate; a first insulating film, the first insulating film being disposed on the first substrate and the first transistor; a first wiring provided in the first insulating film and electrically connected to the first substrate or the first transistor; a second substrate, the second substrate being disposed on the first insulating film; as well as A first plug is provided in the first insulating film and the second substrate and is provided on the first wiring to be electrically connected to the first wiring. 2 . The solid-state imaging device according to claim 1 , further comprising a photoelectric conversion portion and a floating diffusion portion, the photoelectric conversion portion and the floating diffusion portion being provided in the first substrate.

3. The solid-state imaging device according to claim 1, wherein The first transistor includes a transmission transistor, an amplification transistor, a switch transistor or a reset transistor.

4. The solid-state imaging device according to claim 1, wherein The first wiring includes a semiconductor layer.

5. The solid-state imaging device according to claim 4, wherein The semiconductor layer includes a P-type semiconductor layer or an N-type semiconductor layer.

6. The solid-state imaging device according to claim 1, wherein The first plug includes a metal layer.

7. The solid-state imaging device according to claim 1, further comprising: a second transistor, wherein the second transistor is disposed on the second substrate; as well as A second insulating film is provided on the second substrate and the second transistor.

8. The solid-state imaging device according to claim 7, wherein The second transistor includes a select transistor.

9. The solid-state imaging device according to claim 7, wherein: The first plug is provided in the first insulating film, the second substrate, and the second insulating film.

10. The solid-state imaging device according to claim 7, wherein The second transistor includes an amplifying transistor, a switching transistor or a reset transistor.

11. The solid-state imaging device according to claim 1, wherein The first plug is electrically connected to a floating diffusion provided in the first substrate via the first wiring. 12 . The solid-state imaging device according to claim 1 , further comprising a second plug provided in the first insulating film and the second substrate and provided on the first substrate to be electrically connected to the first substrate.

13. The solid-state imaging device according to claim 12, wherein: The second plug is disposed on a diffusion region disposed in the first substrate.

14. The solid-state imaging device according to claim 12, wherein: The second plug includes a metal layer.

15. The solid-state imaging device according to claim 1, further comprising: a lens disposed on the second surface side of the first substrate, The first transistor is arranged on the first surface side of the first substrate.

16. The solid-state imaging device according to claim 7, further comprising: a third substrate, the third substrate being disposed above the second substrate; a third transistor, wherein the third transistor is arranged below the third substrate; as well as A third insulating film is provided below the third substrate and the third insulating film and on the second insulating film.

17. A method for manufacturing a solid-state imaging device, the method comprising: forming a first transistor on a first substrate; forming a first portion of a first insulating film on the first substrate and the first transistor; forming a first wiring on the first portion of the first insulating film to be electrically connected to the first substrate or the first transistor; forming a second portion of the first insulating film on the first portion of the first insulating film and the first wiring; Arranging a second substrate on the first insulating film; as well as A first plug is formed in the first insulating film and the second substrate, the first plug being provided on the first wiring and electrically connected to the first wiring.

18. The method for manufacturing a solid-state imaging device according to claim 17, wherein: The first wiring is formed to include a semiconductor layer. 19 . The method for manufacturing a solid-state imaging device according to claim 18 , further comprising implanting a P-type impurity or an N-type impurity into the semiconductor layer.

20. The method for manufacturing a solid-state imaging device according to claim 17, wherein: The first plug is formed to include a metal layer.

Images