Method for rapidly checking interference Pin between wafer test probe cards Site and wafer test method

Abstract

The invention discloses a method for rapidly checking interference Pin between wafer test probe cards Site and a wafer test method, and belongs to the field of wafer test. When a wafer is tested, electrical interference often occurs in a multi-Site parallel test. According to the method, the unstable Site number during the multi-Site and measurement of the wafer is firstly obtained, then the interfered Site is confirmed from the unstable Site number, and the interference source Site is further checked. Then, an idle digital channel is selected from the ATE test machine resource pin list, the chip pins IO Pin of the interference source Site are sequentially and independently connected to the idle digital channel, the interfered Site and the interference source Site are tested, and the interference Pin of the interference source Site is confirmed according to the test result. And after the interference Pin is confirmed, wafer testing is carried out in a mode of shielding the interference Pin or independently grouping the interference source Stes through a software program. The test yield can be improved without redesigning and manufacturing new high-cost probe card hardware.

Description

Technical Field

[0001] The present invention relates to the field of wafer testing, and more particularly to a method for quickly troubleshooting inter-site interference Pins of a wafer testing probe card and wafer testing. Background Art

[0002] Wafer testing (Chip Probing, abbreviated as CP) is a very critical link in the semiconductor chip manufacturing process. It mainly involves using probes to perform a series of electrical tests on each chip (die) on the wafer that has just been manufactured to ensure that they meet the design specifications in terms of function and performance. This testing process plays a vital role in the yield of the entire chip production and the reliability of the final product.

[0003] For wafers produced on a large scale, in order to improve the efficiency of CP testing, reduce testing time and thus reduce costs, probe cards with more sites (test points) are usually designed and used to test more chips in parallel at the same time, thereby increasing production capacity. When performing multi-site parallel testing, electrical interference problems often occur, namely: in order to design probe cards (ProberCard for short PC) with more sites, multiple signal lines are densely arranged during the PCB wiring of the probe card, and electromagnetic coupling may occur between signals, causing one signal to interfere with another signal. This interference is more obvious in high-frequency signal environments. Even if a metal coaxial shielding wire is put on the tail of the probe, the multi-site parallel testing interference problem during CP testing cannot be completely solved, which is also one of the reasons for the low yield of CP testing.

[0004] When one or several sites are unstable and cause low yield, the current practices are: first, re-optimize the design and manufacture of the probe card, which will greatly increase the cost of hardware design and production; second, try to improve by increasing the probe station (Prober) needle cleaning frequency, adjusting the probe station contact height (OD) size, and physically cleaning or adjusting the probe, but the effect is not significant; you can also increase the number of wafer die re-tests (Re-Probe) to improve, while limitedly improving the yield will also greatly increase the time cost of CP testing, and even increase the needle marks on the wafer (Wafer) die surface needle pressure, thereby affecting the quality of wafer product delivery.

[0005] The Chinese patent application, publication number CN104614658A, published on April 26, 2017, records a method for testing high-frequency chip wafers using a multi-channel probe card, rationally grouping the probe card channels, assigning working channels, and then sending instructions in time. Compared with the parallel transmission of all channels, this invention rationally groups the channels without adjusting the channel spacing of the probe card, thereby increasing the channel spacing and reducing the occurrence of crosstalk without redesigning the probe card. The Chinese patent application, publication number CN110021334A, published on July 15, 2019, records a wafer testing method. When the chips on the wafer under test are tested in parallel, when the chip is abnormal, the power pin voltage of the abnormal chip is set to 0v to reduce the interference of the abnormal chip under test on the test of the normal chip under test. The Chinese patent application, publication number CN114152864A, published on March 8, 2022, describes a method and device for parallel testing of multiple chips, which determines a test group of at least one chip to be tested according to the positions of multiple chips to be tested in a wafer map; tests the chips to be tested in the test group according to the test signal; wherein the phase difference of the test signals corresponding to different chips to be tested is greater than zero, so as to reduce the interference generated between the test signals of adjacent chips to be tested.

[0006] The above patents group and time-share tests on adjacent sites that may interfere with each other, or directly isolate the chips corresponding to the interfered sites, in an attempt to reduce the interference of the test signals of adjacent chips to be tested and improve the stability of the test. The limitations of the above methods are that they cannot solve the following problems: 1) When the interference does not come from adjacent sites, grouping and time-share testing based solely on physical location cannot solve the interference problem; 2) A certain PIN of a site as an interference source may cause multiple site tests to fail. The interference source cannot be solved from the source, and all adjacent sites are directly grouped and delayed for testing, which comprehensively increases the requirements for test software and hardware, resulting in increased complexity and cost of the test work. Moreover, none of these patents proposes a solution for finding and locating the interfering Pin when interference occurs between sites. Summary of the invention

[0007] 1. Technical issues to be solved

[0008] In view of the shortcomings of the background technology, the present invention discloses a method for quickly troubleshooting interference Pins between sites of a wafer test probe card, which can accurately locate the specific interference source on the probe card as a certain interference PIN foot, so that in subsequent tests, the interference source can be isolated and routine operations can be performed. While improving the yield, the complexity of the test method is greatly reduced, and unnecessary delay overhead is reduced.

[0009] 2. Technical solution

[0010] The purpose of the present invention is achieved through the following technical solutions.

[0011] The present invention provides a method for quickly troubleshooting inter-site interference Pins of a wafer test probe card, the steps of which are:

[0012] S1: Get the site number of the unstable site during the wafer multi-site parallel test. The specific method is: during the full-site parallel test of a wafer, when the test completion reaches 30%-50%, according to the yield distribution data, screen out the real low-yield sites that still do not improve the yield after the probe station automatically clears the needle or increases the OD. These sites are unstable sites during the parallel test.

[0013] Preferably, when 50% of all sites have been tested, unstable sites are screened and tested.

[0014] S2: Confirm the disturbed site. The specific method is: test the site one by one and identify the unstable sites during the test. The sites that are stable during the individual test are the disturbed sites.

[0015] Furthermore, sites that fail the individual tests will not be processed.

[0016] S3: Confirm the interference source site. The steps to confirm the interference source site are as follows: select a site to be checked and combine it with the interfered site for testing in order from near to far from the interfered site, run the test program, and record whether the test passes stably; if both the site to be checked and the interfered site pass stably during the test, skip the site to be checked and continue to select a new site to be checked for combined testing; if the interfered site is unstable during the test, but the site to be checked passes, then the site to be checked being tested is confirmed to be the interference source site.

[0017] S4: Select an idle digital channel in the ATE test machine resource pin list to obtain the channel number.

[0018] S5: Connect the chip pins of the interference source Site obtained in S3 to the idle digital channels one by one, run the test program, and measure the interfered Site and the interference source Site, and confirm the interference Pin of the interference source Site according to the test results.

[0019] The specific steps are as follows:

[0020] Sub-step S51: Compare the definitions of chip pins of each site in the test program Socket file, and independently connect one of the chip pins to be checked at the interference source site to the idle digital channel by editing the Socket file;

[0021] Sub-step S52: Run the test program to determine whether the chip pin currently connected to the idle digital channel is an interference source based on the multi-site test results.

[0022] The judgment method is: if the test yield of the disturbed Site returns to the normal level after a certain IO Pin is connected to an idle digital channel, it can be confirmed that the CP multi-site and the interference Pin is the Pin, and the test verification procedure ends. If the test of the disturbed Site is still unstable after a certain IOPin is connected to an idle digital channel, it means that the Pin is not the interference Pin.

[0023] Repeat sub-steps S51 and S52, continue to connect the chip pins to the idle digital channels in sequence, and test and verify again until the interference Pin is found.

[0024] For the interference Pin, we can adopt the Site grouping test method, that is, separate the Site containing the interference source from the interfered Site into groups for testing, which can successfully solve the problem of interference between CP and test Sites, and effectively improve the test yield. Since the pins of the same type of power supply are short-circuited together inside the chip, there is usually no interference between power supplies. If there are three types of power supplies in the specific test: VDD, VDDQ and VBAT, there may be interference between different types of power supplies. At this time, the method proposed in the present invention can be used to connect the interference source power supply pin Pin to the idle DPS channel in turn, and continue to test and troubleshoot the interfered Site and the interference source Site combination. Preferably, the interference source power supply pin Pin is connected to the idle DPS channel in turn by editing the Socket file.

[0025] The present invention also provides a wafer testing method, after confirming the interference Pin, anti-interference measures are taken for the interference Pin and then conventional testing is performed.

[0026] Preferably, the interference Pin is physically isolated and then routine testing is performed.

[0027] Furthermore, if the test yield is still not improved after physically isolating the interference Pin, the interference source Site is grouped into a separate group through software program grouping, and the other Sites are grouped into a group for testing.

[0028] 3. Beneficial effects

[0029] Compared with the prior art, the advantages of the present invention are: the present technical method does not need to redesign and produce new high-cost probe card hardware, but only connects each chip pin in the Socket file of the wafer test program to an idle test machine physical resource channel in turn, runs the test program, and then judges based on the multi-site test results, and can quickly find the unstable interference pin in the multi-site test. In the present invention, the order of distance from the interfered site from near to far can improve efficiency and will not miss non-adjacent interference sources.

[0030] The present invention also proposes a method for testing wafers after physically isolating interference Pins and testing them in groups, which effectively improves the test yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 A flow chart of a method for quickly troubleshooting inter-site interference Pins of a wafer test probe card according to the present invention;

[0032] Figure 2 This is the probe layout diagram of 44Site's probe card. DETAILED DESCRIPTION

[0033] The present invention is described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0034] Example 1

[0035] like Figure 1 As shown, on the one hand, the present invention provides a method for quickly troubleshooting inter-site interference pins of wafer test probe cards, without the need to redesign and produce new high-cost probe card hardware, and can accurately troubleshoot specific interference pins. After isolating the interference pins in subsequent tests, testing can continue according to conventional test plans, thereby reducing interference and improving yield at minimal cost.

[0036] The technical principles of the present invention are explained as follows: First, the present invention obtains a program file Socket file that defines the connection relationship between each pin of the chip at each site and the physical resource channel of the ATE test machine in the wafer test program. The Socket file is a file that defines the connection relationship between each pin of the chip at each site of the probe card and the physical resource channel of the ATE test machine, and is one of the standard test files.

[0037] Secondly, obtain the number of an idle test machine physical resource channel. Since the idle physical resource channel is not actually wired out on the probe card PCB, when a specific chip pin is designated to be connected to the idle physical resource channel, it is equivalent to the chip pin being suspended, that is, the test machine physical resource connected to the probe card is disconnected. At this time, if the test program is run, the suspended chip pin does not participate in the test process, nor does it emit physical electromagnetic signals, and cannot cause any interference to other test sites.

[0038] Again, by editing the Socket file, all the interference source chip pins are connected to the idle test machine physical resource channel (Channel) in sequence and independently. Usually, the IO Pin generates interference, and the corresponding digital channel is connected to an idle channel. Run the test program, and then judge whether the chip pin currently connected to the idle digital channel is the interference source based on the multi-site parallel test results. The judgment method is: if a certain IO Pin is connected to an idle digital channel, the test yield of the interfered Site returns to the normal level, then it can be confirmed that the CP multi-site parallel test interference Pin is the Pin, and the test verification program ends. If a certain IO Pin is connected to an idle digital channel, the interfered Site test is still unstable, which means that the Pin is not an interference Pin. Then continue to connect the chip pins to the idle digital channels in sequence, and test and verify again until the interference Pin is found.

[0039] If there are three types of power supplies in the specific test: VDD, VDDQ and VBAT, there may be interference between different types of power supplies. At this time, the method proposed by the present invention can be used to connect the interference source power supply pin Pin to the idle DPS channel in turn, and continue to test the combination of the interfered Site and the interference source Site. Preferably, the interference source power supply pin Pin is connected to the idle DPS channel in turn by editing the Socket file.

[0040] After confirming the interference pin, further anti-interference improvement measures can be taken, such as physically isolating the interference pin before conducting regular tests.

[0041] The method for quickly troubleshooting the inter-site interference Pin of the wafer test probe card of the present invention is described in detail as follows:

[0042] S1: Get the site number that is unstable during wafer multi-site parallel measurement. The specific method is: when 1 / 2 wafers are measured in all sites, according to the yield distribution data, filter out the real low yield (far below the yield limit flag) sites that still do not improve the yield after the probe station automatically clears the needle or increases the OD. These sites are unstable sites during parallel measurement. In order to facilitate the explanation of the subsequent method steps, several examples are listed here, such as: Site13, Site39, Site43. During the wafer test process of the probe station prober, suppose a wafer has a total of 10,000 dies, and the probe card has 44 sites. Then 44 dies are tested each time. When 50% of the test is completed, stop and analyze the test data. During the test process of the probe station, the probe needs to contact the object to be tested. This contact height is usually expressed by Overdrive (OD). The specific value of OD represents the distance from the probe tip to the surface of the object to be tested. This parameter is very important to ensure the accuracy of the test and the life of the probe.

[0043] S2: Confirm the disturbed sites. Test the unstable sites one by one, and select the sites that pass the individual tests as disturbed sites, such as Site 13 and Site 39.

[0044] For sites that fail the individual tests, it is preliminarily determined that the die being tested is a bad die and no action is taken. There are many unstable dies and it is necessary to screen out those dies that are unstable but good in nature and find their corresponding disturbed sites.

[0045] S3: Confirm the interference source site. In order of distance from the interfered site from near to far, select a site to be checked each time and combine it with the interfered site for testing, run the test program, and record the test results of whether the test is stable or not; if both the site to be checked and the interfered site pass the test stably, skip the site to be checked, and continue to select a new site to be checked for combined testing; if the interfered site is unstable during the test, but the site to be checked passes, then confirm that the site to be checked being tested is the interference source site. For example: if the interfered site is Site 13, then Site 13 and the adjacent Site 12 are tested together. If Site 12 passes stably and Site 13 fails the test (referred to as Fail) or passes unstably, it means that Site 12 interferes with Site 13. If not, continue to test Site 13 and Site 14 in combination for troubleshooting. In this embodiment, the interference source sites are Site 12 and Site 38.

[0046] By analyzing the rules of PCB wiring design, it can be known that most of the interference between the sites is from the interference pins of the adjacent sites, but this is not always the case. Some sites are far away from the interfered site, but the signal lines of the two sites are crossed in the PCB routing or the wiring distance is too close. At this time, even if the site numbers are far apart, interference will occur. In fact, some interference is caused by a ground plane shared by the probe card PCB. In the present invention, the order of distance from the interfered site from near to far can be checked to improve efficiency and avoid missing non-adjacent interference sources.

[0047] like Figure 2 As shown in the figure, taking the probe layout diagram of the probe card of Site 44 as an example, Site 13 is adjacent to Site 12, Site 14, and Site 35. In order of distance from the interfered Site 13, Site 13+Site 12, Site 13+Site 14, and Site 13+35 are firstly tested in combination to identify the interference source Site. If the interference source Site is Site 12, the interference source can be accurately located in the first round of testing. If Site 12, Site 14, and Site 35 are all excluded, the next closest Site will be searched for combination testing. The second batch of Sites to be checked are Site 34 and Site 36, and the third batch will be checked towards more distant Sites.

[0048] S4: Select an idle digital channel that is not used by the probe card in the ATE tester resource pin list (Pinlist for short) to obtain the channel number. In this embodiment, the selected idle digital channel number is 4000.2. The physical resource channel of the ATE tester resource includes the DPS power supply and the IO digital channel. In general tests, there is less interference between the power lines, and the IO pin needs to select an idle digital channel to continue testing.

[0049] S5: Connect the chip pins of the interference source Site obtained in S3 to the idle digital channels one by one, run the test program, and measure the interfered Site and the interference source Site, and confirm the interference Pin of the interference source Site according to the test results.

[0050] The specific steps are as follows:

[0051] Sub-step S51: Compare the chip pin definitions of each Site in the test program Socket file, and independently connect one of the chip pins to be checked at the interference source Site to the idle digital channel by editing the Socket file;

[0052] Sub-step S52: Run the test program to determine whether the chip pin currently connected to the idle digital channel is an interference source based on the multi-site test results.

[0053] The judgment method is: if the test yield of the disturbed Site returns to the normal level after a certain IO Pin is connected to an idle digital channel, it can be confirmed that the CP multi-site and the interference Pin is the Pin, and the test verification procedure ends. If the test of the disturbed Site is still unstable after a certain IOPin is connected to an idle digital channel, it means that the Pin is not the interference Pin.

[0054] Repeat sub-steps S51 and S52, continue to connect the chip pins to the idle digital channels in sequence, and test and verify again until the interference pin is found.

[0055] The Socket file edited in sub-step S51 is a standard file of an ATE test machine, which is used to define the corresponding connection relationship between the pins of the chip to be tested and the physical channel resources of the test machine. In this embodiment, the description of the resource docking relationship in the initial Socketfile of the interference source Site12 is as follows:

[0056] IOPin1ATE digital channel channel, 4003.7

[0057] IOPin2ATE digital channel channel, 4003.6

[0058] …

[0059] DPS Pin1ATE power channel channel, 4016.2

[0060] DPSPin2ATE power channel channel, 4016.3

[0061] …

[0062] Relay1ATEUtility channel, 4005.2

[0063] Relay2ATEUtility channel, 4005.5

[0064] It can be seen that Socket file, as a file of the corresponding connection relationship between chip pins and ATE resources, defines the connection relationship between pins and different types of channels. Taking IOPin1 of Site12 as an example, the IOPin1 interface before modification is connected to the digital channel of ATE, and "4003.7" means that one of the chip pins numbered "IOPin1" of the interference source Site12 is connected to the digital channel numbered 4003.7 of ATE. In sub-step S51, when checking whether "IOPin1" is an interference Pin, first modify the corresponding line in Socketfile, modify the original "4003.7" to the idle digital channel number "4000.2" obtained in step S4, and then run the test program to complete the parallel test of the interfered Site and the interference source Site12.

[0065] When the IO pin troubleshooting of Site 12 is completed, the DPS pin troubleshooting needs to be connected to an idle DPS channel for testing.

[0066] Example 2

[0067] The present invention also provides a wafer testing method, which uses the method of quickly troubleshooting the interfering Pins between the wafer test probe card sites in Example 1, and after quickly locating the interfering Pins, a coaxial shielding line is added to the tail line of the interfering Pin before performing wafer testing. Usually, the problem can be fundamentally solved at this time, but when the shielding of the probe tail line has no effect and the yield has not improved, it means that the probe is the real interferer. At this time, it is impossible to add a shielding line to the probe, and it needs to be solved by program grouping in the software. Specifically, the site grouping test method is: the interference source Site is divided into a group separately, and the other Sites are divided into a group for testing, which can successfully solve the problem of interference between CP and measurement Sites, and effectively improve the test yield.

[0068] The above schematically describes the invention and its implementation methods, which is not restrictive. Without departing from the spirit or basic features of the invention, the invention can be implemented in other specific forms. What is shown in the accompanying drawings is only one of the implementation methods of the invention. The actual structure is not limited thereto, and any figure mark in the claims should not limit the claims involved. Therefore, if a person of ordinary skill in the art is inspired by it, without departing from the purpose of the invention, a structural method and an embodiment similar to the technical solution are designed without creativity, which should all belong to the protection scope of the present invention. In addition, the word "including" does not exclude other elements or steps, and the word "one" before the element does not exclude the inclusion of "multiple" elements. The multiple elements stated in the product claim can also be implemented by one element through software or hardware. The words first, second, etc. are used to indicate the name, and do not indicate any specific order.

Claims

1. A method for quickly troubleshooting inter-site interference Pins of a wafer test probe card, comprising the following steps: S1: Get multiple wafer sites and measure the unstable site number; S2: Confirm the disturbed site; S3: Confirm the interference source site; S4: Select an idle digital channel in the ATE test machine resource pin list to obtain the channel number; S5: Connect the chip pins IO Pin of the interference source Site obtained in S3 to the idle digital channels one by one, run the test program, and measure the interfered Site and the interference source Site, and confirm the interference Pin of the interference source Site according to the test results.

2. A method for quickly troubleshooting inter-site interference Pins of a wafer test probe card according to claim 1, characterized in that: During the full-site parallel testing of a wafer, when the test completion reaches between 30% and 50%, the real low-yield sites that have not improved the yield after automatic needle cleaning or increasing the OD of the probe station are screened out based on the yield distribution data. These sites are unstable sites during parallel testing.

3. The method for quickly troubleshooting inter-site interference Pins of wafer test probe cards according to claim 1, characterized in that: When 50% of all sites have been measured, the unstable sites are screened and measured.

4. The method for quickly troubleshooting inter-site interference Pins of a wafer test probe card according to claim 2, characterized in that: The method for confirming the disturbed sites in step S2 is: testing the sites that are unstable one by one, and the sites that are stable during the individual tests are the disturbed sites.

5. The method for quickly troubleshooting inter-site interference Pins of wafer test probe cards according to claim 4, characterized in that: The method for confirming the interference source site in step S3 is as follows: in order from near to far distance from the interfered site, one site to be checked is selected each time to be combined with the interfered site for testing, the test program is run, and whether the test passes stably; if both the site to be checked and the interfered site pass stably during the test, the site to be checked is skipped, and a new site to be checked is selected for combined testing; if the interfered site is unstable during the test, but the site to be checked passes, the site to be checked being tested is confirmed to be the interference source site.

6. A method for quickly troubleshooting inter-site interference Pins of a wafer test probe card according to claim 5, characterized in that: Step S5 also includes sub-steps: Sub-step S51: Compare the definition of chip pins of each site in the test program Socket file, and independently connect one of the chip pins to be checked at the interference source site to an idle digital channel by editing the Socket file; Sub-step S52: Run the test program to determine whether the chip pin currently connected to the idle digital channel is an interference source based on the multi-site test results.

7. The method for quickly troubleshooting inter-site interference Pins of a wafer test probe card according to claim 6, characterized in that: The judgment method is: if a chip pin is connected to an idle digital channel, and the test yield of the disturbed site returns to the normal level, it can be confirmed that the interference pin during the wafer multi-site test is the chip pin, and the test verification procedure ends; If a chip pin is connected to an idle digital channel and the interfered site test is still unstable, it means that the said pin is not an interference pin; Repeat sub-steps S51 and S52, continue to connect the chip pins to the idle digital channels in sequence, and test and verify again until the interference pin is found.

8. According to a method for quickly troubleshooting inter-site interference Pins of a wafer test probe card according to claim 7, it is characterized in that: The following steps are also included: If there are three types of power supplies in the specific test: VDD, VDDQ and VBAT, the interference source power supply pins are connected to the idle DPS channels in turn to perform combined testing and troubleshooting.

9. The method for quickly troubleshooting inter-site interference Pins of a wafer test probe card according to claim 8, characterized in that: By editing the Socket file, connect the power pins of the interference source to the idle DPS channels in turn.

10. A wafer testing method, after determining the interference Pin by the method for quickly troubleshooting the interference Pin between wafer test probe card sites as described in any one of claims 1-9, first physically isolate the interference Pin and then perform conventional testing; if the yield is still not improved after conventional testing after physically isolating the interference Pin, then the interference source Site is grouped separately into a group through software program grouping, and other Sites are grouped into a group for testing.

Images