A method, device, electronic device and storage medium for chip aging test

Abstract

The present application discloses a chip aging test method, device, electronic device and storage medium. The method includes: converting the standard five-wire communication for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip; selecting a test mode for high-voltage stress testing and determining the test voltage and test time for performing high-voltage stress testing on the target chip; in the test mode, testing the target chip according to the test voltage and test time, and taking the test result as the aging test result of the chip to be tested. By obtaining the target chip through converting the standard five-wire communication inside the chip to be tested into target two-wire communication, and taking the test result obtained by the target chip under high-voltage stress testing as the aging test result, all test items can be completed through only two test channels, while reducing the test time for each chip test, thereby reducing the test cost and improving the test efficiency.

Description

Technical Field

[0001] This application relates to the field of chip testing, and particularly to a chip aging test method, device, electronic device, and storage medium. Background Art

[0002] Chip aging and stress testing are key steps to ensure the quality and reliability of semiconductor products. They screen out potential faulty chips during the manufacturing stage, thus improving the overall product quality and market competitiveness. However, in practical applications, these tests require highly precise test equipment, complex test procedures, a harsh test environment, and a long test time to ensure the effectiveness of the tests. Summary of the Invention

[0003] This application provides a chip aging test method, device, electronic device, and storage medium, which can complete all test items through only two test channels while reducing the test time for each chip test, thereby reducing the test cost and improving the test efficiency.

[0004] According to one aspect of this application, a chip aging test method is provided. The method includes:

[0005] Converting the standard five-wire communication for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip;

[0006] Selecting a test mode for high-voltage stress testing and determining the test voltage and test time for performing high-voltage stress testing on the target chip;

[0007] Testing the target chip according to the test voltage and the test time in the test mode, and using the test result as the aging test result of the chip to be tested.

[0008] According to another aspect of this application, a chip aging test device is provided. The device includes:

[0009] A communication conversion module for converting the standard five-wire communication for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip;

[0010] A test preparation module for selecting a test mode for high-voltage stress testing and determining the test voltage and test time for performing high-voltage stress testing on the target chip;

[0011] An aging test module for testing the target chip according to the test voltage and the test time in the test mode, and using the test result as the aging test result of the chip to be tested.

[0012] According to another aspect of the present application, there is provided an electronic device, which includes:

[0013] at least one processor; and

[0014] a memory communicatively connected to the at least one processor; wherein,

[0015] the memory stores a computer program executable by the at least one processor, and when the computer program is executed by the at least one processor, the at least one processor is enabled to execute the chip aging test method according to any embodiment of the present invention.

[0016] According to another aspect of the present application, there is provided a computer-readable storage medium storing computer instructions for causing a processor to implement the chip aging test method according to any embodiment of the present invention when executed.

[0017] The technical solution of the embodiments of the present application converts the standard five-wire communication for chip testing inside the chip to be tested into the target two-wire communication through a communication protocol conversion controller to obtain a target chip; selects a test mode for high-voltage stress testing, and determines the test voltage and test time for performing high-voltage stress testing on the target chip; in the test mode, tests the target chip according to the test voltage and the test time, and uses the test result as the aging test result of the chip to be tested. The technical solution of the embodiments of the present application can, by converting the standard five-wire communication inside the chip to be tested into the target two-wire communication to obtain the target chip, and obtaining the test result obtained by the target chip under high-voltage stress testing as the aging test result, complete all test items through only two test channels while reducing the test time for each chip test item, thereby reducing the test cost and improving the test efficiency.

[0018] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0020] Figure 1 is a flowchart of a chip aging test method provided according to Embodiment 1 of the present application;

[0021] Figure 2 It is a schematic diagram of a TP-LPCT architecture provided according to Embodiment 1 of the present application;

[0022] Figure 3 It is a flowchart of a chip aging test method provided according to Embodiment 2 of the present application;

[0023] Figure 4 It is a schematic flowchart of implementing TRST through TPCLK and TPIO provided according to Embodiment 2 of the present application;

[0024] Figure 5 It is a schematic diagram of the structure of a chip aging test device provided according to Embodiment 3 of the present application;

[0025] Figure 6 It is a schematic diagram of the structure of an electronic device for implementing the chip aging test method of the embodiments of the present application. Detailed implementation manners

[0026] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] Embodiment 1

[0029] Figure 1FIG. 1 is a flowchart of a chip aging test method provided in Embodiment 1 of the present application. This embodiment is applicable to the situation of aging test of chips. The chip aging test method can be executed by a chip aging test device, which can be implemented in the form of hardware and / or software, and the chip aging test device can be configured in an electronic device. As Figure 1 shown, the method includes:

[0030] S110. Convert the standard five-wire communication for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller, and obtain a target chip.

[0031] Among them, the communication protocol conversion controller is a device capable of converting between different communication protocols, and is used to ensure accurate and efficient transmission of data between different devices or systems. In the embodiment of the present application, the communication protocol converter can be a dual-line serial port controller.

[0032] Among them, the standard five-wire communication is five communication channels for chip testing defined by the international standard electronic circuit test protocol JTAG. The standard five-wire communication includes test clock TCK, test mode selection TMS, test data input TDI, test data output TDO, and test reset TRST.

[0033] Among them, the target two-wire communication is two communication channels for chip testing obtained by converting the standard five-wire communication through a communication protocol conversion controller. The target two-wire communication includes a test clock port TPCLK and a test data input / output port TPIO.

[0034] In the embodiment of the present application, a communication protocol conversion controller can be added on the basis of traditional JTAG, and the traditional standard five-wire communication (TCK, TMS, TDI, TDO, TRST) of JTAG is converted into target two-wire communication (TPCLK, TPIO) inside the chip through the communication protocol conversion controller, and a target chip with a two-port low-pin-count test TP-LPCT architecture is obtained. Exemplarily, Figure 2 FIG. 2 shows a schematic diagram of a TP-LPCT architecture.

[0035] The TP-LPCT architecture is based on the IEEE1149.1 protocol and redefines the format of JTAG transceiver data packets in a serial interface manner. This structure is nearly compatible with all test structures and ideas of IEEE1149.1. At the same time, an IJTAG Network based on IEEE1687 is adopted inside the target chip to connect each test IP, and it can also be used for the ATPG Pattern test of SCAN through TP-LPCT. Specifically, SCAN can be embedded in the IJTAG Network, and the SCAN test of the chip can be selected by configuring JTAG in TP-LPCT. In addition, a Logic BIST controller, a Burn-In controller, etc. can be introduced into the chip and configured into the IJTAG Network inside the chip to further reduce the chip test cost.

[0036] In summary, by converting the standard five-wire communication to the target two-wire communication through the communication protocol conversion controller, the target chip of the TP-LPLT architecture only needs two test channels to complete the test of all test items of the chip, reducing the dependence on test channels, increasing the number of chips that can be tested simultaneously, enabling more chips to be tested simultaneously with a low-performance machine platform, and reducing the test cost.

[0037] S120: Select the test mode for high-voltage stress testing and determine the test voltage and test time for high-voltage stress testing of the target chip.

[0038] Among them, high-voltage stress testing simulates the working state of the device under extreme conditions by applying a higher voltage on the basis of the normal operating voltage of the device. High-voltage stress testing can accelerate the aging and failure process of the internal structure of the device, thus revealing possible defects and hidden dangers of the device.

[0039] Among them, the input voltage of the target chip includes a first voltage, a second voltage, and a third voltage, which are respectively the power supply voltage VDD(CORE_1V5) for powering the core logic part in the integrated circuit, the power supply voltage VDD(CORE_5V) for powering the core logic part in the integrated circuit, and the power supply voltage VDD(IO) for powering the IO port in the integrated circuit. Correspondingly, the test voltage of the target chip includes a first test voltage, a second test voltage, and a third test voltage.

[0040] In the embodiments of the present application, the test items that need to be subjected to high-voltage stress testing can be determined first. According to these test items, the test modes for high-voltage stress testing are selected. Then, referring to industry standards or technical specifications, the test voltage and test time for high-voltage stress testing of the target chip are determined. By determining reasonable test voltage and test time, on the one hand, it can ensure that the test can accurately reflect the performance of the chip under high-voltage stress environment, guaranteeing the effectiveness and accuracy of the test. On the other hand, it can avoid the chip being damaged due to excessive voltage or too long time during the test.

[0041] S130. Under the test mode, test the target chip according to the test voltage and test time, and use the test result as the aging test result of the chip to be tested.

[0042] In the embodiments of the present application, the high-voltage stress testing of the target chip can be carried out under the selected test mode for high-voltage stress testing. Specifically: The first step is to prepare the test environment to ensure that the test equipment is in good working condition; the second step is to select the test mode. According to the test items that need to be subjected to high-voltage stress testing, determine the test mode and select the test pattern with the highest activation rate; the third step is to load the test parameters. Input the previously determined test voltage and test time on the test equipment to ensure that the test process can accurately simulate the working state of the chip under high-voltage stress environment; the fourth step is to conduct the test. Install the target chip on the test socket to ensure good electrical connection, start the test equipment, and start running the chip according to the selected test mode for testing. The fifth step is to collect and analyze the test results. After the test is completed, collect all the data recorded during the test and analyze the test data to evaluate the performance of the chip under high-voltage stress environment. It can be understood that after the high-voltage stress testing of the target chip, the test results of the target chip under high-voltage stress testing can be obtained as the aging test results of the target chip, which are used to screen out the products that may fail early and ensure that the delivered chips have higher reliability. Compared with the traditional method, the test process proposed in the present application can reduce the test time of various tests of the chip and improve the efficiency of chip aging testing.

[0043] In the technical solution of the embodiment of the present application, the standard five-wire communication for chip testing inside the chip to be tested is converted into the target two-wire communication through a communication protocol conversion controller, obtaining a target chip; a test mode for high-voltage stress testing is selected, and the test voltage and test time for performing high-voltage stress testing on the target chip are determined; in the test mode, the target chip is tested according to the test voltage and test time, and the test result is used as the aging test result of the chip to be tested. In the technical solution of the embodiment of the present application, by converting the standard five-wire communication inside the chip to be tested into the target two-wire communication to obtain the target chip, and obtaining the test result obtained by the target chip under high-voltage stress testing as the aging test result, all test items can be completed with only two test channels, while reducing the test time of each chip test, thereby reducing the test cost and improving the test efficiency.

[0044] Embodiment 2

[0045] Figure 3 The flowchart of a chip aging test method provided by Embodiment 2 of the present application is based on the above embodiment for optimization. For the solutions not described in detail in the embodiment of the present application, please refer to the above embodiment. As Figure 3 shown, the method includes:

[0046] S210. Convert the standard five-wire communication for chip testing inside the chip to be tested into the target two-wire communication through a communication protocol conversion controller, obtaining a target chip.

[0047] Optionally, converting the standard five-wire communication for chip testing inside the chip to be tested into the target two-wire communication through a communication protocol conversion controller, obtaining a target chip, includes: generating a test clock TCK through internal frequency division of the test clock port TPCLK; multiplexing the test mode selection TMS, the test data input TDI, and the test data output TDO in the form of data packets on the test data input / output port TPIO in a time-division manner; implementing the test reset TRST through the test clock port TPCLK and the test data input / output port TPIO.

[0048] Among them, time-division multiplexing is a communication technology that can transmit different signals by adopting different time periods of the same physical connection to achieve the purpose of multiplexing.

[0049] In an embodiment of the present application, a test clock TCK can be generated by internally dividing the frequency of the test clock port TPCLK. Multiplexed transmission of the test mode selection TMS, test data input TDI, and test data output TDO in a communication channel is achieved through the test data input / output port TPIO and time-division multiplexing technology. The test reset TRST is implemented through the test clock port TPCLK and the test data input / output port TPIO. Thus, a standard five-wire communication for chip testing can be achieved on the premise of only using two communication channels.

[0050] Optionally, implementing the test reset TRST through the test clock port TPCLK and the test data input / output port TPIO includes: when preparing to start a new test item, using the test data input / output port TPIO as the clock and the test clock port TPCLK as the data input to a set of shift registers; if the test data input / output port TPIO is used as the clock, and within five consecutive clock cycles, the data input by the test clock port TPCLK is all 1, triggering the test reset TRST to reset all test logics.

[0051] In an embodiment of the present application, specific timing signals can be used to control the shift registers and reset the test logics. Specifically, when entering the test mode or when the previous test item ends and preparing to start a new test item, a clock pulse is provided to the shift registers through the test data input / output port TPIO, and data input is provided to the shift registers through the test clock port TPCLK. If the TPCLK signal remains in a specific state of 1 within 5 clock cycles of TPIO, the test reset TRST is triggered to reset (or reinitialize) all test logics in the system. This means that all relevant test registers, counters, state machines, etc. will be reset to their initial states. At the same time, the system will enter a specific test mode according to the preset configuration or selection. Exemplarily, Figure 4 A schematic flow diagram of implementing TRST through TPCLK and TPIO is shown.

[0052] S220. Select a test mode for high-voltage stress testing.

[0053] In the embodiments of the present application, the test items that need to be subjected to high-voltage stress testing can be determined first, and the test modes for high-voltage stress testing can be selected according to these test items. Optionally, the test modes that can be used for high-voltage stress testing include Core SCAN Patterns, Array BIST Patterns, At-Speed Patterns, etc. Preferably, the best solution for selecting the test mode for high-voltage stress testing is to select a special Logic BIST pattern dedicated to aging testing.

[0054] S230. Select a good chip with the same specifications as the target chip as a sample chip, and determine the test voltage of the target chip according to the sample chip.

[0055] In the embodiments of the present application, a good chip with excellent performance in all aspects and the same specifications as the target chip can be selected as a sample chip, and experiments can be carried out through the sample chip to determine the test voltage of the target chip, so as to ensure that the test can accurately reflect the performance of the chip in a high-voltage stress environment and ensure the effectiveness and accuracy of the test.

[0056] Optionally, determining the test voltage of the target chip according to the sample chip includes: determining the maximum voltage defined by the product specifications of the sample chip as the starting voltage, and determining the failure voltage of the sample chip according to the starting voltage; determining the breakdown voltage of the sample chip according to the failure voltage, and determining the test voltage of the sample chip according to the breakdown voltage.

[0057] Wherein, the test voltage includes a first test voltage, a second test voltage, and a third test voltage. Correspondingly, the starting voltage includes a first starting voltage, a second starting voltage, and a third starting voltage, the failure voltage includes a first failure voltage, a second failure voltage, and a third failure voltage, and the breakdown voltage includes a first breakdown voltage, a second breakdown voltage, and a third breakdown voltage.

[0058] In the embodiments of the present application, it can be understood that high-voltage stress testing is to simulate the working state of the device under extreme conditions by applying a higher voltage on the basis of the normal working voltage of the device. Therefore, the maximum voltage defined by the product specifications of the sample chip can be determined as the starting voltage, and the starting voltage can be increased in accordance with a preset step length on the basis of the starting voltage to sequentially determine the failure voltage when the chip fails and the breakdown voltage when the chip is broken down, and then determine the test voltage of the sample chip according to the breakdown voltage to simulate the working state of the device under extreme conditions.

[0059] Optionally, determining the failure voltage of the sample according to the starting voltage includes: fixing the voltage of the second path as the starting voltage of the second path, fixing the voltage of the third path as the starting voltage of the third path, starting from the starting voltage of the first path according to the first preset step size, increasing the value of the voltage of the first path until the chip fails, and determining the failure voltage of the first path of the sample; fixing the voltage of the first path as the starting voltage of the first path, fixing the voltage of the third path as the starting voltage of the third path, starting from the starting voltage of the second path according to the first preset step size, increasing the value of the voltage of the second path until the chip fails, and determining the failure voltage of the second path of the sample; fixing the voltage of the first path as the starting voltage of the first path, fixing the voltage of the second path as the starting voltage of the second path, starting from the starting voltage of the third path according to the first preset step size, increasing the value of the voltage of the third path until the chip fails, and determining the failure voltage of the third path of the sample.

[0060] In the embodiment of the present application, the voltage of the second path can be fixed as the starting voltage of the second path, the voltage of the third path can be fixed as the starting voltage of the third path, and then starting from the starting voltage of the first path according to the first preset step size, increasing the value of the voltage of the first path until the chip fails, to determine the failure voltage of the first path of the sample. Among them, the first preset step size can be set according to the actual situation, such as 100 mV, and the embodiment of the present application does not limit this. After that, the failure voltage of the second path and the failure voltage of the third path can be determined in the same way.

[0061] Optionally, determining the breakdown voltage of the sample according to the failure voltage of the sample, and determining the test voltage of the sample according to the breakdown voltage; includes: fixing the voltage of the second path as the difference between the failure voltage of the second path and the first preset value, fixing the voltage of the third path as the difference between the failure voltage of the third path and the first preset value, starting from the difference between the failure voltage of the first path and the first preset value according to the second preset step size, increasing the voltage of the first path until the chip breaks down, and determining the breakdown voltage of the first path of the sample; fixing the voltage of the first path as the difference between the breakdown voltage of the first path and the second preset value, fixing the voltage of the third path as the difference between the failure voltage of the third path and the first preset value, starting from the difference between the failure voltage of the second path and the first preset value according to the second preset step size, increasing the voltage of the second path until the chip breaks down, and determining the breakdown voltage of the second path of the sample; fixing the voltage of the first path as the difference between the breakdown voltage of the first path and the second preset value, fixing the voltage of the second path as the difference between the breakdown voltage of the second path and the second preset value, starting from the difference between the failure voltage of the third path and the first preset value according to the second preset step size, increasing the voltage of the third path until the chip breaks down, and determining the breakdown voltage of the third path of the sample; respectively taking the product of the breakdown voltage of the first path and the preset coefficient, the product of the breakdown voltage of the second path and the preset coefficient, and the product of the breakdown voltage of the third path and the preset coefficient as the test voltage of the first path, the test voltage of the second path, and the test voltage of the third path.

[0062] In the embodiment of the present application, the two-way voltage can be fixed to a working voltage lower than the first preset value of the two-way failure voltage, and the three-way voltage can be fixed to a working voltage lower than the first preset value of the three-way failure voltage. Starting from the working voltage lower than the first preset value of the one-way failure voltage, the one-way voltage is increased until the chip is broken down according to the second preset step length, and the one-way breakdown voltage of the sample is determined. The first preset value and the second preset step length can be set according to the actual situation, and the embodiment of the present application does not limit this. Exemplarily, the two-way voltage can be fixed to a working voltage 300 mV lower than the two-way failure voltage, the three-way voltage can be fixed to a working voltage 300 mV lower than the three-way failure voltage, and starting from the working voltage 300 mV lower than the one-way failure voltage with a step length of 100 mV, the one-way voltage is increased until the chip is broken down to determine the one-way breakdown voltage of the sample. After that, different from the method of determining the failure voltage, when determining the two-way breakdown voltage, the one-way voltage is fixed to the difference between the one-way breakdown voltage and the second preset value, that is, the working voltage lower than the second preset value of the one-way breakdown voltage. When determining the three-way breakdown voltage, the one-way voltage is fixed to the difference between the one-way breakdown voltage and the second preset value, and the two-way voltage is fixed to the difference between the two-way breakdown voltage and the second preset value. The second preset value can be set according to the actual situation, such as 300 mV, and the embodiment of the present application does not limit this.

[0063] After determining the one-way breakdown voltage, the two-way breakdown voltage, and the three-way breakdown voltage, the product of the one-way breakdown voltage and the preset coefficient, the product of the two-way breakdown voltage and the preset coefficient, and the product of the three-way breakdown voltage and the preset coefficient can be taken as the one-way test voltage, the two-way test voltage, and the three-way test voltage respectively. The preset coefficient can be set according to the actual situation, such as 0.8, and the embodiment of the present application does not limit this.

[0064] S240. Determine the test time for performing the high-voltage stress test on the target chip according to the performance target of the target chip in the design determination stage.

[0065] In the embodiment of the present application, the performance target of the target chip at signoff in the design determination stage can be clarified first to understand the performance indicators and test requirements to be verified. Then, according to the characteristics of the chip such as voltage tolerance and circuit complexity, the test time for performing the high-voltage stress test on the target chip is evaluated.

[0066] S250. In the test mode, test the target chip according to the test voltage and the test time, and use the test result as the aging test result of the chip to be tested.

[0067] In the technical solution of the embodiment of the present application, a communication protocol conversion controller is used to convert the standard five-wire communication for chip testing inside the chip to be tested into target two-wire communication, obtaining a target chip; a test mode for high-voltage stress testing is selected; a good chip with the same specifications as the target chip is selected as a sample chip, and the test voltage of the target chip is determined according to the sample chip; according to the performance target of the target chip in the design determination stage, the test time for performing high-voltage stress testing on the target chip is determined; in the test mode, the target chip is tested according to the test voltage and the test time, and the test result is used as the aging test result of the chip to be tested. In the technical solution of the embodiment of the present application, by converting the standard five-wire communication inside the chip to be tested into target two-wire communication to obtain a target chip, and obtaining the test result obtained by the target chip under high-voltage stress testing as the aging test result, all test items can be completed through only two test channels while reducing the test time of each chip test, thereby reducing the test cost and improving the test efficiency.

[0068] Embodiment III

[0069] Figure 5 FIG. is a schematic structural diagram of a chip aging test device provided in Embodiment III of the present application.

[0070] As Figure 5 shown, the device includes:

[0071] A communication conversion module 310, configured to convert the standard five-wire communication for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller, obtaining a target chip;

[0072] A test preparation module 320, configured to select a test mode for high-voltage stress testing, and determine the test voltage and test time for performing high-voltage stress testing on the target chip;

[0073] An aging test module 330, configured to test the target chip according to the test voltage and the test time in the test mode, and use the test result as the aging test result of the chip to be tested.

[0074] Optionally, the standard five-wire communication includes a test clock TCK, a test mode selection TMS, a test data input TDI, a test data output TDO, and a test reset TRST; the target two-wire communication includes a test clock port TPCLK and a test data input / output port TPIO; the communication conversion module 310 is configured to:

[0075] Generate a test clock TCK through internal frequency division of the test clock port TPCLK;

[0076] The test mode selection TMS, test data input TDI, and test data output TDO are time-division multiplexed in the form of data packets on the test data input / output port TPIO;

[0077] The test reset TRST is implemented through the test clock port TPCLK and the test data input / output port TPIO.

[0078] Optionally, the communication conversion module 310 is specifically configured to:

[0079] When preparing to start a new test item, the test data input / output port TPIO is used as the clock, and the test clock port TPCLK is used as the data input to a set of shift registers;

[0080] If the test data input / output port TPIO is used as the clock, and within five consecutive clock cycles, the data input by the test clock port TPCLK is all 1, the test reset TRST is triggered to reset all test logics.

[0081] Optionally, the test preparation module 320 includes:

[0082] A test voltage determination unit, which is used to select a good chip with the same specification as the target chip as a sample, and determine the test voltage of the target chip according to the sample;

[0083] A test time determination unit, which is used to determine the test time for performing a high-voltage stress test on the target chip according to the performance target of the target chip in the design determination stage.

[0084] Optionally, the test voltage determination unit includes:

[0085] A failure voltage determination subunit, which is used to determine the maximum voltage defined by the product specification of the sample as the starting voltage, and determine the failure voltage of the sample according to the starting voltage;

[0086] A test voltage determination subunit, which is used to determine the breakdown voltage of the sample according to the failure voltage, and determine the test voltage of the sample according to the breakdown voltage.

[0087] Optionally, the starting voltage includes a first starting voltage, a second starting voltage, and a third starting voltage; the failure voltage includes a first failure voltage, a second failure voltage, and a third failure voltage; the failure voltage determination subunit is specifically configured to:

[0088] Fix the second voltage as the second starting voltage, fix the third voltage as the third starting voltage, start from the first starting voltage, increase the value of the first voltage until the chip fails, and determine the first failure voltage of the sample;

[0089] Fix the voltage of one path to the starting voltage of one path, fix the voltages of three paths to the starting voltages of three paths, start from the starting voltage of two paths according to the first preset step size, increase the value of the voltage of two paths until the chip fails, and determine the breakdown voltage of two paths of the sample wafer;

[0090] Fix the voltage of one path to the starting voltage of one path, fix the voltage of two paths to the starting voltage of two paths, start from the starting voltage of three paths according to the first preset step size, increase the value of the voltage of three paths until the chip fails, and determine the breakdown voltage of three paths of the sample wafer.

[0091] Optionally, the breakdown voltage includes the breakdown voltage of one path, the breakdown voltage of two paths, and the breakdown voltage of three paths; the test voltage includes the test voltage of one path, the test voltage of two paths, and the test voltage of three paths; the test voltage determination subunit is specifically used for:

[0092] Fix the voltage of two paths to the difference between the breakdown voltage of two paths and the first preset value, fix the voltage of three paths to the difference between the breakdown voltage of three paths and the first preset value, start from the difference between the breakdown voltage of one path and the first preset value according to the second preset step size, increase the voltage of one path until the chip is broken down, and determine the breakdown voltage of one path of the sample wafer;

[0093] Fix the voltage of one path to the difference between the breakdown voltage of one path and the second preset value, fix the voltage of three paths to the difference between the breakdown voltage of three paths and the first preset value, start from the difference between the breakdown voltage of two paths and the first preset value according to the second preset step size, increase the voltage of two paths until the chip is broken down, and determine the breakdown voltage of two paths of the sample wafer;

[0094] Fix the voltage of one path to the difference between the breakdown voltage of one path and the second preset value, fix the voltage of two paths to the difference between the breakdown voltage of two paths and the second preset value, start from the difference between the breakdown voltage of three paths and the first preset value according to the second preset step size, increase the voltage of three paths until the chip is broken down, and determine the breakdown voltage of three paths of the sample wafer;

[0095] Respectively take the product of the breakdown voltage of one path and the preset coefficient, the product of the breakdown voltage of two paths and the preset coefficient, and the product of the breakdown voltage of three paths and the preset coefficient as the test voltage of one path, the test voltage of two paths, and the test voltage of three paths.

[0096] The chip aging test device provided by the embodiments of the present application can execute the chip aging test method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects for executing the method.

[0097] Embodiment 4

[0098] Figure 6 FIG. 1 shows a schematic structural diagram of an electronic device 10 that can be used to implement embodiments of the present application. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0099] As Figure 6 shown, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc. The memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0100] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0101] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the chip aging test method.

[0102] In some embodiments, the chip aging test method may be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the chip aging test method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to execute the chip aging test method by any other suitable means (e.g., by means of firmware).

[0103] The various embodiments of the systems and techniques described above in this document may be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), systems on a chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that may be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0104] The computer programs for implementing the methods of the present application may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions / operations specified in the flowchart and / or block diagram to be implemented. The computer programs may be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on the remote machine or server.

[0105] In the context of this application, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0106] To provide for interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide for interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0107] The systems and techniques described herein can be implemented in a computing system that includes backend components (such as, for example, a data server), or a computing system that includes middleware components (such as, for example, an application server), or a computing system that includes frontend components (such as, for example, a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (such as, for example, a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0108] A computing system may include a client and a server. The client and the server are generally far from each other and usually interact via a communication network. The client-server relationship is created by computer programs running on respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, solving the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0109] It should be understood that various forms of the processes shown above can be used, steps can be reordered, added or deleted. For example, the steps described in this application can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is imposed herein.

[0110] The above specific embodiments do not constitute a limitation on the protection scope of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the protection scope of this application.

Claims

1. A chip aging test method, characterized in that, The method includes: Converting the standard five - wire communication for chip testing inside the chip to be tested into target two - wire communication through a communication protocol conversion controller to obtain a target chip; Selecting a test mode for high - voltage stress testing and determining the test voltage and test time for performing high - voltage stress testing on the target chip; Testing the target chip according to the test voltage and the test time in the test mode, and using the test result as the aging test result of the chip to be tested; Wherein, the target two - wire communication includes a test clock port TPCLK and a test data input / output port TPIO; The converting the standard five - wire communication for chip testing inside the chip to be tested into target two - wire communication through a communication protocol conversion controller to obtain a target chip includes: Generating a test clock TCK through internal frequency division of the test clock port TPCLK; Time - division multiplexing the test mode selection TMS, the test data input TDI, and the test data output TDO in the form of data packets on the test data input / output port TPIO; Implementing test reset TRST through the test clock port TPCLK and the test data input / output port TPIO; The implementing test reset TRST through the test clock port TPCLK and the test data input / output port TPIO includes: When preparing to start a new test item, using the test data input / output port TPIO as the clock and the test clock port TPCLK as the data to input to a group of shift registers; If using the test data input / output port TPIO as the clock, within five consecutive clock cycles, if the data input by the test clock port TPCLK is all 1, triggering the test reset TRST to reset all test logics.

2. The method according to claim 1, characterized in that, The standard five - wire communication includes a test clock TCK, a test mode selection TMS, a test data input TDI, a test data output TDO, and a test reset TRST.

3. The method according to claim 1, characterized in that, Determining the test voltage and test time for performing high - voltage stress testing on the target chip includes: Selecting a good chip with the same specification as the target chip as a sample, and determining the test voltage of the target chip according to the sample; Determining the test time for performing high - voltage stress testing on the target chip according to the performance target of the target chip in the design determination stage.

4. The method according to claim 3, wherein Determining the test voltage of the target chip according to the sample includes: Determining the maximum voltage defined by the product specification of the sample as the starting voltage, and determining the failure voltage of the sample according to the starting voltage; Determining the breakdown voltage of the sample according to the failure voltage, and determining the test voltage of the sample according to the breakdown voltage.

5. The method according to claim 4, characterized in that, The starting voltage includes a first - path starting voltage, a second - path starting voltage, and a third - path starting voltage; the failure voltage includes a first - path failure voltage, a second - path failure voltage, and a third - path failure voltage; Determining the failure voltage of the sample according to the starting voltage includes: Fix the two-way voltage at the two-way starting voltage, fix the three-way voltage at the three-way starting voltage, and starting from the one-way starting voltage according to the first preset step size, increase the value of the one-way voltage until the chip fails, and determine the one-way failure voltage of the sample wafer; Fix the one-way voltage at the one-way starting voltage, fix the three-way voltage at the three-way starting voltage, and starting from the two-way starting voltage according to the first preset step size, increase the value of the two-way voltage until the chip fails, and determine the two-way failure voltage of the sample wafer; Fix the one-way voltage at the one-way starting voltage, fix the two-way voltage at the two-way starting voltage, and starting from the three-way starting voltage according to the first preset step size, increase the value of the three-way voltage until the chip fails, and determine the three-way failure voltage of the sample wafer.

6. The method according to claim 4, wherein The breakdown voltage includes a one-way breakdown voltage, a two-way breakdown voltage, and a three-way breakdown voltage; the test voltage includes a one-way test voltage, a two-way test voltage, and a three-way test voltage; Determine the breakdown voltage of the sample wafer according to the failure voltage of the sample wafer, and determine the test voltage of the sample wafer according to the breakdown voltage; including: Fix the two-way voltage at the difference between the two-way failure voltage and the first preset value, fix the three-way voltage at the difference between the three-way failure voltage and the first preset value, and starting from the difference between the one-way failure voltage and the first preset value according to the second preset step size, increase the one-way voltage until the chip is broken down, and determine the one-way breakdown voltage of the sample wafer; Fix the one-way voltage at the difference between the one-way breakdown voltage and the second preset value, fix the three-way voltage at the difference between the three-way failure voltage and the first preset value, and starting from the difference between the two-way failure voltage and the first preset value according to the second preset step size, increase the two-way voltage until the chip is broken down, and determine the two-way breakdown voltage of the sample wafer; Fix the one-way voltage at the difference between the one-way breakdown voltage and the second preset value, fix the two-way voltage at the difference between the two-way breakdown voltage and the second preset value, and starting from the difference between the three-way failure voltage and the first preset value according to the second preset step size, increase the three-way voltage until the chip is broken down, and determine the three-way breakdown voltage of the sample wafer; Respectively take the product of the one-way breakdown voltage and the preset coefficient, the product of the two-way breakdown voltage and the preset coefficient, and the product of the three-way breakdown voltage and the preset coefficient as the one-way test voltage, the two-way test voltage, and the three-way test voltage.

7. A chip aging test device, characterized in that, The device includes: A communication conversion module, configured to convert the standard five-wire communication for chip testing inside the chip to be tested into target two-wire communication through a communication protocol conversion controller to obtain a target chip; A test preparation module, configured to select a test mode for high-voltage stress testing, and determine the test voltage and test time for performing high-voltage stress testing on the target chip; An aging test module, configured to test the target chip according to the test voltage and the test time in the test mode, and use the test result as the aging test result of the chip to be tested; Among them, the target two-wire communication includes a test clock port TPCLK and a test data input / output port TPIO; The communication conversion module is used for: Generating a test clock TCK through internal frequency division of the test clock port TPCLK; Time-division multiplexing the test mode selection TMS, the test data input TDI, and the test data output TDO in the form of data packets on the test data input / output port TPIO; Implementing a test reset TRST through the test clock port TPCLK and the test data input / output port TPIO; Specifically, the communication conversion module is used for: When preparing to start a new test item, taking the test data input / output port TPIO as a clock and the test clock port TPCLK as data and inputting them to a set of shift registers; If the test data input / output port TPIO is used as a clock, and within five consecutive clock cycles, the data input by the test clock port TPCLK is all 1, triggering the test reset TRST to reset all test logics.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and A memory communicatively connected to the at least one processor; among them, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the chip aging test method according to any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the chip aging test method according to any one of claims 1-6 when executed by a processor.

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