Packaging device and preparation method thereof

Abstract

The invention relates to a packaging device and a preparation method thereof, and a wiring layer structure of the packaging device comprises a chip, an external circuit module and a photoelectric conversion module. The chip is located on one side of the wiring layer structure in the first direction, and the first direction is the thickness direction of the wiring layer structure. The external circuit module is located on the side, away from the chip, of the wiring layer structure in the first direction. The photoelectric conversion module and the chip and / or the external circuit module are installed on the same side of the wiring layer structure, and the photoelectric conversion module comprises a photoelectric conversion part and an optical interface part. The photoelectric conversion portion is mounted to the wiring layer structure. The optical interface part is connected with the photoelectric conversion part along a second direction, and the optical interface part protrudes relative to the wiring layer structure in the second direction, and the second direction is perpendicular to the first direction. The signal transmission speed can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a packaging device and a preparation method thereof. Background Art

[0002] For some packaged device products, circuit structures are formed on both sides of the wiring layer, wherein one side of the circuit structure includes a chip wrapped by a plastic packaging layer, and the other side includes an external circuit module.

[0003] The signal transmission rate of existing products formed in this way is usually limited. Summary of the invention

[0004] Based on this, the present application provides a packaging device capable of improving signal transmission speed and a method for preparing the same.

[0005] A packaging device, comprising:

[0006] Wiring layer structure;

[0007] A chip is located at one side of the wiring layer structure in a first direction, where the first direction is a thickness direction of the wiring layer structure;

[0008] An external circuit module, located on a side of the wiring layer structure away from the chip in a first direction;

[0009] A photoelectric conversion module is installed on the same side of the wiring layer structure as the chip and / or the external circuit module, and includes a photoelectric conversion part and an optical interface part; the photoelectric conversion part is installed to the wiring layer structure; the optical interface part is connected to the photoelectric conversion part along a second direction, and the optical interface part protrudes relative to the wiring layer structure in the second direction, and the second direction is perpendicular to the first direction.

[0010] In one embodiment, the photoelectric conversion module and the chip are mounted on the same side of the wiring layer structure;

[0011] The packaging device further includes a plastic encapsulation layer, which covers the chip, the wiring layer structure and at least a portion of the photoelectric conversion unit.

[0012] In one of the embodiments, a height of the optical interface portion in the first direction is greater than a height of the photoelectric conversion portion in the first direction.

[0013] In one of the embodiments, the photoelectric conversion module and the external circuit module are installed on the same side of the wiring layer structure;

[0014] The packaging device also includes a first frame structure, which includes a first frame and a socket located on the first frame, the photoelectric conversion part is located on a side of the first frame away from the wiring layer structure, and is connected to the wiring layer structure through the socket; or, the photoelectric conversion part is welded to the wiring layer structure.

[0015] In one embodiment, the photoelectric conversion unit includes an electric chip and an optical chip, the electric chip is mounted on the wiring layer structure, the optical chip is stacked on the electric chip along a first direction, and the optical interface unit is at least connected to the optical chip.

[0016] In one embodiment, the packaging device includes a first frame structure, the first frame structure includes a first frame and a socket located on the first frame, and the first frame structure is provided with a positioning hole;

[0017] The wiring layer structure further includes a positioning pin, which is located on a side of the wiring layer structure away from the chip in a first direction, and the positioning pin is inserted into the positioning hole.

[0018] In one embodiment, the first frame structure further includes an ear piece, the ear piece is connected to the first frame, and the positioning hole is located in the ear piece.

[0019] In one embodiment, the wiring layer structure includes an interposer structure, the interposer structure includes an interposer substrate, a wiring layer and a conductive through-hole structure, the wiring layer is located on one side of the interposer substrate, and the conductive through-hole structure penetrates the interposer substrate and connects the wiring layer; the chip is located on a side of the wiring layer away from the interposer substrate.

[0020] In one of the embodiments, the interposer structure further includes a protective layer, the protective layer is located on a side of the interposer substrate away from the wiring layer, and the conductive via structure penetrates the protective layer and the interposer substrate.

[0021] In one embodiment, the interposer structure further includes:

[0022] A first pad is located on the surface of the wiring layer, and the chip is mounted on the first pad;

[0023] a second pad, located on a side of the interposer substrate away from the wiring layer and covering the conductive through-hole structure, the external circuit module being mounted to the second pad;

[0024] The photoelectric conversion unit is connected to the first pad and / or the second pad;

[0025] The packaged device further comprises:

[0026] A plastic packaging layer, covering the chip and the interposer structure;

[0027] A heat sink is located on a side of the plastic packaging layer away from the intermediate layer structure;

[0028] A first fixing hole, penetrating the intermediate layer structure and the plastic packaging layer;

[0029] A fixing member passes through the first fixing hole to fix the heat sink.

[0030] A method for preparing a packaged device, comprising:

[0031] providing a first carrier board;

[0032] forming an interposer structure on the first carrier, the interposer structure comprising an interposer substrate, a wiring layer and a conductive through-hole structure, the wiring layer being located on a side of the interposer substrate away from the first carrier, the conductive through-hole structure penetrating the interposer substrate along a first direction to connect the wiring layer, the first direction being a thickness direction of the interposer substrate;

[0033] forming a chip on a side of the wiring layer away from the interposer substrate;

[0034] forming a plastic packaging layer covering the chip and the interposer structure;

[0035] removing the first carrier plate;

[0036] forming an external circuit module on a side of the interposer structure away from the chip, wherein the external circuit module is connected to the chip through the interposer structure;

[0037] Wherein, while a chip is formed on a side of the wiring layer away from the interposer substrate, a photoelectric conversion module is also formed on a side of the wiring layer away from the interposer substrate; and / or, while an external circuit module is formed on a side of the interposer structure away from the chip, a photoelectric conversion module is also formed on a side of the interposer structure away from the chip; the photoelectric conversion module includes a photoelectric conversion part and an optical interface part; the photoelectric conversion part is installed to the wiring layer structure; the optical interface part is connected to the photoelectric conversion part along a second direction, and the optical interface part protrudes relative to the wiring layer structure in the second direction, and the second direction is perpendicular to the first direction.

[0038] In one embodiment, the external circuit module includes an external plug-in, and after removing the first carrier board, further includes:

[0039] forming a positioning pin on a side of the interposer structure away from the chip;

[0040] The forming of an external circuit module on a side of the interposer structure away from the chip comprises:

[0041] A first frame structure having a positioning hole is formed on a side of the interposer structure away from the chip, and the positioning pin is inserted into the positioning hole, wherein the first frame structure includes a first frame and a socket located on the first frame;

[0042] An external plug-in is formed on a side of the first frame structure away from the interposer structure, and the external plug-in is connected to the second pad through the socket.

[0043] In the packaged device and the method for preparing the same, a photoelectric conversion module is provided in the packaged device and is mounted on the same side of the wiring layer structure as the chip and / or the external circuit module. The photoelectric conversion module can convert electrical signals into optical signals, thereby effectively improving the signal transmission speed, etc.

[0044] Meanwhile, the photoelectric conversion module includes a photoelectric conversion unit and an optical interface unit. The photoelectric conversion unit is mounted to the wiring layer structure, so that the photoelectric conversion unit and the wiring layer structure are conveniently electrically connected. The optical interface unit protrudes relative to the wiring layer structure in the second direction, so that it can be conveniently connected to an external light receiving device, so that optical signals can be transmitted between the external device. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a schematic diagram of a cross-sectional structure of a packaging device provided in an embodiment;

[0047] Figure 2 is a schematic cross-sectional structural diagram of a packaging device provided in another embodiment;

[0048] Figure 3 is an exploded cross-sectional structural schematic diagram of a local structure of a packaging device provided in an embodiment;

[0049] Figure 4 It is a schematic diagram of an exploded top view of a local structure of a packaging device provided in an embodiment;

[0050] Figure 5 is a flow chart of a method for preparing a packaged device provided in an embodiment;

[0051] Figures 6 to 21It is a schematic diagram of the cross-sectional structure of the structure obtained in each step of the method for preparing a packaging device provided in an embodiment.

[0052] Description of reference numerals:

[0053] 100-photoelectric conversion module, 110-photoelectric conversion unit, 111-electric chip, 112-optical chip, 120-optical interface unit, 200a-first carrier, 200b-second carrier, 200-wiring layer structure, 210-intermediate layer substrate, 220-wiring layer, 230-conductive through hole structure, 240-positioning pin, 2001-intermediate layer initial structure, 2101-intermediate layer initial sheet, 2301-conductive initial structure, 240-first pad, 250-second pad, 260-first graphic dielectric layer, 270-second graphic dielectric layer, 300-chip, 400 -plastic sealing layer, 500-external circuit module, 510-passive device, 520-external plug-in, 521-voltage management module, 522-connector, 600-protective layer, 6001-protective material layer, 710-first adhesive layer, 720-second adhesive layer, 730-adhesive, 740-fixing part, 810-first frame structure, 811-first frame, 812-socket, 813-conductive part, 814-ear piece, 820-second frame structure, 900-heat sink, 10-annular space, 20-first fixing hole, 30-second fixing hole, 40-positioning hole. DETAILED DESCRIPTION

[0054] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0055] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0056] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0057] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0058] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0059] In one embodiment, see Figure 1 or Figure 2 , a packaging device is provided, which includes a wiring layer structure 200, a chip 300, an external circuit module 500 and a photoelectric conversion module 100.

[0060] The wiring layer structure 200 may include a plurality of interconnected wiring layers 220 , and an insulating dielectric layer may be provided between adjacent wiring layers 220 .

[0061] The chip 300 is located at one side of the wiring layer structure 200 in a first direction. The first direction is a thickness direction of the wiring layer structure 200.

[0062] A plurality of chips 300 may be disposed on one side of the wiring layer structure 200. The plurality of chips 300 may be disposed at intervals. Each chip 300 may be electrically connected to the wiring layer 220. Different chips 300 may have different functions.

[0063] The external circuit module 500 is located on a side of the wiring layer structure 200 away from the chip 300 in the first direction. That is, the external circuit module 500 and the chip 300 are located on two opposite sides of the wiring layer structure 200, respectively.

[0064] The external circuit module 500 may include a passive device 510 (IPD) and / or an external plug-in 520 , etc. The external plug-in 520 may include a voltage management module 521 and / or a connector 522 , etc. And the external circuit module 500 may be connected to the chip 300 through the wiring layer structure 200 .

[0065] The photoelectric conversion module 100 and the chip 300 are mounted on the same side of the wiring layer structure 200. Alternatively, the photoelectric conversion module 100 and the external circuit module 500 are mounted on the same side of the wiring layer structure 200. Alternatively, when the number of the photoelectric conversion modules 100 is greater than one, there may be both a photoelectric conversion module 100 mounted on the same side of the wiring layer structure 200 as the chip 300 and a photoelectric conversion module 100 mounted on the same side of the wiring layer structure 200 as the external circuit module 500.

[0066] The number of the photoelectric conversion module 100 may be one or more than one. Moreover, the same photoelectric conversion module 100 includes a photoelectric conversion unit 110 and an optical interface unit 120 .

[0067] The photoelectric conversion unit 110 performs photoelectric conversion.

[0068] At the same time, the photoelectric converter 110 is mounted to the wiring layer structure 200. At this time, on the projection plane perpendicular to the first direction, the orthographic projection of the photoelectric converter 110 overlaps with the orthographic projection of the wiring layer structure 200, thereby facilitating electrical connection between the photoelectric converter 110 and the wiring layer structure 200.

[0069] The optical interface portion 120 is connected to the photoelectric conversion portion 110 along the second direction.

[0070] As an example, the photoelectric conversion unit 110 may include an electric chip 111 and an optical chip 112. The electric chip 111 is mounted to the wiring layer structure 200 so as to be electrically connected to the wiring layer structure 200. The optical chip 112 is stacked on the electric chip 111 along a first direction so as to convert an electric signal on the electric chip 111 into an optical signal, or convert an optical signal into an electric signal and transmit it to the electric chip 111.

[0071] At this time, the optical interface portion 120 may be connected to at least the optical chip 112 .

[0072] Of course, the form of the photoelectric conversion unit 110 is not limited thereto. For example, the photoelectric conversion unit 110 may also include a single chip 300 having a photoelectric conversion function, which is not limited here. For another example, the photoelectric conversion unit 110 may include an electrical chip 111 and an optical chip 112. The electrical chip 111, the optical chip 112, and the optical interface may be arranged in sequence along the second direction.

[0073] The optical interface portion 120 protrudes relative to the wiring layer structure 200 in the second direction, so that it can be easily connected to an external optical receiving device (such as an optical fiber, etc.), so that optical signals can be transmitted between external devices. The second direction is perpendicular to the first direction, that is, the second direction is perpendicular to the thickness direction of the wiring layer structure 200.

[0074] In this embodiment, in the packaged device, a photoelectric conversion module 100 is provided which is mounted on the same side of the wiring layer structure 200 as the chip 300 and / or the external circuit module 500. The photoelectric conversion module 100 can convert electrical signals into optical signals, thereby effectively improving signal transmission speed.

[0075] Meanwhile, the photoelectric conversion module 100 includes a photoelectric conversion unit 110 and an optical interface unit 120. The photoelectric conversion unit 110 is mounted to the wiring layer structure 200, so as to facilitate electrical connection between the photoelectric conversion unit 110 and the wiring layer structure 200. The optical interface unit 120 protrudes relative to the wiring layer structure 200 in the second direction, so as to facilitate connection with an external light receiving device, so as to transmit optical signals between the external devices.

[0076] In one embodiment, see Figure 1 , the photoelectric conversion module 100 and the chip 300 are mounted on the same side of the wiring layer structure 200 .

[0077] The packaged device further includes a plastic encapsulation layer 400. The material of the plastic encapsulation layer 400 may include but is not limited to epoxy molding compound (EMC).

[0078] The plastic encapsulation layer 400 covers the chip 300 , the wiring layer structure 200 and at least a portion of the photoelectric conversion unit 110 .

[0079] As an example, on a projection plane perpendicular to the first direction, the orthographic projection of the photoelectric conversion body 110 may be completely located within the orthographic projection of the wiring layer structure 200. At this time, the plastic encapsulation layer 400 may completely cover the photoelectric conversion body 110.

[0080] As an example, on the projection plane perpendicular to the first direction, the orthographic projection of the photoelectric conversion unit 110 may also partially exceed the orthographic projection of the wiring layer structure 200. In this case, the plastic encapsulation layer 400 may cover the part of the orthographic projection of the photoelectric conversion unit 110 that is within the orthographic projection of the wiring layer structure 200.

[0081] In this embodiment, the photoelectric conversion module 100 and the chip 300 are installed on the same side of the wiring layer structure 200, so that the chip 300 can be plastic-encapsulated and mechanically fixed at the same time as the photoelectric conversion part 110 is plastic-encapsulated and mechanically fixed, so that the photoelectric conversion part 110 does not need to be specially provided with a device (such as a carrier board, etc.) for fixing and protecting the optical chip 112, the electrical chip 111, etc.

[0082] In one embodiment, see Figure 1 The photoelectric conversion module 100 and the chip 300 are mounted on the same side of the wiring layer structure 200 , and the height of the optical interface portion 120 in the first direction is greater than the height of the photoelectric conversion portion 110 in the first direction.

[0083] It can be understood that when the photoelectric conversion body 110 includes an optical chip 112 and an electrical chip 111 stacked together in the first direction, the height of the photoelectric conversion body 110 in the first direction includes the height of the optical chip 112 in the first direction and the height of the electrical chip 111 in the first direction.

[0084] At this time, the height of the photoelectric conversion unit 110 may be relatively small, so that there may be a small height difference with the chip 300. Therefore, when the chip 300 is plastic-sealed, the thickness of the plastic layer 400 may not be affected.

[0085] Meanwhile, the height of the optical interface portion 120 may be relatively large, thereby facilitating connection with an external light receiving device.

[0086] In one embodiment, see Figure 2 , the photoelectric conversion module 100 and the external circuit module 500 are mounted on the same side of the wiring layer structure 200 .

[0087] At this time, as an example, the photoelectric conversion unit 110 may further include a fixing and protecting device (such as a carrier board, etc.) to mechanically fix and protect the optical chip 112 , the electrical chip 111 , etc.

[0088] The heights of the photoelectric conversion unit 110 and the optical interface unit 120 in the first direction may be the same or different, and may be specifically set according to actual needs.

[0089] In one embodiment, see Figure 2 as well as Figure 3 The packaged device may further include a first frame structure 810 . The first frame structure 810 may be mounted to the wiring layer structure 200 .

[0090] The first frame structure 810 may include a first frame 811 and a socket 812. The material of the first frame 811 may include but is not limited to silicone. The socket 812 may be arranged on the first frame 811. Specifically, a mounting groove may be provided on the surface of the first frame 811, and the socket 812 may be placed in the mounting groove, so as to position the socket 812.

[0091] Optionally, the first frame structure 810 may further include a conductive portion 813. The conductive portion 813 may be located in the first frame 811 and may be disposed at the bottom of the socket 812. The material of the conductive portion 813 may include, but is not limited to, conductive rubber.

[0092] The external circuit module 500 may include an external plug-in 520 , etc. The plug pins of the external plug-in 520 may be inserted into the socket 812 , thereby being conductively connected to the wiring layer structure 200 through the socket 812 and the conductive portion 813 .

[0093] The photoelectric converter 110 is located on a side of the first frame 811 away from the wiring layer structure 200 and is connected to the wiring layer structure 200 through the socket 812. Specifically, the photoelectric converter 110 can also be plugged into the socket 812 similar to the external plug-in 520, thereby being conductively connected to the wiring layer structure 200, thereby facilitating installation.

[0094] It is understood that the first frame structure 810 may be provided with a plurality of sockets 812 . The photoelectric conversion unit 110 and the external plug-in 520 may be plugged into different sockets 812 . Different external plug-ins 520 may also be plugged into different sockets 812 .

[0095] Of course, in other embodiments, the installation method of the photoelectric conversion unit 110 is not limited thereto. For example, the photoelectric conversion unit 110 may also be directly welded to the wiring layer structure 200 .

[0096] In one embodiment, see Figure 3 as well as Figure 4 The packaged device includes a first frame structure 810. The first frame structure 810 includes a first frame 811 and a socket 812 located on the first frame 811. In addition, a positioning hole 40 is provided on the first frame structure 810.

[0097] As an example, the first frame structure 810 may further include an ear piece 814. The ear piece 814 may be disposed around the first frame 811. The positioning hole 40 may be disposed in the ear piece 814.

[0098] Of course, the arrangement of the positioning holes 40 is not limited thereto. For example, when preparing the first frame 811, a positioning portion can be formed at the edge of the first frame 811, and the positioning holes 40 can be formed in the positioning portion.

[0099] Meanwhile, the wiring layer structure 200 further includes a positioning pin 240. The positioning pin 240 is located at a side of the wiring layer structure 200 away from the chip 300 in the first direction.

[0100] The positioning pins 240 are inserted into the positioning holes 40 , so that the first frame structure 810 can be fixed to the wiring layer structure 200 .

[0101] The positioning pins 240 and the positioning holes 40 cooperate with each other, and the two are arranged one by one. A corresponding number of positioning pins 240 and positioning holes 40 can be arranged according to actual needs.

[0102] In this embodiment, a corresponding number of positioning pins 240 are directly provided on the wiring layer structure 200, and the positioning pins 240 are directly plugged and positioned with the positioning holes 40 located on the first frame structure 810. At this time, during the packaging process, the first frame structure 810 can be first positioned to the wiring layer structure 200 to ensure the position accuracy of the socket 812. Afterwards, after the external plug-in 520 is inserted into the socket 812, the external plug-in 520 and the wiring layer structure 200 can be accurately connected and conducted.

[0103] In one embodiment, see Figure 1 or Figure 2 The wiring layer structure 200 includes an interposer structure. The interposer structure includes an interposer substrate 210 , a wiring layer 220 , and a conductive via structure 230 .

[0104] The interposer structure may include but is not limited to a silicon interposer. The interposer substrate 210 may include but is not limited to a silicon wafer.

[0105] The wiring layer 220 is located on one side of the interposer substrate 210. One side of the interposer substrate 210 may be provided with multiple interconnected wiring layers 220, and an insulating dielectric layer may be provided between adjacent wiring layers 220. It should be noted that the figure only simply illustrates a partial structure of the wiring layer 220.

[0106] The conductive via structure 230 penetrates the interposer substrate 210 and connects the wiring layer 220. The material of the conductive via structure 230 may include but is not limited to metal materials such as copper.

[0107] The chip 300 is located on a side of the wiring layer 220 away from the interposer substrate 210 .

[0108] A plurality of chips 300 may be disposed on a side of the wiring layer 220 away from the interposer substrate 210. The chips 300 may be electrically connected to the wiring layer 220. The plurality of chips 300 may be disposed at intervals.

[0109] The external circuit module 500 is located on a side of the interposer structure away from the chip 300 .

[0110] In this embodiment, an interposer structure is used to connect the chip 300 and the external circuit module 500, instead of the traditional wiring layer structure 200 formed by coating a PI film layer and then photolithography copper plating, so as to prevent the structural warping caused by the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer 220 with a high degree of integration. Therefore, connecting the chip 300 and the external circuit module 500 through an interposer structure can effectively improve the circuit integration density. Moreover, when the interposer structure is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the method of this embodiment can effectively improve the performance of the packaged device.

[0111] In one embodiment, see Figure 1 or Figure 2 The interposer structure further includes a protective layer 600. The material of the protective layer 600 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride.

[0112] The protection layer 600 is located on a side of the interposer substrate 210 away from the wiring layer 220 , and the conductive via structure 230 penetrates the protection layer 600 and the interposer substrate 210 .

[0113] The protection layer 600 can prevent metal in the conductive via structure 230 from entering the interposer substrate 210 , thereby preventing leakage between adjacent conductive via structures 230 .

[0114] In one embodiment, see Figure 1 or Figure 2 The interposer structure further includes a first pad 240 and a second pad 250. The material of the first pad 240 and / or the second pad 250 may include but is not limited to copper, etc. The number of the first pad 240 and / or the second pad 250 may be multiple.

[0115] The first pad 240 is located on the surface of the wiring layer 220 and may cover at least a portion of the wiring layer 220 , thereby being electrically connected to the wiring layer 220 .

[0116] The chip 300 is mounted to the first pad 240 .

[0117] When the photoelectric conversion module 100 and the chip 300 are mounted on the same side of the wiring layer structure 200 , the photoelectric conversion unit 110 may be connected to the first pad 240 .

[0118] As an example, the photoelectric conversion body 110 may be die-mounted or hybrid-bonded to the first pad 240 together with the chip 300 .

[0119] The second pad 250 may be located on a side of the interposer substrate 210 away from the wiring layer 220 and cover the conductive via structure 230 to be electrically connected to the conductive via structure 230. The external circuit module 500 is mounted to the second pad 250.

[0120] When the photoelectric conversion module 100 and the external circuit module 500 are mounted on the same side of the wiring layer structure 200 , the photoelectric conversion part 110 may be connected to the second pad 250 .

[0121] As an example, the photoelectric conversion unit 110 may be connected to the second pad 250 through the first frame structure 810. Alternatively, the photoelectric conversion unit 110 may also be directly soldered to the second pad 250.

[0122] In one embodiment, see Figure 1 or Figure 2 The packaging device further includes a plastic packaging layer 400 , a heat dissipation plate 900 , a first fixing hole 20 and a fixing member 740 .

[0123] The plastic encapsulation layer 400 covers the chip 300 and the interposer structure.

[0124] The heat sink 900 is located on a side of the plastic encapsulation layer 400 away from the intermediate layer structure. As an example, the heat sink 900 may be bonded to the plastic encapsulation layer 400 by means of an adhesive 730 (eg, TIM adhesive).

[0125] The first fixing hole 20 passes through the intermediate layer structure and the plastic packaging layer 400 .

[0126] The fixing member 740 passes through the first fixing hole 20 to fix the heat sink 900. The fixing member 740 may include but is not limited to bolts and the like.

[0127] After passing through the first fixing hole 20 , the fixing member 740 may not penetrate the heat dissipation plate 900 , or may penetrate the heat dissipation plate 900 .

[0128] As an example, the packaged device may further include a first frame structure 810 and a second frame structure 820 .

[0129] The external circuit structure may be located at a side of the first frame structure 810 away from the interposer structure, and may include a first frame 811 and a socket 812 .

[0130] The second frame structure 820 may include a plug-in slot, in which an external plug-in 520 may be disposed, etc. The second frame structure 820 is used for mechanical fixing and limiting.

[0131] Optionally, the second frame structure 820 may include a frame plate and a frame hole arranged at an edge of the frame plate. The frame plate may cover at least a portion of the photoelectric conversion unit 110, and the optical interface unit 120 may be located in the frame hole.

[0132] The first frame structure 810 may have a second fixing hole 30. The second frame structure 820 may also have a third fixing hole. The second fixing hole 30 and the third fixing hole may be arranged opposite to the first fixing hole 20. The fixing member 740 may also pass through the third fixing hole and the second fixing hole 30 at the same time, so as to fix the second frame structure 820 and the first frame structure 810 at the same time.

[0133] In this embodiment, the fixing member 740 can make the connection between the heat dissipation plate 900 and the plastic packaging layer 400 more reliable.

[0134] In one embodiment, see Figure 5 , a method for preparing a packaged device is provided, comprising the following steps:

[0135] Step S10, see Fig.15 , providing a first carrier board 200a.

[0136] The first carrier plate 200a is a carrier plate that can be used for support. The material of the first carrier plate 200a can include but is not limited to a glass plate, a metal plate or a plastic plate.

[0137] Step S20, see Fig.15 , an interposer structure is formed on the first carrier 200a, the interposer structure includes an interposer substrate 210, a wiring layer 220 and a conductive through-hole structure 230, the wiring layer 220 is located on a side of the interposer substrate 210 away from the first carrier 200a, the conductive through-hole structure 230 penetrates the interposer substrate 210 along a first direction and connects the wiring layer 220, and the first direction is the thickness direction of the interposer substrate 210.

[0138] The interposer structure may include but is not limited to a silicon interposer. The interposer substrate 210 may include but is not limited to a silicon wafer. The material of the conductive via structure 230 may include but is not limited to metal materials such as copper.

[0139] A plurality of interconnected wiring layers 220 may be provided on one side of the interposer substrate 210, and an insulating dielectric layer may be provided between adjacent wiring layers 220. It should be noted that only a partial structure of the wiring layer 220 is simply illustrated in the figure.

[0140] Step S30, see Fig.16 , a chip 300 is formed on a side of the wiring layer 220 away from the interposer substrate 210 .

[0141] A plurality of chips 300 may be formed on a side of the wiring layer 220 away from the interposer substrate 210. The chips 300 may be electrically connected to the wiring layer 220. The plurality of chips 300 may be arranged at intervals. Different chips 300 may have different functions.

[0142] Step S40, see Fig.17 , forming a plastic encapsulation layer 400 covering the chip 300 and the interposer structure.

[0143] The plastic encapsulation layer 400 can completely cover the chip 300, thereby performing plastic encapsulation protection on the chip 300. The material of the plastic encapsulation layer 400 can include but is not limited to epoxy molding compound (EMC).

[0144] Step S50, see Fig.18 , remove the first carrier board 200a.

[0145] The first carrier 200 a may be removed by laser lift-off or the like, thereby exposing a side of the interposer structure away from the chip 300 .

[0146] Step S70, see Fig. 20 as well as Fig.21 An external circuit module 500 is formed on a side of the interposer structure away from the chip 300 , and the external circuit module 500 is connected to the chip 300 through the interposer structure.

[0147] After removing the first carrier board 200 a , the structure may be turned over to facilitate forming the external circuit module 500 .

[0148] The external circuit module 500 may include a passive device 510 (IPD) and / or an external plug-in 520 , etc. The external plug-in 520 may include a voltage management module 521 and / or a connector 522 , etc.

[0149] In step S30, please refer to Fig.16 , while forming the chip 300 on the side of the wiring layer 220 away from the interposer substrate 210 , a photoelectric conversion module is also formed on the side of the wiring layer 220 away from the interposer substrate 210 .

[0150] and / or, see Figure 2 In step S70 , the external circuit module 500 is formed on the side of the interposer structure away from the chip 300 , and the photoelectric conversion module 100 is also formed on the side of the interposer structure away from the chip 300 .

[0151] The photoelectric conversion module 100 includes a photoelectric conversion unit 110 and an optical interface unit 120. The photoelectric conversion unit 110 is mounted to the wiring layer structure 200. The optical interface unit 120 is connected to the photoelectric conversion unit 110 along the second direction. The optical interface unit 120 protrudes relative to the wiring layer structure 200 in the second direction, and the second direction is perpendicular to the first direction.

[0152] In this embodiment, an interposer structure is first formed on the first carrier 200a. Afterwards, the first carrier 200a can be used as a support for the interposer structure, and the chip 300 is formed on the side of the wiring layer 220 away from the interposer substrate 210, and a plastic encapsulation layer 400 is formed to cover the chip 300. Afterwards, the plastic encapsulation layer 400 can be used as a support, so that the first carrier 200a can be removed, and an external circuit module 500 can be formed on the side of the interposer structure away from the chip 300, so that the preparation of the packaged device can be effectively realized.

[0153] At the same time, the packaged device formed by the method of this embodiment uses an interposer structure to connect the chip 300 and the external circuit module 500, instead of using the traditional wiring layer structure 200 formed by coating the PI film layer and then photolithography copper plating, thereby preventing the structure from warping due to the excessive thermal expansion coefficient of the PI film layer and copper. At the same time, the interposer technology can realize a wiring layer 220 with a high degree of integration. Therefore, connecting the chip 300 and the external circuit module 500 through an interposer structure can effectively improve the circuit integration density. Moreover, when the interposer structure is a silicon interposer, the heat dissipation of silicon is relatively good, thereby effectively improving the heat dissipation of the product. Therefore, the method of this embodiment can effectively improve the performance of the packaged device.

[0154] Meanwhile, the present application forms a photoelectric conversion module while forming the chip 300 and / or the external circuit module 500. The photoelectric conversion module can convert electrical signals into optical signals, thereby effectively improving signal transmission speed and the like.

[0155] Meanwhile, the photoelectric conversion module 100 includes a photoelectric conversion unit 110 and an optical interface unit 120. The photoelectric conversion unit 110 is mounted to the wiring layer structure 200, so as to facilitate electrical connection between the photoelectric conversion unit 110 and the wiring layer structure 200. The optical interface unit 120 protrudes relative to the wiring layer structure in the second direction, so as to facilitate connection with an external light receiving device, so as to transmit optical signals between the external devices.

[0156] In one embodiment, the external circuit module 500 includes an external plug-in 520 .

[0157] After step S50, the method further includes:

[0158] Step S61, see Figure 3, a positioning pin 240 is formed on a side of the interposer structure away from the chip 300 .

[0159] A patterned photoresist with an opening may be formed first, and then the locating pin 240 material may be filled in the opening, and then the photoresist and the locating pin 240 material outside the opening may be removed, thereby forming the locating pin 240 .

[0160] Meanwhile, step S70 includes:

[0161] Step S72, see Figure 3 as well as Fig.21 A first frame structure 810 having a positioning hole 40 is formed on a side of the interposer structure away from the chip, and the positioning pin 240 is inserted into the positioning hole 40 . The first frame structure 810 includes a first frame 811 and a socket 812 located on the first frame 811 .

[0162] Step S73, see Fig.21 An external plug-in 520 is formed on a side of the first frame structure 810 away from the interposer structure, and the external plug-in 520 is connected to the second pad 250 through the socket 812 .

[0163] In this embodiment, the first frame structure 810 can be precisely positioned to the interposer structure by plugging the positioning hole 40 with the positioning pin 240, thereby ensuring the socket position accuracy. Then, after the external plug-in 520 is inserted into the socket 812, it can be precisely connected and conducted with the interposer structure.

[0164] In one embodiment, the external circuit module 500 further includes a passive device 510 .

[0165] See also Fig. 20 , before step S72, the following steps may also be included:

[0166] Step S71 , installing the passive device 510 on a portion of the second pad 250 .

[0167] As a part of the external circuit module 500 , the passive component 510 can be directly mounted on the second pad 250 by means of surface mount mounting.

[0168] Meanwhile, when the first frame structure 810 is formed in step S72 , the first frame structure 810 covering the passive device 510 and another portion of the second pad 250 may be formed.

[0169] In one embodiment, see Fig.19 , before step S70, further comprising:

[0170] Step S62 , forming a first fixing hole 20 penetrating the interposer structure and the plastic encapsulation layer 400 .

[0171] After step S70, please refer to Figure 1 , also includes:

[0172] In step S80 , the fixing member 740 is passed through the first fixing hole 20 to fix the heat sink 900 on the side of the plastic packaging layer 400 away from the intermediate layer structure.

[0173] The fixing member 740 may include but is not limited to a bolt or the like.

[0174] As an example, the heat sink 900 may be first bonded to the side of the plastic layer 400 away from the intermediate layer structure by means of adhesive 730 (such as TIM adhesive), and then the heat sink 900 may be fixed by passing the fixing member 740 through the first fixing hole 20 .

[0175] After passing through the first fixing hole 20 , the fixing member 740 may not penetrate the heat dissipation plate 900 , or may penetrate the heat dissipation plate 900 .

[0176] In this embodiment, the fixing member 740 can make the connection between the heat dissipation plate 900 and the plastic packaging layer 400 more reliable.

[0177] In one embodiment, step S20 includes:

[0178] Step S21, see Figure 6 , providing an intermediate layer initial structure 2001, the intermediate layer initial structure 2001 includes an intermediate layer initial sheet 2101, a wiring layer 220 and a conductive initial structure 2301, the wiring layer 220 is located on one side of the intermediate layer initial sheet 2101, and the conductive initial structure 2301 extends inward from the side of the intermediate layer initial sheet 2101 where the wiring layer 220 is provided.

[0179] In the interposer initial structure 2001 , one end of the conductive initial structure 2301 may be connected to the wiring layer 220 . Meanwhile, the other end of the conductive initial structure 2301 may extend to the inside of the interposer initial sheet 2101 , but does not penetrate the interposer initial sheet 2101 .

[0180] Step S22, see Fig. 9 , a first pad 240 is formed on the wiring layer 220, and a side of the interposer initial structure 2001 where the first pad 240 is formed is bonded to the second carrier 200b.

[0181] The material of the first pad 240 may include, but is not limited to, copper, etc. The first pad 240 may cover at least a portion of the wiring layer 220 , thereby being electrically connected to the wiring layer 220 .

[0182] After the interposer initial structure 2001 is bonded to the second carrier 200 b , the second carrier 200 b may serve as a support for subsequent processes.

[0183] Step S23, see Fig.10 , a side of the interposer initial sheet 2101 away from the wiring layer 220 is etched to expose the conductive initial structure 2301 , and the remaining interposer initial sheet 2101 forms the interposer substrate 210 , and the conductive initial structure 2301 protrudes from the surface of the interposer substrate 210 .

[0184] The interposer initial sheet 2101 may be etched and thinned from a side away from the wiring layer 220 by dry etching process, etc., until the thickness of the remaining interposer initial sheet 2101 (interposer substrate 210 ) is smaller than the height of the conductive initial structure 2301 .

[0185] Step S24, see Fig.11 , forming a protection material layer 6001 covering the conductive initial structure 2301 and the interposer substrate 210 .

[0186] The protective material layer 6001 may be formed by a deposition process (such as chemical vapor deposition or atomic layer deposition, etc.). The material of the protective material layer 6001 may include but is not limited to silicon oxide, silicon nitride or silicon oxynitride, etc.

[0187] Step S25, see Fig.12 The conductive initial structure 2301 and the protective material layer 6001 are ground to flatten the protruding portion of the conductive initial structure 2301 , and the remaining conductive initial structure 2301 forms a conductive through-hole structure 230 , and the remaining protective material layer 6001 forms a protective layer 600 .

[0188] Before grinding, the surface of the interposer substrate 210 is covered by the protective material layer 6001. Therefore, during the grinding process, the protective material layer 6001 can prevent the metal of the conductive initial structure 2301 from entering the interposer substrate 210, thereby preventing leakage between adjacent conductive via structures 230.

[0189] Step S26, see Fig.14 , forming a second pad 250 covering the conductive via structure 230 and the protection layer 600 to form an interposer structure, and bonding a side of the interposer structure where the second pad 250 is formed to the first carrier 200a.

[0190] The material of the second pad 250 may include but is not limited to copper, etc. After the second pad 250 is formed, the preparation of the interposer structure may be completed.

[0191] After the interposer initial structure 2001 is bonded to the first carrier 200a, the first carrier 200a and the second carrier 200b may be disposed opposite to each other.

[0192] Step S27, see Fig.15 , remove the second carrier board 200b.

[0193] The second carrier board 200 b may be removed by laser lift-off or the like.

[0194] After the second carrier 200 b is removed, the first carrier 200 a can be used as a support for subsequent processes.

[0195] In this embodiment, in the interposer initial structure 2001 provided at the beginning, the conductive initial structure 2301 does not penetrate the interposer initial sheet 2101. In the subsequent process, the interposer initial sheet 2101 is formed into the interposer substrate 210 through etching, grinding and other processes, thereby effectively reducing the thickness of the interposer substrate, thereby reducing the thickness of the packaged device, and thus facilitating the improvement of the package integration. At the same time, in the process of forming the conductive initial structure 2301, it is also unnecessary to form a through hole penetrating the interposer initial sheet 2101, thereby reducing the process difficulty of the conductive initial structure 2301.

[0196] Furthermore, before the conductive initial structure 2301 and the protective material layer 6001 are ground, a protective material layer 6001 is formed to cover the conductive initial structure 2301 and the interposer substrate 210. Therefore, during the grinding process, the protective material layer 6001 can prevent the metal of the conductive initial structure 2301 from entering the interposer substrate 210, thereby preventing leakage between adjacent conductive via structures 230.

[0197] In one embodiment, step S22 includes:

[0198] Step S221, see Figure 7 , a first pad 240 is formed on the wiring layer 220 .

[0199] First, a first patterned dielectric layer 260 may be formed by a photolithography process, etc., and the first patterned dielectric layer has a first opening. The material of the first patterned dielectric layer 260 may include, but is not limited to, PI. Then, a first patterned photoresist layer may be formed on the first dielectric patterned layer 260. The first patterned photoresist layer has a second opening, and the second opening is arranged opposite to the first opening. Then, a first pad 240 may be formed in the second opening and the first opening by an electroplating process, etc., and the first patterned photoresist layer is removed.

[0200] At this time, as an example, step S30 may include: step S31, mounting the chip 300 on the first pad 240. Or, as an example, step S30 may include: step S32, hybrid bonding the chip 300 to the first pad 240.

[0201] Step S222, see Figure 8 , the structure after the first pad 240 is formed is ring-cut to form a ring-cut space 10.

[0202] During the ring cutting, a portion of the thickness of the edge of the initial sheet 2101 of the intermediate layer can be cut off.

[0203] As an example, the depth of the cutout of the interposer initial sheet 2101 may be greater than the height of the conductive initial structure 2301 .

[0204] Step S223, see Fig. 9 A first adhesive layer 710 is formed on the annular space 10 and the side of the initial structure 2001 of the interposer where the first pad 240 is formed.

[0205] Step S224, see Fig. 9 , the second carrier board 200 b is bonded by the first adhesive layer 710 .

[0206] Thereafter, the first adhesive layer 710 may be cured.

[0207] The formation of the annular space 10 facilitates the initial structure of the interposer 2001 to be more firmly adhered to the second carrier board 200 b .

[0208] Also, see Fig.10 In step S23, the side of the initial interposer sheet 2101 away from the wiring layer 220 is etched to expose the initial conductive structure 2301, and the first adhesive layer 710 located in the annular space 10 is etched away. At this time, the annular space 10 can be hollowed out again.

[0209] When the cutting depth of the initial sheet 2101 of the intermediate layer in step S222 can be greater than the height of the conductive initial structure 2301, it can be ensured that step S23 can etch the initial sheet 2101 of the intermediate layer to expose the first adhesive layer 710 in the annular space 10, and then the first adhesive layer 710 in the annular space 10 can be effectively etched and removed.

[0210] Step S26 includes:

[0211] Step S261, see Fig.13 , forming a second pad 250 covering the conductive via structure 230 and the protection layer 600 to form an interposer structure.

[0212] The second pad 250 may be formed in a similar manner to the first pad 240 .

[0213] First, a second patterned dielectric layer 270 may be formed by a photolithography process, etc., and the second patterned dielectric layer has a third opening. The material of the second patterned dielectric layer 270 may include, but is not limited to, PI. Then, a second patterned photoresist layer may be formed on the second patterned dielectric layer 270. The second patterned photoresist layer has a fourth opening, and the fourth opening is arranged opposite to the third opening. Then, a second pad 250 may be formed in the fourth opening and the third opening by an electroplating process, etc., and the second patterned photoresist layer is removed.

[0214] When step S61 is further included after step S50 , the height of the positioning pin 240 formed in step S61 may be greater than the height of the second pad 250 .

[0215] Step S262, see Fig.14 A second adhesive layer 720 is formed on the annular space 10 and on one side of the interposer structure where the second pad 250 is formed.

[0216] As an example, before step S262 , the following step may further include: forming a positioning pin 240 covering the protection layer 600 .

[0217] At this time, after step S262, a thicker second adhesive layer 720 may be formed to cover both the positioning pin 240 and the second pad. And step S61 may not be included after step S50.

[0218] Step S263, see Fig.14 , the first carrier board 200 a is bonded via the second adhesive layer 720 .

[0219] Thereafter, the second adhesive layer 720 may be cured.

[0220] At this time, the annular space 10 facilitates the initial structure of the intermediate layer 2001 to be more firmly adhered to the first carrier board 200a.

[0221] Then, the structure in the corresponding area of ​​the annular space 10 can be completely removed. Then, in step S27, the second carrier plate 200b is removed. In step S27, see Fig.15 After removing the second carrier board 200 b , the first adhesive layer 710 may be removed to expose the first pad 240 .

[0222] Meanwhile, in the subsequent step S50 , after removing the first carrier board, the second adhesive layer 720 may be removed to expose the second pad 250 .

[0223] In this embodiment, before bonding the second carrier 200b, the annular cutting space 10 is first formed, so that the initial structure of the interposer 2001 can be more firmly bonded to the second carrier 200b through the annular cutting space 10. At the same time, when the initial interposer sheet 2101 is etched and thinned to form the interposer substrate 210, the first adhesive layer 710 of the annular cutting space 10 is removed, so that the annular cutting space 10 is hollowed out again, so that the initial structure of the interposer 2001 can be more firmly bonded to the first carrier 200a through the annular cutting space 10 again.

[0224] Of course, in other embodiments, circumcision may not be performed, and the present application has no limitation to this.

[0225] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0226] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0227] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0228] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A packaging device, characterized in that: include: Wiring layer structure; A chip is located at one side of the wiring layer structure in a first direction, where the first direction is a thickness direction of the wiring layer structure; An external circuit module, located on a side of the wiring layer structure away from the chip in a first direction; A photoelectric conversion module is installed on the same side of the wiring layer structure as the chip and / or the external circuit module, and includes a photoelectric conversion part and an optical interface part; the photoelectric conversion part is installed to the wiring layer structure; the optical interface part is connected to the photoelectric conversion part along a second direction, and the optical interface part protrudes relative to the wiring layer structure in the second direction, and the second direction is perpendicular to the first direction.

2. The packaged device according to claim 1, characterized in that: The photoelectric conversion module and the chip are mounted on the same side of the wiring layer structure; The packaging device further includes a plastic encapsulation layer, which covers the chip, the wiring layer structure and at least a portion of the photoelectric conversion unit.

3. The packaged device according to claim 2, characterized in that: A height of the optical interface portion in the first direction is greater than a height of the photoelectric conversion portion in the first direction.

4. The packaged device according to claim 1, characterized in that: The photoelectric conversion module and the external circuit module are installed on the same side of the wiring layer structure; The packaging device also includes a first frame structure, which includes a first frame and a socket located on the first frame, the photoelectric conversion part is located on a side of the first frame away from the wiring layer structure, and is connected to the wiring layer structure through the socket; or, the photoelectric conversion part is welded to the wiring layer structure.

5. The packaged device according to claim 1, characterized in that: The photoelectric conversion unit includes an electric chip and an optical chip. The electric chip is mounted on the wiring layer structure. The optical chip is stacked on the electric chip along a first direction. The optical interface unit is at least connected to the optical chip.

6. The packaged device according to claim 1, characterized in that: The packaging device comprises a first frame structure, the first frame structure comprises a first frame and a socket located on the first frame, and a positioning hole is provided on the first frame structure; The wiring layer structure further includes a positioning pin, which is located on a side of the wiring layer structure away from the chip in a first direction, and the positioning pin is inserted into the positioning hole.

7. The packaged device according to claim 6, characterized in that: The first frame structure further includes an ear piece, the ear piece is connected to the first frame, and the positioning hole is located in the ear piece.

8. The packaged device according to claim 1, characterized in that: The wiring layer structure includes an interposer structure, the interposer structure includes an interposer substrate, a wiring layer and a conductive through-hole structure, the wiring layer is located on one side of the interposer substrate, and the conductive through-hole structure penetrates the interposer substrate to connect the wiring layer; The chip is located on a side of the wiring layer away from the interposer substrate; The intermediate layer structure further includes: A first pad is located on the surface of the wiring layer, and the chip is mounted on the first pad; a second pad, located on a side of the interposer substrate away from the wiring layer and covering the conductive through-hole structure, the external circuit module being mounted to the second pad; The photoelectric conversion unit is connected to the first pad and / or the second pad; The packaged device further comprises: A plastic packaging layer, covering the chip and the interposer structure; A heat sink is located on a side of the plastic packaging layer away from the intermediate layer structure; A first fixing hole, penetrating the intermediate layer structure and the plastic packaging layer; A fixing member passes through the first fixing hole to fix the heat sink.

9. A method for preparing a packaged device, characterized in that: include: providing a first carrier board; forming an interposer structure on the first carrier, the interposer structure comprising an interposer substrate, a wiring layer and a conductive through-hole structure, the wiring layer being located on a side of the interposer substrate away from the first carrier, the conductive through-hole structure penetrating the interposer substrate along a first direction to connect the wiring layer, the first direction being a thickness direction of the interposer substrate; forming a chip on a side of the wiring layer away from the interposer substrate; forming a plastic packaging layer covering the chip and the interposer structure; removing the first carrier plate; forming an external circuit module on a side of the interposer structure away from the chip, wherein the external circuit module is connected to the chip through the interposer structure; Wherein, while a chip is formed on a side of the wiring layer away from the interposer substrate, a photoelectric conversion module is also formed on a side of the wiring layer away from the interposer substrate; and / or, while an external circuit module is formed on a side of the interposer structure away from the chip, a photoelectric conversion module is also formed on a side of the interposer structure away from the chip; the photoelectric conversion module includes a photoelectric conversion part and an optical interface part; the photoelectric conversion part is installed to the wiring layer structure; the optical interface part is connected to the photoelectric conversion part along a second direction, and the optical interface part protrudes relative to the wiring layer structure in the second direction, and the second direction is perpendicular to the first direction.

10. The method for preparing a packaged device according to claim 9, characterized in that: The external circuit module includes an external plug-in, and after removing the first carrier board, further includes: forming a positioning pin on a side of the interposer structure away from the chip; The forming of an external circuit module on a side of the interposer structure away from the chip comprises: A first frame structure having a positioning hole is formed on a side of the interposer structure away from the chip, and the positioning pin is inserted into the positioning hole, wherein the first frame structure includes a first frame and a socket located on the first frame; An external plug-in is formed on a side of the first frame structure away from the interposer structure, and the external plug-in is connected to the second pad through the socket.

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