Liquid crystal display circuit, display panel, and display device

Abstract

The application discloses a liquid crystal display circuit, a display panel and a display device, and relates to the technical field of display, which comprises a pixel array, the pixel array comprises column pixel units in columns as units and row pixel units in rows as units; a plurality of data signal lines, each data signal line provides a data signal to a corresponding column pixel unit, and adjacent data signal lines provide data signals with opposite polarities; a plurality of first gate lines, each first gate line provides a first gate driving voltage to a pixel point in a corresponding row pixel unit to charge; a plurality of second gate lines, each second gate line provides a second gate driving voltage to a pixel point in a corresponding row pixel unit to charge; wherein the first data signal and the second data signal are opposite in polarity, and the application aims to improve the display quality of LCD products applied to the liquid crystal display circuit.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a liquid crystal display circuit, a display panel, and a display device. Background Technology

[0002] With the continuous development of display technology, LCD (Liquid Crystal Display) products are widely used in mobile phones, automobiles, central control systems, smart homes, smart offices, watches, smart bracelets, and many other fields. Users are also placing higher demands on the display quality of LCD products.

[0003] Existing display technologies, such as TFT (Thin Film Transistor) arrays in liquid crystal displays, typically use a uniform gate voltage (Vgh for high voltage and Vgl for low voltage) to control the switching state of pixels. However, because the IV characteristic of TFTs (i.e., the relationship between drain current and gate-source voltage) is significantly affected by the gate-source voltage (Vgs), pixels with different polarities will exhibit different leakage current characteristics under the same gate voltage. Specifically, when pixel polarity is reversed, its Vgs value changes accordingly, causing the leakage current to change as well. This change in leakage current is the root cause of display quality problems such as image retention, crosstalk, and flicker, seriously affecting the display quality of LCD products.

[0004] Therefore, improving the display quality of LCD products is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide a liquid crystal display circuit, a display panel, and a display device, which aim to improve the display quality of LCD products.

[0006] To achieve the above objectives, this application provides a liquid crystal display circuit, the liquid crystal display circuit comprising:

[0007] A pixel array, comprising column pixel units and row pixel units.

[0008] Multiple data signal lines, each of which provides a data signal to the corresponding column pixel unit, and the data signals provided by adjacent data signal lines have opposite polarities;

[0009] Multiple first gate lines, each of which provides a first gate driving voltage to the corresponding row pixel unit that has the first data signal connected to it for charging;

[0010] Multiple second gate lines, each second gate line providing a second gate drive voltage to the corresponding row pixel unit that receives the second data signal for charging; wherein,

[0011] The first data signal has the opposite polarity to the second data signal.

[0012] In one embodiment, the data signal provided by each of the data signal lines to the corresponding column pixel unit in the Nth frame has the opposite polarity to the data signal provided to the corresponding column pixel unit in the N+1th frame, where N is a natural number greater than zero.

[0013] In one embodiment, each of the data signal lines is electrically connected to the corresponding column pixel unit;

[0014] In each of the column pixel units, the polarity of each pixel is the same as the polarity of the data signal provided by the corresponding data signal line.

[0015] In one embodiment, the pixel that receives the first data signal constitutes a first polarity pixel, and the pixel that receives the second data signal constitutes a second polarity pixel, wherein the first polarity pixel and the second polarity pixel are opposite.

[0016] In each row pixel unit, a first gate line and a second gate line are disposed opposite to each other on both sides of the pixels arranged in a row, and a second polarity pixel is disposed between adjacent first polarity pixels. The first gate line is electrically connected to each first polarity pixel, and the second gate line is electrically connected to each second polarity pixel.

[0017] In one embodiment, in each row pixel unit, when the first gate line provides the first gate driving voltage to each first polarity pixel for charging, the second gate line provides the second gate driving voltage to each second polarity pixel for charging.

[0018] In one embodiment, if the first polarity pixel is a positive polarity pixel, the gate line voltage input to the first gate line connected to the first polarity pixel in the off state of the Nth frame is a first level. After the first polarity pixel is turned on under the drive of the first gate driving voltage to complete the positive charging of the pixel, the first level is switched to a second level until the polarity of the data signal provided by the data signal line electrically connected to the first polarity pixel switches from positive to negative polarity. Then, the second level is switched back to the first level, which serves as the gate line voltage input to the first gate line connected to the first polarity pixel in the off state of the N+1th frame; or...

[0019] If the second polarity pixel is a positive polarity pixel, the gate line voltage input to the second gate line connected to the second polarity pixel in the off state of the Nth frame is at the first level. After the second polarity pixel is turned on under the drive of the second gate driving voltage to complete the positive charging of the pixel, the first level is switched to the second level. This continues until the polarity of the data signal provided by the data signal line electrically connected to the second polarity pixel switches from positive to negative polarity. Then, the second level is switched back to the first level, which serves as the gate line voltage input to the first gate line connected to the second polarity pixel in the off state of the N+1th frame.

[0020] The first level is lower than the second level.

[0021] In one embodiment, if the first polarity pixel is a negative polarity pixel, the gate line voltage input to the first gate line of the first polarity pixel in the off state of the Nth frame is a first level. After the first polarity pixel is turned on under the drive of the first gate driving voltage to complete the negative charging of the pixel, the gate line voltage input to the first polarity pixel in the Nth frame when it switches from the on state to the off state remains unchanged at the first level. When the polarity of the data signal provided by the data signal line electrically connected to the first polarity pixel switches from negative to positive, the first level is used as the gate line voltage input to the first gate line of the first polarity pixel in the off state of the N+1th frame; or...

[0022] If the second polarity pixel is a negative polarity pixel, the gate line voltage input to the second gate line of the second polarity pixel in the cutoff state in the Nth frame is the first level. After the second polarity pixel is turned on under the drive of the second gate driving voltage to complete the negative charging of the pixel, the gate line voltage input to the second polarity pixel in the Nth frame when it switches from the on state to the off state remains unchanged at the first level. When the polarity of the data signal provided by the data signal line electrically connected to the second polarity pixel switches from negative polarity to positive polarity, the first level is used as the gate line voltage input to the first gate line of the second polarity pixel in the N+1th frame when it is in the cutoff state.

[0023] In one embodiment, the first polar pixel includes a first pixel electrode and a first thin-film transistor. The first pass terminal of the first thin-film transistor is electrically connected to the first pixel electrode, the gate terminal of the first thin-film transistor is electrically connected to the first gate line, and the second pass terminal of the first thin-film transistor constitutes the data line identifier terminal of the first polar pixel and is electrically connected to the corresponding data signal line.

[0024] The second polarity pixel includes a second pixel electrode and a second thin-film transistor. A first terminal of the second thin-film transistor is electrically connected to the second pixel electrode, and a gate terminal of the second thin-film transistor is electrically connected to the second gate line. A second terminal of the second thin-film transistor constitutes a data line identifier terminal of the second polarity pixel and is electrically connected to the corresponding data signal line.

[0025] The first pixel electrode is opposite to the second pixel electrode, and the first thin-film transistor is the same as the second thin-film transistor.

[0026] In addition, to achieve the above objectives, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the liquid crystal display circuit described in any of the above claims.

[0027] In addition, to achieve the above objectives, this application also provides a display device, which includes the display panel described above.

[0028] This application provides a liquid crystal display circuit, a display panel, and a display device, which solves the display quality problems such as image retention, crosstalk, and flicker caused by pixel polarity reversal in the prior art, and significantly improves the display quality of LCD products applied to liquid crystal display circuits. Specifically, this application divides the pixel array into column pixel units by column and row pixel units by row, and introduces an alternating polarity data signal line layout, where adjacent data signal lines provide data signals of opposite polarity to their respective row pixel units. Next, a first gate line provided by this application charges the pixels connected to the first data signal with a first gate drive voltage, and a second gate line provided by this application charges the pixels connected to the second data signal (opposite to the first data signal) with a second gate drive voltage. This ensures that all pixels connected to the first data signal in each row pixel unit are charged by the first gate drive voltage provided by the first gate line, and all pixels connected to the second data signal (opposite to the first data signal) are charged by the second gate drive voltage provided by the second gate line. This allows the gate-source voltage difference (Vgs) of the pixels in each row pixel unit to remain at a relatively stable level under different polarity conditions, effectively suppressing the fluctuations in leakage current caused by polarity reversal, avoiding image retention, crosstalk, flicker, and other poor display phenomena, and significantly improving the display quality of LCD products. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0030] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of the IV characteristics of TFT involved in LCD display technology;

[0032] Figure 2 This is a structural block diagram of the first embodiment of the liquid crystal display circuit of this application;

[0033] Figure 3 This is a driving waveform diagram related to an embodiment of the liquid crystal display circuit of this application;

[0034] Figure 4 This is a circuit diagram of an embodiment of the liquid crystal display circuit of this application;

[0035] Figure 5 This is a schematic diagram illustrating the switching of positive and negative frame pixel working states according to an embodiment of the liquid crystal display circuit of this application.

[0036] Explanation of icon numbers:

[0037] 10. Pixel array; L1, column pixel unit; H1, row pixel unit; S1, data signal line; Gna, first gate line; Gnb, second gate line; T1, first thin film transistor; T2, second thin film transistor; VgL, first level; VL, second level.

[0038] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0040] It should be noted that if the embodiments of this application involve directional indicators (such as up, down, left, right, front, back, etc.), the directional indicators are only used to explain the relative positional relationship and movement of the components in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicators will also change accordingly.

[0041] Furthermore, if the embodiments of this application involve descriptions such as "first" or "second," these descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" or "second" may explicitly or implicitly include at least one of those features. Additionally, the technical solutions of various embodiments can be combined with each other, but this must be based on the ability of those skilled in the art to implement them. If the combination of technical solutions is contradictory or impossible to implement, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application.

[0043] Automotive display technology has higher requirements for display quality than conventional display technology, and is particularly sensitive to issues such as image retention, crosstalk, and flicker. In conventional designs, the gate voltages of all pixels are Vgh and Vgl, respectively. However, due to the polarity reversal phenomenon of pixels, using a uniform gate voltage for all pixels is not the optimal choice.

[0044] As is well known, the IV characteristic of a TFT (Thin Film Transistor) is determined by the gate-source voltage Vgs, which can be understood as the voltage difference between the gate voltage and the source voltage of the TFT. Figure 1 As shown, Figure 1 The IV curve of a TFT device, Figure 1 The Id value set on the vertical axis refers to the leakage current. Figure 1 The Vgs value on the horizontal axis refers to the gate-source voltage. Figure 1 It can be seen that the leakage current Id of a TFT device changes with the gate-source voltage Vgs. For example, for a negative pixel, the gate-source voltage Vgs is located at point a; while for a positive pixel, the gate-source voltage Vgs will shift to the left to point b, thus causing a change in leakage current. This change in leakage current can cause display quality problems such as image retention, crosstalk, and flicker.

[0045] To address the display quality issues such as image retention, crosstalk, and flicker caused by pixel polarity reversal in existing LCD display technologies, this application provides a liquid crystal display circuit, a display panel, and a display device.

[0046] This application provides a liquid crystal display circuit, referring to... Figure 2 As shown, Figure 2 This is a structural block diagram of the first embodiment of the liquid crystal display circuit of this application. The liquid crystal display circuit includes:

[0047] A pixel array 10 includes column pixel units L1 (column-based) and row pixel units H1 (row-based); multiple data signal lines S1, each S1 providing a data signal to a corresponding column pixel unit L1, with adjacent data signal lines S1 providing data signals of opposite polarities; multiple first gate lines Gna, each first gate line Gna providing a first gate driving voltage to a pixel in a corresponding row pixel unit H1 that receives the first data signal for charging; and multiple second gate lines Gnb, each second gate line Gnb providing a second gate driving voltage to a pixel in a corresponding row pixel unit H1 that receives the second data signal for charging; wherein the first data signal and the second data signal have opposite polarities.

[0048] In this example, refer to Figure 1 As shown, the pixel array 10 consists of a large number of pixels arranged in a two-dimensional grid to form rows and columns. Specifically, this application divides the pixel array 10 into column pixel units L1, so that each data signal line S1 provides a data signal to the corresponding column pixel unit L1. Furthermore, this application sets the data signals provided by adjacent data signal lines S1 to have opposite polarities, which can effectively reduce the charge accumulation and DC offset problems of each pixel in the pixel array 10, so as to balance the charge distribution of the pixels in the pixel array 10, reduce the afterimage or image retention phenomenon caused by displaying the same image for a long time, and thus extend the service life of LCD products used in liquid crystal display circuits. Next, this application introduces a first gate line Gna and a second gate line Gnb to control pixels that receive data signals of different polarities. That is, in each row of pixel units H1, each pixel receiving the first data signal is connected to the first gate line Gna, and each pixel receiving the second data signal opposite to the first data signal is connected to the second gate line Gnb. This allows for different gate voltages to be provided according to the polarity of each pixel in the row of pixel units H1. Specifically, the first gate line Gna provides a first gate driving voltage to charge the pixels receiving the first data signal, and the second gate line Gnb provides a second gate driving voltage to charge the pixels receiving the second data signal opposite to the first data signal. This ensures that the gate-source voltage difference (Vgs) of the pixels in each row of pixel units H1 under different polarity conditions can be maintained at a relatively stable level, thereby effectively suppressing the fluctuation of leakage current caused by polarity reversal, avoiding the occurrence of poor display phenomena such as image retention, crosstalk, and flicker, and significantly improving the display quality of LCD products.

[0049] It should be noted that, referring to Figure 1 The first gate line Gna-1 and the second gate line Gnb-1 correspond to the row pixel unit H1-1, the first gate line Gna-2 and the second gate line Gnb-2 correspond to the row pixel unit H1-2, the first gate line Gna-3 and the second gate line Gnb-3 correspond to the row pixel unit H1-3, the first gate line Gna-4 and the second gate line Gnb-4 correspond to the row pixel unit H1-4, the first gate line Gna-5 and the second gate line Gnb-5 correspond to the row pixel unit H1-5, and the first gate line Gna-6 and the second gate line Gnb-6 correspond to the row pixel unit H1-6.

[0050] Data signal line S1-1 corresponds to column pixel unit L1-1, data signal line S1-2 corresponds to column pixel unit L1-2, data signal line S1-3 corresponds to column pixel unit L1-3, data signal line S1-4 corresponds to column pixel unit L1-4, data signal line S1-5 corresponds to column pixel unit L1-5, and data signal line S1-6 corresponds to column pixel unit L1-6. Moreover, the polarity of each pixel in the same column unit is the same as the polarity of the data signal provided by the corresponding data signal line S1.

[0051] The pixel array 10 set in this application can be a regular column-reversed pixel array or a column-reversed Z-arranged pixel array. The above is only one feasible implementation method of this application, and this application does not make any restrictions here.

[0052] In summary, this application provides a liquid crystal display circuit, a display panel, and a display device, solving display quality problems such as image retention, crosstalk, and flicker caused by pixel polarity reversal in the prior art, and significantly improving the display quality of LCD products applied to liquid crystal display circuits. Specifically, this application divides the pixel array 10 into column pixel units L1 by columns and row pixel units H1 by rows, and introduces an alternating polarity data signal line S1 layout, that is, adjacent data signal lines S1 provide data signals of opposite polarity to their respective row pixel units H1; next, a first gate driving voltage is provided to the pixels connected to the first data signal through the first gate line Gna provided in this application for charging, and a second gate driving voltage is provided to the pixels connected to the second data signal opposite to the first data signal through the second gate line Gnb provided in this application for charging, ensuring that... In each row of pixel units H1, all pixels connected to the first data signal are charged by the first gate driving voltage provided by the first gate line Gna, and all pixels with the second data signal opposite to the first data signal are charged by the second gate driving voltage provided by the second gate line Gnb. This allows the gate-source voltage difference (Vgs) of the pixels in each row of pixel units H1 to be maintained at a relatively stable level under different polarity conditions, thereby effectively suppressing the fluctuation of leakage current caused by polarity reversal, avoiding the occurrence of poor display phenomena such as image retention, crosstalk, and flicker, and significantly improving the display quality of LCD products.

[0053] Furthermore, in some feasible embodiments, the data signal provided by each data signal line S1 to the corresponding column pixel unit L1 in the Nth frame has the opposite polarity to the data signal provided to the corresponding column pixel unit L1 in the N+1th frame, where N is a natural number greater than zero.

[0054] In this embodiment, each data signal line S1 provides data signals of opposite polarity to its corresponding column pixel unit L1 between consecutive frames (such as the Nth frame and the N+1th frame, where N is a natural number greater than zero). In other words, this application sets each data signal line S1 to output data signals of opposite polarity between different frames, which can not only effectively balance the charge distribution of pixels between different frames, but also adjust the gate source voltage value of pixels to a certain extent, so that the gate source voltage difference of positive polarity pixels and negative polarity pixels tends to be the same during the operation of different frames, thereby improving the problem of different leakage currents and greatly improving the display quality of LCD products in automotive displays and other application scenarios.

[0055] It should be noted that a positive polarity pixel can be understood as a pixel in pixel array 10 whose data signal provided by data signal line S1 has a positive polarity, and a negative polarity pixel can be understood as a pixel in pixel array 10 whose data signal provided by data signal line S1 has a negative polarity. For example, refer to... Figure 2 In this application, the polarity of the data signals provided by data signal lines S1-1, S1-3, and S1-5 is set to positive, meaning that the pixels in column pixel units L1-1, L1-3, and L1-5 are all positive polarity pixels. In addition, the polarity of the data signals provided by data signal lines S1-2, S1-4, and S1-6 is set to negative, meaning that the pixels in column pixel units L1-2, L1-4, and L1-6 are all negative polarity pixels.

[0056] Furthermore, in some other feasible embodiments, each of the data signal lines S1 is electrically connected to the corresponding column pixel unit L1; in each column pixel unit L1, the polarity of each pixel is the same as the polarity of the data signal provided by the corresponding data signal line S1.

[0057] In this embodiment, each data signal line S1 is electrically connected to the corresponding column pixel unit L1. In each column pixel unit L1, the polarity of each pixel is the same as the polarity of the data signal provided by the corresponding data signal line S1. This ensures that the polarity of each pixel in each column pixel unit L1 is the same as the polarity of the data signal provided by the corresponding data signal line S1, thus ensuring the consistency between the pixel polarity and the data signal. This helps to improve the accuracy and stability of LCD products used in liquid crystal display circuits, and reduces display errors that may be caused by inconsistent polarity of pixels in the same column pixel unit L1, thereby effectively improving display quality.

[0058] Furthermore, in some other feasible embodiments, reference is made to... Figure 2 The pixels that receive the first data signal constitute a first polarity pixel, and the pixels that receive the second data signal constitute a second polarity pixel. The first polarity pixel is opposite to the second polarity pixel. In each row pixel unit H1, a first gate line Gna and a second gate line Gnb are disposed opposite to each other on both sides of the pixels arranged in a row. A second polarity pixel is disposed between adjacent first polarity pixels. The first gate line Gna is electrically connected to each first polarity pixel, and the second gate line Gnb is electrically connected to each second polarity pixel.

[0059] In this embodiment, the pixel that receives the first data signal is defined as the first polarity pixel, and the pixel that receives the second data signal constitutes the second polarity pixel. The polarities of the two are opposite, that is, the first polarity pixel and the second polarity pixel are opposite, which effectively realizes the alternating arrangement of pixel polarities. For example, each row of pixel units H1 is provided with a first gate line Gna and a second gate line Gnb, and the first gate line Gna and the second gate line Gnb are positioned opposite each other on both sides of the pixels arranged in rows. This ensures that all first polarity pixels in the same row are directly electrically connected to the first gate line Gna, and all second polarity pixels are directly electrically connected to the second gate line Gnb. This ensures independent control of pixels with different polarities and achieves precise gate voltage control of pixels with opposite polarities (i.e., first polarity pixels and second polarity pixels). This allows the gate-source voltage difference (Vgs) of the pixels in each row of pixel units H1 to be maintained at a relatively stable level under different polarity conditions. This effectively suppresses the fluctuation of leakage current caused by polarity reversal, avoids the occurrence of poor display phenomena such as image retention, crosstalk, and flicker, and significantly improves the display quality of LCD products. Furthermore, this application also provides a second polarity pixel between adjacent first polarity pixels, so that opposite polarity pixels are distributed alternately, which helps to balance the electric field distribution in the display screen, reduce display problems caused by uneven electric field, and thus effectively improve the display quality of LCD products used in liquid crystal display circuits.

[0060] Furthermore, in some feasible embodiments, reference is made to Figure 2 as well as Figure 3 , Figure 3 This is a driving waveform diagram related to an embodiment of the liquid crystal display circuit of this application. In each row pixel unit H1, when the first gate line Gna provides the first gate driving voltage to each first polarity pixel for charging, the second gate line Gnb provides the second gate driving voltage to each second polarity pixel for charging.

[0061] In this embodiment, a timing-synchronized gate voltage control strategy is cleverly implemented in each row of pixel units H1. Specifically, when the first gate line Gna provides a first gate drive voltage to all first polarity pixels in the row of pixel units H1 for charging, the second gate line Gnb synchronously provides a second gate drive voltage to all second polarity pixels in the same row of pixel units H1 for charging. This ensures that pixels with opposite polarities (i.e., first polarity pixels and second polarity pixels) are synchronously excited by the corresponding gate drive voltage within the same time window, effectively avoiding display problems caused by the asynchrony of the first and second gate drive voltages. Furthermore, by using different gate voltages output by different gate lines, the gate-source voltage difference between pixels of different polarities in the row of pixel units H1 is eliminated, thereby significantly improving the display quality of LCD products applied to liquid crystal display circuits.

[0062] In a specific embodiment, Figure 3 In the text, Gna represents the first gate line Gna. Figure 2 In this context, DO represents the data signal line S1, where the output data signal has a positive polarity. Figure 2 In this context, Gnb represents the second gate line Gnb. Figure 2 In this context, DE represents the data signal line S1, where the polarity of the output data signal is negative. For example, taking the driving of pixel array 10 in the Nth frame as an example, when the positive polarity pixel in the row pixel unit H1 is positively charged under the first gate driving voltage (Gna-Vgh) output by the first gate line Gna, the negative polarity pixel in the row pixel unit H1 is synchronously negatively charged under the second gate driving voltage (Gnb-Vgh) output by the second gate line Gnb. This makes the first gate driving voltage (Gna-Vgh) transmitted from the first gate line Gna to the positive polarity pixel in the row pixel unit H1 and the second gate driving voltage (Gnb-Vgh) transmitted from the second gate line Gnb to the negative polarity pixel in the row pixel unit H1 synchronized in timing. Moreover, the magnitudes of the first gate driving voltage (Gna-Vgh) output by the first gate line Gna and the second gate driving voltage (Gnb-Vgh) output by the second gate line Gnb are different, thereby eliminating the gate-source voltage difference between pixels of different polarities in the row pixel unit H1, and thus significantly improving the display quality of LCD products applied to liquid crystal display circuits.

[0063] Furthermore, in some other feasible embodiments, reference is made to... Figures 2 to 3If the first polarity pixel is a positive polarity pixel, the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state of the Nth frame is a first level VgL. After the first polarity pixel is turned on under the drive of the first gate driving voltage to complete the positive charging of the pixel, the first level VgL is switched to a second level VL until the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel changes from positive to negative polarity. Then, the second level VL is switched back to the first level VgL, which serves as the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state of the N+1th frame; or...

[0064] If the second polarity pixel is a positive polarity pixel, the gate line voltage input to the second gate line Gnb, which is connected to the second polarity pixel in the off state in the Nth frame, is the first level VgL. After the second polarity pixel is turned on under the drive of the second gate driving voltage to complete the positive charging of the pixel, the first level VgL is switched to the second level VL. This continues until the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel changes from positive to negative. Then, the second level VL is switched back to the first level VgL, which serves as the gate line voltage input to the first gate line Gna, which is connected to the second polarity pixel in the off state in the N+1th frame. The first level VgL is lower than the second level VL.

[0065] In this embodiment, the first polarity pixel or the second polarity pixel can be regarded as a positive polarity pixel. For example, if the first polarity pixel is a positive polarity pixel, the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off-state of the Nth frame is a first level VgL. After the first polarity pixel is turned on under the drive of the first gate driving voltage to complete positive pixel charging, the first level VgL is switched to the second level VL until the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel changes from positive to negative. Then, the second level VL is switched back to the first level VgL, serving as the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off-state of the N+1th frame. Alternatively, if the second polarity pixel is a positive polarity pixel, the gate line voltage input to the second gate line Gnb connected to the second polarity pixel in the off-state of the Nth frame is a first level VgL. The second polarity pixel is turned on under the drive of the second gate driving voltage to complete positive pixel charging. Then, the first level VgL is switched to the second level VL until the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel changes from positive to negative. At this point, the second level VL is switched back to the first level VgL, which serves as the gate voltage input to the first gate line Gna, which is connected to the second polarity pixel in the cutoff state at frame N+1. This enables dynamic adjustment of the gate voltage based on the pixel polarity change when the polarity of the data signal provided by the data signal line S1 reverses within consecutive frames. This ensures a smooth transition of pixel polarity between different frames for each pixel in the row pixel unit H1, avoiding display problems caused by voltage mismatch, such as brightness flicker and color distortion. It also reduces charge accumulation and ghosting caused by displaying the same polarity image for a long time, improving display stability and clarity, thereby significantly improving the display quality of LCD products.

[0066] It should be noted that both the first level VgL and the second level VL represent low-level signals, and the low-level voltage of the first level VgL is lower than that of the second level VL.

[0067] Furthermore, in some feasible embodiments, reference is made to Figures 2 to 3If the first polarity pixel is a negative polarity pixel, the gate line voltage input to the first gate line Gna in the off state of the first polarity pixel in the Nth frame is the first level VgL. After the first polarity pixel is turned on under the drive of the first gate driving voltage to complete the negative charging of the pixel, the gate line voltage input to the first polarity pixel in the Nth frame when it switches from the on state to the off state remains unchanged at the first level VgL. When the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel switches from negative to positive polarity, the first level VgL is used as the gate line voltage input to the first gate line Gna in the off state of the first polarity pixel in the N+1th frame; or If the second polarity pixel is a negative polarity pixel, the gate line voltage input to the second gate line Gnb connected to the second polarity pixel in the off state in the Nth frame is the first level VgL. After the second polarity pixel is turned on under the drive of the second gate driving voltage to complete the negative charging of the pixel, the gate line voltage connected to the second polarity pixel in the Nth frame when it switches from the on state to the off state remains unchanged at the first level VgL. When the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel switches from negative polarity to positive polarity, the first level VgL is used as the gate line voltage input to the first gate line Gna connected to the second polarity pixel in the off state in the N+1th frame.

[0068] In this embodiment, the first polarity pixel or the second polarity pixel can be regarded as a negative polarity pixel. For example, if the first polarity pixel is a negative polarity pixel, the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the off state of the Nth frame is a first level VgL. After the first polarity pixel completes negative charging under the drive of the first gate driving voltage, the gate line voltage connected to the first polarity pixel in the Nth frame when switching from the on state to the off state remains unchanged at the first level VgL. When the polarity of the data signal provided by the data signal line S1 electrically connected to the first polarity pixel switches from negative to positive, the first level VgL is used as the gate line voltage input to the first gate line Gna connected to the first polarity pixel in the N+1th frame when the first polarity pixel is in the off state. Alternatively, if the second polarity pixel is a negative polarity pixel, the gate line voltage input to the second gate line Gnb connected to the second polarity pixel in the Nth frame is the first level VgL. After the second polarity pixel completes negative charging under the drive of the second gate driving voltage, the gate line voltage connected to the second polarity pixel in the Nth frame when it switches from the on state to the off state remains unchanged at the first level VgL. When the polarity of the data signal provided by the data signal line S1 electrically connected to the second polarity pixel switches from negative to positive, the first level VgL is used as the gate line voltage input of the first gate line Gna connected to the second polarity pixel in the N+1th frame when it is in the off state. This allows the gate line voltage to be adjusted in a timely manner according to the change in the polarity of the data signal, so that the pixel polarity working state of each pixel in the row pixel unit H1 can better adapt to the display requirements. This effectively improves the problem of different leakage current caused by pixel polarity reversal, thereby reducing the occurrence of display quality problems such as image retention, crosstalk, and flicker, and significantly improving the display quality of LCD products.

[0069] Furthermore, in some feasible embodiments, reference is made to Figure 4 , Figure 4This is a circuit diagram of an embodiment of the liquid crystal display circuit of this application. The first polar pixel includes a first pixel electrode and a first thin-film transistor T1. The first pass terminal of the first thin-film transistor T1 is electrically connected to the first pixel electrode, and the gate terminal of the first thin-film transistor T1 is electrically connected to the first gate line Gna. The second pass terminal of the first thin-film transistor T1 constitutes the data line identifier terminal of the first polar pixel and is electrically connected to the corresponding data signal line S1. The second polar pixel includes a second pixel electrode and a second thin-film transistor T2. The first pass terminal of the second thin-film transistor T2 is electrically connected to the second pixel electrode, and the gate terminal of the second thin-film transistor T2 is electrically connected to the second gate line Gnb. The second pass terminal of the second thin-film transistor T2 constitutes the data line identifier terminal of the second polar pixel and is electrically connected to the corresponding data signal line S1. The first pixel electrode is opposite to the second pixel electrode, and the first thin-film transistor T1 is the same as the second thin-film transistor T2.

[0070] It should be noted that, Figure 4 The thin-film transistor electrically connected to the first gate line Gna is the first thin-film transistor T1. Figure 4 The thin-film transistor electrically connected to the second gate line Gnb is the second thin-film transistor T2.

[0071] In this embodiment, refer to Figure 4 Taking a first polarity pixel as a positive polarity pixel and a second polarity pixel as a negative polarity pixel as an example, this application uses a first gate line Gna to control each positive polarity pixel in each row, and a second gate line Gnb to control each negative polarity pixel. Different gate voltages are provided through the two gate lines (i.e., the first gate line Gna and the second gate line Gnb) to satisfy different gate line voltages Vg corresponding to different polarity pixels, and the gate line voltage Vg switches between a first level VgL and a second level VL. For example, refer to... Figure 3 as well as Figure 4In this application, in the Nth frame, the first polarity pixel is set as a positive polarity pixel and electrically connected to the first gate line Gna, and the second polarity pixel is set as a negative polarity pixel and electrically connected to the second gate line Gnb. Before the first gate line Gna inputs the first gate driving voltage (Gna-Vgh) to the positive polarity pixel in the Nth frame, this application sets the gate line voltage Vg provided by the first gate line Gna to the positive polarity pixel in each row to a first level VgL. After the positive polarity pixel completes the positive pixel charging of the first pixel electrode under the drive of the first gate driving voltage (Gna-Vgh), the gate line voltage Vg provided by the first gate line Gna to the positive polarity pixel becomes a second level VL, until the data signal line S1 electrically connected to the positive polarity pixel in each row. When the data signal provided by the DO in the N+1th frame switches from positive polarity (Vdh) to negative polarity (Vdl), that is, when the first polarity pixel in each row switches from the positive polarity pixel in the Nth frame to the negative polarity pixel in the N+1th frame, the gate line voltage Vg provided by the first gate line Gna to the first polarity pixel in the N+1th frame when it is a negative polarity pixel decreases from the second level VL to the first level VgL. After the pixel is negatively charged by the first gate line Gna to the first polarity pixel in the N+1th frame when it is a negative polarity pixel, the gate line voltage Vg provided by the first gate line Gna to the first polarity pixel after the negative pixel is charged remains unchanged at the first level VgL.

[0072] In another embodiment, in the Nth frame, the second polarity pixel is set to be a negative polarity pixel and electrically connected to the second gate line Gnb. The second gate driving voltage (Gnb-Vgh) provided by the second gate line Gnb is synchronized in timing with the first gate driving voltage (Gna-Vgh) provided by the first gate line Gna to the first polarity pixel. Specifically, before the second gate line Gnb inputs the second gate driving voltage (Gnb-Vgh) to the second polarity pixel that is negative polarity in the Nth frame, the application also sets the first gate line Gna in each row to provide a gate line voltage Vg of a first level VgL to the second polarity pixel that is negative polarity in the Nth frame. When the first polarity pixel that is positive polarity in the Nth frame is connected to the first gate driving voltage (Gna-Vgh), the second polarity pixel that is negative polarity in the Nth frame is enabled to synchronously connect to the second gate driving voltage (Gnb-Vgh) to perform pixel negative charging on the second pixel electrode. After completing the pixel negative charging of the second pixel electrode... The gate line voltage Vg provided by the second gate line Gnb to the second polarity pixel remains unchanged at the first level VgL. When the data signal line S1 (i.e. DE) electrically connected to the second polarity pixel as a negative polarity pixel in each row switches the data signal provided by the second polarity pixel as a negative polarity pixel to the positive polarity pixel as a positive polarity pixel in the N+1th frame, the gate line voltage Vg input to the second polarity pixel after the second gate line Gnb has finished charging the negative pixel is set to the first level VgL as the gate line voltage connected to the second polarity pixel before the positive polarity pixel in the N+1th frame is turned on.

[0073] Furthermore, in yet another embodiment, Figure 5 This is a schematic diagram illustrating the switching of positive and negative frame pixel operating states according to an embodiment of the liquid crystal display circuit of this application. Taking the first polarity pixel as an example, Figure 5 This illustration shows that when the first pixel electrode, electrically connected to the first path terminal of the first thin-film transistor T1, switches from a positive pixel to a negative pixel, the gate line voltage Vg output by the first gate line Gna connected to the gate terminal of the first thin-film transistor T1 switches between a first level VgL and a second level VL. The switching point is defined as follows: the switching point where the source voltage Vs of the first thin-film transistor T1 increases occurs after the first pixel electrode has completed positive charging, i.e. Figure 3 At point m of Gna, the gate voltage Vg provided by the first gate line Gna needs to increase from the first level VgL to the second level VL, and the switching point where the source voltage Vs of the first thin-film transistor T1 decreases occurs at the end of a frame when the data line switches from positive to negative polarity, i.e. Figure 3At point n of Gna, the gate voltage Vg provided by the first gate line Gna needs to be reduced from VL to VgL. In other words, this application uses the same gate line to control pixels of the same polarity in each row, and another gate line to control pixels of the same polarity. The two gate lines are supplied with different voltages to meet the different gate line voltages Vg corresponding to pixels of different polarities, while keeping the gate source voltage Vgs as consistent as possible. The gate line voltage Vg is adjusted in a timely manner according to the change of data signal polarity, so that the pixel polarity working state of each pixel in the row pixel unit H1 can better adapt to the display requirements. This effectively improves the problem of different leakage current caused by pixel polarity reversal, thereby reducing the occurrence of display quality problems such as image retention, crosstalk, and flicker, and significantly improving the display quality of LCD products.

[0074] In summary, this application connects positive and negative polarity pixels to different gate signal lines and provides different gate voltages according to pixel polarity to ensure that the gate-source voltage difference Vgs is as similar as possible for positive and negative polarities, thereby improving the problem of different leakage currents, reducing the occurrence of display quality problems such as image retention, crosstalk, and flicker, and significantly improving the display quality of LCD products.

[0075] In addition, this application also provides a display panel, the display panel including a color filter substrate, a liquid crystal layer and an array substrate, the liquid crystal layer being disposed between the array substrate and the color filter substrate, and the array substrate including the liquid crystal display circuit of any of the above.

[0076] In addition, this application also provides a display device. This application further provides a display device, which includes the display panel described above.

[0077] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0078] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0079] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes several instructions to cause a display device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0080] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A liquid crystal display circuit, characterized in that, The liquid crystal display circuit includes: A pixel array, comprising column pixel units and row pixel units. Multiple data signal lines, each of which provides a data signal to the corresponding column pixel unit, and the data signals provided by adjacent data signal lines have opposite polarities; Multiple first gate lines, each of which provides a first gate driving voltage to the corresponding row pixel unit that has received a first data signal for charging; Multiple second gate lines, each of which provides a second gate driving voltage to the corresponding row pixel unit that has received a second data signal for charging; The pixels that receive the first data signal constitute a first polarity pixel, and the pixels that receive the second data signal constitute a second polarity pixel. The first polarity pixel and the second polarity pixel are opposite. In each row pixel unit, a first gate line and a second gate line are disposed opposite to each other on both sides of the pixels arranged in rows, and a second polarity pixel is disposed between adjacent first polarity pixels. The first gate line is electrically connected to each first polarity pixel, and the second gate line is electrically connected to each second polarity pixel. When the first polarity pixel or the second polarity pixel is a positive polarity pixel, the gate line voltage connected to the positive polarity pixel in the off state in the Nth frame is a first low level. After the positive polarity pixel is turned on under the drive of the gate line voltage to complete the positive charging of the pixel, the first low level is switched to a second level until the polarity of the data signal provided by the data signal line electrically connected to the positive polarity pixel changes from positive to negative. Then the second level is switched back to the first low level, which serves as the gate line voltage connected to the positive polarity pixel in the off state in the N+1th frame. The first low level is lower than the second level. When the first polarity pixel or the second polarity pixel is a negative polarity pixel, the gate line voltage accessed by the negative polarity pixel in the off state in the Nth frame is a first low level. After the negative polarity pixel is turned on under the drive of the gate line voltage to complete the negative charging of the pixel, the gate line voltage accessed by the negative polarity pixel in the Nth frame when it switches from the on state to the off state remains unchanged at the first low level. When the polarity of the data signal provided by the data signal line electrically connected to the negative polarity pixel switches from negative polarity to positive polarity, the first low level is used as the gate line voltage accessed by the negative polarity pixel in the off state in the N+1th frame.

2. The liquid crystal display circuit as described in claim 1, characterized in that, The data signal provided by each of the data signal lines to the corresponding column pixel unit in the Nth frame has the opposite polarity to the data signal provided to the corresponding column pixel unit in the N+1th frame, where N is a natural number greater than zero.

3. The liquid crystal display circuit as described in claim 1, characterized in that, Each of the data signal lines is electrically connected to the corresponding column pixel unit; In each of the column pixel units, the polarity of each pixel is the same as the polarity of the data signal provided by the corresponding data signal line.

4. The liquid crystal display circuit as described in claim 1, characterized in that, In each row pixel unit, when the first gate line provides the first gate driving voltage to each first polarity pixel for charging, the second gate line provides the second gate driving voltage to each second polarity pixel for charging.

5. The liquid crystal display circuit as described in claim 1, characterized in that, The first polar pixel includes a first pixel electrode and a first thin-film transistor. The first pass terminal of the first thin-film transistor is electrically connected to the first pixel electrode, the gate terminal of the first thin-film transistor is electrically connected to the first gate line, and the second pass terminal of the first thin-film transistor constitutes the data line identifier terminal of the first polar pixel and is electrically connected to the corresponding data signal line. The second polarity pixel includes a second pixel electrode and a second thin-film transistor. A first terminal of the second thin-film transistor is electrically connected to the second pixel electrode, and a gate terminal of the second thin-film transistor is electrically connected to the second gate line. A second terminal of the second thin-film transistor constitutes a data line identifier terminal of the second polarity pixel and is electrically connected to the corresponding data signal line. The first pixel electrode is opposite to the second pixel electrode, and the first thin-film transistor is the same as the second thin-film transistor.

6. A display panel, characterized in that, The display panel includes a color filter substrate, a liquid crystal layer, and an array substrate. The liquid crystal layer is disposed between the array substrate and the color filter substrate. The array substrate includes a liquid crystal display circuit as described in any one of claims 1 to 5.

7. A display device, characterized in that, The display device includes the display panel as described in claim 6.

Images