A method for calibrating the current limiting accuracy of a current limiting switch

Abstract

This invention discloses a current-limiting accuracy calibration method for a current-limiting switch, applied to a current-limiting accuracy calibration circuit. The calibration circuit includes a mirror circuit, a current-to-voltage module, and an overcurrent comparison module. The mirror circuit is electrically connected to a charge pump. The ratio between the input current I0 and the output current I3 of the mirror circuit is P (I3 = I0 / P). The current-to-voltage module converts the internal reference current I4 and current I3 into corresponding voltages V4 and V3, respectively. The overcurrent comparison module compares the magnitudes of voltage V4 and voltage V3. This invention, by adding a method to adjust the mirror ratio P based on the two-point adjustment method, significantly improves the accuracy of the high-current limiting value in actual chip operation through small current adjustment.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a method for calibrating the current limiting accuracy of a current limiting switch. Background Technology

[0002] With the development of intelligent appliances, product applications are placing higher demands on the power consumption and accuracy of chips. During mass production adjustments, the chip output cannot directly draw the target current limit value (typically 2-6A). The common practice is to draw a small current from the output and adjust it precisely, utilizing the linearity of the circuit to make the output current reach the target current limit value. However, in actual circuit architecture design, tape-out, packaging, and testing, non-ideal effects are introduced, causing deviations in the MOSFET replication ratio and current limiting setting. This results in a significant error between the ideal chip current limit value and the actual current limit value after adjustments. Summary of the Invention

[0003] The purpose of this invention is to at least solve one of the technical problems existing in the prior art, and to provide a current limiting accuracy calibration method for current limiting switches that improves the deviation of target current limiting values ​​for batch chips.

[0004] According to an embodiment of the present invention, a current limiting accuracy calibration method for a current limiting switch is applied to a current limiting accuracy calibration circuit. The current limiting accuracy calibration circuit includes a mirror circuit, a current-to-voltage module, and an overcurrent comparison module. The mirror circuit is electrically connected to a charge pump. The ratio between the current I0 at the input terminal of the mirror circuit and the current I3 at its output terminal is P (I3 = I0 / P). The current-to-voltage module is used to convert the internal reference current I4 and current I3 into corresponding voltages V4 and V3, respectively. The overcurrent comparison module is used to compare the magnitudes of voltage V4 and voltage V3. The method includes the following steps:

[0005] Step 1: Adjust the internal reference current I4 until the voltage V4 is greater than the voltage V3. At this point, no overcurrent phenomenon occurs. The ratio P of the mirror circuit is denoted as P1.

[0006] Step 2: Adjust the current I0 of the mirror circuit to increase it by one level P1*Imin, where Imin is the minimum level current corresponding to the internal reference current I4.

[0007] Step 3: Adjust the internal reference current I4 to increase its range by one level, Imin;

[0008] Step 4: Determine whether the voltage V4 > voltage V3 or voltage V4 < voltage V3.

[0009] If voltage V4 < voltage V3, an overcurrent phenomenon occurs, and step 5 is executed;

[0010] If voltage V4 > voltage V3, no overcurrent occurs, proceed to step 6;

[0011] Step 5: Reduce the ratio P of the mirror circuit until no overcurrent occurs. At this time, the ratio P is recorded as P2. Write the value corresponding to P2 at this time into the chip and execute step 8.

[0012] Step 6: Increase the ratio P of the mirror circuit until an overcurrent occurs. At this point, the ratio P is recorded as P3. Then proceed to step 7.

[0013] Step 7: Reduce the ratio P3 of the mirror circuit by one minimum level. At this time, the ratio P is recorded as P4, and the value corresponding to P4 is written into the chip. Then, proceed to step 8.

[0014] Step 8: Adjust the current I0 of the mirror circuit to the actual current limit value I of the chip, and increase the internal reference current I4 by the corresponding level. The adjustment is complete.

[0015] According to an embodiment of the present invention, a current limiting accuracy calibration method for a current limiting switch has at least the following beneficial effects: The internal reference current I4 and the ratio P of the mirror circuit can both be adjusted by changing the register value. First, adjust the internal reference current I4 until voltage V4 is greater than voltage V3, at which point overcurrent has just occurred. Record the ratio P of the mirror circuit at this point as P1. Then, first adjust the external input current I0 of the mirror circuit, then change the internal reference current I4. Next, determine the relationship between voltage V4 and voltage V3. 1. If voltage V4 < voltage V3, it indicates that overcurrent has occurred, and the ratio P of the mirror circuit needs to be reduced until overcurrent has just occurred. The external input current I0 of the mirror circuit is adjusted to the actual current limit value I of the chip, and the internal reference current I4 is increased by the corresponding level to complete the adjustment. 2. If the voltage V4 > voltage V3 at this time, it means that no overcurrent has occurred. The ratio P of the mirror circuit needs to be increased until an overcurrent occurs. This ratio P is denoted as P3. Since an overcurrent has just occurred, the ratio P3 of the mirror circuit only needs to be reduced by the minimum level, so that the current I3 is reduced by the minimum level current Imin. This will adjust the current from just overcurrent to just no overcurrent. Then, the external input current I0 of the mirror circuit is adjusted to the actual current limit value I of the chip, and the internal reference current I4 is increased by the corresponding level to complete the adjustment. That is, based on the two-point adjustment method, this invention adjusts the mirror ratio P and significantly improves the accuracy of the actual chip's high current limit value by adjusting the small current.

[0016] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0017] The specific embodiments of the present invention will be further described below with reference to the accompanying drawings;

[0018] Figure 1 This is a block diagram of the current limiting accuracy calibration circuit;

[0019] Figure 2 This is the schematic diagram of a mirror circuit;

[0020] Figure 3 This is the schematic diagram of a current-to-voltage converter module;

[0021] Figure 4 This is the schematic diagram of the overcurrent comparator module;

[0022] Figure 5 This is the control flowchart of the current limiting accuracy calibration method. Detailed Implementation

[0023] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0024] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0025] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0026] Reference Figures 1 to 5This invention discloses a current-limiting accuracy calibration method for a current-limiting switch, applied to a current-limiting accuracy calibration circuit. The current-limiting accuracy calibration circuit includes a mirror circuit 10, a current-to-voltage module 20, and an overcurrent comparison module 30. The mirror circuit 10 is electrically connected to a charge pump. The ratio between the input current I0 and the output current I3 of the mirror circuit 10 is P (I3 = I0 / P). The current-to-voltage module 20 converts the internal reference current I4 and current I3 into corresponding voltages V4 and V3, respectively. The overcurrent comparison module 30 compares the magnitudes of voltage V4 and voltage V3. Figure 5 The method includes the following steps:

[0027] Step 1: Adjust the internal reference current I4 until the voltage V4 is greater than the voltage V3. At this point, no overcurrent phenomenon occurs. The ratio P of the mirror circuit is denoted as P1.

[0028] Step 2: Adjust the current I0 of the mirror circuit to increase it by one level P1*Imin, where Imin is the minimum level current corresponding to the internal reference current I4.

[0029] Step 3: Adjust the internal reference current I4 to increase its range by one level, Imin;

[0030] Step 4: Determine whether the voltage V4 > voltage V3 or voltage V4 < voltage V3.

[0031] If voltage V4 < voltage V3, an overcurrent phenomenon occurs, and step 5 is executed;

[0032] If voltage V4 > voltage V3, no overcurrent occurs, proceed to step 6;

[0033] Step 5: Reduce the ratio P of the mirror circuit until no overcurrent occurs. At this time, the ratio P is recorded as P2. Write the value corresponding to P2 at this time into the chip and execute step 8.

[0034] Step 6: Increase the ratio P of the mirror circuit until an overcurrent occurs. At this point, the ratio P is recorded as P3. Then proceed to step 7.

[0035] Step 7: Reduce the ratio P3 of the mirror circuit by one minimum level. At this time, the ratio P is recorded as P4, and the value corresponding to P4 is written into the chip. Then, proceed to step 8.

[0036] Step 8: Adjust the current I0 of the mirror circuit to the actual current limit value I of the chip, and increase the internal reference current I4 by the corresponding level. The adjustment is complete.

[0037] In some embodiments, such as Figure 2As shown, the mirror circuit 10 includes MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7, and Q8, and comparator OP1. MOSFETs Q1 and Q2 form the first mirror circuit 10, and MOSFETs Q4 and Q5 form the second mirror circuit 12. The ratio of the first mirror circuit 11 is M, the ratio of the second mirror circuit 12 is N, and the ratio of the mirror circuit 10 is P = M * N. The gates of MOSFETs Q1 and Q2 are electrically connected to the charge pump, the drains of MOSFETs Q1 and Q2 are connected to the input voltage VIN, and the source of MOSFET Q1 is connected to the comparator OP1. The inverting input terminal of P1 is electrically connected to the source of MOSFET Q3. The output terminal of comparator OP1 is electrically connected to the gate of MOSFET Q3. The drain of MOSFET Q3 is electrically connected to the gate and drain of MOSFET Q4 and the gate of MOSFET Q5, respectively. The sources of MOSFET Q4 and MOSFET Q5 are grounded. The drain of MOSFET Q5 is electrically connected to the source of MOSFET Q8. The drain of MOSFET Q8 is electrically connected to the gate and drain of MOSFET Q6 and the gate of MOSFET Q7, respectively. The sources of MOSFET Q6 and MOSFET Q7 are connected to the operating voltage VCC, respectively. The drain current of MOSFET Q7 is the output current I3, and the source current of MOSFET Q2 is the input current I0.

[0038] like Figure 3 The overcurrent comparator module 30 includes a comparator CMP, MOSFETs Q9 and Q10. The positive input terminal of the comparator CMP receives voltage V4, and the inverting input terminal receives voltage V3. The output terminal of the comparator CMP is electrically connected to the drain and gate of MOSFET Q9 and the gate of MOSFET Q10, respectively, and is electrically connected to the charge pump. The sources of MOSFETs Q9 and Q10 are grounded, and the drain of MOSFET Q10 is electrically connected to the charge pump. When voltage V4 > voltage V3, the comparator CMP outputs a low level, preventing the charge pump from being pulled down, indicating that no overcurrent has occurred. When voltage V4 < voltage V3, the comparator CMP outputs a high level, pulling down the charge pump, indicating that an overcurrent has occurred.

[0039] like Figure 4 The current-to-voltage module 20 includes resistors R1 and R2. One end of resistor R1 is electrically connected to the output terminal of the mirror circuit 10 to input and output current I3. One end of resistor R2 is input to the internal reference current I4. The other ends of resistors R1 and R2 are grounded respectively. Voltage V3 = I3 * R1 and voltage V4 = I4 * R2.

[0040] According to the existing chip technology, both the magnitude of the internal reference current I4 and the ratio P of the mirror circuit 10 can be adjusted by changing the register value, thereby changing the magnitude of the mirror current I3. For example, the register value 00011011 corresponds to 6.75 μA, 00011100 corresponds to 7 μA, and for every increase of 1 in the binary number, the corresponding internal reference current I4 increases by a step of 0.25 μA. This 0.25 μA step is equivalent to the minimum gear current Imin.

[0041] Since batch trimming does not support increasing the current at the output end, the maximum supported current is generally 1 A. The closer it is to 1 A, the shorter the lifespan of the machine probe. Also, the target current at the output end is not fixed and there are various requirements, such as 2 A, 3 A, 3.5 A, etc. To统一测试条件, trim according to the small current, which improves the trimming efficiency; and for the testers, the smaller the current, the lower the risk factor and the safer the test environment. Moreover, the number of chips for batch trimming is relatively large, so compared with large currents, small currents can reduce power consumption. Therefore, in step one, the input current I0 of the mirror circuit 10 needs to be reduced to 0.1 - 1 A for trimming.

[0042] Taking I0 = 700 mA and ratio P = 100000 as an example, for current I3 = I0 / P = 700 mA / 100000 = 7 μA, in the current-to-voltage module 20, V3 = I3 * R1 and V4 = I4 * R2. The judgment basis for just not having an overcurrent is: by changing the register value to traverse and decrease the digital register, just making the voltage V4 > V3, then the overcurrent comparison module 30 outputs a low level and the charge pump will not be pulled down, indicating that there is just no overcurrent at this time. If V4 < V3, the overcurrent comparison module 30 outputs a high level and the charge pump is pulled down, indicating that an overcurrent occurs at this time.

[0043] That is, first reduce the input current I0 of the mirror circuit 10 to 0.1 - 1 A, adjust the internal reference current I4 until the voltage V4 is greater than the voltage V3, and at this time, there is just no overcurrent phenomenon. Record the ratio P of the mirror circuit 10 at this time as P1; then first adjust the external input current I0 of the mirror circuit 10 to increase it by one gear P1 * Imin (0.25 μA * 100000 = 25 mA), then adjust the internal reference current I4 to increase it by a minimum gear current Imin (0.25 μA). Then, through the overcurrent comparison module 30, judge the magnitude relationship between the voltage V4 and the voltage V3 at this time. 1. If the voltage V4 < voltage V3 at this time, it means that an overcurrent phenomenon has occurred and the ratio P of the mirror circuit 10 needs to be reduced. The ratio P can be reduced by reducing Figure 2 the magnitude of the ratio N of the second mirror circuit 10 in it (generally speaking, Figure 2 It should be noted that the part "统一测试条件" in the original text seems to be an incorrect or incomplete expression. I translated it as "To统一测试条件" for the purpose of maintaining the integrity of the translation according to the rules. You may need to check and correct this part in the original text.The ratio M of the first mirror circuit 10 in the circuit cannot be adjusted or changed. In this example, M is set to 5000. The default register value is 10000 (corresponding to N=40, 10001 to N=41). The ratio P is recorded as P2, and the value (binary number) corresponding to P2 is written into the chip. Then, the external input current I0 of the mirror circuit is adjusted to the actual current limit value I of the chip (generally 2 to 6A). The internal reference current I4 is increased by the corresponding level (I-I0) / P2 to complete the adjustment.

[0044] 2. If voltage V4 > voltage V3 at this time, it indicates that no overcurrent has occurred. The proportional gain P of the mirror circuit 10 needs to be increased until an overcurrent occurs. This proportional gain P of the mirror circuit 10 is denoted as P3. Since an overcurrent has just occurred, simply decrease the proportional gain P3 of the mirror circuit 10 by one minimum level, causing the current I3 to decrease by one minimum level, i.e., decrease the register value by one bit, and the corresponding N value decreases by 1. This proportional gain P is denoted as P4. Write the value (binary number) corresponding to P4 into the chip. This adjusts the current from just overcurrent to just no overcurrent. Then, adjust the external input current I0 of the mirror circuit to the actual current limit value I of the chip (generally 2-6A), and increase the internal reference current I4 by the corresponding level (I-I0) / P4 to complete the adjustment. The deviation of the current limit value in batch testing should not exceed ±3%.

[0045] That is, based on the two-point adjustment method, this invention adjusts the mirror ratio P and significantly improves the accuracy of the high current limiting value of the actual chip operation by adjusting the small current.

[0046] It will be readily understood by those skilled in the art that the above preferred methods can be freely combined and superimposed without conflict.

[0047] The above are merely preferred embodiments of the present invention and do not limit the patent scope of the present invention. All equivalent structural transformations made using the contents of the present invention's specification and drawings under the inventive concept of the present invention, or direct or indirect applications in other related technical fields, are included within the patent protection scope of the present invention.

Claims

1. A method for calibrating the current limiting accuracy of a current limiting switch, applied to a current limiting accuracy calibration circuit, characterized in that, The current limiting accuracy calibration circuit includes a mirror circuit (10), a current-to-voltage module (20), and an overcurrent comparison module (30). The mirror circuit (10) is electrically connected to a charge pump. The ratio between the current I0 at the input terminal of the mirror circuit (10) and the current I3 at its output terminal is P (I3 = I0 / P). The current-to-voltage module (20) is used to convert the internal reference current I4 and current I3 into corresponding voltages V4 and V3, respectively. The overcurrent comparison module (30) is used to compare the magnitudes of voltage V4 and voltage V3. The method includes the following steps: Step 1: Adjust the internal reference current I4 until the voltage V4 is greater than the voltage V3. At this point, no overcurrent phenomenon occurs. The ratio P of the mirror circuit is denoted as P1. Step 2: Adjust the current I0 of the mirror circuit to increase it by one level P1*Imin, where Imin is the minimum level current corresponding to the internal reference current I4. Step 3: Adjust the internal reference current I4 to increase its range by one level, Imin; Step 4: Determine whether the voltage V4 > voltage V3 or voltage V4 < voltage V3. If voltage V4 < voltage V3, an overcurrent phenomenon occurs, and step 5 is executed; If voltage V4 > voltage V3, no overcurrent occurs, proceed to step 6; Step 5: Reduce the ratio P of the mirror circuit until no overcurrent occurs. At this time, the ratio P is recorded as P2. Write the value corresponding to P2 at this time into the chip and execute step 8. Step 6: Increase the ratio P of the mirror circuit until an overcurrent occurs. At this point, the ratio P is recorded as P3. Then proceed to step 7. Step 7: Reduce the ratio P3 of the mirror circuit by one minimum level. At this time, the ratio P is recorded as P4, and the value corresponding to P4 is written into the chip. Then, proceed to step 8. Step 8: Adjust the current I0 of the mirror circuit to the actual current limit value I of the chip, and increase the internal reference current I4 by the corresponding level. The adjustment is complete.

2. The current limiting accuracy calibration method for the current limiting switch according to claim 1, characterized in that: In step 1, the input current I0 of the mirror circuit (10) ranges from 0.1 to 1A.

3. The current limiting accuracy calibration method for the current limiting switch according to claim 1, characterized in that: The overcurrent comparison module (30) includes a comparator CMP, a MOSFET Q9, and a MOSFET Q10. The positive input terminal of the comparator CMP receives a voltage V4, and the negative input terminal receives a voltage V3. The output terminal of the comparator CMP is electrically connected to the drain and gate of the MOSFET Q9 and the gate of the MOSFET Q10, respectively, and is electrically connected to the charge pump. The source of the MOSFET Q9 and the source of the MOSFET Q10 are grounded, and the drain of the MOSFET Q10 is electrically connected to the charge pump. When the voltage V4 > the voltage V3, the comparator CMP outputs a low level, so that the charge pump is not pulled down, indicating that no overcurrent has occurred. When the voltage V4 < the voltage V3, the comparator CMP outputs a high level, so that the charge pump is pulled down, indicating that an overcurrent has occurred.

4. The current limiting accuracy calibration method for the current limiting switch according to claim 1, characterized in that: The mirror circuit (10) includes MOSFETs Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8 and comparator OP1. MOSFETs Q1 and Q2 form a first mirror circuit (11), and MOSFETs Q4 and Q5 form a second mirror circuit (12). The ratio of the first mirror circuit (11) is M, the ratio of the second mirror circuit (12) is N, and the ratio of the mirror circuit (10) is P = M * N. The gates of MOSFETs Q1 and Q2 are electrically connected to the charge pump. The drains of MOSFETs Q1 and Q2 are connected to the input voltage VIN. The source of MOSFET Q1 is electrically connected to the inverting input of comparator OP1 and the source of MOSFET Q3. The output of comparator OP1 is electrically connected to the gate of MOSFET Q3. The drain of MOSFET Q3 is electrically connected to the gate, drain, and gate of MOSFET Q4 and MOSFET Q5, respectively. The sources of MOSFETs Q4 and Q5 are grounded. The drain of MOSFET Q5 is electrically connected to the source of MOSFET Q8. The drain of MOSFET Q8 is electrically connected to the gate, drain, and gate of MOSFET Q6 and MOSFET Q7, respectively. The sources of MOSFETs Q6 and Q7 are connected to the operating voltage VCC. The drain current of MOSFET Q7 is the output current I3, and the source current of MOSFET Q2 is the input current I0.

5. The current limiting accuracy calibration method for the current limiting switch according to claim 1, characterized in that: The current-to-voltage module (20) includes resistors R1 and R2. One end of resistor R1 is electrically connected to the output terminal of the mirror circuit to input the output current I3. One end of resistor R2 is input to the internal reference current I4. The other ends of resistors R1 and R2 are grounded respectively. Voltage V3 = I3 * R1 and voltage V4 = I4 * R2.

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