Method for trimming voltage reference in circuit and related circuit

Abstract

The invention relates to a method for trimming a voltage reference in a circuit and a related circuit. A circuit includes positive and negative voltage rails, a reference voltage rail, a non-trimmer bandgap core configured to output a voltage reference on the reference voltage rail, and a trimming element in an auxiliary portion external to the bandgap core. A current source is coupled to the non-trimming bandgap core and the positive voltage rail. An auxiliary diode disposed in an auxiliary portion outside the bandgap core is coupled to the current source and the negative voltage rail. The trimming element is coupled to a current source external to the non-trimming bandgap core and has an adjustable setpoint. The adjustable setpoint is adjusted to inject a corresponding bias current into the auxiliary portion and thereby change the voltage reference during a trimming process.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 578,867, filed on August 25, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure generally relates to fine-tuning circuit topologies and related methods for providing a high precision bandgap reference in a semiconductor device. Background Art

[0004] Modern power electronic devices such as on-board chargers, traction power inverters, analog-to-digital converters, and direct current to direct current (DC-DC) voltage converters rely on advanced silicon technology to meet power and operating efficiency requirements. Precise real-time control of such devices may be achieved using one or more integrated circuits (ICs), for example in the form of microprocessors, memory circuits, sensors, amplifiers, and wireless communication chips. The ICs rely on the availability of a substantially temperature-invariant reference voltage in order to perform many functions.

[0005] To this end, bandgap core circuitry is designed into the IC to provide a substantially constant voltage reference. The voltage reference is based on the energy band difference or "gap" between the valence band and the conduction band of a semiconductor. Therefore, the circuitry is sometimes referred to as a bandgap reference circuit, where the output voltage of the bandgap reference circuit is referred to as the bandgap voltage. For silicon-based bandgap reference circuits, in some embodiments, the bandgap voltage can range between about 1.2 volts to about 1.3 volts.

[0006] Although the bandgap voltage is substantially invariant to temperature fluctuations, the manufacturing process used to construct the bandgap reference circuitry may have variations, which may result in slight chip-to-chip variations in the bandgap voltage on devices fabricated using the same manufacturing process steps. To help correct for such process-induced performance variations, a trimming process is typically performed by adjusting the ratios of the various resistors used to construct the bandgap core (e.g., via digital / bit trimming, laser or ion beam trimming, or switch activation). Thus, trimming within the bandgap core circuitry is typically used to fine-tune the voltage reference to a desired value and thereby ensure consistent performance over the expected temperature range. Summary of the invention

[0007] Disclosed herein are voltage reference trimming methods performed outside of a resident circuitry of a bandgap core, and corresponding circuit topologies for performing such trimming methods. Among other incidental benefits, the performance of the trimming process outside of the bandgap core helps ensure optimized core accuracy with minimal residual errors, the latter of which is more prevalent in integrated circuits that exhibit higher order curvatures in the base-emitter voltage response. The trimming methods described below can be associated with reduced silicon area and required test time relative to trimming processes performed within the circuitry of the bandgap core. The present methods are also compatible with a variety of bandgap reference circuits, including but not limited to those that compensate for higher order base-emitter voltage curvatures.

[0008] In particular, a circuit is disclosed herein having a non-trimmable bandgap core, a current source coupled to the bandgap core, and an auxiliary portion positioned outside the bandgap core. The auxiliary portion includes an auxiliary diode and a trimming element coupled to the current source, and a pair of resistors coupled to the bandgap core. The set point of the trimming element is adjusted so as to inject a bias current into the auxiliary portion. In this manner, a voltage reference is adjusted.

[0009] The embodiments described herein control bias current adjustment by varying the mirror ratio of the above-mentioned current source (eg, a pair of field effect transistors, such as first and second p-channel metal oxide semiconductors). The present teachings are also applicable to circuits having base-emitter voltage curvature compensation circuits.

[0010] The foregoing summary is not intended to represent every embodiment or aspect of the present disclosure. On the contrary, the foregoing summary illustrates certain novel aspects and features as described herein. The above and other features and advantages of the present disclosure will be apparent from the following detailed description of representative embodiments and modes for carrying out the present disclosure when taken in conjunction with the accompanying drawings and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings described herein are for illustration purposes only, are schematic in nature, and are intended to be exemplary rather than limiting the scope of the present disclosure.

[0012] Figure 1 is a circuit diagram of a representative circuit according to the present disclosure.

[0013] Figure 2 A graph depicting the generalized relationship between a voltage proportional to absolute temperature and a voltage complementary to absolute temperature, with voltage depicted on the vertical axis and temperature illustrated on the horizontal axis.

[0014] Figure 3 is a graph of parabolic bandgap voltage over a representative temperature range, with voltage depicted on the vertical axis and temperature illustrated on the horizontal axis.

[0015] Figure 4 is another representative circuit with curvature compensation according to one or more alternative embodiments.

[0016] Figure 5A and 5B To describe and Figure 1 and 4 A flow chart of an exemplary trimming method for use with a circuit.

[0017] Figure 6 For use Figure 4 A schematic diagram of the construction of a circuit constructed with a trimmer resistor can be seen below.

[0018] Figure 7 Describe the various aspects of the present disclosure for implementing Figure 1 or 4. A representative layout of a circuit.

[0019] The present disclosure may be modified or embodied in alternative forms, wherein representative embodiments are shown in the drawings and described in detail below. The inventive aspects of the present disclosure are not limited to the disclosed embodiments. On the contrary, the present disclosure is intended to cover alternatives that fall within the scope of the present disclosure as defined by the appended claims. DETAILED DESCRIPTION

[0020] Referring to the drawings, wherein like reference numerals designate the same or similar parts throughout the several views, Figure 1 1 is a circuit 10 suitable for use as part of an integrated circuit (IC), a system on a chip (SoC), or another semiconductor-based electrical device. The circuit 10 includes a positive voltage rail (V DD )11 + and negative rail (V SS )11 - As is understood in the art, the positive voltage rail 11 + can be connected to a regulated direct current (DC) power source (not shown), for example, about 3.3-5.0 volts (V) in a typical embodiment. - In the illustrated circuit 10 , serves as an electrical ground.

[0021] As envisioned in this paper, Figure 1 The circuit 10 includes a bandgap reference circuit 12 having a non-trimmable bandgap core 12A and an auxiliary portion 12B. Figure 1 Possible underlying hardware configurations of the bandgap core 12A include Kujik, Brokaw, or Widlar cores, all of which are understood in the art, and thus Figure 1 The bandgap core 12A illustrated in FIG. 1 is non-limiting and illustrative of the present teachings.

[0022] The bandgap reference circuit 12 is coupled to the corresponding positive voltage rail 11 + and negative voltage rail 11 - When the bandgap reference circuit 12 is powered by the regulated DC power supply described above, the bandgap reference circuit 12 is configured to output a substantially temperature-invariant voltage reference (V REF ), such as within about ±5%-10% of the desired value in some embodiments. For example, in a typical 3.3V-5V power supply implementation, the bandgap reference circuit 12 may output about 1.2V-1.3V.

[0023] The bandgap reference circuit 12 includes a plurality of resistors 14, which are also individually labeled R1-R5 for clarity, with resistors R1, R2, and R3 residing within a non-trimmable bandgap core 12A. The bandgap reference circuit 12 also includes an operational amplifier (op amp) (A1) 16 and a set of three diodes 18, which are individually labeled D1-D3. On a given semiconductor wafer, the resistors 14 and diodes 18 are typically fabricated as closely together as possible using predetermined layout techniques. Such compactness eliminates sensitivity to local variations in doping and temperature effects. In one or more embodiments, the diodes 18 (D1-D3) may be replaced by bipolar junction transistors (BJTs) that are diode-connected (i.e., shorted between the base and collector), and thus Figure 1 The diode 18 is representative and non-limiting.

[0024] When constructing the bandgap reference circuit 12, each component is provided with a corresponding value to generate a voltage reference (V REF ). Then, as described herein, the voltage reference (V REF ) to account for the above process variations. The voltage reference (V REF ) value is application specific, as is understood in the art, as is the gain of op amp 16. The voltage reference (V REF ) is the main error component of the base-emitter voltage (V BE ) changes, where the error is proportional to absolute temperature behavior (PTAT). Therefore, fine-tuning of the outer side of the bandgap core 12A occurs to adjust the voltage used to generate the voltage reference (V REF ) of the PTAT voltage.

[0025] exist Figure 1In a representative configuration of FIG. 1 , as shown, resistors R4 and R5 of auxiliary portion 12B are arranged in parallel across separate first and second input terminals (+, −) to op amp 16, i.e., the first and second input terminals (+, −) are connected to corresponding resistors R4 and R5. The output of op amp 16 is carried on feedback trace 13. In addition, trimming element 20 as used herein is operable to output a component of the above-mentioned PTAT voltage to corresponding resistors R4 and R5 to change the voltage reference (V REF That is, the operation of the trimming element 20 changes the current density ratio of the diodes D2 and D3 to perform the described trimming function entirely outside of the non-trimable bandgap core 12A.

[0026] exist Figure 1 In the exemplary circuit topology of , resistors R2 and R3 are disposed between reference voltage rail 111 and two of diodes 18, namely diodes D1 and D2, respectively. Additionally, resistor R1 is connected between diode D1 and the positive (first) input to op amp 16, in series with resistor R2. Resistors R4 and R5 are similarly connected to diode D3 (referred to herein for clarity as auxiliary diode D3 to indicate its use in auxiliary portion 12B rather than bandgap core 12A), and diodes D1 (with its resistor R1) and D2 and the positive (first) and negative (second) inputs to op amp 16.

[0027] Due to manufacturing process variations and other factors, the voltage reference (V REF ) will tend to differ from the voltage reference of other identically configured circuits 10. This may be true even for bandgap cores 12A produced in the same batch. Therefore, a trimming process is performed during production via the trimming element 20 to account for such variations.

[0028] As described below, the trimming element 20 in various configurations is coupled to the current source 19, the auxiliary portion 12B of the bandgap reference circuit 12, and the positive voltage rail 11. + The auxiliary diode (D3) has an anode connected to the current source 19 and a cathode connected to the remaining diodes D1 and D2 and goes to the negative voltage rail 11. - The trimming element 20 as contemplated herein is located outside the bandgap core 12A and has an adjustable set point. Thus, the bandgap core 12A is characterized by the absence of an associated trimming switch. The adjustable set point is in turn operable to bias the auxiliary portion 12B during the trimming process, thereby changing the voltage reference (V REF ).

[0029] The fine tuning according to the present disclosure is connected to the bandgap core 12A and the positive voltage rail 11 +The method allows fine tuning of the voltage reference (V REF ).

[0030] The trimming element 20 located outside the non-trimable bandgap core 12A has an adjustable set point that is operable to adjust the bias current (I c3 ) is implanted into the auxiliary portion 12B and thereby fine-tunes the voltage reference (V REF As will be appreciated by those skilled in the art, a 1-point trim is a term used to improve the voltage reference (V REF ) is a calibration technique that can be used to improve the accuracy of the measurement. This occurs by correcting for process variations at a single temperature (typically at or near room temperature). Figure 3 and 4 As described, additional techniques may be implemented to compensate for base-emitter curvature.

[0031] Among the possible methods, Figure 1 The current source 19 illustrated in the example can be implemented as a current mirror. The current mirror can be constructed by shorting or tying together the respective gate terminals of a pair of transistors (e.g., field effect transistors (FETs) 22A and 22B having respective gate (G), source (S), and drain (D) terminals) via an electrical conductor 25. For example, FETs 22A and 22B can be configured as first and second p-channel metal oxide semiconductor (PMOS) elements connected at a node N2. Either FET 22A or 22B can act as a fine-tuning element 20 herein, so Figure 1 FET 22A is exemplary and non-limiting.

[0032] exist Figure 1 In a generalized embodiment of the present invention, diodes D1 and D2 have different respective current densities. The current density of a given diode is given by its total diode current divided by its diode area. In a non-limiting example, diode D2 may have a current density higher than the current density of diode D1, e.g., 800% of (8X), in order to produce a positive dV across resistor R1. BE . Assuming diodes D1 and D2 carry the same current, the current density ratio is inversely proportional to the emitter area ratio. In this embodiment, diode D1 has a relative current density of 1X and a relative area of ​​8X, while diode D2 has a relative current density of 8X and a relative area of ​​1X. Auxiliary diode D3 can have the same area as diode D2. Therefore, there will be a higher current with some variable component due to the trimming. Therefore, in Figure 1 and 4 The notations "1X" and "8X" are used in FIG. 1 to indicate representative relative current densities to produce the first component of the PTAT voltage, as described in detail below.

[0033] In this particular example, diodes D2 and D3 each have an equal smaller area and higher current density, and therefore will exhibit a higher base-emitter voltage (V BE In contrast, diode D1 will exhibit a much lower base-emitter voltage (V BE The exemplary ratio of 8:1 will therefore produce a differential voltage (dV BE ). Then dV is amplified by the ratio R2 / R1 BE Voltage to produce the non-trimming component of the PTAT voltage. For trimming, another component of the PTAT voltage originates from another dV between diodes D2 and D3. BE This voltage is impressed on resistors R4 and R5 and then converted to a full PTAT voltage across resistors R2 and R3. The full PTAT voltage is ultimately used to generate the desired relatively time-invariant reference (V REF ).

[0034] Usually, in Figure 1 In an embodiment of the present invention, fine tuning is enabled via a fine tuning element 20 within the current source 19. The location of the fine tuning element 20 is completely outside / outside the bandgap core 12A, as described above. This location enables cost-effective fine tuning without modifying the bandgap core 12 in any way. It is also helpful that the fine tuning does not affect the auxiliary portion 12B, where the diodes D1, D2 and D3 and the resistors R1-R5 are packaged closely adjacent to each other. This feature becomes more important as the circuit complexity increases when implementing a curvature compensation scheme.

[0035] In the optional configuration, Figure 1 The circuit 10 may include a current digital-to-analog converter (DAC) 27 instead of the fine-tuning element 20 integrated with the FET. Figure 5B and 6 For example, a method similar to method 200M may be implemented to Figure 1 In this case, a digital input signal (arrow CC) from an external processor (P) 50 may be transmitted to the current DAC 27 to tune the resulting bias current Ic3. However, in the absence of the current DAC 27, the bias current Ic3 may be adjusted according to other suitable methods (e.g., as described herein with reference to Figure 5A The method described in 100M) was fine-tuned.

[0036] PTAT and CTAT: A brief reference Figure 2 Graph 30 depicting the general relationship between voltage (V) on the vertical axis and temperature (T) on the horizontal axis, bandgap voltage (V BG ) is represented by trace 32. The bandgap voltage (VBG ) is obtained by dividing the PTAT voltage (trace 34) by the complementary to absolute temperature (CTAT) voltage (trace 36) (i.e., the base to emitter voltage (V BE )) is generated by appropriately scaling the base-to-emitter voltage (dV BE ) is generated by the increment in ). The BJT and associated bandgap core circuitry can be used to generate PTAT and CTAT voltages. Such voltages increase and decrease linearly with temperature, respectively.

[0037] Using basic BJT equations to reveal the circuit diagram with resistors R1, R2, and R3 and diodes D1 and D2 Figure 1 The PTAT voltage in the bandgap core 12A depends only on its resistor ratio:

[0038]

[0039] Where V t is the thermal voltage, and Jc1 and Jc2 are the corresponding current densities of diodes D1 and D2. This equation is only valid when R2=R3. However, as is understood in the art, similar equations can be derived for cases where R2 and R3 have different values. The ratio of CTAT to PTAT can be selected so that the resulting bandgap voltage (V BG )like Figure 2 The generalized curve 30 of is shown as being substantially temperature invariant, ie, constant or flat over the expected operating temperature range. This represents an ideal case with no curvature.

[0040] Reference again Figure 1 , a generalized implementation is illustrated via circuit 10. The biasing of auxiliary diode D3 via bias current Ic3 can be fine-tuned during manufacturing via trimming element 20 in a manner that produces a voltage drop across resistors R4 and R5, through which the auxiliary input is provided to bandgap core 12A. This has the beneficial effect of injecting the fine-tuned bias current Ic3 into the auxiliary portion 12B of the bandgap circuit 12. Because diode D3 is biased by bias current Ic3, the voltage drop across resistors R4 and R5 is effectively proportional to the set point of trimming element 20. Since the set point of trimming element 20 directly controls the dV across resistors R4 and R5 BE , which to some extent is also controlled by Figure 2 The trace 32 represents the components of the PTAT voltage. The PTAT voltage is based on the magnitude of the trimmed bias current Ic3 produced by control of the trimming element 20 during trimming, and thus the present method is a form of a PTAT-based trimming strategy.

[0041] Current mirror ratio: As will be appreciated by those skilled in the art, current mirrors are often used in analog ICs to replicate a given current in different circuit branches. Figure 1 The current source 19 or Figure 4 When the current source 190 is constructed as a current mirror as shown, the mirror ratio can be changed to provide an output current greater than a specific reference current from the bandgap core 12A. That is, the bias current Ic3 can be fine-tuned by changing the mirror ratio of the current source 190. By way of example and not limitation, a voltage-controlled MOSFET, a transconductance amplifying MOSFET, or a MOSFET with a body bias may be used in one or more implementations to achieve Figure 1 The fine-tuning element 20.

[0042] Using the superposition theorem, the bandgap voltage (V) for the above mirror ratio can be derived including the additional variable: BG ) equation (see Figure 2 ). Assume that Figure 1 A representative bandgap core 12A with R2=R3 and R4=R5, with representative and non-limiting 8X and 1X (relative area) core diodes D1 and D2 (and D2 and D3 of the same area):

[0043]

[0044] Those skilled in the art will appreciate that the mirror ratio can be used to adjust the resulting bandgap voltage (V BG A similar approach can be used when the auxiliary circuit is connected to the curvature compensation circuit.

[0045] Curvature compensation: a brief reference Figure 3 and its voltage (V) and temperature (T) curve 40, base to emitter voltage (V BE )(trace 43) (i.e., the CTAT voltage) may exhibit residual nonlinearity with respect to temperature. The PTAT voltage of trace 44 varies linearly as shown, similar to Figure 2 Here, trace 44 is represented by α*dV BE , where α = R2 / R1. By itself, dV BE It can be expressed as:

[0046]

[0047] Where Ic is the current in the collector of the indicated diode D2 or D1 and A is the emitter area of ​​the same diode D2 or D1.

[0048] Trace 42 corresponds to the bandgap voltage (V BG ), which is the sum of traces 43 and 44. That is, the natural V of a BJT operating at a constant currentBE The temperature curve is slightly quadratic or parabolic in shape, as indicated by the parabolic trajectory of trace 42. Curvature compensation schemes are often used to correct for this curvature. One such scheme is known in the art as the Malcovati curvature compensation strategy, such as Figure 4 The CTAT voltage is determined by the absolute BJT voltage, V BE , which in turn may depend on the saturation current and the bias current. As a result, the reference voltage (V REF ) can show process-related changes.

[0049] Reference now Figure 4 The circuit 100 can be configured to correct the Figure 3 The base-emitter voltage (V BE ) provides the aforementioned curvature compensation when the nonlinearity in the bandgap circuit 12 is not provided. Those skilled in the art will recognize that the auxiliary portion 12B of the proposed bandgap circuit 12 is used for Malcovati curvature compensation. In such a topology, additional resistors 14 labeled R7 and R8 can be used within the current source 190.

[0050] The setting of the ratio of resistors R2 (R2=R3) and R4 (R4=R5) effectively cancels the trace 42 ( Figure 3 )'s natural V BE curvature to counteract the curvature, thereby enhancing temperature stability. Figure 4 When curvature compensation is performed in FIG. 1 , op amp 160 includes an output at node N2 connected to respective gate terminals (G) of the pair of FETs 22A, 22B, a first input (−) connected to reference voltage node N1, and a second input (+) connected to fine tuning element 20.

[0051] In this particular case, the trimming element 20, which includes a trimming resistor R6 having an adjustable set point, is directly connected to or referenced to the negative voltage rail 11. - , i.e., electrically grounded, wherein fine-tuning can be performed via adjustment of the trimming resistor R6. Figure 1 Same, in Figure 4 In the circuit 100 , trimming is performed only outside the bandgap core 12A, thus avoiding residual error accumulation typically associated with adjustment of resistor ratios in the bandgap core 12A.

[0052] As will be appreciated by those skilled in the art in view of the foregoing disclosure, Figure 1 and 4The respective circuits 10 and 100 are suitable for fine-tuning a voltage reference (V REF Typically, such methods will be performed during manufacturing via automatic test equipment (not shown).

[0053] In a possible closed loop implementation, a voltmeter may be connected to node N1. The method may include measuring the output voltage of the circuit 10, 100 as a temperature invariant reference voltage (V REF At the same time, the voltage reference (V REF ) is compared with a predetermined value, such as 1.25V. In addition, the method may include adjusting Figure 1 Circuit 10 or Figure 4 The set point of the fine tuning element 20 of the circuit 100, wherein the fine tuning element 20 is located outside the bandgap core 12A in either case.

[0054] Brief reference Figure 5A , which can be performed during manufacturing to fine-tune the voltage reference (V REF In some embodiments, the method 100M may be performed via a linear scan starting at the low end of the defined scan range. If the trim code is consistent with the resulting voltage reference (V REF ) is unknown, or if the relationship is not stable, i.e., not the same for each manufacturing instance, then it may be necessary to perform a scan of each trim code. Although this process may be relatively time consuming, method 100M may be used in certain applications where trimming time is not critical.

[0055] In an exemplary implementation, such method 100M may begin and proceed to method step / block B102 (“Measure V REF ”), where the output voltage of the bandgap reference circuit 12 is measured as a voltage reference (V REF ). Method 100M then proceeds to block B104.

[0056] At block B104 (“Compare V REF With V TGT ”), method 100M may include, for example, using comparator logic of an associated computer device (not shown) to compare the measured voltage reference (V REF ) and the predetermined or calibrated target value (V TGT ) are compared. Method 100M then proceeds to block B105.

[0057] Box B105 (“V REF =V TGT ”) may include determining the voltage reference (V REF) exceeds the target value (V TGT ). When V REF >V TGT When , method 100M proceeds to box B106, and in the alternative proceeds to box B108.

[0058] Box B106 (“V REF = Final”) includes when the voltage reference (V REF ) is equal to a predetermined value, the voltage reference (V REF ) is set to the final value, that is, V REF =Final. Block B106 then includes ceasing to adjust the set point. Once the final value is achieved, method 100M is completed (“End”), recorded in non-volatile memory, and read back, thereby setting the parameters of adjustable element 20.

[0059] Block B108 ("Adjust Trimming Element") includes adjusting the set point of trimming element 20 located outside bandgap core 12A. This can be accomplished in a variety of ways, including using a successive approximation reduction (SAR) algorithm, a linear incremental approach, or a multi-slope approach, all of which are understood in the art. Importantly, the set point adjustment occurs without modifying the parameters of bandgap core 12A, such that bias current Ic3 is injected into auxiliary portion 12B to change the reference voltage (V REF ).

[0060] like Figure 5B Another method described in 200M can be used to find the voltage reference (V REF ), where "best" as used herein means the code that produces the code closest to the desired target (V TGT ) REF Value specific fine-tuning code. Relative to execution Figure 5A An iterative method may be used to predict the final best code to be used by performing a search in a predictive manner from as few as one iteration (e.g., from one measurement) via method 200M. Figure 5B A fine-tuning approach to help minimize and standardize testing time.

[0061] In order to use this method, you must first fine-tune the code and the resulting V REF The values ​​of 20 and 20 must have a well-defined and stable relationship. In other words, the transfer function that defines the resulting trimming behavior for a given code must be predictable, i.e., each die configured with a trimming element 20 should behave in the same way in response to the same trimming code. To measure randomness, any relevant metric may be utilized, such as, but not limited to, integral nonlinearity (INL) and differential nonlinearity (DNL). As will be appreciated by those skilled in the art, in various embodiments, the voltage reference (V REF) is typically a nonlinear function of the fine-tuning code proportional to a logarithmic, exponential, or linear function.

[0062] Brief reference Figure 6 For the sake of clarity, the trimming resistor R6 is shown in more detail. Figure 4 The resistor 14. The trimmer resistor R6 is connected to Figure 4 FET 22A and op amp 160, as indicated, where for simplicity of illustration, from Figure 6 Such structures are omitted.

[0063] During trimming, the resistance value of the trimming resistor R6 can be adjusted via the switch (S W ) to connect or disconnect the corresponding resistor 140A, 140B, or 140C. Again, this occurs without modifying the non-trimmable bandgap core 12A. In a possible implementation, resistors 140A, 140B, and 140C have different values, such as where resistor 140C is a nominal unit resistor and the resistance value of resistor 140A is 1 / 16 of the resistance value of resistor 140C. th In a possible embodiment, the illustrated intermediate resistor 140C, which is shown as a single element for simplicity of illustration, may be configured as forty-eight (48) series connected resistors. This requires a stable transfer function as described above, which will be limited by the matching characteristics of the internal resistors 140A, 140B, or 140C used to construct the trim resistor R6. The temperature measurement implementation allows for optimized INL / DNL results and benefits from the illustrated ground connection. That is, the switch (S) referenced to ground W ) has a maximum gate-to-source voltage that allows for an optimized resistance between the drain and source resistors (i.e., Rds(on)).

[0064] In this particular scheme, the 8-bit trimming range can be implemented as a segmented DAC that provides a combination of a temperature and pressure range and a binary weight range for optimizing INL / DNL. In this case, for simplicity, the thermometric code is implemented on two ranges. The 8-bit code can be split into 2×4 bits, decoded into sixteen levels, that is, 16×16=256 combinations for a full 8-bit bus. Such an arrangement would correspond to a trimming resistor R6 with thirty-two (32) resident switches (Sw). The thermometric nature of the design helps ensure monotonicity and results in good INL / DNL, and therefore good behavioral predictability.

[0065] Figure 5B The method 200M can be used Figure 6 For faster trimming, a trim resistor R6 with a voltage reference (V REF) for predictive fine-tuning of one or two measurements.

[0066] In representative embodiments, Figure 5B Method 200M may begin at block B201 ("Determine Code"), where an "optimal" initial code and code step size are predefined. For example, a code step size may be set equal to 0.001V, and an 8-bit code will produce a total of 256 available codes (from code 0 to code 255). Block B201 may require determining or defining a specific initial code to be used, which may be a code that makes the voltage reference (V REF ) matches the expected target value (V TGT ), for example, based on historical data from similarly configured circuits. In other words, block B201 may entail determining the most likely code to use on trim resistor R6 to produce the target value (V TGT )'s "best guess" of the correct code. Method 200M then proceeds to block B203.

[0067] Box B203 (“Define V TGT ”) includes defining the above-mentioned target voltage reference, for example, 1.2V in a non-limiting exemplary embodiment. This will likely be the same value used to determine the initial code in block B201. Therefore, blocks B201 and B203 may be performed simultaneously, or in different implementations, block B203 is performed before block B201. Method 200M then proceeds to block B205.

[0068] At block B205 ("Run Code"), the initial best code from block B201 is read from non-volatile memory. Figure 6 The trimmer resistor R6 is required to adjust the control signal (CC U 、CC L ) is transmitted to the switches (Sw), as shown, to switch each switch to a specific corresponding state. Using the segmented DAC 52, this action would require transmitting four bits to the sixteen upper switches (Sw) (i.e., corresponding to Figure 6 The switch of resistor 140A at the upper half of resistor R6) and transmits four bits to the sixteen lower switches (Sw), where "lower" in this case corresponds to resistor 140B and means "referenced to ground", which can also be seen in Figure 4 In other words, Figure 6 The trimming resistor R6 includes a first set of internal resistors and switches and a second set of internal resistors and switches, wherein the segmented DAC 52 is operable to control the corresponding switch states of the first set of switches and the second set of switches (Sw) to connect or disconnect the internal resistors 140A, 140B, and / or 140C. The method 200M then proceeds to block B207.

[0069] Box B207 ("Measure V REF ”) includes, for example, measuring a voltage reference (V REF ). Method 200M then proceeds to box B209.

[0070] At block B209 ("Calculation Code F ”), method 200M includes determining a final optimal final code for fine-tuning. Keeping consistent with the previous example discussion:

[0071]

[0072] Where V REF is the measured voltage reference from block B207, and the "code adjustment" is the amount of change required to transition from the current code (the initial code as described above) to the optimal final code. Using V TGT =1.2V and V REF =1.1V, with a predefined code step size of 0.001V, then the "optimal code" in this example is calculated as (1.2V-1.1V) / 0.001V=100. That is, the fine-tune code=100 will be the amount of change required to adjust from the current code to the optimal code, and thus the voltage reference (V REF ) is adjusted from 1.1 V to 1.2 V. Once the optimal final code has been determined, method 200M then proceeds to block B211.

[0073] Block B211 ("Store / Read") entails storing the code from block B209 in non-volatile memory, and then reading the code during a final verification step. Method 200M then proceeds to block B213.

[0074] Box B213 (“V REF =V TGT ”) includes the measurement voltage reference (V REF ) and compare it with the above target value (V TGT ) for comparison. Although unlikely, one or more of the resistors 140A, 140B, and / or 140C of the trimming resistor R6 may be damaged or defective during manufacturing such that the target value (V TGT ) still exists. In this case, the voltage reference (V REF ) will be equal to the target value (V TGT ) do not match. When this occurs, method 200M proceeds to block B215. Otherwise, method 200M ends.

[0075] At block B215 ("Run Alternative Trim"), method 200M may include using an alternative trim method, e.g., Figure 5A Once the fine-tuning is successfully completed, method 200M ends.

[0076] For higher precision, it may be desirable to use 8 or 9 bits for fine tuning. In order to achieve good predictability, it may be necessary to use some form of thermometric code. That is, each bit of the thermometric code controls whether the corresponding identical unit component is turned on or off. For example, in one or more embodiments, the four bits to the lower switch (Sw) may be binary weighted and the remaining four or five bits to the upper switch (Sw) may be thermometric. In this case, sixteen or thirty-two wires / switches and a separate resistor 140 may be used. Since the fine-tuning resistor R6 must be cut into these component parts, such a construction will be a challenge to implement in the hardware of the bandgap core 12A. In contrast, the present method performs fine tuning entirely outside the bandgap core 12A.

[0077] Therefore, methods 100M and 200M measure the output voltage of the non-trimable bandgap core 12A as a voltage reference (V REF ), the voltage reference (V REF ) is compared with the calibrated target value to determine the voltage difference and the voltage difference is used to calculate the final trim code so that the Figure 1 and 4 The auxiliary part 12B of the method 100M and 200M are both adjusted by the final fine-tuning code respectively. Figure 1 This is done by adjusting the set point of the fine tuning element 20 of the circuit 10 or 100 of the non-trimmable bandgap core 12A or 12A. This occurs without modifying the parameters of the non-trimmable bandgap core 12A, wherein the fine tuning element 20 is arranged in the auxiliary part 12B of the circuit 10, 100 outside the non-trimmable bandgap core 12A. Fine tuning also occurs so that the bias current Ic3 is injected into the auxiliary part 12B to adjust the voltage reference (V REF ) to the target value.

[0078] Now go to Figure 7 , the use of the described non-trimmable bandgap core 12A allows for forgoing the required packaging space and complexity needed to implement trimmable switching hardware. Figure 7 Layout 60 of FIG. 1 provides an example of relative spacing in a highly simplified schematic diagram. In a typical semiconductor die, the total surface area may be allocated to various electrical components and circuits. For example, Figure 4 The op amp 16 (A1) can occupy a considerable area and can be used with the voltage reference (V REF The same is true for any additional circuit system 70 that is not related to the provision of ).

[0079] For example, Figure 4The circuit 100 may package the diodes 18 (D1, D2, D3) very closely to the resistors 14 (R1, R2, R3, R4, R5). The individual diodes 18 and resistors 14 are compactly packaged. Figure 4 The bandgap core 12A is therefore highly complex with very limited packaging space. Although the compact package is less sensitive to temperature, process variations, and stress, it is desirable not to inject noise into the diode 18, for example, from the switches associated with the trimming. Therefore, the trimming resistor R6 can be packaged separately from the bandgap core 12A, as described above and as shown in FIG. Figure 7 , for example, adjacent to resistor 14 but in a separate area of ​​the die. Figure 1 The optional current DAC 27 may also be packaged separately from the components of the bandgap core 12A, with the particular layout varying with the intended application of the chip being fabricated.

[0080] Among other ancillary benefits of the foregoing disclosure, Figure 1 and 4 The circuit topology and associated trimming strategy can be used for high precision references with good area / consumption / precision results. The proposed solution does not require changing the resistor ratios within the non-trimmable bandgap core 12A, nor does the proposed solution contain switches that could interfere with the sensitive bandgap core 12A and its operation. Instead, the PTAT voltage is implemented via the trimming element 20 (referenced to ground), which greatly helps practical implementations since trimming typically requires 8-bit accuracy (256 values) or more. Therefore, the voltage drop (dV) injected into resistors R4 and R5 is BE ), that is, purposeful tuning of the input to op amp 16 is used to change the voltage reference (V REF ) and set it to a desired value during a calibration process. The fine-tuning element 20 is located on a different area of ​​the chip than that occupied by the non-fine-tunable bandgap core 12A. By being non-fine-tunable, the bandgap core 12A forgoes the required packaging space and complexity required to implement fine-tuning switch hardware.

[0081] Essentially, the method described in detail above is characterized by having two dV BE PTAT voltage components: (i) dV from normal operation of bandgap core 12A BE component, and (ii) dV from auxiliary portion 12B by tuning current source 19 or 190 via trimming element 20 BE The bandgap core 12A provides a larger PTAT voltage contribution, for example about 80-90% of the total PTAT voltage, while the auxiliary part 12B will contribute the remaining 10-20%.

[0082] The concepts presented herein are compatible with curvature compensation schemes required to achieve high accuracy, such as but not limited to Figure 4 Malcovati compensation settings can be implemented based on wafer sorting to help reduce test costs. Another practical benefit of the foregoing disclosure is that it can easily utilize an effective 1-point trimming scheme through the use of, for example, thermometric codes. This is because the trimming can be implemented on components referenced to ground or power rails, as described above. Those of ordinary skill in the art who now have the benefit of this teaching will understand these and other benefits of the present disclosure.

[0083] Although several modes for carrying out many aspects of the present teachings have been described in detail, those skilled in the art to which these teachings relate will recognize various alternative aspects for practicing the present teachings within the scope of the appended claims. The above description and drawings are illustrative and exemplary of the entire range of alternative embodiments that will be recognized by ordinary technicians as implied by the included content, structurally and / or functionally equivalent to the included content, or otherwise apparent based on the included content, and are not limited to only those embodiments that are explicitly depicted and / or described. In addition, the present concept explicitly includes combinations and sub-combinations of the described elements and features. The detailed description and drawings are support and description of the present teachings, wherein the scope of the present teachings is limited only by the claims.

Claims

1. A circuit comprising: Non-trimmable bandgap core, current source and auxiliary sections, The non-trimmable bandgap core is configured as an output voltage reference; The current source is coupled to the non-trimmable bandgap core; and The auxiliary portion is located outside the non-tunable bandgap core, and the auxiliary portion includes: an auxiliary diode coupled to the current source; a pair of resistors coupled to the bandgap core; and A trim element is coupled to the current source external to the non-trimmable bandgap core, the trim element having an adjustable set point operable to inject a bias current into the auxiliary portion to change the voltage reference during a voltage reference trimming process.

2. The circuit of claim 1, wherein the trimming element is operable to output a voltage component proportional to absolute temperature to the pair of resistors to change the voltage reference during the voltage reference trimming process.

3. The circuit of claim 2, wherein the non-trimmable bandgap core comprises a first diode and a second diode, and wherein an emitter area of ​​the first diode is at least eight times an emitter area of ​​the second diode.

4. The circuit of claim 1, wherein the current source comprises a current mirror, and wherein the bias current is adjusted by changing a mirror ratio of the current mirror.

5. The circuit of claim 4, wherein the current mirror is formed by a pair of field effect transistors. 6 . The circuit of claim 5 , wherein the pair of field effect transistors comprises a first p-channel metal oxide semiconductor (PMOS) and a second PMOS. 7 . The circuit according to claim 6 , wherein the fine-tuning element is integrated with the first PMOS or the second PMOS.

8. The circuit according to claim 7, further comprising: Base-emitter voltage curvature compensation circuit.

9. The circuit of claim 8, wherein the base-emitter voltage curvature compensation circuit comprises an operational amplifier, the operational amplifier comprising: an output connected to respective gate terminals of the pair of field effect transistors; a first input connected to a reference voltage rail; and A second input is connected to the fine tuning element.

10. The circuit of claim 1, wherein the trimming element comprises a trimming resistor.

11. The circuit of claim 10, wherein the trimming resistor comprises a first set of internal resistors and switches and a second set of internal resistors and switches, further comprising: A segmented digital-to-analog converter is operable to control corresponding switch states of the first group of switches and the second group of switches to connect or disconnect the internal resistor.

12. The circuit of claim 11, wherein the first set of internal resistors and switches and the second set of internal resistors and switches include thirty-two of the internal resistors and thirty-two of the switches.

13. A circuit comprising: Positive voltage rail; Negative voltage rail; Reference voltage rail; a non-trimmable bandgap core coupled to the reference voltage rail and the negative voltage rail; a base-emitter voltage curvature compensation circuit, the base-emitter voltage curvature compensation circuit being connected to the positive voltage rail and the negative voltage rail, the base-emitter curvature compensation circuit comprising a current mirror; Current mirror; an auxiliary diode connected to the current mirror and the negative voltage rail; and a trimming resistor coupled to the current mirror external to the bandgap core, the trimming resistor having an adjustable set point, wherein the trimming resistor is configured such that adjustment of the adjustable set point changes a mirror ratio of the current mirror and thereby injects a bias current into the auxiliary diode during a voltage reference trimming process, thereby changing a voltage reference on the reference voltage rail.

14. The circuit of claim 13, wherein the non-trimmable bandgap core comprises an operational amplifier having a first input terminal and a second input terminal connected to a corresponding resistor, and wherein the trimming resistor is operable to output a voltage component proportional to absolute temperature to the corresponding resistor to change the voltage reference during the trimming process.

15. The circuit of claim 13, wherein the current mirror comprises a pair of field effect transistors. 16 . The circuit of claim 15 , wherein the pair of field effect transistors comprises a first p-channel metal oxide semiconductor (PMOS) and a second PMOS.

17. The circuit of claim 13, wherein the non-trimmable bandgap core comprises a first diode and a second diode having different respective emitter areas, and wherein a current density of the auxiliary diode is equal to a current density of a higher of the different respective emitter areas.

18. A method for trimming a voltage reference in a circuit having a non-trimmable bandgap core, the method comprising: In response to reading an initial trim code from a non-volatile memory, measuring an output voltage of the non-trimable bandgap core as the voltage reference; comparing the voltage reference to a calibration value to determine a voltage difference; using the voltage difference to calculate a final trim code; as well as A set point of a trimming element of the circuit is adjusted via the final trimming code without modifying the non-trimmable bandgap core, the trimming element being arranged in an auxiliary portion of the circuit outside the non-trimmable bandgap core such that a bias current is injected into the auxiliary portion to change the voltage reference to a target value.

19. The method of claim 18, wherein the trim element comprises a trim resistor directly referenced to a negative voltage rail of the circuit or electrical ground, and wherein adjusting the set point of the trim element comprises adjusting a set point of the trim resistor.

20. The method of claim 19, wherein adjusting the set point of the fine tuning element comprises adjusting a set point of a field effect transistor of a current source.

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