Power supply circuit and starting method thereof

Abstract

The invention provides a power supply circuit and a start-up method thereof, which can suppress the excessive change of the power supply voltage generated by a regulator. The power supply circuit includes: a reference voltage generation circuit that generates a reference voltage lower than an input voltage; a first regulator that generates a first power supply voltage higher than the reference voltage on the basis of the input voltage and the reference voltage; a first start-up circuit that controls the reference voltage generation circuit so that the reference voltage rises after the input voltage rises; and a second start-up circuit that controls the first regulator such that the first power supply voltage rises after the reference voltage rises.

Description

Technical Field

[0001] The present disclosure relates to a power supply circuit and a startup method thereof. Background Art

[0002] In order to achieve a stable rise in a reference voltage without overshoot, a power regulator including a start-up circuit for starting a reference voltage generation circuit is known (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2005-208968 Summary of the invention

[0004] A power supply circuit may include: a reference voltage generation circuit that generates a reference voltage lower than an input voltage; and a regulator that generates a power supply voltage higher than the reference voltage based on the input power supply voltage and the reference voltage. In this case, when the reference power supply generation circuit and the regulator start to operate simultaneously with the rise of the input voltage, the internal signal state of the reference power supply generation circuit or the regulator is unstable, so that the transient variation of the power supply voltage may become large.

[0005] The present disclosure provides a power supply circuit and a startup method thereof capable of suppressing transient variation of a power supply voltage generated by a regulator.

[0006] The first aspect is a power supply circuit, comprising:

[0007] a reference voltage generating circuit that generates a reference voltage lower than an input voltage;

[0008] a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage;

[0009] a first startup circuit that controls the reference voltage generation circuit so that the reference voltage rises after the input voltage rises; and

[0010] The second startup circuit controls the first regulator so that the first power supply voltage rises after the reference voltage rises.

[0011] The second method is that in the power supply circuit of the first method,

[0012] The first startup circuit includes a first delay circuit that generates a first time from the rise of the input voltage, and increases the reference voltage after the first time has elapsed.

[0013] The third method is that in the power supply circuit of the second method,

[0014] The first start-up circuit enables a first start-up signal of the reference voltage generation circuit after the first time has elapsed.

[0015] The fourth method is that in the power supply circuit of the third method,

[0016] The reference voltage generating circuit includes a bandgap reference circuit for generating the reference voltage.

[0017] The bandgap reference circuit increases the reference voltage when the first enable signal is active.

[0018] The fifth mode is that in the power supply circuit of the third or fourth mode,

[0019] The second startup circuit increases the first power supply voltage after the first startup signal is valid.

[0020] A sixth aspect is a power supply circuit according to the fifth aspect,

[0021] The second start-up circuit includes a second delay circuit that generates a second time after the first start-up signal becomes active, and increases the first power supply voltage after the second time has elapsed.

[0022] The seventh mode is that in the power supply circuit of the sixth mode,

[0023] The second start-up circuit enables a second start-up signal of the first regulator after the second time has elapsed.

[0024] An eighth aspect is a power supply circuit according to any one of the first to seventh aspects,

[0025] The power supply circuit further includes: a second regulator that generates a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage;

[0026] The second startup circuit controls the second regulator so that the second power supply voltage rises after the first power supply voltage rises.

[0027] The ninth aspect is that in the power supply circuit of the eighth aspect,

[0028] The second startup circuit comprises:

[0029] a second delay circuit that generates a second time from a rise of the reference voltage; and

[0030] a third delay circuit that generates a third time longer than the second time from the rise of the reference voltage,

[0031] After the second time has passed, the first power supply voltage is increased,

[0032] After the third time has elapsed, the second power supply voltage is increased.

[0033] The tenth mode is that in the power supply circuit of the ninth mode,

[0034] The second delay circuit is shared with a portion of the third delay circuit.

[0035] In the eleventh aspect, the first startup circuit increases the reference voltage after a first delay time has elapsed from the increase of the input voltage.

[0036] The second startup circuit increases the first power supply voltage after a second delay time longer than the first delay time has elapsed since the input voltage increases.

[0037] A twelfth aspect is a power supply circuit according to the eleventh aspect,

[0038] The power supply circuit further includes: a second regulator that generates a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage;

[0039] The second startup circuit increases the first power supply voltage and the second power supply voltage after the second delay time has elapsed from the increase of the input voltage.

[0040] The thirteenth aspect is a power supply circuit according to the twelfth aspect,

[0041] When a delay time longer than the second delay time from the rise of the input voltage is set as a third delay time, the second startup circuit increases the first power supply voltage from the second delay time to the third delay time, and increases the second power supply voltage after the third delay time.

[0042] A fourteenth method is a method for starting a power supply circuit, wherein:

[0043] The power supply circuit includes: a reference voltage generating circuit that generates a reference voltage lower than an input voltage; and a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage.

[0044] The reference voltage is increased after the input voltage is increased, and the first power supply voltage is increased after the reference voltage is increased.

[0045] Effects of the Invention

[0046] The present disclosure can suppress transient variation in the power supply voltage generated by the regulator. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a diagram showing a configuration example of a power supply circuit according to the first embodiment.

[0048] Figure 2 This is a timing chart showing an example of voltage behavior when a power supply circuit of a comparison method is started.

[0049] Figure 3 This is a timing chart showing an example of voltage behavior when the power supply circuit according to the first embodiment is started up.

[0050] Figure 4 It is a diagram showing a configuration example of a power supply circuit according to the second embodiment.

[0051] Figure 5 It is a diagram showing a configuration example of a power supply circuit according to the third embodiment.

[0052] Figure 6 It is a diagram showing a configuration example of a power supply circuit according to a fourth embodiment.

[0053] Figure 7 is a diagram showing a configuration example of a reference voltage generating circuit.

[0054] Figure 8 This is a diagram showing a configuration example of a start-up circuit.

[0055] Fig. 9 This is a diagram showing a configuration example of the first regulator.

[0056] Fig.10 This is a diagram showing a configuration example of the second regulator.

[0057] Fig.11 It is a diagram showing a first configuration example of a startup timing control circuit.

[0058] Fig.12 It is a diagram showing a second configuration example of the startup timing control circuit. DETAILED DESCRIPTION

[0059] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0060] Figure 1 It is a diagram showing a configuration example of a power supply circuit according to the first embodiment. Figure 1 The power supply circuit 101 shown generates a first power supply voltage VDD1 and a second power supply voltage VDD2 according to an input voltage VDD, and supplies the second power supply voltage VDD2 to a load 201. The power supply circuit 101 is, for example, a semiconductor integrated circuit that operates with a ground AVSS as a reference potential. The power supply circuit 101 includes a reference voltage generation circuit 40, a first regulator 10, a second regulator 20, and a startup timing control circuit 50.

[0061] The reference voltage generation circuit 40 generates a reference voltage VREF lower than the input voltage VDD. The reference voltage generation circuit 40 generates a constant reference voltage VREF lower than the input voltage VDD using, for example, a bandgap reference circuit 42. The reference voltage generation circuit 40 may generate the reference voltage VREF by a known unit (for example, a voltage divider circuit that divides the input voltage VDD by resistance) without using a bandgap reference circuit.

[0062] The input voltage VDD is, for example, a power supply voltage supplied from outside the power supply circuit 101. For example, a voltage value V1 of the input voltage VDD when it is stable after it rises is 5V, and a constant voltage value V2 of the reference voltage VREF after it rises is 1.25V.

[0063] The first regulator 10 is a circuit that generates a first power supply voltage VDD1 higher than the reference voltage VREF based on the input voltage VDD and the reference voltage VREF. The first regulator 10 is controlled so as to maintain the first power supply voltage VDD1 at a constant voltage value V3 higher than the reference voltage VREF.

[0064] The first regulator 10 is, for example, a linear regulator that controls the first power supply voltage VDD1 to maintain a constant voltage value V3 that is lower than the input voltage VDD and higher than the reference voltage VREF. As a specific example of the first regulator 10, an LDO (Low Drop Out) regulator that operates even when the input-output voltage difference is small can be cited.

[0065] The voltage value V3 of the first power supply voltage VDD1 when it is stable after rising is, for example, 3.3V.

[0066] Alternatively, the first regulator 10 may be a switching regulator that is controlled so as to maintain the first power supply voltage VDD1 at a constant voltage value V3 that is lower or higher than the input voltage VDD and higher than the reference voltage VREF.

[0067] The second regulator 20 is a circuit that generates a second power supply voltage VDD2 higher than the reference voltage VREF based on the first power supply voltage VDD1 and the reference voltage VREF. The second regulator 20 is controlled to maintain the second power supply voltage VDD2 at a constant voltage value V4 higher than the reference voltage VREF.

[0068] The second regulator 20 is a linear regulator that controls the second power supply voltage VDD2 to maintain a constant voltage value V4 that is lower than the first power supply voltage VDD1 and higher than the reference voltage VREF. A specific example of the second regulator 20 is an LDO regulator that operates even when the input-output voltage difference is small.

[0069] The voltage value V4 of the second power supply voltage VDD2 when it is stable after rising is, for example, 1.8V.

[0070] Alternatively, the second regulator 20 may be a switching regulator that is controlled so as to maintain the second power supply voltage VDD2 at a constant voltage value V4 that is lower than or higher than the first power supply voltage VDD1 and higher than the reference voltage VREF.

[0071] The startup timing control circuit 50 controls the startup timings of the first regulator 10 and the second regulator 20 .

[0072] Figure 2 This is a timing chart showing an example of voltage behavior when a power supply circuit of a comparison method is started. Figure 3 1 is a timing chart showing an example of voltage behavior when the power supply circuit of the first embodiment is started. The power supply circuit of the first comparative embodiment is different from the power supply circuit 101 of the first embodiment in that the startup timing control circuit 50 is not provided.

[0073] like Figure 2 As shown in FIG. 1 , when the reference voltage generation circuit 40, the first regulator 10, and the second regulator 20 start operating simultaneously with the rise of the input voltage VDD, there is a case where the internal signal state of the reference voltage generation circuit 40, the first regulator 10, or the second regulator 20 becomes unstable. In this case, the transient fluctuation of the reference voltage VREF, the first power supply voltage VDD1, or the second power supply voltage VDD2 may become large.

[0074] If the transient variation of the reference voltage VREF becomes larger, the possibility of malfunction or breakdown of the first regulator 10 or the second regulator 20 to which the reference voltage VREF is input becomes larger. If the transient variation of the first power supply voltage VDD1 becomes larger, the possibility of malfunction or breakdown of the second regulator 20 to which the first power supply voltage VDD1 is input becomes larger. If the transient variation of the second power supply voltage VDD2 becomes larger, the possibility of malfunction or breakdown of the load 201 to which the second power supply voltage VDD2 is input becomes larger.

[0075] In contrast, Figure 3 In the case of, the reference voltage generating circuit 40 increases the reference voltage VREF after the first delay time d1 has passed from the rise of the input voltage VDD. The startup timing control circuit 50 controls the startup of the first regulator 10 so that the first power supply voltage VDD1 rises after the second delay time d2 has passed from the rise of the input voltage VDD. The second delay time d2 is longer than the first delay time d1. Then, the startup timing control circuit 50 controls the startup of the second regulator 20 so that the second power supply voltage VDD2 rises after the third delay time d3 has passed from the rise of the input voltage VDD. The third delay time d3 is longer than the second delay time d2.

[0076] In this way, after the first delay time d1 has passed from the rise of the input voltage VDD, the reference voltage VREF rises. Furthermore, after the second delay time d2 has passed from the rise of the input voltage VDD, which is longer than the first delay time d1, the first power supply voltage VDD1 rises. Furthermore, after the third delay time d3 has passed from the rise of the input voltage VDD, which is longer than the second delay time d2, the second power supply voltage VDD2 rises. By controlling the rise timing of the voltage generated by each circuit through such a startup method, the voltage generated by each circuit rises after the stability of the internal signal state of the reference voltage generating circuit 40, the first regulator 10, or the second regulator 20 is improved. Thus, as Figure 3 As shown, Figure 2 Compared with the case shown in FIG. 1 , the increase in transient variation of the reference voltage VREF, the first power supply voltage VDD1 or the second power supply voltage VDD2 is suppressed. Therefore, the possibility of malfunction or breakdown of the first regulator 10, the second regulator 20 or the load 201 is reduced.

[0077] exist Figure 3 In the case of , the startup timing control circuit 50 controls the startup of the first regulator 10 so that the first power supply voltage VDD1 rises from the elapse of the second delay time d2 to the elapse of the third delay time d3. As a result, since the first power supply voltage VDD1 rises before the second power supply voltage VDD2 rises, the increase in the transient variation of the second power supply voltage VDD2 generated by the second regulator 20 based on the first power supply voltage VDD1 is suppressed. Therefore, the possibility of malfunction or withstand voltage breakdown of the load 201 is reduced.

[0078] The first delay time d1 is set, for example, to be longer than the time it takes for the input voltage VDD to rise from zero to the voltage value V1. Thus, after the input voltage VDD rises to the voltage value V1 and the stability of the internal signal state of the reference voltage generating circuit 40 is improved, the reference voltage generating circuit 40 can start to increase the reference voltage VREF. Therefore, the increase in the transient variation of the reference voltage VREF is suppressed.

[0079] The second delay time d2 is set, for example, to be longer than the time from when the input voltage VDD rises from zero to when the reference voltage VREF rises from zero to the voltage value V2. Thus, after the reference voltage VREF rises to the voltage value V2 and the stability of the internal signal state of the first regulator 10 is improved, the first regulator 10 can start to increase the first power supply voltage VDD1. Therefore, the increase of the transient variation of the first power supply voltage VDD1 is suppressed.

[0080] The third delay time d3 is set, for example, to be longer than the time from when the input voltage VDD rises from zero to when the first power supply voltage VDD1 rises from zero to the voltage value V5. Thus, after the first power supply voltage VDD1 rises to the voltage value V5 and the stability of the internal signal state of the second regulator 20 is improved, the second regulator 20 can start the rise of the second power supply voltage VDD2. Therefore, the increase of the transient variation of the second power supply voltage VDD2 is suppressed. The voltage value V5 is, for example, higher than the voltage value V4 and lower than the voltage value V3.

[0081] The third delay time d3 may also be set to be longer than the time from when the input voltage VDD rises from zero to when the first power supply voltage VDD1 rises from zero to the voltage value V3. Thus, after the first power supply voltage VDD1 rises to the voltage value V3 and the stability of the internal signal state of the second regulator 20 is improved, the second regulator 20 can start to increase the second power supply voltage VDD2. Therefore, the increase of the transient variation of the second power supply voltage VDD2 is suppressed.

[0082] exist Figure 1 In the embodiment, the reference voltage generation circuit 40 includes a startup circuit 41, which controls the startup of the bandgap reference circuit 42 so that the reference voltage VREF starts to rise after the input voltage VDD rises. The startup circuit 41 is an example of a first startup circuit that increases the reference voltage VREF after the input voltage VDD rises. In addition, the startup circuit 41 is a part of the structure of the reference voltage generation circuit 40, but it can also be a part of the structure of the startup timing control circuit 50.

[0083] The startup circuit 41 may include a first delay circuit that generates a first time T1 from the rise of the input voltage VDD. The startup circuit 41 enables the startup signal STA of the reference voltage generation circuit 40 after a predetermined first time T1 has passed from the rise of the input voltage VDD. The startup signal STA is an example of a first startup signal. The first time T1 corresponds to the first delay time d1.

[0084] The startup timing control circuit 50 controls the startup of the first regulator 10 so that the first power supply voltage VDD1 starts to rise after the reference voltage VREF rises. The startup timing control circuit 50 is an example of a second startup circuit that increases the first power supply voltage VDD1 after the reference voltage VREF rises.

[0085] The start timing control circuit 50 includes a first control circuit 55 that enables the enable signal CE1 of the first regulator 10 after a predetermined second time T2 has passed since the start signal STA was enabled. The first control circuit 55 is an example of a second delay circuit that generates the second time T2 from the rise of the reference voltage VREF, or an example of a second delay circuit that generates the second time T2 from the first start signal being enabled.

[0086] When the enable signal CE1 is active, the first regulator 10 increases the first power supply voltage VDD1. Thus, the first regulator 10 can increase the first power supply voltage VDD1 after the second delay time d2 has elapsed from the increase of the input voltage VDD. The enable signal CE1 is an example of a second start signal.

[0087] The start timing control circuit 50 includes a second control circuit 56 that enables the enable signal CE2 of the second regulator 20 after a predetermined third time T3 has passed since the start signal STA was enabled. The second control circuit 56 is an example of a third delay circuit that generates a third time T3 longer than the second time T2 from the rise of the reference voltage VREF, or an example of a third delay circuit that generates the third time T3 from the activation of the first start signal.

[0088] When the enable signal CE2 is active, the second regulator 20 increases the second power supply voltage VDD2. Thus, the second regulator 20 can increase the second power supply voltage VDD2 after the third delay time d3 has elapsed from the increase of the input voltage VDD. The enable signal CE2 is an example of a third start signal.

[0089] Figure 4 1 is a diagram showing a configuration example of a power supply circuit according to a second embodiment. In the second embodiment, the configuration, operation, and effects that are the same as those of the first embodiment are omitted by citing the above description. The power supply circuit 102 according to the second embodiment is different from the power supply circuit 101 according to the first embodiment in that the second regulator 20 generates a second power supply voltage VDD2 higher than the reference voltage VREF based on the input voltage VDD and the reference voltage VREF.

[0090] In the second embodiment, the second regulator 20 is, for example, a linear regulator that is controlled to maintain the second power supply voltage VDD2 at a constant voltage value V4 that is lower than the input voltage VDD and higher than the reference voltage VREF. The second regulator 20 may also be a switching regulator that is controlled to maintain the second power supply voltage VDD2 at a constant voltage value V4 that is lower than or higher than the input voltage VDD and higher than the reference voltage VREF.

[0091] In a second embodiment, by Figure 3 By controlling the rising timing of the voltage generated by each circuit, transient fluctuations of the reference voltage VREF, the first power supply voltage VDD1 or the second power supply voltage VDD2 are suppressed. This reduces the possibility of malfunction or breakdown of the first regulator 10, the second regulator 20 or the load 201.

[0092] In the second embodiment, the startup timing control circuit 50 may control the startup of the first regulator 10 and the second regulator 20 so that the first power supply voltage VDD1 and the second power supply voltage VDD2 rise simultaneously after the second delay time d2 has elapsed from the rise of the input voltage VDD. Thus, since the transient variation of the first power supply voltage VDD1 or the second power supply voltage VDD2 is suppressed, the possibility of malfunction or withstand voltage breakdown of the second regulator 20 or the load 201 is reduced.

[0093] Figure 5 1 is a diagram showing a configuration example of a power supply circuit according to a third embodiment. In the third embodiment, the configuration, operation, and effects that are the same as those of the first embodiment are omitted by citing the above description. The power supply circuit 103 according to the third embodiment is different from the power supply circuit 101 according to the first embodiment in that the second regulator 20 is not provided and the first power supply voltage VDD1 generated by the first regulator 10 is supplied to the load 201.

[0094] In a third embodiment, by Figure 3 By controlling the rising timing of the voltage generated by each circuit in this way, transient fluctuations of the reference voltage VREF or the first power supply voltage VDD1 are suppressed. This reduces the possibility of malfunction or breakdown of the first regulator 10 or the load 201.

[0095] Figure 6 1 is a diagram showing a configuration example of a power supply circuit according to a fourth embodiment. In the fourth embodiment, the configuration, function, and effect similar to those of the first embodiment are omitted by citing the above description. The power supply circuit 104 according to the fourth embodiment differs from the power supply circuit 101 according to the first embodiment in that it further includes a third regulator 30.

[0096] The third regulator 30 is a circuit that generates a third power supply voltage VDD3 higher than the reference voltage VREF based on the input voltage VDD and the reference voltage VREF. The third regulator 30 is controlled so as to maintain the third power supply voltage VDD3 at a constant voltage value V6 higher than the reference voltage VREF. The third power supply voltage VDD3 is supplied to the load 202.

[0097] The third regulator 30 is a linear regulator that controls the third power supply voltage VDD3 to maintain a constant voltage value V6 that is lower than the input voltage VDD and higher than the reference voltage VREF. A specific example of the third regulator 30 is an LDO regulator that operates even when the input-output voltage difference is small.

[0098] The voltage value V6 of the third power supply voltage VDD3 when it is stable after rising is, for example, 2.5V.

[0099] Alternatively, the third regulator 30 may be a switching regulator that is controlled so as to maintain the third power supply voltage VDD3 at a constant voltage value V6 that is lower or higher than the input voltage VDD and higher than the reference voltage VREF.

[0100] In a fourth embodiment, by Figure 3 By controlling the rising timing of the voltage generated by each circuit, transient fluctuations of the reference voltage VREF, the first power supply voltage VDD1, the second power supply voltage VDD2, or the third power supply voltage VDD3 are suppressed. As a result, the possibility of malfunction or withstand voltage breakdown of the first regulator 10, the second regulator 20, the third regulator 30, the load 201, or the load 202 is reduced.

[0101] In the fourth embodiment, the startup timing control circuit 50 can control the startup of the first regulator 10 and the third regulator 30 so that the first power supply voltage VDD1 and the third power supply voltage VDD3 rise at the same time or at different times after the second delay time d2 has passed since the input voltage VDD rises. As a result, since the transient variation of the first power supply voltage VDD1 or the third power supply voltage VDD3 is suppressed, the possibility of malfunction or withstand voltage breakdown of the second regulator 20, the load 201 or the load 202 is reduced.

[0102] After the predetermined second time T2 or the predetermined fourth time T4 has passed after the start signal STA is valid, the start timing control circuit 50 enables the enable signal CE3 of the third regulator 30. When the enable signal CE3 is valid, the third regulator 30 increases the third power supply voltage VDD3. Thus, the third regulator 30 can increase the third power supply voltage VDD3 after the second delay time d2 has passed since the input voltage VDD rises. The enable signal CE3 is an example of the fourth start signal.

[0103] Figure 7 2 is a diagram showing a configuration example of a reference voltage generating circuit. The reference voltage generating circuit 40 includes a start-up circuit 41 and a bandgap reference circuit 42 .

[0104] The start-up circuit 41 activates the start-up signal STA for controlling the start-up of the reference voltage generating circuit 40 so that the reference voltage VREF starts to rise after a predetermined first time T1 has elapsed from the rise of the input voltage VDD. The first time T1 corresponds to the first delay time d1.

[0105] The bandgap reference circuit 42 includes resistors R1, R2, R3 and R4, a pair of diodes (here, diode-connected PNP bipolar transistors Q1 and Q2), and an operational amplifier 43. The bandgap reference circuit 42 may also be other well-known circuit structures.

[0106] The operational amplifier 43 operates with an input voltage VDD. The operational amplifier 43 has a non-inverting input terminal connected to a node N1 between the emitter of the bipolar transistor Q1 and the resistor R1, and an inverting input terminal connected to a node N2 between the resistor R2 and the resistor R3. The resistor R3 is connected in series between the node N2 and the emitter of the bipolar transistor Q2. The output terminal of the operational amplifier 43 is connected to the node N1 via the resistor R4 and the resistor R1, and is connected to the node N2 via the resistor R4 and the resistor R2.

[0107] The bandgap reference circuit 42 has such a configuration, and can maintain the reference voltage VREF at a constant value (approximately 1.25 V) regardless of changes in the input voltage VDD or changes in the ambient temperature.

[0108] When the start signal STA is active, the bandgap reference circuit 42 increases the reference voltage VREF. Thus, the reference voltage generation circuit 40 can start outputting the reference voltage VREF after the input voltage VDD increases to the stable voltage value V1 and the stability of the internal signal state of the bandgap reference circuit 42 is improved.

[0109] For example, when the start signal STA is activated, the input voltage VDD is applied to the operational amplifier 43. As a result, the reference voltage VREF starts to be output from the reference voltage generation circuit 40 to the above-mentioned regulators.

[0110] Figure 8 1 is a diagram showing a configuration example of a startup circuit. The startup circuit 41 includes a first delay circuit 80 that generates a first time T1 after the input voltage VDD rises. The startup circuit 41 activates a startup signal STA for increasing the reference voltage VREF after the first time T1 has passed.

[0111] The first delay circuit 80 has a capacitor 82, a charging circuit 81 that charges the capacitor 82 with an input voltage VDD, and a buffer circuit 83 that receives the voltage of the capacitor 82 and outputs a start signal STA. The charging circuit 81 includes a plurality of MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) connected in series with the capacitor 82. The plurality of MOSFETs include a first diode-connected MOSFET and a plurality of second MOSFETs whose gates are connected to each other. The source of the first MOSFET is connected to a terminal of the input voltage VDD. Each gate of the plurality of second MOSFETs is connected to the ground AVSS.

[0112] Fig. 9 1 is a diagram showing a configuration example of a first regulator. The first regulator 10 includes an output transistor 11, an input circuit 12, an error amplifier 13, a feedback circuit 14, and a discharge transistor 16. The input circuit 12 includes an inverter 12a and an inverter 12b. The feedback circuit 14 includes a capacitor 14c and bleeder resistors 14a and 14b.

[0113] When the enable signal CE1 is valid, the input circuit 12 turns off the discharge transistor 16 through the output of the inverter 12a, and starts the error amplifier 13 that controls the output transistor 11 through the output of the inverter 12b. The error amplifier 13 controls the gate of the output transistor 11 according to the difference between the reference voltage VREF from the reference voltage generation circuit 40 and the output feedback voltage from the feedback circuit 14. Thus, the first regulator 10 maintains the first power supply voltage VDD1 at a constant voltage value.

[0114] When the enable signal CE1 is inactive, the input circuit 12 turns on the discharge transistor 16 through the output of the inverter 12a, and stops the error amplifier 13 controlling the output transistor 11 through the output of the inverter 12b. Thus, the first regulator 10 decreases the first power supply voltage VDD1 toward zero.

[0115] Fig.10 2 is a diagram showing a configuration example of a second regulator. The second regulator 20 includes an output transistor 21, an input circuit 22, an error amplifier 23, a feedback circuit 24, and a discharge transistor 26. The input circuit 22 includes an inverter 22a and an inverter 22b. The feedback circuit 24 includes a capacitor 24c and bleeder resistors 24a and 24b. The size of the output transistor and the resistance value of the bleeder resistor of the second regulator 20 are different from those of the first regulator 10.

[0116] When the enable signal CE2 is valid, the input circuit 22 turns off the discharge transistor 26 through the output of the inverter 22a, and starts the error amplifier 23 for controlling the output transistor 21 through the output of the inverter 22b. The error amplifier 23 controls the gate of the output transistor 21 according to the difference between the reference voltage VREF from the reference voltage generation circuit 40 and the output feedback voltage from the feedback circuit 24. Thus, the second regulator 20 maintains the second power supply voltage VDD2 at a constant voltage value.

[0117] When the enable signal CE2 is inactive, the input circuit 22 turns on the discharge transistor 26 through the output of the inverter 22a, and stops the error amplifier 23 controlling the output transistor 21 through the output of the inverter 22b. Thus, the second regulator 20 decreases the second power supply voltage VDD2 toward zero.

[0118] Fig.11 1 is a diagram showing a first configuration example of a startup timing control circuit. The startup timing control circuit 50A is an example of the startup timing control circuit 50. The startup timing control circuit 50A includes a plurality of (four in this example) delay circuits 51, 52, 53, and 54 having the same configuration.

[0119] The delay circuit 51 includes a transistor 51a, a capacitor 51b, a constant current source 51c, and an inverter circuit 51d. The transistor 51a is turned on or off according to the logic level of the start signal STA input to the gate. The capacitor 51b is connected in parallel with the transistor 51a. The capacitor 51b is discharged by turning on the transistor 51a, and is charged by the constant current supplied from the constant current source 51c by turning off the transistor 51a. The inverter circuit 51d outputs the signal after inverting the voltage level of the capacitor 51b to the delay circuit 52 of the next stage. The outputs of the delay circuits of the previous stage are input to the delay circuits 52, 53, and 54, respectively.

[0120] After a predetermined second time T2 has passed since the start signal STA is activated, the delay circuits 51 and 52 activate the enable signal CE1 of the first regulator 10. The delay circuits 51 and 52 are examples of second delay circuits that generate the second time T2 from the rise of the reference voltage VREF.

[0121] After a predetermined third time T3 has passed since the start signal STA was activated, the delay circuits 51, 52, 53, 54 activate the enable signal CE2 of the second regulator 20. The delay circuits 51, 52, 53, 54 are examples of third delay circuits that generate a third time T3 longer than the second time T2 from the rise of the reference voltage VREF.

[0122] Delay circuits 51 and 52 for generating enable signal CE1 and delay circuits 51, 52, 53, and 54 for generating enable signal CE2 share a portion. By sharing a portion of the circuit, the circuit scale of the start-up timing control circuit 50A for generating enable signals CE1 and CE2 can be reduced.

[0123] Fig.12 is a diagram showing a second configuration example of a startup timing control circuit. The startup timing control circuit 50B is an example of the startup timing control circuit 50. The startup timing control circuit 50B includes: a voltage divider circuit 61 that performs resistance voltage division on a reference voltage VREF; a voltage divider circuit 62 that performs resistance voltage division on an input voltage VDD; and a comparison circuit 63 that compares the voltage division output of the voltage divider circuit 61 with the voltage division output of the voltage divider circuit 62. When the reference voltage VREF is higher than the first divided voltage of the input voltage VDD, the comparison circuit 63 enables the enable signal CE1. The voltage divider circuits 61, 62 and the comparison circuit 63 function as a second delay circuit that generates a second time T2 from the rise of the reference voltage VREF.

[0124] The startup timing control circuit 50B includes a voltage divider circuit 71 that performs resistance voltage division on a first power supply voltage VDD1, a voltage divider circuit 72 that performs resistance voltage division on an input voltage VDD, and a comparison circuit 73 that compares a voltage division output of the voltage divider circuit 71 with a voltage division output of the voltage divider circuit 72. When the first power supply voltage VDD1 is higher than a second divided voltage of the input voltage VDD, the comparison circuit 73 enables the enable signal CE2. The voltage divider circuits 71, 72 and the comparison circuit 73 function as a third delay circuit that generates a third time T3 that is longer than the second time T2 from the rise of the reference voltage VREF.

[0125] As described above, the embodiments are described, but the above embodiments are proposed as examples, and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other ways, and various combinations, omissions, substitutions, changes, etc. can be made without departing from the scope of the main purpose of the invention. These embodiments and their variations are included in the scope and main purpose of the invention, and are included in the invention described in the scope of the patent protection requested and the scope equivalent thereto.

[0126] Explanation of symbols

[0127] 10First Regulator

[0128] 12 Input Circuit

[0129] 12a, 12b Inverter

[0130] 12b Inverter

[0131] 13 Error Amplifier

[0132] 14 Feedback Circuit

[0133] 14a, 14b bleeder resistor

[0134] 14c capacitor

[0135] 15, 16 discharge transistor

[0136] 20 Second Regulator

[0137] 21 output transistors

[0138] 22 Input Circuit

[0139] 22a, 22b Inverter

[0140] 23 Error Amplifier

[0141] 24 Feedback Circuit

[0142] 24a, 24b bleeder resistor

[0143] 24c capacitor

[0144] 25, 26 Discharge transistor

[0145] 30Third regulator

[0146] 40 Reference voltage generation circuit

[0147] 41 Starter circuit

[0148] 42 Bandgap Reference Circuit

[0149] 43 Operational Amplifier

[0150] 50, 50A, 50B start timing control circuit

[0151] 51, 52, 53, 54 delay circuit

[0152] 51a transistor

[0153] 51b capacitor

[0154] 51c constant current source

[0155] 51d inverter circuit

[0156] 55 first control circuit

[0157] 56 Second control circuit

[0158] 61, 62 voltage divider circuit

[0159] 63 Comparison circuit

[0160] 71, 72 voltage divider circuit

[0161] 73 Comparison circuit

[0162] 80 first delay circuit

[0163] 81 Charging Circuit

[0164] 82 Capacitor

[0165] 83 Buffer Circuit

[0166] 101, 102, 103, 104 power supply circuit

[0167] 201, 202 load

[0168] AVSS ground

[0169] N1 and N2 nodes

[0170] Q1, Q2 bipolar transistors

[0171] R1, R2, R3, R4 resistors.

Claims

1. A power supply circuit, characterized in that: have: a reference voltage generating circuit that generates a reference voltage lower than an input voltage; a first regulator that generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage; a first start-up circuit that controls the reference voltage generation circuit so that the reference voltage rises after the input voltage rises; as well as The second startup circuit controls the first regulator so that the first power supply voltage rises after the reference voltage rises.

2. The power supply circuit according to claim 1, characterized in that: The first startup circuit includes a first delay circuit that generates a first time from the rise of the input voltage, and increases the reference voltage after the first time has elapsed.

3. The power supply circuit according to claim 2, characterized in that: The first start-up circuit enables a first start-up signal of the reference voltage generation circuit after the first time has elapsed.

4. The power supply circuit according to claim 3, characterized in that: The reference voltage generating circuit includes a bandgap reference circuit for generating the reference voltage. The bandgap reference circuit increases the reference voltage when the first enable signal is active.

5. The power supply circuit according to claim 3, characterized in that: The second startup circuit increases the first power supply voltage after the first startup signal is valid.

6. The power supply circuit according to claim 5, characterized in that: The second start-up circuit includes a second delay circuit that generates a second time after the first start-up signal becomes active, and increases the first power supply voltage after the second time has elapsed.

7. The power supply circuit according to claim 6, characterized in that: The second start-up circuit enables a second start-up signal of the first regulator after the second time has elapsed.

8. The power supply circuit according to claim 1, characterized in that: The power supply circuit further includes: a second regulator that generates a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage; The second startup circuit controls the second regulator so that the second power supply voltage rises after the first power supply voltage rises.

9. The power supply circuit according to claim 8, characterized in that: The second startup circuit comprises: a second delay circuit that generates a second time from a rise of the reference voltage; as well as a third delay circuit that generates a third time longer than the second time from the rise of the reference voltage, After the second time has passed, the first power supply voltage is increased, After the third time has elapsed, the second power supply voltage is increased.

10. The power supply circuit according to claim 9, characterized in that: The second delay circuit is shared with a portion of the third delay circuit.

11. The power supply circuit according to claim 1, characterized in that: The first startup circuit increases the reference voltage after a first delay time has elapsed from the increase of the input voltage. The second startup circuit increases the first power supply voltage after a second delay time longer than the first delay time has elapsed since the input voltage increases.

12. The power supply circuit according to claim 11, characterized in that: The power supply circuit further includes: a second regulator that generates a second power supply voltage higher than the reference voltage based on the first power supply voltage and the reference voltage; The second startup circuit increases the first power supply voltage and the second power supply voltage after the second delay time has elapsed from the increase of the input voltage.

13. The power supply circuit according to claim 12, characterized in that: When a delay time longer than the second delay time from the rise of the input voltage is set to a third delay time, the second startup circuit increases the first power supply voltage from the second delay time to the third delay time, and increases the second power supply voltage after the third delay time.

14. A method for starting a power supply circuit, the power supply circuit comprising: a reference voltage generating circuit that generates a reference voltage lower than an input voltage; and a first regulator, which generates a first power supply voltage higher than the reference voltage based on the input voltage and the reference voltage, wherein the startup method is characterized in that: The reference voltage is increased after the input voltage is increased, and the first power supply voltage is increased after the reference voltage is increased.

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