Integrated circuit device

Abstract

There is provided an integrated circuit device including: a memory in which pruned data is stored; a sleep register that inputs the trim data to the sleep function block; a normal register that inputs the pruned data to the normal function block; a memory controller that loads the pruned data stored in the memory to the sleep register or the normal register; and a wake-up controller that loads the pruned data stored in the normal register into the sleep register via the memory controller at the time of first self-wake-up after power-up to allow the memory to be loaded for the first time only after power-up. According to the integrated circuit device, the magnitude of current for memory loading in a low-power mode can be reduced.

Description

Technical Field

[0001] Exemplary embodiments of the present disclosure relate to an integrated circuit device. Background Art

[0002] Typically, the integrated circuits that diagnose and manage the battery status are powered by the battery.

[0003] The large battery current draw from these ICs can affect battery life and performance.

[0004] To minimize this effect, the IC uses a low-power mode (sleep mode) and switches to a high-power mode (normal mode) only when needed.

[0005] However, each time the power mode is switched from the low power mode to the high power mode, the integrated circuit performs a memory loading operation.

[0006] This results in increased battery current drain, which may shorten battery life, increase the time required for mode switching, and increase the risk of mode switching failure.

[0007] The background technology of the present disclosure is disclosed in Korean Patent Unexamined Publication No. 10-2018-0057230 (published on May 30, 2018) titled “BATT DIAGNOSTIC APPARATUS AND METHOD”. Summary of the invention

[0008] Various embodiments are directed to an integrated circuit device capable of reducing the amount of current used in memory loading by executing a memory loading operation to be performed only the first time a power mode is switched from a low power mode to a high power mode at powered up.

[0009] In one aspect, the present disclosure provides an integrated circuit device, comprising: a memory in which trim data is stored; a sleep register that inputs the trim data to a sleep function block; a normal register that inputs the trim data to a normal function block; a memory controller that loads the trim data stored in the memory into the sleep register or the normal register; and a wake-up controller that, at the first self-wake-up after power-on, loads the trim data stored in the normal register into the sleep register via the memory controller, so that the memory is only loaded for the first time after power-on.

[0010] The wake-up controller may be configured to power up the memory, the memory controller, the normal registers, and the normal functional blocks upon receiving a stable completion signal from the sleep functional block at power up.

[0011] The memory controller may be configured to load trim data into the sleep registers and the normal registers, and prior to entering the low power mode, load the trim data stored in the normal registers into the sleep registers.

[0012] The memory can be configured to retain trim data even when power is removed (power-off).

[0013] The memory controller may be configured to load the trim data stored in the sleep registers into the normal registers upon external wakeup following a self wakeup.

[0014] The sleep registers may be configured to retain trim data during always-on power supply.

[0015] The normal registers may be configured to retain trim data during both always-on and normal power supply.

[0016] An integrated circuit device according to one aspect of the present disclosure performs a memory load operation to be performed during a first switch from a low power mode to a high power mode at power-on only, thereby reducing the amount of current used for memory loading in the low power mode.

[0017] An integrated circuit device according to another aspect of the present disclosure shortens the time to switch to a high power mode, thereby enabling a quick response to a fault condition.

[0018] An integrated circuit device according to yet another aspect of the present disclosure pre-applies trim data to a functional block, thereby increasing wake-up robustness. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a diagram showing a system configuration to which an integrated circuit device according to an embodiment of the present disclosure can be applied;

[0020] Figure 2 is a block diagram illustrating an integrated circuit device according to an embodiment of the present disclosure;

[0021] Figure 3 is a diagram showing a self-wake-up sequence of an integrated circuit device according to an embodiment of the present disclosure;

[0022] Figure 4 is a diagram showing an external wake-up sequence of an integrated circuit device according to an embodiment of the present disclosure;

[0023] Figure 5 is a diagram showing a memory loading sequence according to an embodiment of the present disclosure;

[0024] Figure 6is a diagram showing an example of reducing a high power mode switching time according to an embodiment of the present disclosure; and

[0025] Figure 7 is a diagram illustrating an example of pre-application pruning data according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] The components described in the example embodiments may be implemented by hardware components, including, for example, at least one digital signal processor (DSP), a processor, a controller, an application-specific integrated circuit (ASIC), a programmable logic element (e.g., a field-programmable gate array (FPGA)), other electronic devices, or a combination thereof. At least some of the functions or processes described in the example embodiments may be implemented by software, and the software may be recorded on a recording medium. The components, functions, and processes described in the example embodiments may be implemented by a combination of hardware and software.

[0027] The method according to the example embodiment may be embodied as a program executable by a computer and may be implemented as various recording media such as a magnetic storage medium, an optical reading medium, and a digital storage medium.

[0028] The various techniques described herein may be implemented as digital electronic circuits, or as computer hardware, firmware, software, or a combination thereof. These techniques may be implemented as a computer program product, i.e., tangibly embodied in an information carrier (e.g., in a machine-readable storage device (e.g., a computer-readable medium)) or tangibly embodied in a propagated signal, for processing by a data processing device (e.g., a programmable processor, a computer, or multiple computers) or controlling the operation of a data processing device. Computer programs may be written in any form of programming language (including compiled or interpreted languages) and may be deployed in any form including stand-alone programs or modules, components, subroutines, or other units suitable for use in a computing environment. Computer programs may be deployed to execute on one computer or on multiple computers at one site, or distributed across multiple sites and interconnected by a communication network.

[0029] For example, processors suitable for executing computer programs include general and special purpose microprocessors, and any one or more processors of any type of digital computer. Typically, the processor will receive instructions and data from a read-only memory or a random access memory or both. The elements of a computer may include at least one processor that executes instructions and one or more memory devices that store instructions and data. Typically, a computer will also include or be connected to one or more mass storage devices (such as magnetic disks, magneto-optical disks, or optical disks) for storing data, to receive data from it, to transfer data to it, or to perform both. Examples of information carriers suitable for implementing computer program instructions and data include semiconductor storage devices, such as: magnetic media (such as hard disks, floppy disks and magnetic tapes), optical media (such as compact disk read only memory (CD-ROM), digital video disk (DVD), etc.), magneto-optical media (such as floppy disks), and read only memory (ROM), random access memory (RAM), flash memory, erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) and any other known computer readable medium. The processor and memory may be supplemented by or integrated into special purpose logic circuits.

[0030] The processor can run an operating system (OS) and one or more software applications running on the OS. The processor device can also access, store, operate, process, and create data in response to the execution of the software. For simplicity, the description of the processor device is used in the singular form; however, those skilled in the art will understand that the processor device may include multiple processing elements and / or multiple types of processing elements. For example, the processor device may include multiple processors or a processor and a controller. In addition, different processing configurations are also possible, such as parallel processors.

[0031] Additionally, non-transitory computer readable media can be any available media that can be accessed by a computer and can include both computer storage media and transmission media.

[0032] This specification includes many details of specific implementations, but it should be understood that these details do not limit any invention or what may be claimed in the specification, but rather describe the features of specific example embodiments. The features described in the specification in the context of various example embodiments may be implemented as a combination in a single example embodiment. Conversely, the various features described in the specification in the context of a single example embodiment may be implemented in multiple example embodiments individually or in appropriate sub-combinations. In addition, features may operate in a particular combination and may be initially described as being claimed in the combination, but in some cases, one or more features may be excluded from the claimed combination, and the claimed combination may be changed to a sub-combination or a modification of the sub-combination.

[0033] Similarly, even if operations are described in a particular order on the accompanying drawings, it should not be understood that the operations need to be performed in a particular order or sequence to obtain the desired results, or that all operations need to be performed. In certain circumstances, multitasking and parallel processing may be advantageous. In addition, it should not be understood that the various device components in the above-described example embodiments need to be separated in all example embodiments, and it should be understood that the above-described program components and devices can be included in a single software product or can be packaged in multiple software products.

[0034] It should be understood that the exemplary embodiments disclosed herein are merely illustrative and are not intended to limit the scope of the present invention. It will be apparent to any person skilled in the art that various modifications may be made to the exemplary embodiments without departing from the spirit and scope of the technical solutions disclosed herein and their equivalents.

[0035] Hereinafter, with reference to the accompanying drawings, embodiments of the present disclosure will be described in detail so that those skilled in the art can easily perform the present disclosure. However, the present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0036] In the following description of the embodiments of the present disclosure, when the detailed description of known functions and configurations incorporated herein may make the subject matter of the present disclosure rather unclear, it will be omitted. Parts of the drawings that are not related to the description of the present disclosure are omitted, and similar parts are represented by similar reference numerals.

[0037] In the present disclosure, components that are distinguished from each other are intended to clearly illustrate each feature. However, this does not necessarily mean that these components are separate. That is, multiple components can be integrated into one hardware or software unit, or a single component can be distributed into multiple hardware or software units. Therefore, unless otherwise stated, such integrated or distributed embodiments are also included in the scope of the present disclosure.

[0038] In the present disclosure, the components described in various embodiments are not necessarily necessary components, and some components may be optional components. Therefore, the embodiment consisting of a subset of the components described in an embodiment is also included in the scope of the present disclosure. In addition, the embodiment that also includes other components in addition to the components described in each embodiment is also included in the scope of the present disclosure.

[0039] Hereinafter, with reference to the accompanying drawings, embodiments of the present disclosure will be described in detail so that those skilled in the art can easily perform the present disclosure. However, the present disclosure can be embodied in many different forms and is not limited to the embodiments described herein.

[0040] In the following description of the embodiments of the present disclosure, when the detailed description of known functions and configurations incorporated herein may make the subject matter of the present disclosure rather unclear, it will be omitted. Parts of the drawings that are not related to the description of the present disclosure are omitted, and similar parts are represented by similar reference numerals.

[0041] In the present disclosure, when a component is referred to as being "linked", "coupled" or "connected" to another component, it should be understood that not only a direct connection relationship but also an indirect connection relationship through an intermediate component may be included. In addition, when a component is referred to as "including" or "having" another component, it may mean that the other component is also included, rather than excluded, unless there is a clear description to the contrary.

[0042] In the present disclosure, unless otherwise specifically stated, the terms first, second, etc. are used only for the purpose of distinguishing one component from another component, and do not limit the order or importance of the components, etc. Therefore, within the scope of the present disclosure, a first component in one exemplary embodiment may be referred to as a second component in another embodiment, and similarly, a second component in one exemplary embodiment may be referred to as a first component.

[0043] In the present disclosure, components that are different from each other are intended to clearly illustrate each feature. However, this does not necessarily mean that these components are separate. That is, multiple components can be integrated into one hardware or software unit, or a single component can be distributed into multiple hardware or software units. Therefore, unless otherwise stated, such integrated or distributed embodiments are also included in the scope of the present disclosure.

[0044] In the present disclosure, the components described in various embodiments are not necessarily necessary components, and some components may be optional components. Therefore, the embodiment consisting of a subset of the components described in an embodiment is also included in the scope of the present disclosure. In addition, the embodiment that also includes other components in addition to the components described in each embodiment is also included in the scope of the present disclosure.

[0045] Hereinafter, an integrated circuit device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings. In the description, for the sake of clarity and convenience of explanation, the thickness of the lines or the size of the components shown in the drawings may be exaggerated. In addition, the terms to be described later are terms defined in consideration of the functions in the present disclosure, which may vary according to the intention of the user or operator or the conventional practice in the art. Therefore, the definitions of these terms should be based on the entire content of this specification.

[0046] Figure 1 is a diagram showing a system configuration to which an integrated circuit device according to an embodiment of the present disclosure can be applied.

[0047] refer to Figure 1 , a plurality of integrated circuits (ICs) 10 may be connected to the battery 20 to diagnose the status of the battery 20 .

[0048] Each of the plurality of ICs 10 always consumes current from the battery 20 .

[0049] To reduce current consumption from the battery, the IC 10 switches from a low power mode (sleep mode) to a high power mode (normal mode) only when needed.

[0050] At each switch from the low power mode to the high power mode, the IC 10 performs a memory load operation, which consumes a large amount of current.

[0051] Therefore, it is necessary to reduce current consumption by limiting memory load operations.

[0052] The integrated circuit device according to an embodiment of the present disclosure performs a memory load operation when switching from a low power mode to a high power mode after the first power-up, and is performed only for the first time at power-up.

[0053] Figure 2 is a block diagram showing an integrated circuit device according to an embodiment of the present disclosure, Figure 3 is a diagram showing a self-wake-up sequence of an integrated circuit device according to an embodiment of the present disclosure, Figure 4 is a diagram showing an external wake-up sequence of an integrated circuit device according to an embodiment of the present disclosure, Figure 5 is a diagram showing a memory loading sequence according to an embodiment of the present disclosure, Figure 6 is a diagram showing an example of reducing a high power mode switching time according to an embodiment of the present disclosure; and Figure 7 is a diagram illustrating an example of pre-application pruning data according to an embodiment of the present disclosure.

[0054] refer to Figure 2According to an embodiment of the present disclosure, the integrated circuit device includes a sleep function block (sleep intellectual properties (IP)) 110, a sleep register 120, a wake-up controller 130, a normal function block 210, a memory 220, a memory controller 230 and a normal register 240.

[0055] The sleep function block 110 , the sleep register 120 , and the wake-up controller 130 operate in a sleep domain 100 that is always on.

[0056] The wake-up controller 130 , the normal function block 210 , the memory 220 , the memory controller 230 , and the normal register 240 operate in the normal domain 200 which is cycled on and off.

[0057] The sleep function block 110 may be an analog function block that operates in a sleep mode.

[0058] The sleep function block 110 may operate with the trim data stored in the sleep register 120 .

[0059] The trimming data may be clock frequency or current information for the corresponding functional block to achieve maximum performance within a power range according to its specification.

[0060] The sleep function block 110 may recognize a wake-up signal.

[0061] During the first self wake-up sequence after power-up, the sleep functional block 110 may communicate a stable completion signal (Power OK) from the wake-up controller 130 .

[0062] The normal function block 210 may be an analog function block that operates in a normal mode.

[0063] The normal function block 210 may operate with the trimmed data stored in the normal register 240 .

[0064] The sleep register 120 may be always powered on to retain the trim data.

[0065] The sleep register 120 may input the trim data to the sleep function block 110 , thereby allowing the sleep function block 110 to apply the trim data in the sleep register 120 .

[0066] Before entering the low power mode upon self-wake-up, in response to a control command from the memory controller 230 , the sleep register 120 may receive the trim data from the normal register 240 and store the trim data therein.

[0067] Upon external wakeup, in response to a control command from the memory controller 230 , the sleep register 120 may load the trim data into the normal register 240 .

[0068] When powered on, the wake-up controller 130 may receive a stabilization completion signal from the sleep function block 110 .

[0069] Upon receiving the stabilization completion signal, the wake-up controller 130 may power on the normal power of the normal domain 200. That is, the wake-up controller 130 may power on the memory 220, the memory controller 230, the normal register 240, and the normal function block 210.

[0070] The wake-up controller 130 enables the memory load operation to be performed only for the first time at power-up.

[0071] That is, at the first self wakeup after power-on, before entering the low power mode, the wakeup controller 130 loads the trim data stored in the normal register 240 into the sleep register 120 via the memory controller 230 .

[0072] Furthermore, at the time of external wakeup after self-wakeup, the wakeup controller 130 loads the trim data stored in the sleep register 120 into the normal register 240 via the memory controller 230 .

[0073] In other words, if Figure 5 As shown, current consumption can be greatly reduced by performing a memory load operation only for the first time at the first self wakeup after power-on, rather than performing a memory load operation every time the low power mode is switched to the high power mode in response to an external wakeup signal.

[0074] The memory 220 may store trimming data therein.

[0075] The memory 220 may transfer the trim data to the normal register 240 in response to a control command from the memory controller 230 .

[0076] The memory 220 retains the trim data even when power is off.

[0077] Normal registers 240 may store trim data therein.

[0078] Normal register 240 may retain trim data during always-on power and normal power supply.

[0079] The normal register 240 may input the trimmed data to the normal function block, thereby allowing the normal function block to apply the trimmed data in the normal register 240 .

[0080] Upon self-wake-up, before entering the low power mode, in response to a control command from the memory controller 230 , the normal register 240 may load the trim data into the sleep register 120 .

[0081] Upon external wakeup, in response to a control command from the memory controller 230 , the normal register 240 may receive the trim data from the sleep register 120 and store the trim data therein.

[0082] At the time of self-wake-up, the memory controller 230 may load the trim data stored in the memory 220 into the sleep register 120 and the normal register 240 .

[0083] Once the trim data is loaded into the sleep register 120 , the sleep function block 110 may apply the trim data stored in the sleep register 120 from that point in time.

[0084] Once the trim data is loaded into the normal register 240 , the normal function block 210 may apply the trim data stored in the normal register 240 from that point in time.

[0085] Subsequently, before entering the low power mode, the memory controller 230 stores the trim data stored in the normal register 240 in the sleep register 120. Therefore, since the sleep register 120 retains the trim data, even when entering the low power mode from the high power mode, the sleep function block 110 retains the trim data stored in the sleep register 120 being applied. On the other hand, since the normal function block is not powered on, the normal function block 210 does not retain the applied trim data.

[0086] This will refer to Figure 3 and Figure 4 Detailed description.

[0087] refer to Figure 3 When self-waking up after power-on, the sleep function block 110 transmits a stabilization completion signal to the wake-up controller 130 .

[0088] When receiving the stabilization completion signal from the sleep function block 110, the wake-up controller 130 powers on the normal domain 200. Therefore, the normal function block 210, the normal register 240, the memory controller 230, and the memory 220 are powered on.

[0089] When normal power is powered on, the wake-up controller 130 activates the operation of the memory controller 230 .

[0090] The memory controller 230 loads the trim data stored in the memory 220 into the sleep register 120 and the normal register 240 .

[0091] Once the trim data is loaded into the sleep register 120 , the sleep function block 110 may apply the trim data stored in the sleep register 120 from that point in time.

[0092] Once the trim data is loaded into the normal register 240 , the normal function block 210 may apply the trim data stored in the normal register 240 from that point in time.

[0093] Subsequently, before entering the low power mode, the memory controller 230 loads the trim data stored in the normal register 240 into the sleep register 120. In this case, since the sleep register 120 retains the trim data, the sleep function block 110 retains the trim data stored in the sleep register 120 being applied even when entering the low power mode from the high power mode. In contrast, since the normal function block is not powered on, the normal function block 210 does not retain the trim data being applied.

[0094] refer to Figure 4 , at the time of external wakeup after self-wakeup, the sleep function block 110 has applied the trimming data in the sleep register 120 through self-wakeup.

[0095] Upon receiving the wake-up signal, the sleep function block 110 transmits wake-up signal reception information to the wake-up controller 130 .

[0096] The wake-up controller 130 powers on the normal domain 200. Therefore, the normal function block 210, the normal register 240, the memory controller 230, and the memory 220 are powered on.

[0097] When the normal power is powered on, the memory controller 230 loads the trim data stored in the sleep register 120 into the normal register 240. Therefore, the normal function block 210 applies the trim data stored in the normal register 240.

[0098] In other words, if Figure 5 As shown, before entering the low power mode, the memory controller 230 can load the trim data stored in the normal register 240 into the sleep register 120 when it wakes up by itself, and then upload the trim data from the sleep register 120 to the normal register 240 when it wakes up externally, so as to allow memory loading to be performed only for the first time after power-on, thereby reducing the amount of current used for memory loading in the low power mode.

[0099] In addition, if Figure 6 As shown, the memory loading time of each IC 10 connected to the battery 20 can be reduced, thereby reducing the memory loading time of a number of ICs 10, which reduces the fault reaction time.

[0100] For example, if it takes about 1ms to load 2k bits of memory, and 20 IC 10s are installed, the total memory loading time can be reduced by 20ms.

[0101] In addition, if Figure 7 As shown, wakeup robustness can be improved by applying pruning data in advance.

[0102] For example, if a 100 kHz oscillator identifying the wake-up pulse frequency is outside the frequency range, the oscillator may not be woken up. However, the present embodiment can overcome the no wake-up problem by preloading the trim data into the sleep register 120 .

[0103] Although the present disclosure has been described with reference to the embodiments shown in the accompanying drawings, these embodiments are merely exemplary, and those skilled in the art will appreciate that various modifications and other equivalent embodiments may be made therefrom. Therefore, the technical protection scope of the present disclosure is limited by the technical solutions of the present disclosure.

Claims

1. An integrated circuit device, comprising: a memory, in which the trimmed data is stored; a sleep register that inputs the trim data to a sleep function block; a normal register that inputs the trimmed data to a normal function block; a memory controller that loads the trim data stored in the memory into the sleep register or the normal register; as well as A wake-up controller loads the trim data stored in the normal register into the sleep register via the memory controller when the controller wakes itself up for the first time after power-on, so as to allow the memory to be loaded only for the first time after power-on.

2. The integrated circuit device according to claim 1, wherein: The wake-up controller is configured to power on the memory, the memory controller, the normal register, and the normal function block upon receiving a stable completion signal from the sleep function block at power-on.

3. The integrated circuit device according to claim 1, wherein: The memory controller is configured to load the trim data into the sleep register and the normal register, and before entering a low power mode, load the trim data stored in the normal register into the sleep register.

4. The integrated circuit device according to claim 1, wherein: The memory is configured to retain the trim data even when power is lost.

5. The integrated circuit device according to claim 1, wherein: The memory controller is configured to load the trim data stored in the sleep register into the normal register upon external wakeup following a self wakeup.

6. The integrated circuit device according to claim 1, wherein: The sleep register is configured to retain the trim data during an always-on power supply.

7. The integrated circuit device according to claim 1, wherein: The normal register is configured to retain the trim data during always-on power and normal power supply.

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