Memory control method and device
By detecting multiple memory channels and selecting normal channels for data transmission, the system unavailability problem caused by abnormal channels in multi-channel memory systems is solved, and the reliability and robustness of the system are improved.
Patent Information
- Application Number
- CN202311079691.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-08-23
- Publication Date
- 2025-02-25
AI Technical Summary
In a multi-channel memory system, if one or more memory channels experience exceptions, the system will not work properly, resulting in reduced reliability and robustness.
By detecting multiple channels of memory, identify at least one normal memory channel, and selecting one or more working memory channels from it for data transmission, avoiding the use of abnormal channels.
When an exception occurs in one or more memory channels, it can still ensure that the memory is normally transmitted and improve the reliability and robustness of the system.
Smart Images
Figure CN119512441A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present application relate to the field of memory technology, and more particularly to a memory control method and device. Background Art
[0002] Memory is an important component of electronic devices, also known as internal memory and main memory. It is used to temporarily store the calculation data in the central processing unit (CPU) and the data exchanged with external memory such as hard disk. In order to increase the bandwidth of memory, multi-memory channel technology is usually used, such as using a 4-memory channel system to form a 64-bit bit width.
[0003] However, if one memory channel in a multi-memory channel system is abnormal, even if the other memory channels are normal, the system will not work properly, which will reduce the reliability and robustness of the system and make the electronic device unable to start up.
[0004] Therefore, how to enable the memory to perform data transmission normally when one or more memory channels of the multi-channel memory are abnormal is one of the problems that technicians in this field need to solve urgently. Summary of the invention
[0005] The embodiment of the present application provides a memory control method and device, which can enable the memory to perform data transmission normally when one or more memory channels of the multi-channel memory are abnormal. To achieve the above purpose, the embodiment of the present application adopts the following technical solutions:
[0006] In a first aspect, an embodiment of the present application provides a memory control method, the method comprising: detecting M memory channels of a memory to determine at least one normal memory channel or at least one abnormal memory channel. Determine at least one working memory channel serving the system from the at least one normal memory channel. Each of the M memory channels is used for N-bit data transmission, and the M memory channels are used together to implement N×M-bit data transmission.
[0007] It can be seen that the method provided in the embodiment of the present application can determine a normal memory channel from multiple memory channels of the memory, and then select a working memory channel for transmitting data from the normal memory channel, thereby avoiding the system from being unable to operate normally due to using an abnormal memory channel in the multi-channel memory to transmit data. As a result, when an abnormality occurs in one or more memory channels of the multi-channel memory, the memory can perform data transmission normally.
[0008] In a possible implementation, first data may be written into a memory using a first memory channel, where the first memory channel is any one of the M memory channels; second data in the memory may be read using the first memory channel; and the first data and the second data may be compared to determine whether the first memory channel is normal or abnormal.
[0009] It is understandable that data will not change when transmitted through a normal memory channel, but data may be lost when transmitted through an abnormal channel. Therefore, data can be input and read through the memory channel, and the memory channel can be judged to be normal or abnormal by comparing whether the input data and the read data are consistent.
[0010] In a possible implementation, the at least one abnormal memory channel may be powered off to reduce power consumption of the memory system.
[0011] In a possible implementation, the at least one working memory channel may be used to perform data transmission when serving the system.
[0012] It can be understood that by using the at least one working memory channel for data transmission, it is possible to avoid using an abnormal memory channel for data transmission during system service, which may cause the system to fail to operate.
[0013] In a possible implementation, the at least one working memory channel is a plurality of working memory channels, and the plurality of working memory channels may be used for data transmission in an interleaved manner.
[0014] It can be understood that using the above-mentioned multiple working memory channels for data transmission in an interleaved manner can balance the load of the memory channels.
[0015] In a possible implementation, the M memory channels of the memory may be detected when the system is started.
[0016] It is understandable that, when the system starts, detecting the M memory channels of the memory can prevent the system from using abnormal memory channels to transmit data due to failure to detect the M memory channels, thereby causing the system to fail to start normally.
[0017] In a possible implementation manner, the data transmission includes at least one of data writing or data reading.
[0018] In a second aspect, the present application implements a memory control device, which includes a detection unit and a processing unit. The detection unit is used to detect M memory channels of the memory to determine at least one normal memory channel or at least one abnormal memory channel, each of the M memory channels is used for N-bit data transmission, and the M memory channels are used together to implement N×M-bit data transmission. The processing unit is used to determine at least one working memory channel serving the system from the at least one normal memory channel.
[0019] In a possible implementation, the detection unit is specifically used to: write first data to the memory using a first memory channel, where the first memory channel is any one of the M memory channels; read second data in the memory using the first memory channel; and compare the first data with the second data to determine whether the first memory channel is normal or abnormal.
[0020] In a possible implementation, the processing unit is further configured to: power off the at least one abnormal memory channel.
[0021] In a possible implementation, the processing unit is further configured to: when serving the system, utilize the at least one working memory channel to perform data transmission.
[0022] In a possible implementation, the at least one working memory channel is a plurality of working memory channels, and the processing unit is specifically configured to: perform data transmission by using the plurality of working memory channels in an interleaved manner.
[0023] In a possible implementation, the detection unit is specifically configured to detect the M memory channels of the memory when the system is started.
[0024] In a possible implementation manner, the data transmission includes at least one of data writing or data reading.
[0025] In a third aspect, an embodiment of the present application further provides a memory control device, which includes: at least one processor, when the at least one processor executes program code or instructions, it implements the method described in the above first aspect or any possible implementation method thereof.
[0026] Optionally, the memory control device may further include at least one memory, and the at least one memory is used to store the program code or instruction.
[0027] In a fourth aspect, an embodiment of the present application further provides a chip, comprising: an input interface, an output interface, and at least one processor. Optionally, the chip further comprises a memory. The at least one processor is used to execute the code in the memory, and when the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation thereof.
[0028] Optionally, the above chip may also be an integrated circuit.
[0029] In a fifth aspect, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, wherein the computer program includes methods for implementing the method described in the above-mentioned first aspect or any possible implementation thereof.
[0030] In a sixth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method described in the first aspect or any possible implementation thereof.
[0031] The memory control device, computer storage medium, computer program product and chip provided in this embodiment are all used to execute the method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the method provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0033] Figure 1 A schematic diagram of a memory provided in an embodiment of the present application;
[0034] Figure 2 A flowchart of a memory control method provided in an embodiment of the present application;
[0035] Figure 3 A schematic diagram of a memory channel detection process provided in an embodiment of the present application;
[0036] Figure 4 A schematic diagram of a data transmission process provided in an embodiment of the present application;
[0037] Figure 5 A schematic diagram of the structure of a memory control device provided in an embodiment of the present application;
[0038] Figure 6A schematic diagram of the structure of a chip provided in an embodiment of the present application;
[0039] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.
[0041] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.
[0042] The terms "first" and "second" and the like in the description and drawings of the embodiments of the present application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.
[0043] In addition, the terms "including" and "having" and any variations thereof mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may optionally include other steps or units that are not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.
[0044] It should be noted that in the description of the embodiments of the present application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of the present application should not be interpreted as having priority or advantage over other embodiments or designs. Specifically, the use of words such as "exemplarily" or "for example" is intended to present related concepts in a specific way.
[0045] The present application embodiment provides a memory control method, which can be applied to a memory. The above memory can be set in an electronic device, Figure 1 A schematic diagram of a memory 100 provided in an embodiment of the present application. Figure 1The memory 100 shown is a storage system including a DDR memory, referred to as a memory for short. The memory 100 may include: a double data rate synchronous dynamic random access memory controller (double data rate controller, DDRC) 101, a memory channel 102 and a DDR device 103. If a description is required, the following embodiments are introduced using DDR as a memory type, but the technical personnel can understand that the technical solution of the embodiment is not limited to DDR type memory, and can also be applied to other types of memory.
[0046] DDRC 101 is used to generate a command to schedule a DDR device according to a request from a processor. And is used to execute the memory control method provided in the embodiment of the present application. DDRC 101 can be located on different chips with memory channel 102 and DDR device 103. For example, DDRC 101 can be located on the same chip as the processor.
[0047] The memory channel 102 is used for data transmission. Each memory channel may correspond to one or more DDR devices 103, and data and memory access commands and addresses may be transmitted to the DDR devices corresponding to the memory channel through the memory channel.
[0048] The memory channel 102 is a bridge connecting the DDR device 103 and the DDRC. The memory channel 102 is responsible for converting the data sent by the DDRC into a signal that complies with the DDR protocol and sends it to the DDR device. Correspondingly, the memory channel 102 is also responsible for converting the data sent by the DDR device into a signal that complies with the DDR physical layer interface (DDR PHY Interface, DFI) protocol and sending it to the DDRC.
[0049] The DDR device 103 is used to store data.
[0050] Exemplarily, the DDR device 103 may be DDR (such as DDR3, DDR4, DDR5, etc.), low power DDR (LPDDR) (such as LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, etc.), graphics DDR (GDDR) (such as GDDR5, GDDR5X or GDDR6), synchronous dynamic random-access memory (SDRAM) or high bandwidth memory (HBM).
[0051] Each DDR device 103 may be a memory particle including a plurality of particle layers (banks), and each bank may include a plurality of memory cells.
[0052] For example, a DDR device with a size of 1 gigabyte (GB) may include 8 banks with a size of 128 megabytes (MB). That is, stacking 8 banks with a size of 128MB together constitutes a DDR device with a size of 1GB. A bank includes multiple cells with a size of 1 byte, and multiple cells can be divided into rows and columns, and rows and columns can be used to uniquely locate a cell.
[0053] In a possible implementation, the memory 100 may further include a memory control device, and the memory control device may exist independently or be integrated in a DDR controller.
[0054] Exemplarily, the memory control device may be a DDR interleave controller (DIC) in a DDR controller. Alternatively, the memory control device may be applied to other types of storage controllers, not limited to DDRC, which is not limited in this embodiment.
[0055] In a possible implementation, the electronic device may be a mobile phone, a tablet computer, an e-reader, a laptop computer, a vehicle-mounted device, a wearable device or other electronic devices.
[0056] Figure 2 A memory control method provided by an embodiment of the present application is shown. The method can be performed by Figure 1 The method comprises:
[0057] S201. Detect M memory channels of a memory to determine at least one normal memory channel or at least one abnormal memory channel.
[0058] Each of the M memory channels is used for N-bit data transmission, and the M memory channels are used together to realize N×M-bit data transmission.
[0059] Exemplarily, four memory channels of the memory may be detected to determine at least one normal memory channel or at least one abnormal memory channel, wherein each of the four memory channels is used for 16-bit data transmission, and the four memory channels are used together to implement 64-bit data transmission.
[0060] It should be noted that an abnormal memory channel may be a damaged memory channel, such as a memory channel damaged due to a poor solder joint on a pin of a memory channel. An abnormal memory channel may also be a memory channel that cannot work properly due to damage to a DDR device corresponding to the memory channel, such as damage to a bank in the DDR device corresponding to the memory channel or damage to a cell in the DDR device. Memory channel abnormality may cause the memory channel or the DDR device corresponding to the memory channel to not work properly. In this embodiment, these two types of damage are collectively referred to as memory channel abnormality.
[0061] It should be noted that the above example is only used to illustrate that the memory includes 4 memory channels. In other implementations, the memory may include more or fewer memory channels, and the embodiments of the present application do not specifically limit this.
[0062] In a possible implementation, the first memory channel may be used to write first data into the memory. The first memory channel may be used to read second data in the memory. The first data and the second data may be compared to determine whether the first memory channel is normal or abnormal. The first memory channel may be any memory channel among the M memory channels.
[0063] For example, the first memory channel can be used to write the first data 0xAAAA to the memory, and the first memory channel can be used to read the second data in the memory. If the second data is 0xAAAA, that is, the second data is consistent with the first data, then it can be determined that the first memory channel is normal. If the second data is not 0xAAAA, that is, the second data is inconsistent with the first data, then it can be determined that the first memory channel is abnormal.
[0064] It is understandable that data will not change when transmitted through a normal memory channel (i.e., the first data written and the second data read using the same memory channel are the same), but data may be lost when transmitted through an abnormal channel. Therefore, data can be input and read through a memory channel, and the memory channel can be judged to be normal or abnormal by comparing whether the input data and the read data are consistent.
[0065] It should be noted that the M memory channels may be detected simultaneously, or one or more memory channels may be detected each time, such as 2 memory channels or 4 memory channels may be detected each time.
[0066] For example, Figure 3 As shown, one memory channel can be detected each time and the number of detected memory channels i can be counted. When the number of detected memory channels i is less than the total number of detected memory channels M, the next memory channel can be detected. When the number of detected memory channels i is not less than the total number of detected memory channels M, the detection is stopped.
[0067] For the i-th detected memory channel, the first data can be written to the memory using the memory channel. The second data in the above memory can be read using the memory channel. If the first data and the second data are consistent, it can be determined that the memory channel is normal, and Flag[i] representing the state of the memory channel can be assigned a value of 1 to indicate that the memory channel is normal. On the contrary, if the first data and the second data are inconsistent, it can be determined that the memory channel is abnormal, and Flag[i] representing the state of the memory channel can be assigned a value of 0 to indicate that the memory channel is abnormal.
[0068] As another example, the first memory channel can be used to write the first data into the memory and calculate the error checking and correction (ECC) code of the first data, and the first memory channel can be used to read the ECC code of the second data in the memory. If the ECC code of the first data and the ECC code of the second data are the same, it can be determined that the first memory channel is normal. If the ECC code of the first data and the ECC code of the second data are different, it can be determined that the first memory channel is abnormal.
[0069] In another possible implementation, the M memory channels of the memory may also be tested by other methods, such as DDR memory built-in self-test (DDR Mbist).
[0070] In a possible implementation, the M memory channels of the memory may be detected when the system is started.
[0071] Among them, the above-mentioned system can be a hardware system, such as a memory system, etc., or it can be a real-time operating system (RealTime eXecutive, RTX), such as Harmony operating system, Android operating system, Windows operating system, etc.
[0072] Exemplarily, when the memory system is powered on, the M memory channels of the memory may be detected.
[0073] It is understandable that, when the system starts, detecting the M memory channels of the memory can prevent the system from using abnormal memory channels to transmit data due to failure to detect the M memory channels, thereby causing the system to fail to start normally.
[0074] In a possible implementation manner, the at least one abnormal memory channel may also be powered off.
[0075] Exemplarily, in addition to powering off the abnormal memory channel, the DDR device corresponding to the abnormal memory channel, the DDR physical layer corresponding to the abnormal memory channel, and the control circuit corresponding to the abnormal memory channel may also be powered off.
[0076] It can be understood that powering off the at least one abnormal memory channel can reduce the power consumption of the memory.
[0077] S202: Determine at least one working memory channel serving the system from at least one normal memory channel.
[0078] In a possible implementation, the at least one working memory channel may be used to perform data transmission when serving the system.
[0079] Exemplarily, two normal memory channels may be determined from three normal memory channels as working channels. When the memory serves a real-time operating system, the two working memory channels may be used for data transmission.
[0080] In a possible implementation, if the at least one working memory channel is a plurality of working memory channels, the plurality of working memory channels may be used in an interleaved manner for data transmission. This process may be performed by the DIC mentioned in the previous embodiment.
[0081] Exemplarily, two normal memory channels may be determined from three normal memory channels as working channels. Since there are multiple working channels, the two working memory channels may be used for data transmission in an interleaved manner.
[0082] The interleaving refers to sequentially transmitting data of the same data granularity using the multiple working memory channels.
[0083] For example, Figure 4 As shown, the two working memory channels can be used for data transmission in an interleaved manner according to the data granularity of 64 bytes. That is, the first 64 bytes of data are transmitted through the first working channel, the second 64 bytes of data are transmitted through the second working channel, the third 64 bytes of data are transmitted through the first working channel, and the fourth 64 bytes of data are transmitted through the second working channel, and so on and so forth until the data transmission is completed.
[0084] It can be understood that using multiple working memory channels for data transmission in an interleaved manner can make the amount of data transmitted by each working memory channel the same, avoid a single working memory channel from transmitting too much data, and thus balance the load of the working memory channels.
[0085] It should be noted that the above example is only used for the data granularity of 64 bytes. In other implementations, data can be transmitted in an interleaved manner using the memory channel according to other data granularities, such as 128 bytes, 256 bytes, etc. The embodiments of the present application do not specifically limit this.
[0086] In a possible implementation, the number of the working memory channels may be 2^K. K may be 0 or a positive integer. For example, the number of the working memory channels may be 1, 2, 4, or 8.
[0087] It is understandable that the number of memory channels in the prior art is generally 2^K. Setting the number of working memory channels to 2^K not only complies with the design conventions in the DDR field, but also reduces the difficulty of using multiple working memory channels in an interleaved manner for data transmission.
[0088] In a possible implementation manner, the data transmission includes at least one of data writing or data reading.
[0089] The following will be combined Figure 5 A memory control device for executing the above memory control method is introduced. The memory control device corresponds to Figure 1 DDRC 101 in.
[0090] It is understandable that, in order to realize the above functions, the memory control device includes hardware and / or software modules corresponding to the execution of each function. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.
[0091] The embodiment of the present application can divide the functional modules of the memory control device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. There may be other division methods in actual implementation.
[0092] In the case of dividing each functional module into corresponding functional modules, Figure 5 A possible schematic diagram of the composition of the memory control device involved in the above embodiment is shown. Figure 5As shown, the memory control device 500 may include: a detection unit 501 and a processing unit 502 .
[0093] The detection unit 501 is used to detect M memory channels of the memory to determine at least one normal memory channel or at least one abnormal memory channel, each of the M memory channels is used for N-bit data transmission, and the M memory channels are collectively used to implement N×M-bit data transmission.
[0094] The processing unit 502 is configured to determine at least one working memory channel serving the system from the at least one normal memory channel.
[0095] In a possible implementation, the detection unit 501 is specifically used to: write first data to the memory using a first memory channel, where the first memory channel is any one of the M memory channels; read second data in the memory using the first memory channel; and compare the first data with the second data to determine whether the first memory channel is normal or abnormal.
[0096] In a possible implementation, the processing unit 502 is further configured to: power off the at least one abnormal memory channel.
[0097] In a possible implementation, the processing unit 502 is further configured to: when serving the system, utilize the at least one working memory channel to perform data transmission.
[0098] In a possible implementation, the at least one working memory channel is a plurality of working memory channels, and the processing unit 502 is specifically configured to: perform data transmission by using the plurality of working memory channels in an interleaved manner.
[0099] In a possible implementation, the detection unit 502 is specifically configured to detect the M memory channels of the memory when the system is started.
[0100] In a possible implementation manner, the data transmission includes at least one of data writing or data reading.
[0101] The embodiment of the present application also provides a chip. Figure 6 A schematic diagram of the structure of a chip 600 is shown. The chip can be arranged in the above-mentioned memory control device or Figure 1 In the DDRC 101 shown, the chip 600 includes one or more processors 601 and an interface circuit 602. Optionally, the chip 600 may further include a bus 603.
[0102] The processor 601 may be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above memory control method may be completed by an integrated logic circuit of hardware in the processor 601 or by instructions in the form of software.
[0103] Optionally, the processor 601 may be a general purpose processor, a digital signal processing (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods and steps disclosed in the embodiments of the present application may be implemented or executed. The general purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
[0104] The interface circuit 602 can be used to send or receive data, instructions or information. The processor 601 can use the data, instructions or other information received by the interface circuit 602 to process, and can send the processing completion information through the interface circuit 602.
[0105] Optionally, the chip also includes a memory, which may include a read-only memory and a random access memory, and provides operation instructions and data to the processor. A portion of the memory may also include a non-volatile random access memory (NVRAM).
[0106] Optionally, the memory stores executable software modules or data structures, and the processor can perform corresponding operations by calling operation instructions stored in the memory (the operation instructions can be stored in the operating system).
[0107] Optionally, the chip can be used in the memory control device involved in the embodiment of the present application. Optionally, the interface circuit 602 can be used to output the execution result of the processor 601. The memory control method provided by one or more embodiments of the embodiment of the present application can refer to the aforementioned embodiments, which will not be repeated here.
[0108] It should be noted that the functions corresponding to the processor 601 and the interface circuit 602 can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.
[0109] Figure 7Schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device 700 can be used to perform any step of the memory control method provided in an embodiment of the present application. Figure 7 As shown, the electronic device 700 includes a processor 701, a transceiver 702, and a communication circuit 703 and Figure 1 The memory 100 shown includes a DDRC 101 , a memory channel 102 and a DDR device 103 .
[0110] The processor 701 may send a request to the memory 100 to schedule the DDR device. For example, the processor 701 may select to call the communication line 703 to send a request to the DDRC 101 to schedule the DDR device. For example, the processor 701 may be located on the same chip as the communication line 703 and the DDR controller 101 in the memory 100. The description of the memory 100 may refer to Figure 1 The description of the illustrated embodiment will not be repeated here.
[0111] Furthermore, the electronic device 700 may further include a memory 704 . The processor 701 , the memory 704 and the transceiver 702 may be connected via a communication line 703 .
[0112] The processor 701 is a central processing unit, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 701 may also be other devices with processing functions, such as circuits, devices, or software modules, without limitation.
[0113] The transceiver 702 is used to communicate with other devices or other communication networks, such as Ethernet, radio access network (RAN), wireless local area network (WLAN), etc. The transceiver 702 can be a module, a circuit, a transceiver or any device capable of achieving communication.
[0114] The transceiver 702 is mainly used for sending and receiving commands and information, etc., and may include a transmitter and a receiver, which respectively send and receive commands and information, etc.; operations other than sending and receiving commands and information, etc. are implemented by the processor.
[0115] The communication line 703 is used to transmit information between the components included in the electronic device 700.
[0116] In one design, the processor may be considered as the logic circuit and the transceiver may be considered as the interface circuit.
[0117] The memory 704 is used to store instructions, where the instructions may be computer programs.
[0118] The memory 704 may be a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memories. The nonvolatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct rambus RAM (DRRAM). The memory 704 may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, etc. It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.
[0119] It should be noted that the memory 704 can exist independently of the processor 701, or can be integrated with the processor 701. The memory 704 can be used to store instructions or program codes or some data, etc. The memory 704 can be located inside the electronic device 700, or outside the electronic device 700, without limitation. The processor 701 is used to execute the instructions stored in the memory 704 to implement the method provided in the above embodiment of the present application.
[0120] In one example, the processor 701 may include one or more processors, such as Figure 7 Processor 0 and processor 1 in.
[0121] As an optional implementation, the electronic device 700 includes multiple processors, for example, Figure 7 In addition to the processor 701, a processor 707 may also be included.
[0122] As an optional implementation, the electronic device 700 further includes an output device 705 and an input device 706. Exemplarily, the input device 706 is a keyboard, a mouse, a microphone, a joystick, and the like, and the output device 705 is a display screen, a speaker, and the like.
[0123] It should be noted that the electronic device 700 may be a chip system or a Figure 7 Devices with similar structures in the chip system. Among them, the chip system can be composed of chips, or it can include chips and other discrete devices. The actions, terms, etc. involved in the various embodiments of this application can refer to each other without limitation. The message name or parameter name in the message exchanged between the various devices in the embodiment of this application is only an example, and other names can also be used in the specific implementation without limitation. In addition, Figure 7 The components shown in the figure do not constitute a limitation on the electronic device 700. Figure 7 In addition to the components shown, the electronic device 700 may include Figure 7 More or fewer components may be shown, or certain components may be combined, or the components may be arranged differently.
[0124] The processor and transceiver described in the present application can be implemented in an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.
[0125] An embodiment of the present application also provides a memory control device, which includes: at least one processor, when the at least one processor executes program code or instructions, the above-mentioned related method steps are implemented to implement the memory control method in the above-mentioned embodiment.
[0126] Optionally, the device may further include at least one memory, and the at least one memory is used to store the program code or instruction.
[0127] An embodiment of the present application also provides a computer storage medium, in which computer instructions are stored. When the computer instructions are executed on a memory control device, the memory control device executes the above-mentioned related method steps to implement the memory control method in the above-mentioned embodiment.
[0128] The embodiment of the present application also provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the memory control method in the above-mentioned embodiment.
[0129] The embodiment of the present application also provides a memory control device, which can be a chip, an integrated circuit, a component or a module. Specifically, the device may include a connected processor and a memory for storing instructions, or the device includes at least one processor for obtaining instructions from an external memory. When the device is running, the processor can execute instructions so that the chip executes the memory control method in the above-mentioned method embodiments.
[0130] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0131] Those of ordinary skill in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.
[0132] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.
[0133] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the above units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.
[0134] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, and may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0135] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0136] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the above methods of each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, Read Only Memory (ROM), Random Access Memory (RAM), disk or optical disk, and other media that can store program codes.
[0137] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A memory control method, characterized in that: The method comprises: Detecting M memory channels of a memory to determine at least one normal memory channel or at least one abnormal memory channel, each of the M memory channels being used for N-bit data transmission, and the M memory channels being used together to implement N×M-bit data transmission; At least one working memory channel serving the system is determined from the at least one normal memory channel.
2. The method according to claim 1, characterized in that The detecting of the M memory channels of the memory to determine at least one normal memory channel or at least one abnormal memory channel includes: Writing first data into a memory using a first memory channel, where the first memory channel is any memory channel among the M memory channels; Reading second data in the memory using the first memory channel; The first data and the second data are compared to determine whether the first memory channel is normal or abnormal.
3. The method according to claim 1 or 2, characterized in that: The method further comprises: The at least one abnormal memory channel is powered off.
4. The method according to any one of claims 1 to 3, characterized in that The method further comprises: When serving the system, the at least one working memory channel is used for data transmission.
5. The method according to claim 4, characterized in that The at least one working memory channel is a plurality of working memory channels, and the at least one working memory channel is used to perform data transmission, including: The plurality of working memory channels are utilized in an interleaved manner for data transmission.
6. The method according to any one of claims 1 to 5, characterized in that The detecting of the M memory channels of the memory includes: When the system starts, the M memory channels of the memory are detected.
7. The method according to any one of claims 1 to 6, characterized in that The data transmission includes at least one of data writing or data reading.
8. A memory control device, characterized in that: The device comprises a detection unit and a processing unit; The detection unit is used to detect M memory channels of the memory to determine at least one normal memory channel or at least one abnormal memory channel, each of the M memory channels is used for N-bit data transmission, and the M memory channels are used together to implement N×M-bit data transmission; The processing unit is used to determine at least one working memory channel serving the system from the at least one normal memory channel.
9. The device according to claim 8, characterized in that The detection unit is specifically used for: Writing first data into a memory using a first memory channel, where the first memory channel is any memory channel among the M memory channels; Reading second data in the memory using the first memory channel; The first data and the second data are compared to determine whether the first memory channel is normal or abnormal.
10. The device according to claim 8 or 9, characterized in that The processing unit is also used for: The at least one abnormal memory channel is powered off.
11. The device according to any one of claims 8 to 10, characterized in that The processing unit is also used for: When serving the system, the at least one working memory channel is used for data transmission.
12. The device according to claim 11, characterized in that The at least one working memory channel is a plurality of working memory channels, and the processing unit is specifically used for: The plurality of working memory channels are utilized in an interleaved manner for data transmission.
13. The device according to any one of claims 8 to 12, characterized in that The detection unit is specifically used for: When the system starts, the M memory channels of the memory are detected.
14. The device according to any one of claims 8 to 13, characterized in that The data transmission includes at least one of data writing or data reading.
15. A memory control device, comprising at least one processor and a memory, characterized in that: The at least one processor executes a program or instruction stored in the memory, so that the memory control device implements the method according to any one of claims 1 to 7.
16. A computer-readable storage medium for storing a computer program, characterized in that: When the computer program is executed on a computer or a processor, the computer or the processor is enabled to implement the method according to any one of claims 1 to 7.
17. A computer program product, comprising instructions, characterized in that: When the instructions are executed on a computer or a processor, the computer or the processor is enabled to implement the method according to any one of claims 1 to 7.