An all-memory-acceleration circuit, chip and device supporting multi-mode convolution

Abstract

The application discloses a kind of support multi-mode convolution's memory computing integrated acceleration circuit, chip and equipment, the memory computing integrated acceleration circuit of the application includes input buffer (1), column address decoder (2) and 64 multiply-accumulate operation arrays (3), the multiply-accumulate operation array (3) includes: row address decoder (31), multi-mode adaptability controller (32), SRAM array (33), multiplier (34) and addition tree network (35), the 64 multiply-accumulate operation arrays (3) share one common column address decoder (2) and are connected to same input buffer (1).The application aims at using the flexibility and scalability inherent in digital CIM, without sacrificing the original CIM storage density, to design efficient control logic, to support various convolutions with minimal additional area cost and maintain high computing efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital SRAM in-memory computing, and particularly relates to a memory-computing integrated acceleration circuit, chip and device supporting multi-mode convolution. BACKGROUND

[0002] With the increase of data movement between CPU and memory unit, SRAM Computing-in-Memory (SRAM-CIM) deep neural network accelerator (SRAM-CIM macro) has two orders of magnitude energy efficiency improvement (63TOPS / W vs 2.827TOPS / W) compared with traditional von Neumann architecture (such as H100). Digital SRAM-CIM has high noise recovery capability and precise computing capability, and is considered as a promising alternative to traditional von Neumann DNN accelerator. The digital SRAM-CIM macro proposed at present adopts weight stationary (WS) in-place computing, which is a computing paradigm with less weight data movement. However, these SRAM-CIM macros still face several challenges: 1) WS cannot bring about reduction of off-chip and on-chip data communication, and additional data movement will bring pressure to bandwidth. 2) WS cannot ensure high utilization of on-chip computing units of certain convolution layers.

[0003] Figure 1 For the comparison of activation data amount of CIM (Computing-in-Memory) macro adopting WS in-place computing in different networks and the calculation resource utilization rate diagram of each layer of MobileNet-V2, Figure 1 (a) in FIG. 1 is a comparison of activation data amount in different networks, Figure 1 the ordinate of (a) in FIG. 1 is the total amount of activation data, the abscissa is the type of network, including VGG16, ResNet18, ResNet50 and MobileNet-V2, the diagonal line legend column chart represents the amount of data actually moved from off-chip to the internal CIM macro, the square legend column chart represents the total amount of activation data of the network, and the data on the left side of the arrow represents the multiple difference between the column chart data. Figure 1 (b) in FIG. 1 is a calculation resource utilization rate diagram of each layer of MobileNet-V2, Figure 1 the ordinate of (b) in FIG. 1 is the calculation resource utilization rate of CIM, and the abscissa is the network level division of MobileNet-V2. As shown in Figure 1CIM macro in different networks. This redundancy is especially evident when performing VGG16. Therefore, for any CIM macro that only supports WS data flow, the problem of data redundancy is inevitable due to the uniformity of CIM macro functionality. Furthermore, we map the MobileNet-V2 network onto a CIM macro with a size of 64x64, as shown in (b) of FIG. 1. Due to the mismatch between the matrix and the CIM size, less than 25% of the CIM is used during the execution of the first convolutional layer. Furthermore, when performing operations other than traditional convolution (e.g., depth convolution in MobileNet-V2), where depth convolution is referred to as DepthWidth (DW) convolution. Due to the inflexibility of the adder tree, the utilization of the CIM macro drops to less than 5%. Figure 1

[0004] Figure 2 DW convolution and its mapping in a traditional 64x64 digital SRAM-CIM macro, standard convolution and its mapping in a traditional 64x64 digital SRAM-CIM macro, and the structure of the digital SRAM-CIM macro and the area ratio of each module. Figure 2 DW convolution and its mapping in a traditional 64x64 digital SRAM-CIM macro, Figure 2 standard convolution and its mapping in a traditional 64x64 digital SRAM-CIM macro, Figure 2 the structure of the digital SRAM-CIM macro and the area ratio of each module, where C represents the number of channels of the input image, I represents the side length of the input image, N represents the number of output channels, kxk represents the size of the convolution kernel, and im2col represents the conversion of the original convolution form to matrix multiplication form for calculation by the im2col method. Figure 2 The calculation process of the digital SRAM-CIM macro is detailed in (c) of FIG. 1. In this setting, the input vector is broadcasted across the entire SRAM array and then multiplied with each column of data in the array. The results are then vertically pooled to form the final output. To mitigate the overhead associated with data exchange in the SRAM array, multiple SRAM arrays typically use a shared set of adder trees. Therefore, once the processing of one matrix is complete, only the adjacent SRAM array needs to be activated for consecutive computation. Specifically, for all SRAM-CIM macros that employ WS data flow, the weight data is stored in the SRAM cells in a fixed order, while the activation data is converted to matrix form by im2col. In a typical neural network, such as Figure 2 ​As shown in (b), there are C activations and N weights. Each weight is convolved with one of the C activation functions to produce the final result. However, in some special networks, such as the DW convolution in MobileNet, each activation requires a corresponding weight. Figure 2 As shown in (a), when we try to apply these types of convolutions to traditional CIM macros, we observe that for traditional neural network convolutions, if N is insufficient to match the size of the CIM macro, the weights cannot occupy all the storage units within the CIM macro. This problem is even more significant for DW convolutions. Furthermore, the amount of activation data after im2col transformation is amplified to varying degrees, leading to repeated movement of activation data. Activation redundancy R can be used to characterize the repeated movement of activation data, and the calculation function expression for activation redundancy R is as follows:

[0005] ,

[0006] In the above formula, W K H K W I and H I Let S represent the width and height of the kernel and activation, respectively, S represent the stride of the convolution, and C represent the number of activation channels. Here, we substitute the parameters of the first layer of the VGG16 model, where S equals 1, W... I and H I Both are 226, W K and H K Since both are 3, C equals 3. This means a total of 1.2 million active data chips from off-chip memory need to be copied, resulting in data movement and bandwidth requirements being 8 times greater than originally needed. Therefore, designing efficient control logic without sacrificing the original CIM storage density has become a critical technical problem that urgently needs to be solved. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide an in-memory computing acceleration circuit, chip and device that supports multi-mode convolution, in order to address the above-mentioned problems of the prior art. The present invention aims to utilize the inherent flexibility and scalability of digital CIM to design efficient control logic without sacrificing the original CIM storage density, so as to support various convolutions with minimal additional area cost and maintain high computing efficiency.

[0008] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0009] The application discloses a kind of support multi-mode convolution's memory computing integrated acceleration circuit, including input buffer, column address decoder and 64 multiply-accumulate operation arrays, the multiply-accumulate operation array includes: row address decoder, for selecting the row of data writing SRAM array for and column address decoder cooperate to complete the accurate writing of data to SRAM array;Multi-mode adaptability controller, for controlling multiply-accumulate operation array according to external input signal Xin, Yin and Zin to carry out convolution or matrix multiplication;SRAM array, for storing weight WS or activation data IS according to the data flow mode of memory computing integrated acceleration circuit;Multiplier, for the bit multiplication operation of the output data of row SRAM array and input buffer output data;Addition tree network, for the data of all multiplier outputs are grouped and added according to control signal and output the outside of memory computing integrated acceleration circuit;The 64 multiply-accumulate operation arrays share a common column address decoder and are connected to the same input buffer.

[0010] Optionally, the SRAM array is composed of SRAM cells, the SRAM cell includes a first transfer gate, a second transfer gate, a third transfer gate, a first inverter, a second inverter and a third inverter, an input signal WBLB of the SRAM cell is connected to a first input end of the first transfer gate, an output end of the first transfer gate is connected to an input end of the third transfer gate in sequence through the first inverter and the third inverter, and an output end of the third transfer gate is used for outputting an output signal RBLB of the SRAM cell, a second input end of the first transfer gate is connected to a write signal WWL, and a control end is connected to a write signal WWLB, a first input end of the second transfer gate is connected to intermediate junction points of the first inverter and the third inverter through a reversely arranged second inverter, a second input end of the second transfer gate is connected to the write signal WWLB, a control end is connected to the write signal WWL, and an output end is connected to the output end of the first transfer gate, one input end of the third transfer gate is connected to the output end of the third inverter, the other input end is connected to a read signal RWL, and a control end is connected to a read signal RWLB, when the write signal WWL and the write signal WWLB are respectively set to "1" and "0", the first transfer gate is activated, data of the input WBLB is written into the SRAM cell, and the data is kept in the SRAM cell through the first inverter and the third inverter; when the read signal RWL and the read signal RWLB are respectively set to "1" and "0", the data stored in the SRAM cell is output as the output signal RBLB through the third transfer gate.

[0011] Optionally, the SRAM array is composed of 64 memory banks, each memory bank contains 4x4 SRAM cells, the storage size of the SRAM array is 1kb, each memory bank is connected to the multiplier through four data read lines, and one column of each memory bank is selected to output in each operation, and the selection process is controlled by a multi-mode adaptive controller; in each clock cycle, the multiplier uses a 4x1 multiplexer to select 4-bit data from the input buffer and perform bit multiplication with the data stored in the SRAM array, and then output the result to the addition tree network, the addition tree network collects the 4-bitx1-bit results according to the requirements of the control logic, and then the collected results are transmitted to the internal shift accumulator, and the shift accumulator uses the shift accumulation method to obtain the final required 4-bitx4-bit or 4-bitx8-bit data and output through the output line NOUT of the addition tree network.

[0012] Optionally, the addition tree network is composed of a 6-layer addition tree and an integration module, wherein the first layer of the addition tree includes 32 two-input adders and an interrupt module IE arranged at the front end of the 32 two-input adders, the two-input adder is composed of a plurality of full adders FA, the first layer of the addition tree is used to receive the multiplication result of 64x4 bits of each SRAM unit output data and input cache input C-CIM data, and the multiplication result is sorted in order of 0-63 sequence of memory banks as an addend. The addend corresponding to the sequence number is added by two two-input adders, and if the two adjacent addends do not need to be added, the corresponding interrupt module IE is enabled to break the addition and directly output, wherein one addend is output to the second layer of the addition tree, and the other addend is output to the third or fourth layer of the addition tree; the second layer of the addition tree includes 16 two-input adders, which are used to add the 32 two-input adders of the first layer of the addition tree two by two, and if there is an addition break in a two-input adder of the two-input adder of the first layer of the addition tree, only the nearest one of the two addends of the two-input adder is taken as the input of the corresponding two-input adder in the second layer of the addition tree; the third layer of the addition tree includes 6 two-input adders and 2 N-2 adder selectors, the two-input adders of the third layer of the addition tree are used to add the outputs of the 12 two-input adders of the second layer of the addition tree, and the two N-2 adder selectors of the third layer of the addition tree are used to add the outputs of the 12 two-input adders of the second layer of the addition tree and the addend broken by the interrupt module IE of the first layer of the addition tree; the fourth layer of the addition tree includes 2 two-input adders and 2 N-2 adder selectors, and the output ends of the 2 two-input adders and 2 N-2 adder selectors in the fourth layer of the addition tree are connected with a shift accumulator RA arranged thereon, the two two-input adders of the fourth layer of the addition tree are used to add the outputs of the 4 two-input adders of the third layer of the addition tree, and the two N-2 adder selectors of the fourth layer of the addition tree are used to add the outputs of the 4 two-input adders of the third layer of the addition tree and the addend broken by the interrupt module IE of the first layer of the addition tree; the fifth layer of the addition tree includes 2 N-2 adder selectors, and the output ends of the 2 N-2 adder selectors in the fifth layer of the addition tree are connected with a shift accumulator RA arranged thereon, the two N-2 adder selectors in the fifth layer of the addition tree are used to add the outputs of the 1 two-input adder and 1 N-2 adder selector of the fourth layer of the addition tree; the sixth layer of the addition tree includes 1 N-2 adder selector, and the output ends of the N-2 adder selector in the sixth layer of the addition tree are connected with a shift accumulator RA arranged thereon, and the N-2 adder selector in the sixth layer of the addition tree is used to add the outputs of the 2 N-2 adder selectors of the fifth layer of the addition tree; the outputs of the shift accumulators RA of each layer of the addition tree are connected with the input ends of the integration module.

[0013] Optionally, the inputs of the full adder FA include three addends A, B and Cin, and the outputs include carry CO and sum S, the carry CO is "1" only when the inputs of the addends A, B and Cin are all "1" or two of the inputs of the addends are "1", otherwise the carry CO is always "0"; the sum S is "0" only when two of the inputs of the addends A, B and Cin are "1" or all of the inputs of the addends are "0", otherwise the sum S is always "1".

[0014] Optionally, the interrupt module IE includes a plurality of one-bit data interrupt modules IE, each of the one-bit data interrupt modules IE is composed of one MOS transistor and one transmission gate, one-bit data Ii input is connected to the input end of the transmission gate, the output end of the transmission gate outputs Ii' and is connected to one input end of a two-input adder, the control end of the transmission gate is connected to control signals Ctr and CtrB respectively, the output end of the transmission gate is grounded through the MOS transistor, and the control end of the MOS transistor is connected to the control signal Ctr, the transmission gate is interrupted when the control signals Ctr and CtrB are "1" and "0", the output Ii' is grounded to zero, and the purpose of interrupting transmission is achieved.

[0015] Optionally, the shift accumulator RA includes: a first N-1 selector for selecting one of input data c_in and 0 based on a control signal ctrl; a three-input adder for performing accumulation calculation on the output of the first N-1 selector, the result of left shift operation of the shift accumulator RA output and input data P_sum; a second N-1 selector for selecting one of the output of the three-input adder and the input data P_sum based on the control signal ctrl; a register for outputting the output data of the second N-1 selector after temporary storage; and a one-bit shifter for performing left shift operation on part of the output of the register as the result of left shift operation of the shift accumulator RA output and inputting the result to the three-input adder.

[0016] Optionally, the multi-mode adaptive controller comprises a plurality of controller modules and a plurality of C-NOT gates, the controller modules comprise a plurality of data channels, each data channel comprises three sub-control modules and a switch connected in sequence, each controller module inputs the internal sub-control modules and the switch by receiving the same input Xin and the respective input Yin, the sub-control modules are connected by a switch and a C-NOT gate, the switch is composed of a transmission gate T0, a MOS tube T2 and an inverter T1, the control ends of the transmission gate T0 and the MOS tube T2 are connected with the input Xin, the transmission gate T0 determines whether to open the output RWL for transmitting the input Yin to the transmission gate T0 according to the input Xin; if the input Xin is set to "1", the transmission gate T0 is opened, the MOS tube T2 is closed, the input Yin is transmitted to the output RWL, and the inverter T1 generates the reverse output RWLB by inverting the input Yin; if the input Xin is set to "0", the transmission gate T0 is closed, the MOS tube T2 is opened, the output RWL is grounded and outputs "0"; the C-NOT gate is composed of a transmission gate T4 and an inverter T3, if the input Xin is set to "1", the inverter T3 works in the form of an inverter, the transmission gate T4 is closed, and the output Yout is the inverse of the input Yin, if the input Xin is set to "0", the inverter T3 works in the form of a transmission gate, and the transmission gate T4 is opened to enhance the Yin input, at this time the output Yout is equal to the input Yin; the sub-control modules output Yout, output RWL and reverse output RWLB based on the preset truth table by inputting Xin and Yin, output Yout is transmitted from left to right to the next sub-control module until it is transmitted to the switch, the output RWL and the reverse output RWLB signals of each sub-control module and the switch are finally output by integration to output the multi-mode adaptive controller, each output RWL and reverse output RWLB controls the data readout of three columns of the SRAM array, and the C-NOT gate obtains the data selection signals of the other five columns of the SRAM array by combining the output RWL and the reverse output RWLB and the input Z for controlling the data readout of the other five columns of the SRAM array.

[0017] In addition, the application further provides a chip comprising a chip body and a memory-compute integrated acceleration circuit arranged in the chip body, wherein the memory-compute integrated acceleration circuit is the aforementioned memory-compute integrated acceleration circuit supporting multi-mode convolution.

[0018] In addition, the application further provides a computer device comprising a microprocessor and a memory connected to each other, wherein the microprocessor comprises the aforementioned memory-compute integrated acceleration circuit supporting multi-mode convolution.

[0019] Compared with the prior art, the application has the following advantages: the memory-compute integrated acceleration circuit supporting multi-mode convolution includes an input buffer, a column address decoder and 64 multiply-accumulate operation arrays, the memory-compute integrated acceleration circuit supporting multi-mode convolution can flexibly switch data flow modes to maintain high utilization of C-CIM under any workload, the application can support multiple convolution modes and flexibly support convolution of different convolution kernel sizes, and the application supports on-chip convolution, greatly reduces off-chip and on-chip data transmission, and saves power consumption and time cost caused by off-chip data transmission to the C-CIM. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 The figure is a comparison of the activation data amount of the CIM using the WS in-place calculation in the prior art in different networks and the per-layer calculation resource utilization graph of MobileNet-V2.

[0021] Figure 2 The figure is a standard convolution of the DW convolution in the prior art and its mapping in the traditional 64*64 digital SRAM-CIM macro, a mapping of the standard convolution in the traditional 64*64 digital SRAM-CIM macro and an area ratio of the digital SRAM-CIM macro structure and each module.

[0022] Figure 3 The figure is a structure schematic diagram of the memory-compute integrated acceleration circuit in the embodiment of the application.

[0023] Figure 4 The figure is a structure schematic diagram of the SRAM array in the embodiment of the application.

[0024] Figure 5 The figure is a structure schematic diagram of the addition tree network in the embodiment of the application.

[0025] Figure 6 The figure is a local structure (the first two layers) schematic diagram of the addition tree network in the embodiment of the application.

[0026] Figure 7 The figure is a structure schematic diagram of the shift accumulator RA in the embodiment of the application.

[0027] Figure 8 The figure is a structure schematic diagram of the multi-mode adaptive controller in the embodiment of the application.

[0028] Figure 9 The figure is a structure schematic diagram of the sub-control module in the embodiment of the application.

[0029] Figure 10 The figure is a control schematic diagram of the SRAM array in the embodiment of the application.

[0030] Figure 11The calculation process of C-CIM in a 3x3 convolution mode in the embodiment of the application.

[0031] Figure 12 The calculation process of C-CIM in a matrix multiplication mode in the embodiment of the application.

[0032] Figure 13 The calculation process of C-CIM in a 5x5 convolution mode in the embodiment of the application.

[0033] Legend: 1, input buffer; 2, column address decoder; 3, multiply-accumulate operation array; 31, row address decoder; 32, multi-mode adaptive controller; 321, controller module; 322, C-NOT gate; 323, sub-control module; 324, switch; 33, SRAM array; 331, first transfer gate; 332, second transfer gate; 333, third transfer gate; 334, first inverter; 335, second inverter; 336, third inverter; 34, multiplier; 35, addition tree network; 351, first N-1 selector; 352, three-input adder; 353, second N-1 selector; 354, register; 355, one-bit shifter. DETAILED DESCRIPTION

[0034] As shown in Figure 3 The embodiment provides a compute-in-memory acceleration circuit (C-CIM) supporting multi-mode convolution, which comprises an input buffer 1, a column address decoder 2, and 64 multiply-accumulate operation arrays (MAC arrays) 3. The multiply-accumulate operation arrays 3 comprise a row address decoder 31 for selecting a row of the SRAM array 33 to which data is written for precise writing of the data to the SRAM array 33 in cooperation with the column address decoder 2; a multi-mode adaptive controller 32 for controlling the multiply-accumulate operation arrays 3 to perform convolution or matrix multiplication according to external input signals Xin, Yin, and Zin; an SRAM array 33 for storing weight values WS or activation data IS according to the data flow mode of the compute-in-memory acceleration circuit; a multiplier 34 for bit multiplication of the output data of the SRAM array 33 and the output data of the input buffer 1; an addition tree network 35 for grouping and adding the data output by all the multipliers 34 according to a control signal and outputting the data outside the compute-in-memory acceleration circuit; and the 64 multiply-accumulate operation arrays 3 share one common column address decoder 2 and are connected to the same input buffer 1.

[0035] In this embodiment, each multiply-accumulate array 3 comprises a 1kb SRAM bitcell and a bit multiplication unit constructed using NOR gates and an adder tree network. The SRAM array is composed of 64 memory banks, each containing a 4x4 12T SRAM bitcell. The 64 banks are divided into 8 blocks, with the first seven blocks each containing 9 banks and the last block containing 1 bank. To enable the simultaneous performance of bit multiplication and addition operations on 64 sets of 4-bit data, each bank is connected to the multiplier via four data read lines, with one column of each bank being selected for output at each operation, the selection being controlled by the controller. At each clock cycle, the multiplier 34 uses a 4x1 multiplexer to select 4-bit data from the input buffer 1 for bit multiplication with data stored in the SRAM array 33 and outputs the result to the adder tree network 35, which, according to the requirements of the control logic, aggregates the 4-bit x 1-bit results, which are then passed to an internal shift-accumulate accumulator, which uses a shift-accumulate method to obtain the final required 4-bit x 4-bit or 4-bit x 8-bit data and outputs it via the output line NOUT of the adder tree network 35.

[0036] As Figure 4As shown, the SRAM array 33 is composed of SRAM cells, each of which includes a first transmission gate 331, a second transmission gate 332, a third transmission gate 333, a first inverter 334, a second inverter 335, and a third inverter 336. An input signal WBLB of the SRAM cell is connected to a first input terminal of the first transmission gate 331. An output terminal of the first transmission gate 331 is connected to an input terminal of the third transmission gate 333 via the first inverter 334 and the third inverter 336 in sequence. An output terminal of the third transmission gate 333 is used to output an output signal RBLB of the SRAM cell. A second input terminal of the first transmission gate 331 is connected to a write signal WWL, and a control terminal thereof is connected to a write signal WWLB. A first input terminal of the second transmission gate 332 is connected to an intermediate connection point of the first inverter 334 and the third inverter 336 via a reversely arranged second inverter 335. A second input terminal of the second transmission gate 332 is connected to the write signal WWLB, a control terminal thereof is connected to the write signal WWL, and an output terminal thereof is connected to the output terminal of the first transmission gate 331. One input terminal of the third transmission gate 333 is connected to an output terminal of the third inverter 336, another input terminal thereof is connected to a read signal RWL, and a control terminal thereof is connected to a read signal RWLB. When the write signal WWL and the write signal WWLB are set to "1" and "0" respectively, the first transmission gate 331 is activated, data of the input WBLB is written into the SRAM cell, and the data is kept in the SRAM cell via the first inverter 334 and the third inverter 336. When the read signal RWL and the read signal RWLB are set to "1" and "0" respectively, the data stored in the SRAM cell is output as the output signal RBLB via the third transmission gate 333.

[0037] In this embodiment, the SRAM array 33 is composed of 64 memory banks, each containing 4x4 SRAM cells, and the storage size of the SRAM array 33 is 1 kb. Each memory bank is connected to the multiplier 34 through four read data lines, and each memory bank selects one column to output in each operation. The selection process is controlled by the multi-mode adaptive controller 32. In each clock cycle, the multiplier 34 uses a 4x1 multiplexer to select 4-bit data from the input buffer 1 and perform bit multiplication with the data stored in the SRAM array 33, and then output the result to the addition tree network 35. The addition tree network 35 collects the 4-bit x 1-bit results according to the control logic requirements, and then passes these collected results to the internal shift accumulator. The shift accumulator uses the shift and accumulation method to obtain the final required 4-bit x 4-bit or 4-bit x 8-bit data and outputs it through the output line NOUT of the addition tree network 35.

[0038] Based on the fact that different sizes of convolution kernels correspond to different accumulation groups, in this embodiment, an addition tree network (ATN) is designed to enhance the interconnection between each adder. This enables the addition tree to automatically split according to the corresponding convolution mode. For example, Figure 5As shown, the addition tree network 35 is composed of 6 layers of addition trees and integration modules, wherein the first layer of addition tree includes 32 two-input adders and interrupt modules IE arranged in front of the 32 two-input adders, the two-input adders are composed of a plurality of full adders FA, the first layer of addition tree is used to receive the 64x4-bit multiplication result of the data output by each SRAM unit and the input cache 1 input C-CIM data, the multiplication result is sorted in order of the sequence of 0-63 of the memory bank as the addend, the addend corresponding to the sequence number is added by two by two through the two-input adder, and if the two adjacent addends do not need to be added, the corresponding interrupt module IE is enabled to break the addition and directly output, wherein one addend is output to the second layer of addition tree, and the other addend is output to the third or fourth layer of addition tree; the second layer of addition tree includes 16 two-input adders, which are used to add the 32 two-input adders of the first layer of addition tree by two, and if there is an addition break in a two-input adder of the two-input adder of the first layer of addition tree, only the nearest one of the two addends of the two-input adder is taken as the input of the corresponding two-input adder in the second layer of addition tree; the third layer of addition tree includes 6 two-input adders and 2 N-2 adder selectors, the two-input adders of the third layer of addition tree are respectively used to add the outputs of the 12 two-input adders of the second layer of addition tree, and the two N-2 adder selectors of the third layer of addition tree are respectively used to add the outputs of the 12 two-input adders of the second layer of addition tree and the addends broken by the interrupt module IE of the first layer of addition tree; the fourth layer of addition tree includes 2 two-input adders and 2 N-2 adder selectors, the output ends of the 2 two-input adders and 2 N-2 adder selectors in the fourth layer of addition tree are connected and arranged with a shift accumulator RA, the two two-input adders of the fourth layer of addition tree are respectively used to add the outputs of the 4 two-input adders of the third layer of addition tree, and the two N-2 adder selectors of the fourth layer of addition tree are respectively used to add the outputs of the 4 two-input adders of the third layer of addition tree and the addends broken by the interrupt module IE of the first layer of addition tree; the fifth layer of addition tree includes 2 N-2 adder selectors, and the output ends of the 2 N-2 adder selectors in the fifth layer of addition tree are connected and arranged with a shift accumulator RA, the two N-2 adder selectors in the fifth layer of addition tree are respectively used to add the outputs of the 1 two-input adder and 1 N-2 adder selector of the fourth layer of addition tree; the sixth layer of addition tree includes 1 N-2 adder selector, and the output ends of the N-2 adder selector in the sixth layer of addition tree are connected and arranged with a shift accumulator RA, the N-2 adder selector in the sixth layer of addition tree is respectively used to add the outputs of the 2 N-2 adder selectors of the fifth layer of addition tree; the outputs of the shift accumulators RA of each layer of addition tree are connected with the input ends of the integration module. Figure 5The addition tree accumulation process of 3x3 convolution mode is described in the middle. Since the SRAM cells of C-CIM are placed in units of 4, 64 SRAM cells are also divided into 16 groups, and since the on-chip convolution of the 3x3 kernel size involves the accumulation of only 9 data each time, data 8 is not accumulated with data 9. At this time, the interrupt module IE between the storage data 8 and data 9 is enabled by the control signal Ctr signal, which separates the accumulation path of data 8 and data 9-11. At this time, data 8 is separately transmitted to the fourth stage of the addition tree and the accumulation result of the first 8 numbers, while data 9-11 is added with the accumulation result of data 12-17, and finally 7 accumulation results are obtained and output. Similarly, when selecting a 5x5 convolution mode, the interrupt module IE interrupts the addition tree network 35 from the center. For matrix multiplication and 7x7 convolution mode, the CTR signal is disabled, and all data is accumulated with adjacent data. The final result is obtained through a 6-stage addition tree.

[0039] Figure 6 The schematic diagram of the local structure (the first two layers) of the addition tree network in the MAC array is shown in FIG. 6. The full adder FA is composed of 20 MOS transistors and 4 inverters, and obtains the carry CO and the addition result S by adding the three addends A, B and Cin. The interrupt module IE is used for interrupt processing of the accumulated signal according to the input Ctr / CtrB signal group. When Ctr / CtrB is set to "1 / 0", the transmission gate is interrupted, the output A' is grounded to zero, and the purpose of interrupting transmission is achieved. When the data is interrupted and transmitted, the original input data is output from the interrupt module IE to the integration module. The integration module integrates the outputs of the interrupt module IE and the full adder FA, and divides the outputs into left and right parts, and adds the left and right data accumulation results Out_L and Out_R of the enabled interrupt module IE.

[0040] The full adder FA is a conventional circuit structure, which is composed of 20 MOS transistors and 4 inverters, and obtains the carry CO and the addition result S by adding the three addends A, B and Cin. As shown in FIG. 7, the inputs of the full adder FA include the addends A, B and Cin, and the outputs include the carry CO and the addition result S. Only when the input addends A, B and Cin are all set to "1" or two of the input addends are set to "1", the output carry CO is "1", otherwise the output carry CO is always "0". When two of the input addends A, B and Cin are set to "1" or all of the three addends are set to "0", the output addition result S is "0", otherwise the output addition result S is always "1". Figure 6

[0041] Figure 6 ​​As shown, the interrupt module IE includes multiple one-bit data interrupt modules IE. Each one-bit data interrupt module IE consists of one MOSFET and one transmission gate. The input one-bit data Ii is connected to the input terminal of the transmission gate. The output terminal of the transmission gate outputs Ii' and is connected to one input terminal of a two-input adder. The control terminal of the transmission gate is connected to the control signals Ctr and CtrB respectively. The output terminal of the transmission gate is grounded through the MOSFET, and the control terminal of the MOSFET is connected to the control signal Ctr. When the control signals Ctr and CtrB are set to "1" and "0" respectively, the transmission gate is interrupted, and the output Ii' is grounded and set to zero, thus achieving the purpose of interrupt transmission.

[0042] like Figure 7 As shown, the shift accumulator RA in this embodiment includes: a first N-1 selector 351, used to select an output from input data c_in and 0 based on the control signal ctrl; a three-input adder 352, used to accumulate the output of the first N-1 selector 351, the result of the left shift operation of the output of the shift accumulator RA by one bit, and the input data P_sum; a second N-1 selector 353, used to select an output from the output of the three-input adder 352 and the input data P_sum based on the control signal ctrl; a register 354, used to temporarily store the output data of the second N-1 selector 353 before outputting it; and a one-bit shifter 355, which performs a left shift operation on a portion of the output of the register 354 and inputs the result of the left shift operation of the output of the shift accumulator RA to the three-input adder 352.

[0043] In the addition tree network 35, which is a 6-layer addition tree, the first layer of the addition tree receives the 64×4-bit multiplication result of the output data of each SRAM cell and the input C-CIM data of the input buffer. The multiplication results are sorted according to banks from 0 to 63. Data with corresponding indexes are added pairwise (odd and even). Figure 6 The inputs shown in the two dashed boxes on the left and right are 2-input adders composed of different numbers of FAs depending on the bit width of the input data, such as... Figure 6The bit width of the first layer input addend of the middle-adder tree is 4, so the 2-input adder is composed of 4 FAs. If the two adjacent addends do not need to be accumulated, the corresponding interrupt module IE is enabled to interrupt the addition, and the output of the 2-input adder is divided into two parts and output to different layers. For example, the four-bit input of result 0 and result 1 correspond to A0-A3 and B0-B3 respectively, A0-A3 input the interrupt module IE, B0-B3 directly input the FA, the four-bit input of result 2 and result 3 correspond to C0-C3 and D0-D3 respectively, D0-D3 input the interrupt module IE, C0-C3 directly input the first layer FA, input Ctr0 / CtrB0 to control the accumulation of result 0 and result 1, input Ctr2 / CtrB2 to control the accumulation of result 2 and result 3, if no accumulation is needed, result 0 or result 3 is output to the integration module through the IE to get Out_L output, and A' or D' output from the interrupt module IE is set to 0 (i.e. data B and data C are added with 0 respectively); the 2-input adder of the second layer of the addition tree receives the output results of the first layer of the 2-input adder to accumulate two by two (if the addition tree is interrupted in the first layer, only the output of the nearest first layer is received, for example, the addition path of data 8 and data 9 is split in the first layer, so the 2-input adder corresponding to the two numbers does not accumulate, but directly outputs the two numbers, data 9 is directly sent to the second layer 2-input adder), the accumulation result is output to the third layer N-2 addition selector or 2-input adder, which partially implements the corresponding Figure 5The 2-input adder of the third layer adder tree receives the output results of the 2-input adders of the second layer to add two by two, the N-2 adder selector selects the accumulated data according to the interrupt of the first layer adder tree, if an interrupt occurs, for example, the data 26 and 27 interrupt the accumulation path in the first layer, which indicates that the data before the data 26 will not be added with the data after the data 27, at this time, the N-2 adder selector only selects the output of the 2-input adder at the interrupt module of the first layer and the output of the 2-input adder of the second layer, and directly outputs to the N-2 adder selector of the sixth layer. Otherwise, the output results of two adjacent 2-input adders are selected to add and output to the 2-input adder of the fourth layer; the 2-input adder of the fourth layer adder tree receives the output results of the 2-input adders of the third layer to add two by two, the N-2 adder selector selects the accumulation path according to the interrupt of the first layer adder tree, if an interrupt of the adder tree occurs, for example, the data 8 and 9 interrupt the accumulation path in the first layer, which indicates that the data before the data 8 will not be added with the data after the data 9, at this time, the N-2 adder selector only selects the output of the 2-input adder at the interrupt module of the first layer and the output of the 2-input adder of the third layer, and the output results of the adder tree after the interrupt in this layer are directly output to the RA module for shift accumulation operation and output to the off-chip. If no interrupt occurs, the N-2 selector only selects the output of the two nearest 2-input adders of the third layer to add, and the output results are transmitted to the fifth layer; in the fifth layer adder tree, if the previous accumulation path is not split by the interrupt module IE, the N-2 adder selector directly receives the accumulation results of the N-2 adder selector and the 2-input adder of the fourth layer to add, and the output results are output to the sixth layer, otherwise the N-2 adder selector receives the partial accumulation sums of the nearest second layer and third layer to add and outputs to the shift accumulator RA; in the sixth layer adder tree, if the previous accumulation path is not split by the interrupt module IE, the output results of the two N-2 adder selectors of the fifth layer are directly received to add, otherwise only the outputs of the two 2-input adders and the N-2 adder selector of the nearest third layer are received and added, both of which will output the final results to the shift accumulator RA.

[0044] As Figure 8As shown, the multi-mode adaptive controller 32 in the embodiment includes a plurality of controller modules 321 and a plurality of C-NOT gates 322. The controller module 321 includes a plurality of data channels, each of which includes three sub-control modules 323 and a switch 324 connected in sequence. Each controller module 321 inputs the internal sub-control modules 323 and the switch 324 respectively by receiving the same input Xin and the respective input Yin. The multi-mode adaptive controller 32 obtains the RWL / RWLB read signals required by each SRAM cell according to the three input signals Xin, Yin and Zin, and outputs the RWL / RWLB read signals to the SRAM cell, thereby controlling the SRAM cell.

[0045] As shown, Figure 9 The sub-control module 323 in the embodiment is composed of a switch 324 and a C-NOT gate 322. The switch 324 is composed of a transmission gate T0, a MOS transistor T2 (specifically a PMOSFET transistor in the embodiment) and an inverter T1. The control terminals of the transmission gate T0 and the MOS transistor T2 are connected to the input Xin. The transmission gate T0 determines whether to open the output RWL to pass the input Yin to the transmission gate T0 according to the input Xin. If the input Xin is set to "1", the transmission gate T0 is opened and the MOS transistor T2 is closed, so that the input Yin is passed to the output RWL. The inverter T1 generates the reverse output RWLB by inverting the input Yin. If the input Xin is set to "0", the transmission gate T0 is closed and the MOS transistor T2 is opened, so that the output RWL is grounded and output as "0".

[0046] As shown, Figure 9As shown, the C-NOT gate 322 in the embodiment is composed of a transmission gate T4 and an inverter T3. If the input Xin is set to "1", the inverter T3 works in the manner of an inverter, and the transmission gate T4 is closed, so that the output Yout is the negation of the input Yin. If the input Xin is set to "0", the inverter T3 works in the manner of a transmission gate, and the transmission gate T4 is opened to enhance the Yin input, so that the output Yout is equal to the input Yin. The sub-control module 323 outputs Yout, RWL and reverse output RWLB based on a preset truth table through the input Xin and the input Yin. The output Yout is transmitted from left to right to the next sub-control module 323 until it is transmitted to the switch 324. The output RWL and the reverse output RWLB signals of each sub-control module 323 and the switch 324 are finally output by integration. Each output RWL and reverse output RWLB controls the data readout of three columns of the SRAM array 33. The C-NOT gate 322 combines the output RWL and the reverse output RWLB and the input Z to obtain data selection signals of the other five columns of the SRAM array 33 for controlling the data readout of the other five columns of the SRAM array 33. In the embodiment, the truth table used by the sub-control module 323 to output Yout, RWL and reverse output RWLB based on the input Xin and the input Yin is shown in Table 1.

[0047] Table 1: Truth table

[0048]

[0049] The C-CIM supporting multi-mode convolution in the embodiment provides four computing modes: matrix multiplication (equivalent to 1x1 convolution), 3x3 convolution, 5x5 convolution and 7x7 convolution. Figure 10 The control principle diagram of the SRAM array in the embodiment is shown in FIG. 6. In order to facilitate understanding of the subsequent computing modes, the internal modules in the multi-mode adaptive controller 32 are dispersed into the SRAM unit in the embodiment, so as to intuitively show that each sub-control module 323 controls the data readout of three SRAM unit memories. The input signals Xin[0]-Xin[3] are external input signals Xin, the input signals Yin[0][0]-Yin[0][2] are external input signals Yin, and the input signals Zin[0]-Zin[2] are external input signals Zin.

[0050] Figure 11The calculation process of the compute-in-memory acceleration circuit (C-CIM) supporting multi-mode convolution in the 3x3 convolution mode of the present embodiment. Among the A-I in the 3x3 weight, the 0-17 in the input are weight data and activation data, which are stored in the SRAM unit according to the serial number. The convolution kernel slides from left to right in order. The black solid line short arrow represents that the line is activated to "1". The data in the dashed box area is multiplied by the weight on the left side of the array. The SRAM unit in the dashed box represents that the internal data is replaced. Xin and Yin are shared in all control modules. When the step of convolution is set to 1 and 2 respectively, the input Yin[2:0] will switch according to a specific order, and the state will alternate between {111, 110, 100} and {111, 100, 110}. At the same time, Xin[3:0] is switched according to the column serial number of the required convolution data, and the control module controls the data readout of the SRAM unit according to the input Xin and Yin. For the first convolution, the first column of data is selected. Therefore, Xin[3:0] is set to "0001". Subsequently, for the second convolution, the first two columns of data are used, and the result is that Xin[3:0] is set to "0011". At the same time, during the second convolution process, data "n" is written in parallel to the original data 0 position to alleviate the bandwidth pressure of data replacement. In order to support this data replacement, the present embodiment designs a write selector module WRSE. The write selector module WRSE selects the first address of the bank according to the input of 6-bit address data, and then controls the interval and quantity of data to be written through the control signals Winterval[3:0] and Wrows[1:0]. In this case, the present embodiment sets Winterval[3:0] and Wrows[1:0] to 9 and 2 respectively. Therefore, data will be written to the first SRAM column of Bank0 and Bank9.

[0051] Figure 12 The calculation process of the compute-in-memory acceleration circuit (C-CIM) supporting multi-mode convolution in the 3x3 convolution mode of the present embodiment. Among the A-I in the 3x3 weight, the 0-17 in the input are weight data and activation data, which are stored in the SRAM unit according to the serial number. The convolution kernel slides from left to right in order. The black solid line short arrow represents that the line is activated to "1". The data in the dashed box area is multiplied by the weight on the left side of the array. The SRAM unit in the dashed box represents that the internal data is replaced. Xin and Yin are shared in all control modules. When the step of convolution is set to 1 and 2 respectively, the input Yin[2:0] will switch according to a specific order, and the state will alternate between {111, 110, 100} and {111, 100, 110}. At the same time, Xin[3:0] is switched according to the column serial number of the required convolution data, and the control module controls the data readout of the SRAM unit according to the input Xin and Yin. For the first convolution, the first column of data is selected. Therefore, Xin[3:0] is set to "0001". Subsequently, for the second convolution, the first two columns of data are used, and the result is that Xin[3:0] is set to "0011". At the same time, during the second convolution process, data "n" is written in parallel to the original data 0 position to alleviate the bandwidth pressure of data replacement. In order to support this data replacement, the present embodiment designs a write selector module WRSE. The write selector module WRSE selects the first address of the bank according to the input of 6-bit address data, and then controls the interval and quantity of data to be written through the control signals Winterval[3:0] and Wrows[1:0]. In this case, the present embodiment sets Winterval[3:0] and Wrows[1:0] to 9 and 2 respectively. Therefore, data will be written to the first SRAM column of Bank0 and Bank9. Figure 11

[0052] Figure 13 ​The calculation process of the compute-in-memory acceleration circuit (C-CIM) supporting multi-mode convolution of the present embodiment in 5x5 convolution mode. When 5x5 convolution mode is selected, the multiply-accumulate operation array 3 (MAC array) can only use two 5x5 convolution kernels for sliding operation at the same time. Therefore, the present embodiment divides the available SRAM array into two groups, of which the first group includes block 0-block 2 and the first three banks of block 3, and the second group includes the last three banks of block 3 and block 4-block 6. At present, the four control modules only share the input Xin. The present embodiment divides the SRAM array according to the original 3x3 convolution, so that five data are stored in every six banks, and the last bank is set to zero. Every two Yin controls the sliding of the convolution kernel, for example, the input Yin[0][0] and Yin[0][1] simultaneously control the reading of the first five data in the SRAM array. The data mapping and replacement strategy follow the 3, and the convolution is performed according to the state shown in Table 2 (cyclically with 5 convolution operations as a period).

[0053] Table 2: State switching table for 5x5 convolution

[0054]

[0055] When the 7x7 convolution mode is selected, the present embodiment only uses the first 7 blocks (block 0-block 6), each of which stores data in the first 7 banks, and the remaining banks are filled with zeros. In this case, the present embodiment introduces an additional input Z[2:0] to control the interruption. The data mapping follows the same mode as the 3x3 convolution, and the convolution is performed according to the state shown in Table 3 (cyclically with 7 convolution operations as a period).

[0056] Table 3: State switching table for 7x7 convolution

[0057]

[0058] In summary, the compute-in-memory acceleration circuit (C-CIM) supporting multi-mode convolution of the present embodiment aims to enhance the traditional digital SRAM-CIM architecture by merging control logic to regulate data flow, taking advantage of the inherent flexibility and scalability of digital CIM. It is crucial to design efficient control logic without sacrificing the original CIM storage density. The mapping mechanism between control logic and data is also important because it can reduce the repeated movement of data. Secondly, since a single functional adder tree cannot support multiple accumulation forms, it is crucial to design a flexible and adaptive adder tree network to address this limitation. The goal of the compute-in-memory acceleration circuit (C-CIM) supporting multi-mode convolution of the present embodiment is to support various convolutions with minimal additional area cost, and the present embodiment also provides a novel adder tree network to maintain high computational efficiency.

[0059] Furthermore, the embodiment also provides a chip, comprising a chip body and a memory-compute integrated acceleration circuit arranged in the chip body, the memory-compute integrated acceleration circuit being the aforementioned memory-compute integrated acceleration circuit supporting multi-mode convolution.

[0060] Furthermore, the embodiment also provides a computer device, comprising a microprocessor and a memory connected to each other, and the microprocessor comprises the aforementioned memory-compute integrated acceleration circuit supporting multi-mode convolution.

[0061] The above merely describes the preferred embodiments of the present application, and the protection scope of the present application is not limited to the above-mentioned embodiments only, and any technical solutions falling within the concept of the present application shall fall within the protection scope of the present application. It should be noted that, for ordinary skilled persons in the art, some improvements and refinements without departing from the principles of the present application shall also be considered as falling within the protection scope of the present application.

Claims

1. An in-memory computing acceleration circuit supporting multi-mode convolution, the circuit comprising: The application relates to a memory-compute integrated acceleration circuit, which comprises an input buffer, a column address decoder and 64 multiply-accumulate operation arrays, wherein the multiply-accumulate operation arrays comprise a row address decoder for selecting a row of the SRAM array for precise writing of data into the SRAM array in cooperation with the column address decoder; a multi-mode adaptive controller for controlling the multiply-accumulate operation arrays to perform convolution or matrix multiplication according to external input signals Xin, Yin and Zin; an SRAM array for storing weight values WS or activation data IS according to the data flow mode of the memory-compute integrated acceleration circuit; a multiplier for bit multiplication of the output data of the row SRAM array and the output data of the input buffer; and an addition tree network for grouping and adding the data output by all the multipliers according to a control signal and outputting the external of the memory-compute integrated acceleration circuit; the 64 multiply-accumulate operation arrays share a common column address decoder and are connected to the same input buffer; the SRAM array is composed of an SRAM unit, which comprises a first transfer gate, a second transfer gate, a third transfer gate, a first inverter, a second inverter and a third inverter; an input signal WBLB of the SRAM unit is connected to a first input end of the first transfer gate; the output end of the first transfer gate is connected to the input end of the third transfer gate through the first inverter and the third inverter in sequence; the output end of the third transfer gate is used for outputting an output signal RBLB of the SRAM unit; a second input end of the first transfer gate is connected to a write signal WWL, and a control end is connected to a write signal WWLB; a first input end of the second transfer gate is connected to the intermediate junction points of the first inverter and the third inverter through a reversely arranged second inverter; a second input end of the second transfer gate is connected to the write signal WWLB, a control end is connected to the write signal WWL, and an output end is connected to the output end of the first transfer gate; one input end of the third transfer gate is connected to the output end of the third inverter, the other input end is connected to a read signal RWL, and a control end is connected to a read signal RWLB; when the write signal WWL and the write signal WWLB are set to "1" and "0" respectively, the first transfer gate is activated, the data of the input WBLB is written into the SRAM unit, and the data is kept in the SRAM unit through the first inverter and the third inverter; when the read signal RWL and the read signal RWLB are set to "1" and "0" respectively, the data stored in the SRAM unit is output as the output signal RBLB through the third transfer gate.

2. The memory compute integrated acceleration circuit supporting multi-mode convolution of claim 1, wherein, The SRAM array is composed of 64 memory banks, each of which contains 4*4 SRAM cells, and the storage space of the SRAM array is 1kb, each memory bank is connected to the multiplier through four data read lines, and each memory bank selects one column to output in each operation, and the selection process is controlled by a multi-mode adaptive controller; in each clock cycle, the multiplier selects 4-bit data from the input buffer and the data stored in the SRAM array through a 4*1 multiplexer, and then outputs the bit multiplication result to the addition tree network, the addition tree network collects the 4-bit*1-bit results according to the control logic, and then the collected results are transmitted to the internal shift accumulator, and the shift accumulator uses the shift accumulation method to obtain the final required 4-bit*4-bit or 4-bit*8-bit data and outputs through the output line NOUT of the addition tree network.

3. The memory compute integrated acceleration circuit supporting multi-mode convolution of claim 1, wherein, The addition tree network is composed of a 6-layer addition tree and an integration module, wherein the first layer of the addition tree includes 32 two-input adders and an interrupt module IE arranged in front of the 32 two-input adders, the two-input adder is composed of a plurality of full adders FA, the first layer of the addition tree is used to receive the 64x4-bit multiplication result of the data output by each SRAM unit and the data output by the input buffer, the multiplication result is sorted according to the order of the bank number from 0 to 63 and used as an addend, the addends corresponding to the order numbers are added by two two-input adders, and if the two adjacent addends do not need to be added, the corresponding interrupt module IE is enabled to break the addition and directly output, wherein one addend is output to the second layer of the addition tree, and the other addend is output to the third or fourth layer of the addition tree; the second layer of the addition tree includes 16 two-input adders, which are used to add the 32 two-input adders of the first layer of the addition tree by two, and if there is an addition break in a two-input adder of the first layer of the addition tree, only the nearest one of the two addends of the two-input adder is used as the input of the corresponding two-input adder in the second layer of the addition tree; the third layer of the addition tree includes 6 two-input adders and 2 N-2 adder selectors, the two-input adders of the third layer of the addition tree are used to add the outputs of the 12 two-input adders of the second layer of the addition tree, and the two N-2 adder selectors of the third layer of the addition tree are used to add the outputs of the 12 two-input adders of the second layer of the addition tree and the addends broken by the interrupt module IE of the first layer of the addition tree; the fourth layer of the addition tree includes 2 two-input adders and 2 N-2 adder selectors, the output ends of the 2 two-input adders and 2 N-2 adder selectors in the fourth layer of the addition tree are connected and arranged with a shift accumulator RA, the two two-input adders of the fourth layer of the addition tree are used to add the outputs of the 4 two-input adders of the third layer of the addition tree, and the two N-2 adder selectors of the fourth layer of the addition tree are used to add the outputs of the 4 two-input adders of the third layer of the addition tree and the addends broken by the interrupt module IE of the first layer of the addition tree; the fifth layer of the addition tree includes 2 N-2 adder selectors, and the output ends of the 2 N-2 adder selectors in the fifth layer of the addition tree are connected and arranged with a shift accumulator RA, the two N-2 adder selectors in the fifth layer of the addition tree are used to add the outputs of the 1 two-input adder and 1 N-2 adder selector of the fourth layer of the addition tree; the sixth layer of the addition tree includes 1 N-2 adder selector, and the output ends of the N-2 adder selector in the sixth layer of the addition tree are connected and arranged with a shift accumulator RA, the N-2 adder selector in the sixth layer of the addition tree is used to add the outputs of the 2 N-2 adder selectors in the fifth layer of the addition tree; the outputs of the shift accumulators RA of each layer of the addition tree are connected with the input ends of the integration module.

4. The compute-in-memory acceleration circuit that supports multi-mode convolution of claim 3, wherein, The inputs of the full adder FA include three addends A, B and Cin, and the outputs include carry CO and sum S. The carry CO is "1" only when the inputs A, B and Cin are all "1" or two of the inputs are "1", otherwise the carry CO is always "0". The sum S is "0" only when two of the inputs A, B and Cin are "1", or all of the inputs are "0", otherwise the sum S is always "1".

5. The memory compute integrated acceleration circuit supporting multi-mode convolution of claim 3, wherein, The interrupt module IE includes a plurality of one-bit data interrupt module IE, which is composed of one MOS tube and one transmission gate, and the input one-bit data I i is connected to the input end of the transmission gate, and the output end of the transmission gate outputs I i , and is connected to one input end of the two-input adder, the control end of the transmission gate is connected with control signals Ctr and CtrB respectively, the output end of the transmission gate is grounded through the MOS tube, and the control end of the MOS tube is connected with the control signal Ctr, when the control signals Ctr and CtrB are set as "1" and "0", the transmission gate is interrupted, the output I i is grounded to zero, so as to achieve the purpose of interrupting transmission.

6. The memory compute integrated acceleration circuit supporting multi-mode convolution of claim 3, wherein, The shift accumulator RA includes a first N-1 selector for selecting one of the input data c_in and 0 based on a control signal ctrl, a three-input adder for performing accumulation calculation on the output of the first N-1 selector, a result of left shift operation of the shift accumulator RA and input data P_sum, a second N-1 selector for selecting one of the output of the three-input adder and the input data P_sum based on the control signal ctrl, a register for outputting the output data of the second N-1 selector after temporary storage, and a one-bit shifter for performing left shift operation on the partial sum output by the register as the result of left shift operation of the shift accumulator RA and inputting the result into the three-input adder.

7. The in-memory computing acceleration circuit supporting multi-mode convolution of claim 1, wherein, The multi-mode adaptive controller includes a plurality of controller modules and a plurality of C-NOT gates. Each of the controller modules includes a plurality of data channels, each of which includes three sub-control modules and a switch connected in sequence. Each of the controller modules inputs the same input Xin and respective input Yin into the sub-control modules and the switch respectively. Each of the sub-control modules is composed of a switch and a C-NOT gate. The switch is composed of a transmission gate T0, a MOS transistor T2 and an inverter T1. The control terminals of the transmission gate T0 and the MOS transistor T2 are connected to the input Xin. The transmission gate T0 determines whether to open the output RWL to pass the input Yin according to the input Xin. If the input Xin is "1", the transmission gate T0 is opened and the MOS transistor T2 is closed, so that the input Yin is passed to the output RWL. The inverter T1 generates an inverted output RWLB according to the input Yin. If the input Xin is "0", the transmission gate T0 is closed and the MOS transistor T2 is opened, so that the output RWL is grounded and outputs "0". The C-NOT gate is composed of a transmission gate T4 and an inverter T3. If the input Xin is "1", the inverter T3 works as an inverter and the transmission gate T4 is closed, so that the output Yout is the inverse of the input Yin. If the input Xin is "0", the inverter T3 works as a transmission gate and the transmission gate T4 is opened to enhance the input Yin, so that the output Yout is equal to the input Yin. The sub-control module outputs Yout, RWL and reverse output RWLB based on preset truth table through input Xin and input Yin, Yout is transmitted to next stage sub-control module from left to right until transmission to switch, the output RWL and reverse output RWLB signal of each sub-control module and switch are finally outputted through integration to output multi-mode adaptive controller, each output RWL and reverse output RWLB control the data readout of three columns of SRAM array, the C-NOT gate combines output RWL and reverse output RWLB and input Z to obtain data selection signal of another five columns of SRAM array after processing to control the data readout of another five columns of SRAM array.

8. A chip comprising a chip body and an in-memory computing acceleration circuit provided in the chip body, characterized in that, The memory computing integrated acceleration circuit is the memory computing integrated acceleration circuit supporting multi-mode convolution in any one of claims 1-7.

9. A computer device comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor comprises the memory computing integrated acceleration circuit supporting multi-mode convolution in any one of claims 1-7.

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