FPGA (Field Programmable Gate Array) online upgrading method

Abstract

The invention discloses an FPGA online upgrading method, and relates to the technical field of airborne electronic systems. The method comprises the following steps of: erasing a sector: after electrification, sending an upgrading instruction by a computer, after an FPGA upgrading logic module receives the instruction, initializing Flash and erasing the sector, and judging erasing: if the erasing is finished, entering the next step, and if the erasing is not finished, returning an unfinished erasing mark to the computer, and if the upgrading is failed, configuring programming; if yes, an erasure completion mark is returned to the computer, the computer sends the configuration file needing to be upgraded through the serial port for programming and data backward reading after receiving the erasure completion mark, the data backward reading is performed for verification after programming of the configuration file is completed, and if verification is passed, a verification passing mark is returned to the computer, and upgrading succeeds. According to the upgrading method provided by the invention, logic version upgrading can be realized without disassembling a machine and changing an original hardware circuit design, an emulator is omitted, and a common serial port is used, so that the method has relatively high practicability and feasibility.

Description

Technical Field

[0001] The present invention relates to the technical field of airborne electronic systems, and in particular to an FPGA online upgrade method. Background Art

[0002] FPGA plays an increasingly important role in airborne electronic systems due to its powerful performance and flexibility. New products will frequently update their logic from design to finalization. FPGA supports loading modes such as BPI Flash, SPI Flash, and microprocessors. Among them, SPI mode is the most commonly used because it has fewer pins, supports X1, X2, and X4 operations, and has simple peripheral circuits. Figure 2 As shown in the figure, it is a JTAG upgrade principle block diagram. The computer and FPGA are connected through the JTAG emulator, and the configuration file is indirectly burned to the SPI Flash through the JTAG interface. The driver software of the whole process is supported by development tools, such as Vivado. After the FPGA is powered on again, the clock clk will be driven internally, the chip select cs will be pulled down, and the configuration file will be read out through the serial data output pin dout to complete the program loading.

[0003] At present, the above method is usually used to upgrade the logic of FPGA products. However, the JTAG interface requires 6 wires, which is a large number. Considering the signal integrity, it is not suitable for long-distance routing to the outside of the product. Therefore, it is inevitable to open the chassis cover during the upgrade process, and then connect the JTAG emulator to burn the configuration file. The operation is cumbersome. At the same time, with the development trend of lightweight and miniaturization of aviation products, the size of the chassis is getting smaller and smaller, which will be more inconvenient to plug and unplug the emulator, thus bringing difficulties to product upgrades and maintenance. For this reason, an FPGA online upgrade method is proposed. Summary of the invention

[0004] In view of this, the present invention provides an FPGA online upgrade method to solve the problem that the above method is usually adopted when upgrading the logic of FPGA products.

[0005] The technical solution adopted by the present invention is: an FPGA online upgrade method, characterized in that it includes the following steps: S1. Erase sectors: After power-on, the computer sends an upgrade command. After receiving the command, the FPGA upgrade logic module initializes the Flash and erases the sectors. S2, erasing judgment: if the erasing is completed, go to the next step; if the erasing is not completed, return an erasing incomplete flag to the computer, and the upgrade fails; S3, configuration burning: if the erasure is completed, the erase completion mark is returned to the computer, and after receiving it, the computer sends the configuration file to be upgraded through the serial port for burning; S4. Read back data: After the configuration file is burned, the data is read back for verification. If the verification passes, a verification pass mark is returned to the computer, indicating that the upgrade is successful. If the verification fails, a verification failure mark is returned to the computer, indicating that the upgrade fails.

[0006] Further, the FPGA upgrade logic module includes a UART module, a RAM control module and a Flash controller module; The UART module is used to encode and decode serial data, receive instructions and configuration files from the computer, and return status information during the upgrade process; The RAM control module is used to complete the cache of serial port data; The Flash controller module is used for reading and writing data.

[0007] Furthermore, the RAM control module is divided into Block 1 and Block 2; Block 1 stores odd-numbered data packets from the configuration file, and Block 2 stores even-numbered data packets from the configuration file; when the odd-numbered data packets are stored, a Ping signal is generated, and Flash writing starts. The Flash writing time is shorter than the time for the RAM control module to cache a packet of serial port data, so after the odd-numbered data packets are written to the Flash, the even-numbered data packets are not stored yet; when the even-numbered data packets are stored, a Pong signal is generated, and the next round of Flash writing starts, and the Ping signal and the Pang signal are continuously alternating until the file is sent.

[0008] Furthermore, the Flash controller module uses a state machine to complete the operation of Flash and realize data reading and writing; the state machine includes idle state, initialization, erasing, reading status register, writing data, reading data, CRC check and END end; before executing the erase command, the read status register is set, and after the erase command is executed, the status register value is read to determine whether the erasure is completed. If the WIP of the status register is 0 within a period of time, it means that the erasure is successful, otherwise if WIP=1, it means a write error and exits the operation process; before executing the write data command, the status register is set, and when writing data, the write command and write address are sent first, and then the status register value is read for judgment. If the WIP of the status register is 0 within a period of time, it means that the writing is successful, otherwise if WIP=1, it means a write error and exits the operation process; after writing, the read command and read address are sent, and then the data is received for CRC check, and the check passes this upgrade END and ends.

[0009] The beneficial effects of the present invention are as follows: 1. The present invention sets an FPGA upgrade logic module, utilizes 4 SPI hardware connections between FPGA and Flash, designs the upgrade control logic by itself, integrates the FPGA upgrade logic module, writes the configuration file to be upgraded directly into the Flash and overwrites the previous content, and the new configuration file will be loaded at the next power-on startup, and the logic version upgrade can be achieved without disassembling the machine and changing the original hardware circuit design.

[0010] 2. After the FPGA is powered on, the present invention automatically reads the configuration file and completes the loading, so it is separated from the simulator, and uses the serial port to directly write the configuration file to be upgraded into the Flash through the serial port and overwrite the previous content. The serial port is more commonly used in aviation product design and is often used as a maintenance port, so the method is simple to implement and has high practicality and feasibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a flow chart of the FPGA online upgrade method of the present invention.

[0012] Figure 2 This is the principle block diagram of the original JTAG upgrade.

[0013] Figure 3 It is a principle block diagram of upgrading the FPGA upgrading logic module of the present invention.

[0014] Figure 4 It is a schematic diagram of the basic process of upgrading the FPGA upgrade logic module of the present invention.

[0015] Figure 5 It is a logic structure block diagram of the FPGA upgrade logic module of the present invention.

[0016] Figure 6 It is a principle block diagram of the ping-pong operation of the RAM control module of the present invention.

[0017] Figure 7 It is a state machine schematic diagram of the Flash controller module of the present invention. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0019] like Figures 1 to 7 As shown, a method for online upgrading of FPGA includes the following steps: S1. Erase sectors: After power-on, the computer sends an upgrade command. After receiving the command, the FPGA upgrade logic module initializes the Flash and erases the sectors. S2, erasing judgment: if the erasing is completed, go to the next step; if the erasing is not completed, return an erasing incomplete flag to the computer, and the upgrade fails; S3, configuration burning: if the erasure is completed, the erase completion mark is returned to the computer, and after receiving it, the computer sends the configuration file to be upgraded through the serial port for burning; S4, read back data: after the configuration file is burned, read back the data for verification. If the verification passes, a verification pass mark is returned to the computer, indicating that the upgrade is successful. If the verification fails, a verification failure mark is returned to the computer, indicating that the upgrade fails. Specifically, to upgrade the FPGA logic version, you need to use the 4 SPI hardware connections between the FPGA and the Flash, design the upgrade control logic yourself, and integrate it into the entire FPGA as a functional module to obtain the FPGA upgrade logic module. After the FPGA upgrade logic module is running, the configuration file to be upgraded is written into the Flash through the functional module. Figure 3 As shown, the computer is connected to the FPGA via a USB to serial port board. The serial port is simple to implement and is commonly used in aviation product design and is often used as a maintenance port. Under logic control, the configuration file to be upgraded will be directly written into the Flash through the serial port and overwrite the previous content. The new configuration file will be loaded at the next power-on startup, so that the logic version upgrade can be achieved without disassembling the machine and changing the original hardware circuit design. After the FPGA is powered on, the configuration file is read and loaded automatically, so it is separated from the simulator.

[0020] In summary, Figure 4 The basic process of upgrading is described. After power-on, the computer sends an upgrading instruction. After receiving the instruction, the FPGA initializes the Flash and erases the sector. After the erasing is completed, it returns an erasing completion mark to the computer. After receiving it, the computer sends the configuration file to be upgraded through the serial port for burning. After the burning is completed, the data is read back for verification. If it passes, it means the upgrade is successful.

[0021] In this embodiment, the FPGA upgrade logic module includes a UART module, a RAM control module and a Flash controller module; Specifically, Figure 5 As shown: (1) UART module: The UART module mainly encodes and decodes serial data, receives instructions and configuration files from the computer, and returns status information during the upgrade process.

[0022] (2) RAM control module: In order to match the speed of the serial port and SPI, the RAM control module on the FPGA chip is used to cache the serial port data. Figure 6As shown, the RAM control module is divided into Block1 and Block2, where Block1 is used to store odd-numbered data packets from the configuration file, and Block2 is used to store even-numbered data packets from the configuration file. When the odd-numbered data packets are stored, a Ping signal is generated to start Flash writing. Since Flash writing is very fast, the time is much shorter than the time it takes for the RAM to cache a packet of serial port data. Therefore, when the odd-numbered data packets are written to the Flash, the even-numbered data packets are not stored. When the even-numbered data packets are stored, a Pong signal is generated, and the next round of Flash writing begins. In this way, Ping (Ping) and Pong (Pong) operations are continuously performed, and there will never be conflicts in reading and writing until the file is sent.

[0023] (3) Flash controller module: The Flash controller module uses a state machine to complete the operation of the Flash, which can realize data reading and writing in an orderly manner. Figure 7 As shown in the figure, the working status of Flash can be divided into idle state (Idle), initialization, erase, read status register, write data (write), read data (read), CRC check, end (END), etc. Before executing the erase command, a write enable command operation is required to set the status register. After the erase command is executed, the status register value is read to determine whether the erase is completed. If the WIP of the status register is 0 within a period of time, it means that the erase is successful. Otherwise, if WIP=1, it means a write error and the operation process is exited.

[0024] Like the erase command operation, the write enable command needs to be written to the Flash before the write data command is executed, and the status register is set. When writing data, the write command and write address are sent first, and then the status register value is read for judgment. If the WIP of the status register is 0 within a period of time, it means the write is successful, otherwise if WIP=1, it means the write is wrong and the operation process is exited. After writing, the read command and read address are sent, and then the data is received for verification. If the verification passes, the upgrade is completed.

[0025] In summary: This FPGA online upgrade method, by setting up the FPGA upgrade logic module, uses the 4 SPI hardware connections between FPGA and Flash, designs the upgrade control logic by itself, and integrates the FPGA upgrade logic module. The configuration file to be upgraded is directly written into the Flash and overwrites the previous content. The new configuration file will be loaded at the next power-on startup. The logic version upgrade can be achieved without disassembling the machine and changing the original hardware circuit design. After the FPGA is powered on, the configuration file is read and loaded automatically, so it is separated from the simulator, and the configuration file to be upgraded is directly written into the Flash through the serial port through the serial port and overwrites the previous content. The serial port is more commonly used in aviation product design and is often used as a maintenance port, so this method is simple to implement and has high practicality and feasibility.

Claims

1. A method for online upgrading of FPGA, characterized in that: The steps include: S1. Erase sectors: After power-on, the computer sends an upgrade command. After receiving the command, the FPGA upgrade logic module initializes the Flash and erases the sectors. S2, erasing judgment: if the erasing is completed, go to the next step; if the erasing is not completed, return an erasing incomplete flag to the computer, and the upgrade fails; S3, configuration burning: if the erasure is completed, the erase completion mark is returned to the computer, and after receiving it, the computer sends the configuration file to be upgraded through the serial port for burning; S4. Read back data: After the configuration file is burned, the data is read back for verification. If the verification passes, a verification pass mark is returned to the computer, indicating that the upgrade is successful. If the verification fails, a verification failure mark is returned to the computer, indicating that the upgrade fails.

2. The FPGA online upgrade method according to claim 1, characterized in that: The FPGA upgrade logic module includes a UART module, a RAM control module and a Flash controller module; The UART module is used to encode and decode serial data, receive instructions and configuration files from the computer, and return status information during the upgrade process; The RAM control module is used to complete the cache of serial port data; The Flash controller module is used for reading and writing data.

3. The FPGA online upgrade method according to claim 2, characterized in that: The RAM control module is divided into Block1 and Block2; Block1 stores odd-numbered data packets from the configuration file, and Block2 stores even-numbered data packets from the configuration file; when the odd-numbered data packets are stored, a Ping signal is generated and Flash writing starts. The Flash writing time is shorter than the time for the RAM control module to cache a packet of serial port data, so after the odd-numbered data packets are written to the Flash, the even-numbered data packets are not stored yet; when the even-numbered data packets are stored, a Pong signal is generated and the next round of Flash writing starts, and the Ping signal and the Pang signal are continuously alternating until the file is sent.

4. The FPGA online upgrade method according to claim 2, characterized in that: The Flash controller module uses a state machine to complete the operation of Flash and realize data reading and writing; the state machine includes idle state, initialization, erasing, reading status register, writing data, reading data, CRC check and END end; before executing the erase command, the read status register is set, and after the erase command is executed, the status register value is read to determine whether the erasure is completed. If the WIP of the status register is 0 within a period of time, it means that the erasure is successful, otherwise if WIP=1, it means a write error and exits the operation process; before executing the write data command, the status register is set, and when writing data, the write command and write address are sent first, and then the status register value is read for judgment. If the WIP of the status register is 0 within a period of time, it means that the write is successful, otherwise if WIP=1, it means a write error and exits the operation process; after writing, the read command and read address are sent, and then the data is received for CRC check. The check passes this upgrade END and ends.

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